target/linux/lantiq/patches/809-mt-vpe.patch

   1 --- a/arch/mips/Kconfig
   2 +++ b/arch/mips/Kconfig
   3 @@ -1669,6 +1669,28 @@ config MIPS_VPE_LOADER
   4           Includes a loader for loading an elf relocatable object
   5           onto another VPE and running it.
   6
   7 +config IFX_VPE_EXT
   8 +       bool "IFX APRP Extensions"
   9 +       depends on MIPS_VPE_LOADER
  10 +       default y
  11 +       help
  12 +         IFX included extensions in APRP
  13 +
  14 +config PERFCTRS
  15 +       bool "34K Performance counters"
  16 +       depends on MIPS_MT && PROC_FS
  17 +       default n
  18 +       help
  19 +         34K Performance counter through /proc
  20 +
  21 +config MTSCHED
  22 +       bool "Support mtsched priority configuration for TCs"
  23 +       depends on MIPS_MT && PROC_FS
  24 +       default y
  25 +       help
  26 +         Support for mtsched priority configuration for TCs through
  27 +         /proc/mips/mtsched
  28 +
  29  config MIPS_MT_SMTC_IM_BACKSTOP
  30         bool "Use per-TC register bits as backstop for inhibited IM bits"
  31         depends on MIPS_MT_SMTC
  32 --- a/arch/mips/include/asm/mipsmtregs.h
  33 +++ b/arch/mips/include/asm/mipsmtregs.h
  34 @@ -28,14 +28,34 @@
  35  #define read_c0_vpeconf0()             __read_32bit_c0_register($1, 2)
  36  #define write_c0_vpeconf0(val)         __write_32bit_c0_register($1, 2, val)
  37
  38 +#define read_c0_vpeconf1()              __read_32bit_c0_register($1, 3)
  39 +#define write_c0_vpeconf1(val)          __write_32bit_c0_register($1, 3, val)
  40 +
  41 +#define read_c0_vpeschedule()           __read_32bit_c0_register($1, 5)
  42 +#define write_c0_vpeschedule(val)       __write_32bit_c0_register($1, 5, val)
  43 +
  44 +#define read_c0_vpeschefback()         __read_32bit_c0_register($1, 6)
  45 +#define write_c0_vpeschefback(val)     __write_32bit_c0_register($1, 6, val)
  46 +
  47 +#define read_c0_vpeopt()              __read_32bit_c0_register($1, 7)
  48 +#define write_c0_vpeopt(val)          __write_32bit_c0_register($1, 7, val)
  49 +
  50  #define read_c0_tcstatus()             __read_32bit_c0_register($2, 1)
  51  #define write_c0_tcstatus(val)         __write_32bit_c0_register($2, 1, val)
  52
  53  #define read_c0_tcbind()               __read_32bit_c0_register($2, 2)
  54 +#define write_c0_tcbind(val)           __write_32bit_c0_register($2, 2, val)
  55
  56  #define read_c0_tccontext()            __read_32bit_c0_register($2, 5)
  57  #define write_c0_tccontext(val)                __write_32bit_c0_register($2, 5, val)
  58
  59 +#define read_c0_tcschedule()           __read_32bit_c0_register($2, 6)
  60 +#define write_c0_tcschedule(val)       __write_32bit_c0_register($2, 6, val)
  61 +
  62 +#define read_c0_tcschefback()          __read_32bit_c0_register($2, 7)
  63 +#define write_c0_tcschefback(val)      __write_32bit_c0_register($2, 7, val)
  64 +
  65 +
  66  #else /* Assembly */
  67  /*
  68   * Macros for use in assembly language code
  69 @@ -74,6 +94,8 @@
  70  #define MVPCONTROL_STLB_SHIFT  2
  71  #define MVPCONTROL_STLB                (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
  72
  73 +#define MVPCONTROL_CPA_SHIFT   3
  74 +#define MVPCONTROL_CPA         (_ULCAST_(1) << MVPCONTROL_CPA_SHIFT)
  75
  76  /* MVPConf0 fields */
  77  #define MVPCONF0_PTC_SHIFT     0
  78 @@ -84,6 +106,8 @@
  79  #define MVPCONF0_TCA           ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
  80  #define MVPCONF0_PTLBE_SHIFT   16
  81  #define MVPCONF0_PTLBE         (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
  82 +#define MVPCONF0_PCP_SHIFT     27
  83 +#define MVPCONF0_PCP           (_ULCAST_(1) << MVPCONF0_PCP_SHIFT)
  84  #define MVPCONF0_TLBS_SHIFT    29
  85  #define MVPCONF0_TLBS          (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
  86  #define MVPCONF0_M_SHIFT       31
  87 @@ -121,9 +145,25 @@
  88  #define VPECONF0_VPA           (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
  89  #define VPECONF0_MVP_SHIFT     1
  90  #define VPECONF0_MVP           (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
  91 +#define VPECONF0_ICS_SHIFT      16
  92 +#define VPECONF0_ICS           (_ULCAST_(1) << VPECONF0_ICS_SHIFT)
  93 +#define VPECONF0_DCS_SHIFT      17
  94 +#define VPECONF0_DCS            (_ULCAST_(1) << VPECONF0_DCS_SHIFT)
  95  #define VPECONF0_XTC_SHIFT     21
  96  #define VPECONF0_XTC           (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
  97
  98 +/* VPEOpt fields */
  99 +#define VPEOPT_DWX_SHIFT       0
 100 +#define VPEOPT_IWX_SHIFT       8
 101 +#define VPEOPT_IWX0            ( _ULCAST_(0x1) << VPEOPT_IWX_SHIFT)
 102 +#define VPEOPT_IWX1            ( _ULCAST_(0x2) << VPEOPT_IWX_SHIFT)
 103 +#define VPEOPT_IWX2            ( _ULCAST_(0x4) << VPEOPT_IWX_SHIFT)
 104 +#define VPEOPT_IWX3            ( _ULCAST_(0x8) << VPEOPT_IWX_SHIFT)
 105 +#define VPEOPT_DWX0            ( _ULCAST_(0x1) << VPEOPT_DWX_SHIFT)
 106 +#define VPEOPT_DWX1            ( _ULCAST_(0x2) << VPEOPT_DWX_SHIFT)
 107 +#define VPEOPT_DWX2            ( _ULCAST_(0x4) << VPEOPT_DWX_SHIFT)
 108 +#define VPEOPT_DWX3            ( _ULCAST_(0x8) << VPEOPT_DWX_SHIFT)
 109 +
 110  /* TCStatus fields (per TC) */
 111  #define TCSTATUS_TASID         (_ULCAST_(0xff))
 112  #define TCSTATUS_IXMT_SHIFT    10
 113 @@ -350,6 +390,14 @@ do {                                                                       \
 114  #define write_vpe_c0_vpecontrol(val)   mttc0(1, 1, val)
 115  #define read_vpe_c0_vpeconf0()         mftc0(1, 2)
 116  #define write_vpe_c0_vpeconf0(val)     mttc0(1, 2, val)
 117 +#define read_vpe_c0_vpeschedule()      mftc0(1, 5)
 118 +#define write_vpe_c0_vpeschedule(val)  mttc0(1, 5, val)
 119 +#define read_vpe_c0_vpeschefback()     mftc0(1, 6)
 120 +#define write_vpe_c0_vpeschefback(val) mttc0(1, 6, val)
 121 +#define read_vpe_c0_vpeopt()            mftc0(1, 7)
 122 +#define write_vpe_c0_vpeopt(val)        mttc0(1, 7, val)
 123 +#define read_vpe_c0_wired()            mftc0(6, 0)
 124 +#define write_vpe_c0_wired(val)                mttc0(6, 0, val)
 125  #define read_vpe_c0_count()            mftc0(9, 0)
 126  #define write_vpe_c0_count(val)                mttc0(9, 0, val)
 127  #define read_vpe_c0_status()           mftc0(12, 0)
 128 @@ -381,6 +429,12 @@ do {                                                                       \
 129  #define write_tc_c0_tchalt(val)                mttc0(2, 4, val)
 130  #define read_tc_c0_tccontext()         mftc0(2, 5)
 131  #define write_tc_c0_tccontext(val)     mttc0(2, 5, val)
 132 +#define read_tc_c0_tcschedule()                mftc0(2, 6)
 133 +#define write_tc_c0_tcschedule(val)    mttc0(2, 6, val)
 134 +#define read_tc_c0_tcschefback()       mftc0(2, 7)
 135 +#define write_tc_c0_tcschefback(val)   mttc0(2, 7, val)
 136 +#define read_tc_c0_entryhi()            mftc0(10, 0)
 137 +#define write_tc_c0_entryhi(val)        mttc0(10, 0, val)
 138
 139  /* GPR */
 140  #define read_tc_gpr_sp()               mftgpr(29)
 141 --- a/arch/mips/kernel/Makefile
 142 +++ b/arch/mips/kernel/Makefile
 143 @@ -84,7 +84,8 @@ obj-$(CONFIG_MIPS32_O32)      += binfmt_elfo3
 144
 145  obj-$(CONFIG_KGDB)             += kgdb.o
 146  obj-$(CONFIG_PROC_FS)          += proc.o
 147 -
 148 +obj-$(CONFIG_MTSCHED)          += mtsched_proc.o
 149 +obj-$(CONFIG_PERFCTRS)         += perf_proc.o
 150  obj-$(CONFIG_64BIT)            += cpu-bugs64.o
 151
 152  obj-$(CONFIG_I8253)            += i8253.o
 153 --- a/arch/mips/kernel/mips-mt.c
 154 +++ b/arch/mips/kernel/mips-mt.c
 155 @@ -21,26 +21,95 @@
 156  #include <asm/cacheflush.h>
 157
 158  int vpelimit;
 159 -
 160  static int __init maxvpes(char *str)
 161  {
 162         get_option(&str, &vpelimit);
 163 -
 164         return 1;
 165  }
 166 -
 167  __setup("maxvpes=", maxvpes);
 168
 169  int tclimit;
 170 -
 171  static int __init maxtcs(char *str)
 172  {
 173         get_option(&str, &tclimit);
 174 +       return 1;
 175 +}
 176 +__setup("maxtcs=", maxtcs);
 177
 178 +#ifdef CONFIG_IFX_VPE_EXT
 179 +int stlb;
 180 +static int __init istlbshared(char *str)
 181 +{
 182 +       get_option(&str, &stlb);
 183         return 1;
 184  }
 185 +__setup("vpe_tlb_shared=", istlbshared);
 186
 187 -__setup("maxtcs=", maxtcs);
 188 +int vpe0_wired;
 189 +static int __init vpe0wired(char *str)
 190 +{
 191 +       get_option(&str, &vpe0_wired);
 192 +       return 1;
 193 +}
 194 +__setup("vpe0_wired_tlb_entries=", vpe0wired);
 195 +
 196 +int vpe1_wired;
 197 +static int __init vpe1wired(char *str)
 198 +{
 199 +       get_option(&str, &vpe1_wired);
 200 +       return 1;
 201 +}
 202 +__setup("vpe1_wired_tlb_entries=", vpe1wired);
 203 +
 204 +#ifdef CONFIG_MIPS_MT_SMTC
 205 +extern int nostlb;
 206 +#endif
 207 +void configure_tlb(void)
 208 +{
 209 +       int vpeflags, tcflags, tlbsiz;
 210 +       unsigned int config1val;
 211 +       vpeflags = dvpe();
 212 +       tcflags = dmt();
 213 +       write_c0_vpeconf0((read_c0_vpeconf0() | VPECONF0_MVP));
 214 +       write_c0_mvpcontrol((read_c0_mvpcontrol() | MVPCONTROL_VPC));
 215 +       mips_ihb();
 216 +       //printk("stlb = %d, vpe0_wired = %d vpe1_wired=%d\n", stlb,vpe0_wired, vpe1_wired);
 217 +       if (stlb) {
 218 +               if (!(read_c0_mvpconf0() & MVPCONF0_TLBS)) {
 219 +                       emt(tcflags);
 220 +                       evpe(vpeflags);
 221 +                       return;
 222 +               }
 223 +
 224 +               write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB);
 225 +               write_c0_wired(vpe0_wired + vpe1_wired);
 226 +               if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) {
 227 +                       config1val = read_vpe_c0_config1();
 228 +                       tlbsiz = (((config1val >> 25) & 0x3f) + 1);
 229 +                       if (tlbsiz > 64)
 230 +                               tlbsiz = 64;
 231 +                       cpu_data[0].tlbsize = current_cpu_data.tlbsize = tlbsiz;
 232 +               }
 233 +
 234 +       }
 235 +       else {
 236 +               write_c0_mvpcontrol(read_c0_mvpcontrol() & ~MVPCONTROL_STLB);
 237 +               write_c0_wired(vpe0_wired);
 238 +       }
 239 +
 240 +       ehb();
 241 +       write_c0_mvpcontrol((read_c0_mvpcontrol() & ~MVPCONTROL_VPC));
 242 +       ehb();
 243 +       local_flush_tlb_all();
 244 +
 245 +       printk("Wired TLB entries for Linux read_c0_wired() = %d\n", read_c0_wired());
 246 +#ifdef CONFIG_MIPS_MT_SMTC
 247 +       nostlb = !stlb;
 248 +#endif
 249 +       emt(tcflags);
 250 +       evpe(vpeflags);
 251 +}
 252 +#endif
 253
 254  /*
 255   * Dump new MIPS MT state for the core. Does not leave TCs halted.
 256 @@ -78,18 +147,18 @@ void mips_mt_regdump(unsigned long mvpct
 257                         if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
 258                                 printk("  VPE %d\n", i);
 259                                 printk("   VPEControl : %08lx\n",
 260 -                                      read_vpe_c0_vpecontrol());
 261 +                                       read_vpe_c0_vpecontrol());
 262                                 printk("   VPEConf0 : %08lx\n",
 263 -                                      read_vpe_c0_vpeconf0());
 264 +                                       read_vpe_c0_vpeconf0());
 265                                 printk("   VPE%d.Status : %08lx\n",
 266 -                                      i, read_vpe_c0_status());
 267 +                                       i, read_vpe_c0_status());
 268                                 printk("   VPE%d.EPC : %08lx %pS\n",
 269 -                                      i, read_vpe_c0_epc(),
 270 -                                      (void *) read_vpe_c0_epc());
 271 +                                       i, read_vpe_c0_epc(),
 272 +                                       (void *) read_vpe_c0_epc());
 273                                 printk("   VPE%d.Cause : %08lx\n",
 274 -                                      i, read_vpe_c0_cause());
 275 +                                       i, read_vpe_c0_cause());
 276                                 printk("   VPE%d.Config7 : %08lx\n",
 277 -                                      i, read_vpe_c0_config7());
 278 +                                       i, read_vpe_c0_config7());
 279                                 break; /* Next VPE */
 280                         }
 281                 }
 282 @@ -287,6 +356,9 @@ void mips_mt_set_cpuoptions(void)
 283                 printk("Mapped %ld ITC cells starting at 0x%08x\n",
 284                         ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
 285         }
 286 +#ifdef CONFIG_IFX_VPE_EXT
 287 +       configure_tlb();
 288 +#endif
 289  }
 290
 291  /*
 292 --- a/arch/mips/kernel/proc.c
 293 +++ b/arch/mips/kernel/proc.c
 294 @@ -7,6 +7,7 @@
 295  #include <linux/kernel.h>
 296  #include <linux/sched.h>
 297  #include <linux/seq_file.h>
 298 +#include <linux/proc_fs.h>
 299  #include <asm/bootinfo.h>
 300  #include <asm/cpu.h>
 301  #include <asm/cpu-features.h>
 302 @@ -108,3 +109,19 @@ const struct seq_operations cpuinfo_op =
 303         .stop   = c_stop,
 304         .show   = show_cpuinfo,
 305  };
 306 +
 307 +/*
 308 + * Support for MIPS/local /proc hooks in /proc/mips/
 309 + */
 310 +
 311 +static struct proc_dir_entry *mips_proc = NULL;
 312 +
 313 +struct proc_dir_entry *get_mips_proc_dir(void)
 314 +{
 315 +       /*
 316 +        * This ought not to be preemptable.
 317 +        */
 318 +       if(mips_proc == NULL)
 319 +               mips_proc = proc_mkdir("mips", NULL);
 320 +       return(mips_proc);
 321 +}
 322 --- a/arch/mips/kernel/smtc.c
 323 +++ b/arch/mips/kernel/smtc.c
 324 @@ -1335,6 +1335,13 @@ void smtc_get_new_mmu_context(struct mm_
 325         asid = asid_cache(cpu);
 326
 327         do {
 328 +#ifdef CONFIG_IFX_VPE_EXT
 329 +               /* If TLB is shared between AP and RP (AP is running SMTC),
 330 +                  leave out max ASID i.e., ASID_MASK for RP
 331 +                */
 332 +               if (!nostlb && ((asid & ASID_MASK) == (ASID_MASK - 1)))
 333 +                       asid++;
 334 +#endif
 335                 if (!((asid += ASID_INC) & ASID_MASK) ) {
 336                         if (cpu_has_vtag_icache)
 337                                 flush_icache_all();
 338 --- a/arch/mips/kernel/vpe.c
 339 +++ b/arch/mips/kernel/vpe.c
 340 @@ -77,6 +77,58 @@ static struct kspd_notifications kspd_ev
 341  static int kspd_events_reqd;
 342  #endif
 343
 344 +#ifdef CONFIG_IFX_VPE_EXT
 345 +static int is_sdepgm;
 346 +extern int stlb;
 347 +extern int vpe0_wired;
 348 +extern int vpe1_wired;
 349 +unsigned int vpe1_load_addr;
 350 +
 351 +static int __init load_address(char *str)
 352 +{
 353 +       get_option(&str, &vpe1_load_addr);
 354 +       return 1;
 355 +}
 356 +__setup("vpe1_load_addr=", load_address);
 357 +
 358 +#include <asm/mipsmtregs.h>
 359 +#define write_vpe_c0_wired(val)                mttc0(6, 0, val)
 360 +
 361 +#ifndef COMMAND_LINE_SIZE
 362 +#      define COMMAND_LINE_SIZE        512
 363 +#endif
 364 +
 365 +char command_line[COMMAND_LINE_SIZE * 2];
 366 +
 367 +static unsigned int vpe1_mem;
 368 +static int __init vpe1mem(char *str)
 369 +{
 370 +       vpe1_mem = memparse(str, &str);
 371 +       return 1;
 372 +}
 373 +__setup("vpe1_mem=", vpe1mem);
 374 +
 375 +uint32_t vpe1_wdog_ctr;
 376 +static int __init wdog_ctr(char *str)
 377 +{
 378 +       get_option(&str, &vpe1_wdog_ctr);
 379 +       return 1;
 380 +}
 381 +
 382 +__setup("vpe1_wdog_ctr_addr=", wdog_ctr);
 383 +EXPORT_SYMBOL(vpe1_wdog_ctr);
 384 +
 385 +uint32_t vpe1_wdog_timeout;
 386 +static int __init wdog_timeout(char *str)
 387 +{
 388 +        get_option(&str, &vpe1_wdog_timeout);
 389 +        return 1;
 390 +}
 391 +
 392 +__setup("vpe1_wdog_timeout=", wdog_timeout);
 393 +EXPORT_SYMBOL(vpe1_wdog_timeout);
 394 +
 395 +#endif
 396  /* grab the likely amount of memory we will need. */
 397  #ifdef CONFIG_MIPS_VPE_LOADER_TOM
 398  #define P_SIZE (2 * 1024 * 1024)
 399 @@ -269,6 +321,13 @@ static void *alloc_progmem(unsigned long
 400         void *addr;
 401
 402  #ifdef CONFIG_MIPS_VPE_LOADER_TOM
 403 +#ifdef CONFIG_IFX_VPE_EXT
 404 +       if (vpe1_load_addr) {
 405 +               memset((void *)vpe1_load_addr, 0, len);
 406 +               return (void *)vpe1_load_addr;
 407 +       }
 408 +#endif
 409 +
 410         /*
 411          * This means you must tell Linux to use less memory than you
 412          * physically have, for example by passing a mem= boot argument.
 413 @@ -747,6 +806,12 @@ static int vpe_run(struct vpe * v)
 414         }
 415
 416         /* Write the address we want it to start running from in the TCPC register. */
 417 +#if defined(CONFIG_IFX_VPE_EXT) && 0
 418 +       if (stlb)
 419 +               write_vpe_c0_wired(vpe0_wired + vpe1_wired);
 420 +       else
 421 +               write_vpe_c0_wired(vpe1_wired);
 422 +#endif
 423         write_tc_c0_tcrestart((unsigned long)v->__start);
 424         write_tc_c0_tccontext((unsigned long)0);
 425
 426 @@ -760,6 +825,20 @@ static int vpe_run(struct vpe * v)
 427
 428         write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
 429
 430 +#if defined(CONFIG_IFX_VPE_EXT) && 0
 431 +       /*
 432 +        * $a2 & $a3 are used to pass command line parameters to VPE1. $a2
 433 +        * points to the start of the command line string and $a3 points to
 434 +        * the end of the string. This convention is identical to the Linux
 435 +        * kernel boot parameter passing mechanism. Please note that $a3 is
 436 +        * used to pass physical memory size or 0 in SDE tool kit. So, if you
 437 +        * are passing comand line parameters through $a2 & $a3 SDE programs
 438 +        * don't work as desired.
 439 +        */
 440 +       mttgpr(6, command_line);
 441 +       mttgpr(7, (command_line + strlen(command_line)));
 442 +       if (is_sdepgm)
 443 +#endif
 444         /*
 445          * The sde-kit passes 'memsize' to __start in $a3, so set something
 446          * here...  Or set $a3 to zero and define DFLT_STACK_SIZE and
 447 @@ -834,6 +913,9 @@ static int find_vpe_symbols(struct vpe *
 448         if ( (v->__start == 0) || (v->shared_ptr == NULL))
 449                 return -1;
 450
 451 +#ifdef CONFIG_IFX_VPE_EXT
 452 +       is_sdepgm = 1;
 453 +#endif
 454         return 0;
 455  }
 456
 457 @@ -995,6 +1077,15 @@ static int vpe_elfload(struct vpe * v)
 458                            (unsigned long)v->load_addr + v->len);
 459
 460         if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) {
 461 +#ifdef CONFIG_IFX_VPE_EXT
 462 +               if (vpe1_load_addr) {
 463 +                       /* Conversion to KSEG1 is required ??? */
 464 +                       v->__start = KSEG1ADDR(vpe1_load_addr);
 465 +                       is_sdepgm = 0;
 466 +                       return 0;
 467 +               }
 468 +#endif
 469 +
 470                 if (v->__start == 0) {
 471                         printk(KERN_WARNING "VPE loader: program does not contain "
 472                                "a __start symbol\n");
 473 @@ -1065,6 +1156,9 @@ static int vpe_open(struct inode *inode,
 474         struct vpe_notifications *not;
 475         struct vpe *v;
 476         int ret;
 477 +#ifdef CONFIG_IFX_VPE_EXT
 478 +   int progsize;
 479 +#endif
 480
 481         if (minor != iminor(inode)) {
 482                 /* assume only 1 device at the moment. */
 483 @@ -1091,14 +1185,23 @@ static int vpe_open(struct inode *inode,
 484                 cleanup_tc(get_tc(tclimit));
 485         }
 486
 487 +#ifdef CONFIG_IFX_VPE_EXT
 488 +       progsize = (vpe1_mem  != 0) ? vpe1_mem : P_SIZE;
 489 +       //printk("progsize = %x\n", progsize);
 490 +       v->pbuffer = vmalloc(progsize);
 491 +       v->plen = progsize;
 492 +#else
 493         /* this of-course trashes what was there before... */
 494         v->pbuffer = vmalloc(P_SIZE);
 495         v->plen = P_SIZE;
 496 +#endif
 497         v->load_addr = NULL;
 498         v->len = 0;
 499
 500 +#if 0
 501         v->uid = filp->f_cred->fsuid;
 502         v->gid = filp->f_cred->fsgid;
 503 +#endif
 504
 505  #ifdef CONFIG_MIPS_APSP_KSPD
 506         /* get kspd to tell us when a syscall_exit happens */
 507 @@ -1351,6 +1454,133 @@ static void kspd_sp_exit( int sp_id)
 508         cleanup_tc(get_tc(sp_id));
 509  }
 510  #endif
 511 +#ifdef CONFIG_IFX_VPE_EXT
 512 +int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags)
 513 +{
 514 +       enum vpe_state state;
 515 +       struct vpe *v = get_vpe(tclimit);
 516 +       struct vpe_notifications *not;
 517 +
 518 +       if (tcmask || flags) {
 519 +               printk(KERN_WARNING "Currently tcmask and flags should be 0.\
 520 +                               other values not supported\n");
 521 +               return -1;
 522 +       }
 523 +
 524 +       state = xchg(&v->state, VPE_STATE_INUSE);
 525 +       if (state != VPE_STATE_UNUSED) {
 526 +               vpe_stop(v);
 527 +
 528 +               list_for_each_entry(not, &v->notify, list) {
 529 +                       not->stop(tclimit);
 530 +               }
 531 +       }
 532 +
 533 +       v->__start = (unsigned long)sw_start_addr;
 534 +       is_sdepgm = 0;
 535 +
 536 +       if (!vpe_run(v)) {
 537 +               printk(KERN_DEBUG "VPE loader: VPE1 running successfully\n");
 538 +               return 0;
 539 +       }
 540 +       return -1;
 541 +}
 542 +
 543 +EXPORT_SYMBOL(vpe1_sw_start);
 544 +
 545 +int32_t vpe1_sw_stop(uint32_t flags)
 546 +{
 547 +       struct vpe *v = get_vpe(tclimit);
 548 +
 549 +       if (!vpe_free(v)) {
 550 +               printk(KERN_DEBUG "RP Stopped\n");
 551 +               return 0;
 552 +       }
 553 +       else
 554 +               return -1;
 555 +}
 556 +
 557 +EXPORT_SYMBOL(vpe1_sw_stop);
 558 +
 559 +uint32_t vpe1_get_load_addr (uint32_t flags)
 560 +{
 561 +       return vpe1_load_addr;
 562 +}
 563 +
 564 +EXPORT_SYMBOL(vpe1_get_load_addr);
 565 +
 566 +uint32_t vpe1_get_max_mem (uint32_t flags)
 567 +{
 568 +       if (!vpe1_mem)
 569 +               return P_SIZE;
 570 +       else
 571 +               return vpe1_mem;
 572 +}
 573 +
 574 +EXPORT_SYMBOL(vpe1_get_max_mem);
 575 +
 576 +void* vpe1_get_cmdline_argument(void)
 577 +{
 578 +       return saved_command_line;
 579 +}
 580 +
 581 +EXPORT_SYMBOL(vpe1_get_cmdline_argument);
 582 +
 583 +int32_t vpe1_set_boot_param(char *field, char *value, char flags)
 584 +{
 585 +       char *ptr, string[64];
 586 +       int start_off, end_off;
 587 +       if (!field)
 588 +               return -1;
 589 +       strcpy(string, field);
 590 +       if (value) {
 591 +               strcat(string, "=");
 592 +               strcat(string, value);
 593 +               strcat(command_line, " ");
 594 +               strcat(command_line, string);
 595 +       }
 596 +       else {
 597 +               ptr = strstr(command_line, string);
 598 +               if (ptr) {
 599 +                       start_off = ptr - command_line;
 600 +                       ptr += strlen(string);
 601 +                       while ((*ptr != ' ') && (*ptr != '\0'))
 602 +                               ptr++;
 603 +                       end_off = ptr - command_line;
 604 +                       command_line[start_off] = '\0';
 605 +                       strcat (command_line, command_line+end_off);
 606 +               }
 607 +       }
 608 +       return 0;
 609 +}
 610 +
 611 +EXPORT_SYMBOL(vpe1_set_boot_param);
 612 +
 613 +int32_t vpe1_get_boot_param(char *field, char **value, char flags)
 614 +{
 615 +       char *ptr, string[64];
 616 +       int i = 0;
 617 +       if (!field)
 618 +               return -1;
 619 +       if ((ptr = strstr(command_line, field))) {
 620 +               ptr += strlen(field) + 1; /* including = */
 621 +               while ((*ptr != ' ') && (*ptr != '\0'))
 622 +                       string[i++] = *ptr++;
 623 +               string[i] = '\0';
 624 +               *value = kmalloc((strlen(string) + 1), GFP_KERNEL);
 625 +               if (*value != NULL)
 626 +                       strcpy(*value, string);
 627 +       }
 628 +       else
 629 +               *value = NULL;
 630 +
 631 +       return 0;
 632 +}
 633 +
 634 +EXPORT_SYMBOL(vpe1_get_boot_param);
 635 +
 636 +extern void configure_tlb(void);
 637 +#endif
 638
 639  static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
 640                           const char *buf, size_t len)
 641 @@ -1432,6 +1662,18 @@ static int __init vpe_module_init(void)
 642                 printk("VPE loader: not a MIPS MT capable processor\n");
 643                 return -ENODEV;
 644         }
 645 +#ifdef CONFIG_IFX_VPE_EXT
 646 +#ifndef CONFIG_MIPS_MT_SMTC
 647 +       configure_tlb();
 648 +#endif
 649 +#endif
 650 +
 651 +#ifndef CONFIG_MIPS_MT_SMTC
 652 +       if (!vpelimit)
 653 +               vpelimit = 1;
 654 +       if (!tclimit)
 655 +               tclimit = 1;
 656 +#endif
 657
 658         if (vpelimit == 0) {
 659                 printk(KERN_WARNING "No VPEs reserved for AP/SP, not "
 660 @@ -1476,10 +1718,12 @@ static int __init vpe_module_init(void)
 661         mtflags = dmt();
 662         vpflags = dvpe();
 663
 664 +       back_to_back_c0_hazard();
 665 +
 666         /* Put MVPE's into 'configuration state' */
 667         set_c0_mvpcontrol(MVPCONTROL_VPC);
 668
 669 -       /* dump_mtregs(); */
 670 +       dump_mtregs();
 671
 672         val = read_c0_mvpconf0();
 673         hw_tcs = (val & MVPCONF0_PTC) + 1;
 674 @@ -1491,6 +1735,7 @@ static int __init vpe_module_init(void)
 675                  * reschedule send IPIs or similar we might hang.
 676                  */
 677                 clear_c0_mvpcontrol(MVPCONTROL_VPC);
 678 +               back_to_back_c0_hazard();
 679                 evpe(vpflags);
 680                 emt(mtflags);
 681                 local_irq_restore(flags);
 682 @@ -1516,6 +1761,7 @@ static int __init vpe_module_init(void)
 683                         }
 684
 685                         v->ntcs = hw_tcs - tclimit;
 686 +                        write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1);
 687
 688                         /* add the tc to the list of this vpe's tc's. */
 689                         list_add(&t->tc, &v->tc);
 690 @@ -1584,6 +1830,7 @@ static int __init vpe_module_init(void)
 691  out_reenable:
 692         /* release config state */
 693         clear_c0_mvpcontrol(MVPCONTROL_VPC);
 694 +       back_to_back_c0_hazard();
 695
 696         evpe(vpflags);
 697         emt(mtflags);
 698 --- /dev/null
 699 +++ b/arch/mips/kernel/mtsched_proc.c
 700 @@ -0,0 +1,279 @@
 701 +/*
 702 + * /proc hooks for MIPS MT scheduling policy management for 34K cores
 703 + *
 704 + *  This program is free software; you can distribute it and/or modify it
 705 + *  under the terms of the GNU General Public License (Version 2) as
 706 + *  published by the Free Software Foundation.
 707 + *
 708 + *  This program is distributed in the hope it will be useful, but WITHOUT
 709 + *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 710 + *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 711 + *  for more details.
 712 + *
 713 + *  You should have received a copy of the GNU General Public License along
 714 + *  with this program; if not, write to the Free Software Foundation, Inc.,
 715 + *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
 716 + *
 717 + * Copyright (C) 2006 Mips Technologies, Inc
 718 + */
 719 +
 720 +#include <linux/kernel.h>
 721 +
 722 +#include <asm/cpu.h>
 723 +#include <asm/processor.h>
 724 +#include <asm/system.h>
 725 +#include <asm/mipsregs.h>
 726 +#include <asm/mipsmtregs.h>
 727 +#include <asm/uaccess.h>
 728 +#include <linux/proc_fs.h>
 729 +
 730 +static struct proc_dir_entry *mtsched_proc;
 731 +
 732 +#ifndef CONFIG_MIPS_MT_SMTC
 733 +#define NTCS 2
 734 +#else
 735 +#define NTCS NR_CPUS
 736 +#endif
 737 +#define NVPES 2
 738 +
 739 +int lastvpe = 1;
 740 +int lasttc = 8;
 741 +
 742 +static int proc_read_mtsched(char *page, char **start, off_t off,
 743 +                       int count, int *eof, void *data)
 744 +{
 745 +       int totalen = 0;
 746 +       int len;
 747 +
 748 +       int i;
 749 +       int vpe;
 750 +       int mytc;
 751 +       unsigned long flags;
 752 +       unsigned int mtflags;
 753 +       unsigned int haltstate;
 754 +       unsigned int vpes_checked[NVPES];
 755 +       unsigned int vpeschedule[NVPES];
 756 +       unsigned int vpeschefback[NVPES];
 757 +       unsigned int tcschedule[NTCS];
 758 +       unsigned int tcschefback[NTCS];
 759 +
 760 +       /* Dump the state of the MIPS MT scheduling policy manager */
 761 +       /* Inititalize control state */
 762 +       for(i = 0; i < NVPES; i++) {
 763 +               vpes_checked[i] = 0;
 764 +               vpeschedule[i] = 0;
 765 +               vpeschefback[i] = 0;
 766 +       }
 767 +       for(i = 0; i < NTCS; i++) {
 768 +               tcschedule[i] = 0;
 769 +               tcschefback[i] = 0;
 770 +       }
 771 +
 772 +       /* Disable interrupts and multithreaded issue */
 773 +       local_irq_save(flags);
 774 +       mtflags = dvpe();
 775 +
 776 +       /* Then go through the TCs, halt 'em, and extract the values */
 777 +       mytc = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
 778 +       for(i = 0; i < NTCS; i++) {
 779 +               if(i == mytc) {
 780 +                       /* No need to halt ourselves! */
 781 +                       tcschedule[i] = read_c0_tcschedule();
 782 +                       tcschefback[i] = read_c0_tcschefback();
 783 +                       /* If VPE bound to TC hasn't been checked, do it */
 784 +                       vpe = read_c0_tcbind() & TCBIND_CURVPE;
 785 +                       if(!vpes_checked[vpe]) {
 786 +                               vpeschedule[vpe] = read_c0_vpeschedule();
 787 +                               vpeschefback[vpe] = read_c0_vpeschefback();
 788 +                               vpes_checked[vpe] = 1;
 789 +                       }
 790 +               } else {
 791 +                       settc(i);
 792 +                       haltstate = read_tc_c0_tchalt();
 793 +                       write_tc_c0_tchalt(TCHALT_H);
 794 +                       mips_ihb();
 795 +                       tcschedule[i] = read_tc_c0_tcschedule();
 796 +                       tcschefback[i] = read_tc_c0_tcschefback();
 797 +                       /* If VPE bound to TC hasn't been checked, do it */
 798 +                       vpe = read_tc_c0_tcbind() & TCBIND_CURVPE;
 799 +                       if(!vpes_checked[vpe]) {
 800 +                           vpeschedule[vpe] = read_vpe_c0_vpeschedule();
 801 +                           vpeschefback[vpe] = read_vpe_c0_vpeschefback();
 802 +                           vpes_checked[vpe] = 1;
 803 +                       }
 804 +                       if(!haltstate) write_tc_c0_tchalt(0);
 805 +               }
 806 +       }
 807 +       /* Re-enable MT and interrupts */
 808 +       evpe(mtflags);
 809 +       local_irq_restore(flags);
 810 +
 811 +       for(vpe=0; vpe < NVPES; vpe++) {
 812 +               len = sprintf(page, "VPE[%d].VPEschedule  = 0x%08x\n",
 813 +                       vpe, vpeschedule[vpe]);
 814 +               totalen += len;
 815 +               page += len;
 816 +               len = sprintf(page, "VPE[%d].VPEschefback = 0x%08x\n",
 817 +                       vpe, vpeschefback[vpe]);
 818 +               totalen += len;
 819 +               page += len;
 820 +       }
 821 +       for(i=0; i < NTCS; i++) {
 822 +               len = sprintf(page, "TC[%d].TCschedule    = 0x%08x\n",
 823 +                       i, tcschedule[i]);
 824 +               totalen += len;
 825 +               page += len;
 826 +               len = sprintf(page, "TC[%d].TCschefback   = 0x%08x\n",
 827 +                       i, tcschefback[i]);
 828 +               totalen += len;
 829 +               page += len;
 830 +       }
 831 +       return totalen;
 832 +}
 833 +
 834 +/*
 835 + * Write to perf counter registers based on text input
 836 + */
 837 +
 838 +#define TXTBUFSZ 1024
 839 +
 840 +static int proc_write_mtsched(struct file *file, const char *buffer,
 841 +                               unsigned long count, void *data)
 842 +{
 843 +       int len = 0;
 844 +       char mybuf[TXTBUFSZ];
 845 +       /* At most, we will set up 9 TCs and 2 VPEs, 11 entries in all */
 846 +       char entity[1];   //, entity1[1];
 847 +       int number[1];
 848 +       unsigned long value[1];
 849 +       int nparsed = 0 , index = 0;
 850 +       unsigned long flags;
 851 +       unsigned int mtflags;
 852 +       unsigned int haltstate;
 853 +       unsigned int tcbindval;
 854 +
 855 +       if(count >= TXTBUFSZ) len = TXTBUFSZ-1;
 856 +       else len = count;
 857 +       memset(mybuf,0,TXTBUFSZ);
 858 +       if(copy_from_user(mybuf, buffer, len)) return -EFAULT;
 859 +
 860 +       nparsed = sscanf(mybuf, "%c%d %lx",
 861 +                &entity[0] ,&number[0], &value[0]);
 862 +
 863 +       /*
 864 +        * Having acquired the inputs, which might have
 865 +        * generated exceptions and preemptions,
 866 +        * program the registers.
 867 +        */
 868 +       /* Disable interrupts and multithreaded issue */
 869 +       local_irq_save(flags);
 870 +       mtflags = dvpe();
 871 +
 872 +       if(entity[index] == 't' ) {
 873 +               /* Set TCSchedule or TCScheFBack of specified TC */
 874 +               if(number[index] > NTCS) goto skip;
 875 +               /* If it's our own TC, do it direct */
 876 +               if(number[index] ==
 877 +                               ((read_c0_tcbind() & TCBIND_CURTC)
 878 +                               >> TCBIND_CURTC_SHIFT)) {
 879 +                       if(entity[index] == 't')
 880 +                                write_c0_tcschedule(value[index]);
 881 +                       else
 882 +                               write_c0_tcschefback(value[index]);
 883 +               } else {
 884 +               /* Otherwise, we do it via MTTR */
 885 +                       settc(number[index]);
 886 +                       haltstate = read_tc_c0_tchalt();
 887 +                       write_tc_c0_tchalt(TCHALT_H);
 888 +                       mips_ihb();
 889 +                       if(entity[index] == 't')
 890 +                                write_tc_c0_tcschedule(value[index]);
 891 +                       else
 892 +                               write_tc_c0_tcschefback(value[index]);
 893 +                       mips_ihb();
 894 +                       if(!haltstate) write_tc_c0_tchalt(0);
 895 +               }
 896 +       } else if(entity[index] == 'v') {
 897 +               /* Set VPESchedule of specified VPE */
 898 +               if(number[index] > NVPES) goto skip;
 899 +               tcbindval = read_c0_tcbind();
 900 +               /* Are we doing this to our current VPE? */
 901 +               if((tcbindval & TCBIND_CURVPE) == number[index]) {
 902 +                       /* Then life is simple */
 903 +                       write_c0_vpeschedule(value[index]);
 904 +               } else {
 905 +                       /*
 906 +                        * Bind ourselves to the other VPE long enough
 907 +                        * to program the bind value.
 908 +                        */
 909 +                       write_c0_tcbind((tcbindval & ~TCBIND_CURVPE)
 910 +                                          | number[index]);
 911 +                       mips_ihb();
 912 +                       write_c0_vpeschedule(value[index]);
 913 +                       mips_ihb();
 914 +                       /* Restore previous binding */
 915 +                       write_c0_tcbind(tcbindval);
 916 +                       mips_ihb();
 917 +               }
 918 +       }
 919 +
 920 +       else if(entity[index] == 'r') {
 921 +               unsigned int vpes_checked[2], vpe ,i , mytc;
 922 +               vpes_checked[0] = vpes_checked[1] = 0;
 923 +
 924 +               /* Then go through the TCs, halt 'em, and extract the values */
 925 +               mytc = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
 926 +
 927 +               for(i = 0; i < NTCS; i++) {
 928 +                       if(i == mytc) {
 929 +                               /* No need to halt ourselves! */
 930 +                               write_c0_vpeschefback(0);
 931 +                               write_c0_tcschefback(0);
 932 +                       } else {
 933 +                               settc(i);
 934 +                               haltstate = read_tc_c0_tchalt();
 935 +                               write_tc_c0_tchalt(TCHALT_H);
 936 +                               mips_ihb();
 937 +                               write_tc_c0_tcschefback(0);
 938 +                               /* If VPE bound to TC hasn't been checked, do it */
 939 +                               vpe = read_tc_c0_tcbind() & TCBIND_CURVPE;
 940 +                               if(!vpes_checked[vpe]) {
 941 +                                   write_vpe_c0_vpeschefback(0);
 942 +                                   vpes_checked[vpe] = 1;
 943 +                               }
 944 +                               if(!haltstate) write_tc_c0_tchalt(0);
 945 +                       }
 946 +               }
 947 +       }
 948 +       else {
 949 +               printk ("\n Usage : <t/v><0/1> <Hex Value>\n Example : t0 0x01\n");
 950 +       }
 951 +
 952 +skip:
 953 +       /* Re-enable MT and interrupts */
 954 +       evpe(mtflags);
 955 +       local_irq_restore(flags);
 956 +       return (len);
 957 +}
 958 +
 959 +static int __init init_mtsched_proc(void)
 960 +{
 961 +       extern struct proc_dir_entry *get_mips_proc_dir(void);
 962 +       struct proc_dir_entry *mips_proc_dir;
 963 +
 964 +       if (!cpu_has_mipsmt) {
 965 +               printk("mtsched: not a MIPS MT capable processor\n");
 966 +               return -ENODEV;
 967 +       }
 968 +
 969 +       mips_proc_dir = get_mips_proc_dir();
 970 +
 971 +       mtsched_proc = create_proc_entry("mtsched", 0644, mips_proc_dir);
 972 +       mtsched_proc->read_proc = proc_read_mtsched;
 973 +       mtsched_proc->write_proc = proc_write_mtsched;
 974 +
 975 +       return 0;
 976 +}
 977 +
 978 +/* Automagically create the entry */
 979 +module_init(init_mtsched_proc);
 980 --- /dev/null
 981 +++ b/arch/mips/kernel/perf_proc.c
 982 @@ -0,0 +1,191 @@
 983 +/*
 984 + * /proc hooks for CPU performance counter support for SMTC kernel
 985 + * (and ultimately others)
 986 + * Copyright (C) 2006 Mips Technologies, Inc
 987 + */
 988 +
 989 +#include <linux/kernel.h>
 990 +
 991 +#include <asm/cpu.h>
 992 +#include <asm/processor.h>
 993 +#include <asm/system.h>
 994 +#include <asm/mipsregs.h>
 995 +#include <asm/uaccess.h>
 996 +#include <linux/proc_fs.h>
 997 +
 998 +/*
 999 + * /proc diagnostic and statistics hooks
1000 + */
1001 +
1002 +
1003 +/* Internal software-extended event counters */
1004 +
1005 +static unsigned long long extencount[4] = {0,0,0,0};
1006 +
1007 +static struct proc_dir_entry *perf_proc;
1008 +
1009 +static int proc_read_perf(char *page, char **start, off_t off,
1010 +                               int count, int *eof, void *data)
1011 +{
1012 +       int totalen = 0;
1013 +       int len;
1014 +
1015 +       len = sprintf(page, "PerfCnt[0].Ctl : 0x%08x\n", read_c0_perfctrl0());
1016 +       totalen += len;
1017 +       page += len;
1018 +       len = sprintf(page, "PerfCnt[0].Cnt : %Lu\n",
1019 +               extencount[0] + (unsigned long long)((unsigned)read_c0_perfcntr0()));
1020 +       totalen += len;
1021 +       page += len;
1022 +       len = sprintf(page, "PerfCnt[1].Ctl : 0x%08x\n", read_c0_perfctrl1());
1023 +       totalen += len;
1024 +       page += len;
1025 +       len = sprintf(page, "PerfCnt[1].Cnt : %Lu\n",
1026 +               extencount[1] + (unsigned long long)((unsigned)read_c0_perfcntr1()));
1027 +       totalen += len;
1028 +       page += len;
1029 +       len = sprintf(page, "PerfCnt[2].Ctl : 0x%08x\n", read_c0_perfctrl2());
1030 +       totalen += len;
1031 +       page += len;
1032 +       len = sprintf(page, "PerfCnt[2].Cnt : %Lu\n",
1033 +               extencount[2] + (unsigned long long)((unsigned)read_c0_perfcntr2()));
1034 +       totalen += len;
1035 +       page += len;
1036 +       len = sprintf(page, "PerfCnt[3].Ctl : 0x%08x\n", read_c0_perfctrl3());
1037 +       totalen += len;
1038 +       page += len;
1039 +       len = sprintf(page, "PerfCnt[3].Cnt : %Lu\n",
1040 +               extencount[3] + (unsigned long long)((unsigned)read_c0_perfcntr3()));
1041 +       totalen += len;
1042 +       page += len;
1043 +
1044 +       return totalen;
1045 +}
1046 +
1047 +/*
1048 + * Write to perf counter registers based on text input
1049 + */
1050 +
1051 +#define TXTBUFSZ 1024
1052 +
1053 +static int proc_write_perf(struct file *file, const char *buffer,
1054 +                               unsigned long count, void *data)
1055 +{
1056 +       int len;
1057 +       int nparsed;
1058 +       int index;
1059 +       char mybuf[TXTBUFSZ];
1060 +
1061 +       int which[4];
1062 +       unsigned long control[4];
1063 +       long long ctrdata[4];
1064 +
1065 +       if(count >= TXTBUFSZ) len = TXTBUFSZ-1;
1066 +       else len = count;
1067 +       memset(mybuf,0,TXTBUFSZ);
1068 +       if(copy_from_user(mybuf, buffer, len)) return -EFAULT;
1069 +
1070 +       nparsed = sscanf(mybuf,
1071 +                       "%d %lx %Ld %d %lx %Ld %d %lx %Ld %d %lx %Ld",
1072 +                               &which[0], &control[0], &ctrdata[0],
1073 +                               &which[1], &control[1], &ctrdata[1],
1074 +                               &which[2], &control[2], &ctrdata[2],
1075 +                               &which[3], &control[3], &ctrdata[3]);
1076 +
1077 +       for(index = 0; nparsed >= 3; index++) {
1078 +               switch (which[index]) {
1079 +               case 0:
1080 +                       write_c0_perfctrl0(control[index]);
1081 +                       if(ctrdata[index] != -1) {
1082 +                           extencount[0] = (unsigned long long)ctrdata[index];
1083 +                           write_c0_perfcntr0((unsigned long)0);
1084 +                       }
1085 +                       break;
1086 +               case 1:
1087 +                       write_c0_perfctrl1(control[index]);
1088 +                       if(ctrdata[index] != -1) {
1089 +                           extencount[1] = (unsigned long long)ctrdata[index];
1090 +                           write_c0_perfcntr1((unsigned long)0);
1091 +                       }
1092 +                       break;
1093 +               case 2:
1094 +                       write_c0_perfctrl2(control[index]);
1095 +                       if(ctrdata[index] != -1) {
1096 +                           extencount[2] = (unsigned long long)ctrdata[index];
1097 +                           write_c0_perfcntr2((unsigned long)0);
1098 +                       }
1099 +                       break;
1100 +               case 3:
1101 +                       write_c0_perfctrl3(control[index]);
1102 +                       if(ctrdata[index] != -1) {
1103 +                           extencount[3] = (unsigned long long)ctrdata[index];
1104 +                           write_c0_perfcntr3((unsigned long)0);
1105 +                       }
1106 +                       break;
1107 +               }
1108 +               nparsed -= 3;
1109 +       }
1110 +       return (len);
1111 +}
1112 +
1113 +extern int (*perf_irq)(void);
1114 +
1115 +/*
1116 + * Invoked when timer interrupt vector picks up a perf counter overflow
1117 + */
1118 +
1119 +static int perf_proc_irq(void)
1120 +{
1121 +       unsigned long snapshot;
1122 +
1123 +       /*
1124 +        * It would be nice to do this as a loop, but we don't have
1125 +        * indirect access to CP0 registers.
1126 +        */
1127 +       snapshot = read_c0_perfcntr0();
1128 +       if ((long)snapshot < 0) {
1129 +               extencount[0] +=
1130 +                       (unsigned long long)((unsigned)read_c0_perfcntr0());
1131 +               write_c0_perfcntr0(0);
1132 +       }
1133 +       snapshot = read_c0_perfcntr1();
1134 +       if ((long)snapshot < 0) {
1135 +               extencount[1] +=
1136 +                       (unsigned long long)((unsigned)read_c0_perfcntr1());
1137 +               write_c0_perfcntr1(0);
1138 +       }
1139 +       snapshot = read_c0_perfcntr2();
1140 +       if ((long)snapshot < 0) {
1141 +               extencount[2] +=
1142 +                       (unsigned long long)((unsigned)read_c0_perfcntr2());
1143 +               write_c0_perfcntr2(0);
1144 +       }
1145 +       snapshot = read_c0_perfcntr3();
1146 +       if ((long)snapshot < 0) {
1147 +               extencount[3] +=
1148 +                       (unsigned long long)((unsigned)read_c0_perfcntr3());
1149 +               write_c0_perfcntr3(0);
1150 +       }
1151 +       return 0;
1152 +}
1153 +
1154 +static int __init init_perf_proc(void)
1155 +{
1156 +       extern struct proc_dir_entry *get_mips_proc_dir(void);
1157 +
1158 +       struct proc_dir_entry *mips_proc_dir = get_mips_proc_dir();
1159 +
1160 +       write_c0_perfcntr0(0);
1161 +       write_c0_perfcntr1(0);
1162 +       write_c0_perfcntr2(0);
1163 +       write_c0_perfcntr3(0);
1164 +       perf_proc = create_proc_entry("perf", 0644, mips_proc_dir);
1165 +       perf_proc->read_proc = proc_read_perf;
1166 +       perf_proc->write_proc = proc_write_perf;
1167 +       perf_irq = perf_proc_irq;
1168 +
1169 +       return 0;
1170 +}
1171 +
1172 +/* Automagically create the entry */
1173 +module_init(init_perf_proc);