package/fonera-mp3-drv/src/ar531xlnx.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright © 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  */
   8
   9 /*
  10  * This file contains definitions needed in order to compile
  11  * AR531X products for linux.  Definitions that are largely
  12  * AR531X-specific and independent of operating system belong
  13  * in ar531x.h rather than this file.
  14  */
  15 #ifndef __AR531XLNX_H
  16 #define __AR531XLNX_H
  17 #include "ar531x.h"
  18
  19 #define AR531X_HIGH_PRIO                0x10
  20 #define AR531X_MISC_IRQ_BASE            0x20
  21 #define AR531X_GPIO_IRQ_BASE            0x30
  22
  23 /* Software's idea of interrupts handled by "CPU Interrupt Controller" */
  24 #ifndef CONFIG_AR531X_COBRA
  25 #define CONFIG_AR531X_COBRA 0
  26 #endif
  27
  28 #if CONFIG_AR531X_COBRA
  29 #define AR531X_IRQ_NONE         MIPS_CPU_IRQ_BASE+0
  30 #define AR531X_IRQ_MISC_INTRS   MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
  31 #define AR531X_IRQ_WLAN0_INTRS  MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
  32 #define AR531X_IRQ_ENET0_INTRS  MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
  33 #define AR531X_IRQ_LCBUS_PCI    MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
  34 #define AR531X_IRQ_WLAN0_POLL   MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
  35 #define AR531X_IRQ_CPU_CLOCK    MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
  36 #else
  37 #define AR531X_IRQ_NONE         MIPS_CPU_IRQ_BASE+0
  38 #define AR531X_IRQ_WLAN0_INTRS  MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
  39 #define AR531X_IRQ_ENET0_INTRS  MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
  40 #define AR531X_IRQ_ENET1_INTRS  MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
  41 #define AR531X_IRQ_WLAN1_INTRS  MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
  42 #define AR531X_IRQ_MISC_INTRS   MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
  43 #define AR531X_IRQ_CPU_CLOCK    MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
  44 #endif
  45
  46 /* Miscellaneous interrupts, which share IP6 or IP2 */
  47 #define AR531X_MISC_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
  48 #define AR531X_MISC_IRQ_TIMER           AR531X_MISC_IRQ_BASE+1
  49 #define AR531X_MISC_IRQ_AHB_PROC        AR531X_MISC_IRQ_BASE+2
  50 #define AR531X_MISC_IRQ_AHB_DMA         AR531X_MISC_IRQ_BASE+3
  51 #define AR531X_MISC_IRQ_GPIO            AR531X_MISC_IRQ_BASE+4
  52 #define AR531X_MISC_IRQ_UART0           AR531X_MISC_IRQ_BASE+5
  53 #define AR531X_MISC_IRQ_UART0_DMA       AR531X_MISC_IRQ_BASE+6
  54 #define AR531X_MISC_IRQ_WATCHDOG        AR531X_MISC_IRQ_BASE+7
  55 #define AR531X_MISC_IRQ_LOCAL           AR531X_MISC_IRQ_BASE+8
  56 #define AR531X_MISC_IRQ_COUNT           9
  57
  58 /* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
  59 #define AR531X_GPIO_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
  60 #define AR531X_GPIO_IRQ(n)              AR531X_MISC_IRQ_BASE+(n)+1
  61 #define AR531X_GPIO_IRQ_COUNT           9
  62
  63 #define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
  64 //#define PHYS_TO_K0(physaddr) KSEG0ADDR(physaddr)
  65 #define UNMAPPED_TO_PHYS(vaddr)  PHYSADDR(vaddr)
  66 #define IS_UNMAPPED_VADDR(vaddr) \
  67     ((KSEGX(vaddr) == KSEG0) || (KSEGX(vaddr) == KSEG1))
  68
  69 /* IOCTL commands for /proc/ar531x */
  70 #define AR531X_CTRL_DO_BREAKPOINT       1
  71 #define AR531X_CTRL_DO_MADWIFI          2
  72
  73 /*
  74  * Definitions for operating system portability.
  75  * These are vxWorks-->Linux translations.
  76  */
  77 #define LOCAL static
  78 #define BOOL int
  79 #define TRUE 1
  80 #define FALSE 0
  81 #define UINT8 u8
  82 #define UINT16 u16
  83 #define UINT32 u32
  84 #define PRINTF printk
  85 #if /* DEBUG */ 1
  86 #define DEBUG_PRINTF printk
  87 #define printf printk
  88 #define INLINE
  89 #else
  90 DEBUG_PRINTF while (0) printk
  91 #define INLINE inline
  92 #endif
  93 #define sysUDelay(usecs) udelay(usecs)
  94 #define sysMsDelay(msecs) mdelay(msecs)
  95 typedef volatile UINT8 *VIRT_ADDR;
  96 #define MALLOC(sz) kmalloc(sz, GFP_KERNEL)
  97 #define MALLOC_NOSLEEP(sz) kmalloc(sz, GFP_ATOMIC)
  98 #define FREE(ptr) kfree((void *)ptr)
  99 #define BSP_BUG() do { printk("kernel BSP BUG at %s:%d!\n", __FILE__, __LINE__); *(int *)0=0; } while (0)
 100 #define BSP_BUG_ON(condition) do { if (unlikely((condition)!=0)) BSP_BUG(); } while(0)
 101 #define ASSERT(x) BSP_BUG_ON(!(x))
 102
 103 extern struct ar531x_boarddata *ar531x_board_configuration;
 104 extern char *ar531x_radio_configuration;
 105 extern char *enet_mac_address_get(int MACUnit);
 106
 107 extern void kgdbInit(void);
 108 extern int kgdbEnabled(void);
 109 extern void breakpoint(void);
 110 extern int kgdbInterrupt(void);
 111 extern unsigned int ar531x_cpu_frequency(void);
 112 extern unsigned int ar531x_sys_frequency(void);
 113
 114 /* GPIO support */
 115 extern struct irqaction spurious_gpio;
 116 extern unsigned int gpioIntMask;
 117 extern void ar531x_gpio_intr_init(int irq_base);
 118 extern void ar531x_gpio_ctrl_output(int gpio);
 119 extern void ar531x_gpio_ctrl_input(int gpio);
 120 extern void ar531x_gpio_set(int gpio, int val);
 121 extern int  ar531x_gpio_get(int gpio);
 122 extern void ar531x_gpio_intr_enable(unsigned int irq);
 123 extern void ar531x_gpio_intr_disable(unsigned int irq);
 124
 125 /* Watchdog Timer support */
 126 extern int watchdog_start(unsigned int milliseconds);
 127 extern int watchdog_stop(void);
 128 extern int watchdog_is_enabled(void);
 129 extern unsigned int watchdog_min_timer_reached(void);
 130 extern void watchdog_notify_alive(void);
 131
 132 #define A_DATA_CACHE_INVAL(start, length) \
 133         dma_cache_inv((UINT32)(start),(length))
 134
 135 #define sysWbFlush() mb()
 136
 137 #define intDisable(x) cli()
 138 #define intEnable(x) sti()
 139
 140 #endif   /* __AR531XLNX_H */