2 * Broadcom SiliconBackplane MIPS definitions
4 * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
5 * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
6 * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7 * interface. The core revision is stored in the SB ID register in SB
10 * Copyright 2004, Broadcom Corporation
11 * All Rights Reserved.
13 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
24 #ifndef _LANGUAGE_ASSEMBLY
26 /* cpp contortions to concatenate w/arg prescan */
28 #define _PADLINE(line) pad ## line
29 #define _XSTR(line) _PADLINE(line)
30 #define PAD _XSTR(__LINE__)
33 typedef volatile struct {
43 extern uint32
sb_flag(void *sbh
);
44 extern uint
sb_irq(void *sbh
);
46 extern void sb_serial_init(void *sbh
, void (*add
)(void *regs
, uint irq
, uint baud_base
, uint reg_shift
));
48 extern void sb_mips_init(void *sbh
);
49 extern uint32
sb_mips_clock(void *sbh
);
50 extern bool sb_mips_setclock(void *sbh
, uint32 mipsclock
, uint32 sbclock
, uint32 pciclock
);
52 extern uint32
sb_memc_get_ncdl(void *sbh
);
54 #endif /* _LANGUAGE_ASSEMBLY */
56 #endif /* _SBMIPS_H */
This page took 0.049512 seconds and 5 git commands to generate.