Add libpthread dependency
[openwrt.git] / openwrt / package / linux / kernel-source / include / sbpci.h
1 /*
2 * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
3 *
4 * $Id$
5 * Copyright 2004, Broadcom Corporation
6 * All Rights Reserved.
7 *
8 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 */
13
14 #ifndef _SBPCI_H
15 #define _SBPCI_H
16
17 /* cpp contortions to concatenate w/arg prescan */
18 #ifndef PAD
19 #define _PADLINE(line) pad ## line
20 #define _XSTR(line) _PADLINE(line)
21 #define PAD _XSTR(__LINE__)
22 #endif
23
24 /* Sonics side: PCI core and host control registers */
25 typedef struct sbpciregs {
26 uint32 control; /* PCI control */
27 uint32 PAD[3];
28 uint32 arbcontrol; /* PCI arbiter control */
29 uint32 PAD[3];
30 uint32 intstatus; /* Interrupt status */
31 uint32 intmask; /* Interrupt mask */
32 uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
33 uint32 PAD[9];
34 uint32 bcastaddr; /* Sonics broadcast address */
35 uint32 bcastdata; /* Sonics broadcast data */
36 uint32 PAD[2];
37 uint32 gpioin; /* ro: gpio input (>=rev2) */
38 uint32 gpioout; /* rw: gpio output (>=rev2) */
39 uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
40 uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
41 uint32 PAD[36];
42 uint32 sbtopci0; /* Sonics to PCI translation 0 */
43 uint32 sbtopci1; /* Sonics to PCI translation 1 */
44 uint32 sbtopci2; /* Sonics to PCI translation 2 */
45 uint32 PAD[445];
46 uint16 sprom[36]; /* SPROM shadow Area */
47 uint32 PAD[46];
48 } sbpciregs_t;
49
50 /* PCI control */
51 #define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
52 #define PCI_RST 0x02 /* Value driven out to pin */
53 #define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
54 #define PCI_CLK 0x08 /* Gate for clock driven out to pin */
55
56 /* PCI arbiter control */
57 #define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
58 #define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
59 #define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
60 #define PCI_PARKID_SHIFT 1
61 #define PCI_PARKID_LAST 0 /* Last requestor */
62 #define PCI_PARKID_4710 1 /* 4710 */
63 #define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
64 #define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
65
66 /* Interrupt status/mask */
67 #define PCI_INTA 0x01 /* PCI INTA# is asserted */
68 #define PCI_INTB 0x02 /* PCI INTB# is asserted */
69 #define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
70 #define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
71 #define PCI_PME 0x10 /* PCI PME# is asserted */
72
73 /* (General) PCI/SB mailbox interrupts, two bits per pci function */
74 #define MAILBOX_F0_0 0x100 /* function 0, int 0 */
75 #define MAILBOX_F0_1 0x200 /* function 0, int 1 */
76 #define MAILBOX_F1_0 0x400 /* function 1, int 0 */
77 #define MAILBOX_F1_1 0x800 /* function 1, int 1 */
78 #define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
79 #define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
80 #define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
81 #define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
82
83 /* Sonics broadcast address */
84 #define BCAST_ADDR_MASK 0xff /* Broadcast register address */
85
86 /* Sonics to PCI translation types */
87 #define SBTOPCI0_MASK 0xfc000000
88 #define SBTOPCI1_MASK 0xfc000000
89 #define SBTOPCI2_MASK 0xc0000000
90 #define SBTOPCI_MEM 0
91 #define SBTOPCI_IO 1
92 #define SBTOPCI_CFG0 2
93 #define SBTOPCI_CFG1 3
94 #define SBTOPCI_PREF 0x4 /* prefetch enable */
95 #define SBTOPCI_BURST 0x8 /* burst enable */
96
97 /* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
98 #define cap_list rsvd_a[0]
99 #define bar0_window dev_dep[0x80 - 0x40]
100 #define bar1_window dev_dep[0x84 - 0x40]
101 #define sprom_control dev_dep[0x88 - 0x40]
102
103 #ifndef _LANGUAGE_ASSEMBLY
104
105 extern int sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
106 extern int sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
107 extern void sbpci_ban(uint16 core);
108 extern int sbpci_init(void *sbh);
109 extern void sbpci_check(void *sbh);
110
111 #endif /* !_LANGUAGE_ASSEMBLY */
112
113 #endif /* _SBPCI_H */
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