package/b43/src/b43.h

   1 #ifndef B43_H_
   2 #define B43_H_
   3
   4 #include <linux/kernel.h>
   5 #include <linux/spinlock.h>
   6 #include <linux/interrupt.h>
   7 #include <linux/hw_random.h>
   8 #include <linux/ssb/ssb.h>
   9 #include <net/mac80211.h>
  10
  11 #include "debugfs.h"
  12 #include "leds.h"
  13 #include "rfkill.h"
  14 #include "lo.h"
  15 #include "phy.h"
  16
  17
  18 /* The unique identifier of the firmware that's officially supported by
  19  * this driver version. */
  20 #define B43_SUPPORTED_FIRMWARE_ID       "FW13"
  21
  22
  23 #ifdef CONFIG_B43_DEBUG
  24 # define B43_DEBUG      1
  25 #else
  26 # define B43_DEBUG      0
  27 #endif
  28
  29 #define B43_RX_MAX_SSI                  60
  30
  31 /* MMIO offsets */
  32 #define B43_MMIO_DMA0_REASON            0x20
  33 #define B43_MMIO_DMA0_IRQ_MASK          0x24
  34 #define B43_MMIO_DMA1_REASON            0x28
  35 #define B43_MMIO_DMA1_IRQ_MASK          0x2C
  36 #define B43_MMIO_DMA2_REASON            0x30
  37 #define B43_MMIO_DMA2_IRQ_MASK          0x34
  38 #define B43_MMIO_DMA3_REASON            0x38
  39 #define B43_MMIO_DMA3_IRQ_MASK          0x3C
  40 #define B43_MMIO_DMA4_REASON            0x40
  41 #define B43_MMIO_DMA4_IRQ_MASK          0x44
  42 #define B43_MMIO_DMA5_REASON            0x48
  43 #define B43_MMIO_DMA5_IRQ_MASK          0x4C
  44 #define B43_MMIO_MACCTL                 0x120   /* MAC control */
  45 #define B43_MMIO_MACCMD                 0x124   /* MAC command */
  46 #define B43_MMIO_GEN_IRQ_REASON         0x128
  47 #define B43_MMIO_GEN_IRQ_MASK           0x12C
  48 #define B43_MMIO_RAM_CONTROL            0x130
  49 #define B43_MMIO_RAM_DATA               0x134
  50 #define B43_MMIO_PS_STATUS              0x140
  51 #define B43_MMIO_RADIO_HWENABLED_HI     0x158
  52 #define B43_MMIO_SHM_CONTROL            0x160
  53 #define B43_MMIO_SHM_DATA               0x164
  54 #define B43_MMIO_SHM_DATA_UNALIGNED     0x166
  55 #define B43_MMIO_XMITSTAT_0             0x170
  56 #define B43_MMIO_XMITSTAT_1             0x174
  57 #define B43_MMIO_REV3PLUS_TSF_LOW       0x180   /* core rev >= 3 only */
  58 #define B43_MMIO_REV3PLUS_TSF_HIGH      0x184   /* core rev >= 3 only */
  59 #define B43_MMIO_TSF_CFP_REP            0x188
  60 #define B43_MMIO_TSF_CFP_START          0x18C
  61 #define B43_MMIO_TSF_CFP_MAXDUR         0x190
  62
  63 /* 32-bit DMA */
  64 #define B43_MMIO_DMA32_BASE0            0x200
  65 #define B43_MMIO_DMA32_BASE1            0x220
  66 #define B43_MMIO_DMA32_BASE2            0x240
  67 #define B43_MMIO_DMA32_BASE3            0x260
  68 #define B43_MMIO_DMA32_BASE4            0x280
  69 #define B43_MMIO_DMA32_BASE5            0x2A0
  70 /* 64-bit DMA */
  71 #define B43_MMIO_DMA64_BASE0            0x200
  72 #define B43_MMIO_DMA64_BASE1            0x240
  73 #define B43_MMIO_DMA64_BASE2            0x280
  74 #define B43_MMIO_DMA64_BASE3            0x2C0
  75 #define B43_MMIO_DMA64_BASE4            0x300
  76 #define B43_MMIO_DMA64_BASE5            0x340
  77
  78 /* PIO on core rev < 11 */
  79 #define B43_MMIO_PIO_BASE0              0x300
  80 #define B43_MMIO_PIO_BASE1              0x310
  81 #define B43_MMIO_PIO_BASE2              0x320
  82 #define B43_MMIO_PIO_BASE3              0x330
  83 #define B43_MMIO_PIO_BASE4              0x340
  84 #define B43_MMIO_PIO_BASE5              0x350
  85 #define B43_MMIO_PIO_BASE6              0x360
  86 #define B43_MMIO_PIO_BASE7              0x370
  87 /* PIO on core rev >= 11 */
  88 #define B43_MMIO_PIO11_BASE0            0x200
  89 #define B43_MMIO_PIO11_BASE1            0x240
  90 #define B43_MMIO_PIO11_BASE2            0x280
  91 #define B43_MMIO_PIO11_BASE3            0x2C0
  92 #define B43_MMIO_PIO11_BASE4            0x300
  93 #define B43_MMIO_PIO11_BASE5            0x340
  94
  95 #define B43_MMIO_PHY_VER                0x3E0
  96 #define B43_MMIO_PHY_RADIO              0x3E2
  97 #define B43_MMIO_PHY0                   0x3E6
  98 #define B43_MMIO_ANTENNA                0x3E8
  99 #define B43_MMIO_CHANNEL                0x3F0
 100 #define B43_MMIO_CHANNEL_EXT            0x3F4
 101 #define B43_MMIO_RADIO_CONTROL          0x3F6
 102 #define B43_MMIO_RADIO_DATA_HIGH        0x3F8
 103 #define B43_MMIO_RADIO_DATA_LOW         0x3FA
 104 #define B43_MMIO_PHY_CONTROL            0x3FC
 105 #define B43_MMIO_PHY_DATA               0x3FE
 106 #define B43_MMIO_MACFILTER_CONTROL      0x420
 107 #define B43_MMIO_MACFILTER_DATA         0x422
 108 #define B43_MMIO_RCMTA_COUNT            0x43C
 109 #define B43_MMIO_RADIO_HWENABLED_LO     0x49A
 110 #define B43_MMIO_GPIO_CONTROL           0x49C
 111 #define B43_MMIO_GPIO_MASK              0x49E
 112 #define B43_MMIO_TSF_CFP_START_LOW      0x604
 113 #define B43_MMIO_TSF_CFP_START_HIGH     0x606
 114 #define B43_MMIO_TSF_CFP_PRETBTT        0x612
 115 #define B43_MMIO_TSF_0                  0x632   /* core rev < 3 only */
 116 #define B43_MMIO_TSF_1                  0x634   /* core rev < 3 only */
 117 #define B43_MMIO_TSF_2                  0x636   /* core rev < 3 only */
 118 #define B43_MMIO_TSF_3                  0x638   /* core rev < 3 only */
 119 #define B43_MMIO_RNG                    0x65A
 120 #define B43_MMIO_IFSCTL                 0x688 /* Interframe space control */
 121 #define  B43_MMIO_IFSCTL_USE_EDCF       0x0004
 122 #define B43_MMIO_POWERUP_DELAY          0x6A8
 123
 124 /* SPROM boardflags_lo values */
 125 #define B43_BFL_BTCOEXIST               0x0001  /* implements Bluetooth coexistance */
 126 #define B43_BFL_PACTRL                  0x0002  /* GPIO 9 controlling the PA */
 127 #define B43_BFL_AIRLINEMODE             0x0004  /* implements GPIO 13 radio disable indication */
 128 #define B43_BFL_RSSI                    0x0008  /* software calculates nrssi slope. */
 129 #define B43_BFL_ENETSPI                 0x0010  /* has ephy roboswitch spi */
 130 #define B43_BFL_XTAL_NOSLOW             0x0020  /* no slow clock available */
 131 #define B43_BFL_CCKHIPWR                0x0040  /* can do high power CCK transmission */
 132 #define B43_BFL_ENETADM                 0x0080  /* has ADMtek switch */
 133 #define B43_BFL_ENETVLAN                0x0100  /* can do vlan */
 134 #define B43_BFL_AFTERBURNER             0x0200  /* supports Afterburner mode */
 135 #define B43_BFL_NOPCI                   0x0400  /* leaves PCI floating */
 136 #define B43_BFL_FEM                     0x0800  /* supports the Front End Module */
 137 #define B43_BFL_EXTLNA                  0x1000  /* has an external LNA */
 138 #define B43_BFL_HGPA                    0x2000  /* had high gain PA */
 139 #define B43_BFL_BTCMOD                  0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
 140 #define B43_BFL_ALTIQ                   0x8000  /* alternate I/Q settings */
 141
 142 /* GPIO register offset, in both ChipCommon and PCI core. */
 143 #define B43_GPIO_CONTROL                0x6c
 144
 145 /* SHM Routing */
 146 enum {
 147         B43_SHM_UCODE,          /* Microcode memory */
 148         B43_SHM_SHARED,         /* Shared memory */
 149         B43_SHM_SCRATCH,        /* Scratch memory */
 150         B43_SHM_HW,             /* Internal hardware register */
 151         B43_SHM_RCMTA,          /* Receive match transmitter address (rev >= 5 only) */
 152 };
 153 /* SHM Routing modifiers */
 154 #define B43_SHM_AUTOINC_R               0x0200  /* Auto-increment address on read */
 155 #define B43_SHM_AUTOINC_W               0x0100  /* Auto-increment address on write */
 156 #define B43_SHM_AUTOINC_RW              (B43_SHM_AUTOINC_R | \
 157                                          B43_SHM_AUTOINC_W)
 158
 159 /* Misc SHM_SHARED offsets */
 160 #define B43_SHM_SH_WLCOREREV            0x0016  /* 802.11 core revision */
 161 #define B43_SHM_SH_PCTLWDPOS            0x0008
 162 #define B43_SHM_SH_RXPADOFF             0x0034  /* RX Padding data offset (PIO only) */
 163 #define B43_SHM_SH_PHYVER               0x0050  /* PHY version */
 164 #define B43_SHM_SH_PHYTYPE              0x0052  /* PHY type */
 165 #define B43_SHM_SH_ANTSWAP              0x005C  /* Antenna swap threshold */
 166 #define B43_SHM_SH_HOSTFLO              0x005E  /* Hostflags for ucode options (low) */
 167 #define B43_SHM_SH_HOSTFMI              0x0060  /* Hostflags for ucode options (middle) */
 168 #define B43_SHM_SH_HOSTFHI              0x0062  /* Hostflags for ucode options (high) */
 169 #define B43_SHM_SH_RFATT                0x0064  /* Current radio attenuation value */
 170 #define B43_SHM_SH_RADAR                0x0066  /* Radar register */
 171 #define B43_SHM_SH_PHYTXNOI             0x006E  /* PHY noise directly after TX (lower 8bit only) */
 172 #define B43_SHM_SH_RFRXSP1              0x0072  /* RF RX SP Register 1 */
 173 #define B43_SHM_SH_CHAN                 0x00A0  /* Current channel (low 8bit only) */
 174 #define  B43_SHM_SH_CHAN_5GHZ           0x0100  /* Bit set, if 5Ghz channel */
 175 #define B43_SHM_SH_BCMCFIFOID           0x0108  /* Last posted cookie to the bcast/mcast FIFO */
 176 /* SHM_SHARED TX FIFO variables */
 177 #define B43_SHM_SH_SIZE01               0x0098  /* TX FIFO size for FIFO 0 (low) and 1 (high) */
 178 #define B43_SHM_SH_SIZE23               0x009A  /* TX FIFO size for FIFO 2 and 3 */
 179 #define B43_SHM_SH_SIZE45               0x009C  /* TX FIFO size for FIFO 4 and 5 */
 180 #define B43_SHM_SH_SIZE67               0x009E  /* TX FIFO size for FIFO 6 and 7 */
 181 /* SHM_SHARED background noise */
 182 #define B43_SHM_SH_JSSI0                0x0088  /* Measure JSSI 0 */
 183 #define B43_SHM_SH_JSSI1                0x008A  /* Measure JSSI 1 */
 184 #define B43_SHM_SH_JSSIAUX              0x008C  /* Measure JSSI AUX */
 185 /* SHM_SHARED crypto engine */
 186 #define B43_SHM_SH_DEFAULTIV            0x003C  /* Default IV location */
 187 #define B43_SHM_SH_NRRXTRANS            0x003E  /* # of soft RX transmitter addresses (max 8) */
 188 #define B43_SHM_SH_KTP                  0x0056  /* Key table pointer */
 189 #define B43_SHM_SH_TKIPTSCTTAK          0x0318
 190 #define B43_SHM_SH_KEYIDXBLOCK          0x05D4  /* Key index/algorithm block (v4 firmware) */
 191 #define B43_SHM_SH_PSM                  0x05F4  /* PSM transmitter address match block (rev < 5) */
 192 /* SHM_SHARED WME variables */
 193 #define B43_SHM_SH_EDCFSTAT             0x000E  /* EDCF status */
 194 #define B43_SHM_SH_TXFCUR               0x0030  /* TXF current index */
 195 #define B43_SHM_SH_EDCFQ                0x0240  /* EDCF Q info */
 196 /* SHM_SHARED powersave mode related */
 197 #define B43_SHM_SH_SLOTT                0x0010  /* Slot time */
 198 #define B43_SHM_SH_DTIMPER              0x0012  /* DTIM period */
 199 #define B43_SHM_SH_NOSLPZNATDTIM        0x004C  /* NOSLPZNAT DTIM */
 200 /* SHM_SHARED beacon/AP variables */
 201 #define B43_SHM_SH_BTL0                 0x0018  /* Beacon template length 0 */
 202 #define B43_SHM_SH_BTL1                 0x001A  /* Beacon template length 1 */
 203 #define B43_SHM_SH_BTSFOFF              0x001C  /* Beacon TSF offset */
 204 #define B43_SHM_SH_TIMBPOS              0x001E  /* TIM B position in beacon */
 205 #define B43_SHM_SH_DTIMP                0x0012  /* DTIP period */
 206 #define B43_SHM_SH_MCASTCOOKIE          0x00A8  /* Last bcast/mcast frame ID */
 207 #define B43_SHM_SH_SFFBLIM              0x0044  /* Short frame fallback retry limit */
 208 #define B43_SHM_SH_LFFBLIM              0x0046  /* Long frame fallback retry limit */
 209 #define B43_SHM_SH_BEACPHYCTL           0x0054  /* Beacon PHY TX control word (see PHY TX control) */
 210 #define B43_SHM_SH_EXTNPHYCTL           0x00B0  /* Extended bytes for beacon PHY control (N) */
 211 /* SHM_SHARED ACK/CTS control */
 212 #define B43_SHM_SH_ACKCTSPHYCTL         0x0022  /* ACK/CTS PHY control word (see PHY TX control) */
 213 /* SHM_SHARED probe response variables */
 214 #define B43_SHM_SH_PRSSID               0x0160  /* Probe Response SSID */
 215 #define B43_SHM_SH_PRSSIDLEN            0x0048  /* Probe Response SSID length */
 216 #define B43_SHM_SH_PRTLEN               0x004A  /* Probe Response template length */
 217 #define B43_SHM_SH_PRMAXTIME            0x0074  /* Probe Response max time */
 218 #define B43_SHM_SH_PRPHYCTL             0x0188  /* Probe Response PHY TX control word */
 219 /* SHM_SHARED rate tables */
 220 #define B43_SHM_SH_OFDMDIRECT           0x01C0  /* Pointer to OFDM direct map */
 221 #define B43_SHM_SH_OFDMBASIC            0x01E0  /* Pointer to OFDM basic rate map */
 222 #define B43_SHM_SH_CCKDIRECT            0x0200  /* Pointer to CCK direct map */
 223 #define B43_SHM_SH_CCKBASIC             0x0220  /* Pointer to CCK basic rate map */
 224 /* SHM_SHARED microcode soft registers */
 225 #define B43_SHM_SH_UCODEREV             0x0000  /* Microcode revision */
 226 #define B43_SHM_SH_UCODEPATCH           0x0002  /* Microcode patchlevel */
 227 #define B43_SHM_SH_UCODEDATE            0x0004  /* Microcode date */
 228 #define B43_SHM_SH_UCODETIME            0x0006  /* Microcode time */
 229 #define B43_SHM_SH_UCODESTAT            0x0040  /* Microcode debug status code */
 230 #define  B43_SHM_SH_UCODESTAT_INVALID   0
 231 #define  B43_SHM_SH_UCODESTAT_INIT      1
 232 #define  B43_SHM_SH_UCODESTAT_ACTIVE    2
 233 #define  B43_SHM_SH_UCODESTAT_SUSP      3       /* suspended */
 234 #define  B43_SHM_SH_UCODESTAT_SLEEP     4       /* asleep (PS) */
 235 #define B43_SHM_SH_MAXBFRAMES           0x0080  /* Maximum number of frames in a burst */
 236 #define B43_SHM_SH_SPUWKUP              0x0094  /* pre-wakeup for synth PU in us */
 237 #define B43_SHM_SH_PRETBTT              0x0096  /* pre-TBTT in us */
 238
 239 /* SHM_SCRATCH offsets */
 240 #define B43_SHM_SC_MINCONT              0x0003  /* Minimum contention window */
 241 #define B43_SHM_SC_MAXCONT              0x0004  /* Maximum contention window */
 242 #define B43_SHM_SC_CURCONT              0x0005  /* Current contention window */
 243 #define B43_SHM_SC_SRLIMIT              0x0006  /* Short retry count limit */
 244 #define B43_SHM_SC_LRLIMIT              0x0007  /* Long retry count limit */
 245 #define B43_SHM_SC_DTIMC                0x0008  /* Current DTIM count */
 246 #define B43_SHM_SC_BTL0LEN              0x0015  /* Beacon 0 template length */
 247 #define B43_SHM_SC_BTL1LEN              0x0016  /* Beacon 1 template length */
 248 #define B43_SHM_SC_SCFB                 0x0017  /* Short frame transmit count threshold for rate fallback */
 249 #define B43_SHM_SC_LCFB                 0x0018  /* Long frame transmit count threshold for rate fallback */
 250
 251 /* Hardware Radio Enable masks */
 252 #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
 253 #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 254
 255 /* HostFlags. See b43_hf_read/write() */
 256 #define B43_HF_ANTDIVHELP       0x000000000001ULL /* ucode antenna div helper */
 257 #define B43_HF_SYMW             0x000000000002ULL /* G-PHY SYM workaround */
 258 #define B43_HF_RXPULLW          0x000000000004ULL /* RX pullup workaround */
 259 #define B43_HF_CCKBOOST         0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */
 260 #define B43_HF_BTCOEX           0x000000000010ULL /* Bluetooth coexistance */
 261 #define B43_HF_GDCW             0x000000000020ULL /* G-PHY DC canceller filter bw workaround */
 262 #define B43_HF_OFDMPABOOST      0x000000000040ULL /* Enable PA gain boost for OFDM */
 263 #define B43_HF_ACPR             0x000000000080ULL /* Disable for Japan, channel 14 */
 264 #define B43_HF_EDCF             0x000000000100ULL /* on if WME and MAC suspended */
 265 #define B43_HF_TSSIRPSMW        0x000000000200ULL /* TSSI reset PSM ucode workaround */
 266 #define B43_HF_20IN40IQW        0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */
 267 #define B43_HF_DSCRQ            0x000000000400ULL /* Disable slow clock request in ucode */
 268 #define B43_HF_ACIW             0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */
 269 #define B43_HF_2060W            0x000000001000ULL /* 2060 radio workaround */
 270 #define B43_HF_RADARW           0x000000002000ULL /* Radar workaround */
 271 #define B43_HF_USEDEFKEYS       0x000000004000ULL /* Enable use of default keys */
 272 #define B43_HF_AFTERBURNER      0x000000008000ULL /* Afterburner enabled */
 273 #define B43_HF_BT4PRIOCOEX      0x000000010000ULL /* Bluetooth 4-priority coexistance */
 274 #define B43_HF_FWKUP            0x000000020000ULL /* Fast wake-up ucode */
 275 #define B43_HF_VCORECALC        0x000000040000ULL /* Force VCO recalculation when powering up synthpu */
 276 #define B43_HF_PCISCW           0x000000080000ULL /* PCI slow clock workaround */
 277 #define B43_HF_4318TSSI         0x000000200000ULL /* 4318 TSSI */
 278 #define B43_HF_FBCMCFIFO        0x000000400000ULL /* Flush bcast/mcast FIFO immediately */
 279 #define B43_HF_HWPCTL           0x000000800000ULL /* Enable hardwarre power control */
 280 #define B43_HF_BTCOEXALT        0x000001000000ULL /* Bluetooth coexistance in alternate pins */
 281 #define B43_HF_TXBTCHECK        0x000002000000ULL /* Bluetooth check during transmission */
 282 #define B43_HF_SKCFPUP          0x000004000000ULL /* Skip CFP update */
 283 #define B43_HF_N40W             0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */
 284 #define B43_HF_ANTSEL           0x000020000000ULL /* Antenna selection (for testing antenna div.) */
 285 #define B43_HF_BT3COEXT         0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */
 286 #define B43_HF_BTCANT           0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */
 287 #define B43_HF_ANTSELEN         0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */
 288 #define B43_HF_ANTSELMODE       0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */
 289 #define B43_HF_MLADVW           0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */
 290 #define B43_HF_PR45960W         0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */
 291
 292 /* MacFilter offsets. */
 293 #define B43_MACFILTER_SELF              0x0000
 294 #define B43_MACFILTER_BSSID             0x0003
 295
 296 /* PowerControl */
 297 #define B43_PCTL_IN                     0xB0
 298 #define B43_PCTL_OUT                    0xB4
 299 #define B43_PCTL_OUTENABLE              0xB8
 300 #define B43_PCTL_XTAL_POWERUP           0x40
 301 #define B43_PCTL_PLL_POWERDOWN          0x80
 302
 303 /* PowerControl Clock Modes */
 304 #define B43_PCTL_CLK_FAST               0x00
 305 #define B43_PCTL_CLK_SLOW               0x01
 306 #define B43_PCTL_CLK_DYNAMIC            0x02
 307
 308 #define B43_PCTL_FORCE_SLOW             0x0800
 309 #define B43_PCTL_FORCE_PLL              0x1000
 310 #define B43_PCTL_DYN_XTAL               0x2000
 311
 312 /* PHYVersioning */
 313 #define B43_PHYTYPE_A                   0x00
 314 #define B43_PHYTYPE_B                   0x01
 315 #define B43_PHYTYPE_G                   0x02
 316 #define B43_PHYTYPE_N                   0x04
 317 #define B43_PHYTYPE_LP                  0x05
 318
 319 /* PHYRegisters */
 320 #define B43_PHY_ILT_A_CTRL              0x0072
 321 #define B43_PHY_ILT_A_DATA1             0x0073
 322 #define B43_PHY_ILT_A_DATA2             0x0074
 323 #define B43_PHY_G_LO_CONTROL            0x0810
 324 #define B43_PHY_ILT_G_CTRL              0x0472
 325 #define B43_PHY_ILT_G_DATA1             0x0473
 326 #define B43_PHY_ILT_G_DATA2             0x0474
 327 #define B43_PHY_A_PCTL                  0x007B
 328 #define B43_PHY_G_PCTL                  0x0029
 329 #define B43_PHY_A_CRS                   0x0029
 330 #define B43_PHY_RADIO_BITFIELD          0x0401
 331 #define B43_PHY_G_CRS                   0x0429
 332 #define B43_PHY_NRSSILT_CTRL            0x0803
 333 #define B43_PHY_NRSSILT_DATA            0x0804
 334
 335 /* RadioRegisters */
 336 #define B43_RADIOCTL_ID                 0x01
 337
 338 /* MAC Control bitfield */
 339 #define B43_MACCTL_ENABLED              0x00000001      /* MAC Enabled */
 340 #define B43_MACCTL_PSM_RUN              0x00000002      /* Run Microcode */
 341 #define B43_MACCTL_PSM_JMP0             0x00000004      /* Microcode jump to 0 */
 342 #define B43_MACCTL_SHM_ENABLED          0x00000100      /* SHM Enabled */
 343 #define B43_MACCTL_SHM_UPPER            0x00000200      /* SHM Upper */
 344 #define B43_MACCTL_IHR_ENABLED          0x00000400      /* IHR Region Enabled */
 345 #define B43_MACCTL_PSM_DBG              0x00002000      /* Microcode debugging enabled */
 346 #define B43_MACCTL_GPOUTSMSK            0x0000C000      /* GPOUT Select Mask */
 347 #define B43_MACCTL_BE                   0x00010000      /* Big Endian mode */
 348 #define B43_MACCTL_INFRA                0x00020000      /* Infrastructure mode */
 349 #define B43_MACCTL_AP                   0x00040000      /* AccessPoint mode */
 350 #define B43_MACCTL_RADIOLOCK            0x00080000      /* Radio lock */
 351 #define B43_MACCTL_BEACPROMISC          0x00100000      /* Beacon Promiscuous */
 352 #define B43_MACCTL_KEEP_BADPLCP         0x00200000      /* Keep frames with bad PLCP */
 353 #define B43_MACCTL_KEEP_CTL             0x00400000      /* Keep control frames */
 354 #define B43_MACCTL_KEEP_BAD             0x00800000      /* Keep bad frames (FCS) */
 355 #define B43_MACCTL_PROMISC              0x01000000      /* Promiscuous mode */
 356 #define B43_MACCTL_HWPS                 0x02000000      /* Hardware Power Saving */
 357 #define B43_MACCTL_AWAKE                0x04000000      /* Device is awake */
 358 #define B43_MACCTL_CLOSEDNET            0x08000000      /* Closed net (no SSID bcast) */
 359 #define B43_MACCTL_TBTTHOLD             0x10000000      /* TBTT Hold */
 360 #define B43_MACCTL_DISCTXSTAT           0x20000000      /* Discard TX status */
 361 #define B43_MACCTL_DISCPMQ              0x40000000      /* Discard Power Management Queue */
 362 #define B43_MACCTL_GMODE                0x80000000      /* G Mode */
 363
 364 /* MAC Command bitfield */
 365 #define B43_MACCMD_BEACON0_VALID        0x00000001      /* Beacon 0 in template RAM is busy/valid */
 366 #define B43_MACCMD_BEACON1_VALID        0x00000002      /* Beacon 1 in template RAM is busy/valid */
 367 #define B43_MACCMD_DFQ_VALID            0x00000004      /* Directed frame queue valid (IBSS PS mode, ATIM) */
 368 #define B43_MACCMD_CCA                  0x00000008      /* Clear channel assessment */
 369 #define B43_MACCMD_BGNOISE              0x00000010      /* Background noise */
 370
 371 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
 372 #define B43_TMSLOW_GMODE                0x20000000      /* G Mode Enable */
 373 #define B43_TMSLOW_PHYCLKSPEED          0x00C00000      /* PHY clock speed mask (N-PHY only) */
 374 #define  B43_TMSLOW_PHYCLKSPEED_40MHZ   0x00000000      /* 40 MHz PHY */
 375 #define  B43_TMSLOW_PHYCLKSPEED_80MHZ   0x00400000      /* 80 MHz PHY */
 376 #define  B43_TMSLOW_PHYCLKSPEED_160MHZ  0x00800000      /* 160 MHz PHY */
 377 #define B43_TMSLOW_PLLREFSEL            0x00200000      /* PLL Frequency Reference Select (rev >= 5) */
 378 #define B43_TMSLOW_MACPHYCLKEN          0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
 379 #define B43_TMSLOW_PHYRESET             0x00080000      /* PHY Reset */
 380 #define B43_TMSLOW_PHYCLKEN             0x00040000      /* PHY Clock Enable */
 381
 382 /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */
 383 #define B43_TMSHIGH_DUALBAND_PHY        0x00080000      /* Dualband PHY available */
 384 #define B43_TMSHIGH_FCLOCK              0x00040000      /* Fast Clock Available (rev >= 5) */
 385 #define B43_TMSHIGH_HAVE_5GHZ_PHY       0x00020000      /* 5 GHz PHY available (rev >= 5) */
 386 #define B43_TMSHIGH_HAVE_2GHZ_PHY       0x00010000      /* 2.4 GHz PHY available (rev >= 5) */
 387
 388 /* Generic-Interrupt reasons. */
 389 #define B43_IRQ_MAC_SUSPENDED           0x00000001
 390 #define B43_IRQ_BEACON                  0x00000002
 391 #define B43_IRQ_TBTT_INDI               0x00000004
 392 #define B43_IRQ_BEACON_TX_OK            0x00000008
 393 #define B43_IRQ_BEACON_CANCEL           0x00000010
 394 #define B43_IRQ_ATIM_END                0x00000020
 395 #define B43_IRQ_PMQ                     0x00000040
 396 #define B43_IRQ_PIO_WORKAROUND          0x00000100
 397 #define B43_IRQ_MAC_TXERR               0x00000200
 398 #define B43_IRQ_PHY_TXERR               0x00000800
 399 #define B43_IRQ_PMEVENT                 0x00001000
 400 #define B43_IRQ_TIMER0                  0x00002000
 401 #define B43_IRQ_TIMER1                  0x00004000
 402 #define B43_IRQ_DMA                     0x00008000
 403 #define B43_IRQ_TXFIFO_FLUSH_OK         0x00010000
 404 #define B43_IRQ_CCA_MEASURE_OK          0x00020000
 405 #define B43_IRQ_NOISESAMPLE_OK          0x00040000
 406 #define B43_IRQ_UCODE_DEBUG             0x08000000
 407 #define B43_IRQ_RFKILL                  0x10000000
 408 #define B43_IRQ_TX_OK                   0x20000000
 409 #define B43_IRQ_PHY_G_CHANGED           0x40000000
 410 #define B43_IRQ_TIMEOUT                 0x80000000
 411
 412 #define B43_IRQ_ALL                     0xFFFFFFFF
 413 #define B43_IRQ_MASKTEMPLATE            (B43_IRQ_TBTT_INDI | \
 414                                          B43_IRQ_ATIM_END | \
 415                                          B43_IRQ_PMQ | \
 416                                          B43_IRQ_MAC_TXERR | \
 417                                          B43_IRQ_PHY_TXERR | \
 418                                          B43_IRQ_DMA | \
 419                                          B43_IRQ_TXFIFO_FLUSH_OK | \
 420                                          B43_IRQ_NOISESAMPLE_OK | \
 421                                          B43_IRQ_UCODE_DEBUG | \
 422                                          B43_IRQ_RFKILL | \
 423                                          B43_IRQ_TX_OK)
 424
 425 /* The firmware register to fetch the debug-IRQ reason from. */
 426 #define B43_DEBUGIRQ_REASON_REG         63
 427 /* Debug-IRQ reasons. */
 428 #define B43_DEBUGIRQ_PANIC              0       /* The firmware panic'ed */
 429 #define B43_DEBUGIRQ_DUMP_SHM           1       /* Dump shared SHM */
 430 #define B43_DEBUGIRQ_DUMP_REGS          2       /* Dump the microcode registers */
 431 #define B43_DEBUGIRQ_MARKER             3       /* A "marker" was thrown by the firmware. */
 432 #define B43_DEBUGIRQ_ACK                0xFFFF  /* The host writes that to ACK the IRQ */
 433
 434 /* The firmware register that contains the "marker" line. */
 435 #define B43_MARKER_ID_REG               2
 436 #define B43_MARKER_LINE_REG             3
 437
 438 /* The firmware register to fetch the panic reason from. */
 439 #define B43_FWPANIC_REASON_REG          3
 440 /* Firmware panic reason codes */
 441 #define B43_FWPANIC_DIE                 0 /* Firmware died. Don't auto-restart it. */
 442 #define B43_FWPANIC_RESTART             1 /* Firmware died. Schedule a controller reset. */
 443
 444
 445 /* Device specific rate values.
 446  * The actual values defined here are (rate_in_mbps * 2).
 447  * Some code depends on this. Don't change it. */
 448 #define B43_CCK_RATE_1MB                0x02
 449 #define B43_CCK_RATE_2MB                0x04
 450 #define B43_CCK_RATE_5MB                0x0B
 451 #define B43_CCK_RATE_11MB               0x16
 452 #define B43_OFDM_RATE_6MB               0x0C
 453 #define B43_OFDM_RATE_9MB               0x12
 454 #define B43_OFDM_RATE_12MB              0x18
 455 #define B43_OFDM_RATE_18MB              0x24
 456 #define B43_OFDM_RATE_24MB              0x30
 457 #define B43_OFDM_RATE_36MB              0x48
 458 #define B43_OFDM_RATE_48MB              0x60
 459 #define B43_OFDM_RATE_54MB              0x6C
 460 /* Convert a b43 rate value to a rate in 100kbps */
 461 #define B43_RATE_TO_BASE100KBPS(rate)   (((rate) * 10) / 2)
 462
 463 #define B43_DEFAULT_SHORT_RETRY_LIMIT   7
 464 #define B43_DEFAULT_LONG_RETRY_LIMIT    4
 465
 466 #define B43_PHY_TX_BADNESS_LIMIT        1000
 467
 468 /* Max size of a security key */
 469 #define B43_SEC_KEYSIZE                 16
 470 /* Security algorithms. */
 471 enum {
 472         B43_SEC_ALGO_NONE = 0,  /* unencrypted, as of TX header. */
 473         B43_SEC_ALGO_WEP40,
 474         B43_SEC_ALGO_TKIP,
 475         B43_SEC_ALGO_AES,
 476         B43_SEC_ALGO_WEP104,
 477         B43_SEC_ALGO_AES_LEGACY,
 478 };
 479
 480 struct b43_dmaring;
 481
 482 /* The firmware file header */
 483 #define B43_FW_TYPE_UCODE       'u'
 484 #define B43_FW_TYPE_PCM         'p'
 485 #define B43_FW_TYPE_IV          'i'
 486 struct b43_fw_header {
 487         /* File type */
 488         u8 type;
 489         /* File format version */
 490         u8 ver;
 491         u8 __padding[2];
 492         /* Size of the data. For ucode and PCM this is in bytes.
 493          * For IV this is number-of-ivs. */
 494         __be32 size;
 495 } __attribute__((__packed__));
 496
 497 /* Initial Value file format */
 498 #define B43_IV_OFFSET_MASK      0x7FFF
 499 #define B43_IV_32BIT            0x8000
 500 struct b43_iv {
 501         __be16 offset_size;
 502         union {
 503                 __be16 d16;
 504                 __be32 d32;
 505         } data __attribute__((__packed__));
 506 } __attribute__((__packed__));
 507
 508
 509 struct b43_phy {
 510         /* Band support flags. */
 511         bool supports_2ghz;
 512         bool supports_5ghz;
 513
 514         /* GMODE bit enabled? */
 515         bool gmode;
 516
 517         /* Analog Type */
 518         u8 analog;
 519         /* B43_PHYTYPE_ */
 520         u8 type;
 521         /* PHY revision number. */
 522         u8 rev;
 523
 524         /* Radio versioning */
 525         u16 radio_manuf;        /* Radio manufacturer */
 526         u16 radio_ver;          /* Radio version */
 527         u8 radio_rev;           /* Radio revision */
 528
 529         bool dyn_tssi_tbl;      /* tssi2dbm is kmalloc()ed. */
 530
 531         /* ACI (adjacent channel interference) flags. */
 532         bool aci_enable;
 533         bool aci_wlan_automatic;
 534         bool aci_hw_rssi;
 535
 536         /* Radio switched on/off */
 537         bool radio_on;
 538         struct {
 539                 /* Values saved when turning the radio off.
 540                  * They are needed when turning it on again. */
 541                 bool valid;
 542                 u16 rfover;
 543                 u16 rfoverval;
 544         } radio_off_context;
 545
 546         u16 minlowsig[2];
 547         u16 minlowsigpos[2];
 548
 549         /* TSSI to dBm table in use */
 550         const s8 *tssi2dbm;
 551         /* Target idle TSSI */
 552         int tgt_idle_tssi;
 553         /* Current idle TSSI */
 554         int cur_idle_tssi;
 555
 556         /* LocalOscillator control values. */
 557         struct b43_txpower_lo_control *lo_control;
 558         /* Values from b43_calc_loopback_gain() */
 559         s16 max_lb_gain;        /* Maximum Loopback gain in hdB */
 560         s16 trsw_rx_gain;       /* TRSW RX gain in hdB */
 561         s16 lna_lod_gain;       /* LNA lod */
 562         s16 lna_gain;           /* LNA */
 563         s16 pga_gain;           /* PGA */
 564
 565         /* Desired TX power level (in dBm).
 566          * This is set by the user and adjusted in b43_phy_xmitpower(). */
 567         u8 power_level;
 568         /* A-PHY TX Power control value. */
 569         u16 txpwr_offset;
 570
 571         /* Current TX power level attenuation control values */
 572         struct b43_bbatt bbatt;
 573         struct b43_rfatt rfatt;
 574         u8 tx_control;          /* B43_TXCTL_XXX */
 575
 576         /* Hardware Power Control enabled? */
 577         bool hardware_power_control;
 578
 579         /* Current Interference Mitigation mode */
 580         int interfmode;
 581         /* Stack of saved values from the Interference Mitigation code.
 582          * Each value in the stack is layed out as follows:
 583          * bit 0-11:  offset
 584          * bit 12-15: register ID
 585          * bit 16-32: value
 586          * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
 587          */
 588 #define B43_INTERFSTACK_SIZE    26
 589         u32 interfstack[B43_INTERFSTACK_SIZE];  //FIXME: use a data structure
 590
 591         /* Saved values from the NRSSI Slope calculation */
 592         s16 nrssi[2];
 593         s32 nrssislope;
 594         /* In memory nrssi lookup table. */
 595         s8 nrssi_lt[64];
 596
 597         /* current channel */
 598         u8 channel;
 599
 600         u16 lofcal;
 601
 602         u16 initval;            //FIXME rename?
 603
 604         /* PHY TX errors counter. */
 605         atomic_t txerr_cnt;
 606
 607         /* The device does address auto increment for the OFDM tables.
 608          * We cache the previously used address here and omit the address
 609          * write on the next table access, if possible. */
 610         u16 ofdmtab_addr; /* The address currently set in hardware. */
 611         enum { /* The last data flow direction. */
 612                 B43_OFDMTAB_DIRECTION_UNKNOWN = 0,
 613                 B43_OFDMTAB_DIRECTION_READ,
 614                 B43_OFDMTAB_DIRECTION_WRITE,
 615         } ofdmtab_addr_direction;
 616
 617 #if B43_DEBUG
 618         /* Manual TX-power control enabled? */
 619         bool manual_txpower_control;
 620         /* PHY registers locked by b43_phy_lock()? */
 621         bool phy_locked;
 622 #endif /* B43_DEBUG */
 623 };
 624
 625 /* Data structures for DMA transmission, per 80211 core. */
 626 struct b43_dma {
 627         struct b43_dmaring *tx_ring_AC_BK; /* Background */
 628         struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */
 629         struct b43_dmaring *tx_ring_AC_VI; /* Video */
 630         struct b43_dmaring *tx_ring_AC_VO; /* Voice */
 631         struct b43_dmaring *tx_ring_mcast; /* Multicast */
 632
 633         struct b43_dmaring *rx_ring;
 634 };
 635
 636 struct b43_pio_txqueue;
 637 struct b43_pio_rxqueue;
 638
 639 /* Data structures for PIO transmission, per 80211 core. */
 640 struct b43_pio {
 641         struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */
 642         struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */
 643         struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */
 644         struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */
 645         struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */
 646
 647         struct b43_pio_rxqueue *rx_queue;
 648 };
 649
 650 /* Context information for a noise calculation (Link Quality). */
 651 struct b43_noise_calculation {
 652         u8 channel_at_start;
 653         bool calculation_running;
 654         u8 nr_samples;
 655         s8 samples[8][4];
 656 };
 657
 658 struct b43_stats {
 659         u8 link_noise;
 660         /* Store the last TX/RX times here for updating the leds. */
 661         unsigned long last_tx;
 662         unsigned long last_rx;
 663 };
 664
 665 struct b43_key {
 666         /* If keyconf is NULL, this key is disabled.
 667          * keyconf is a cookie. Don't derefenrence it outside of the set_key
 668          * path, because b43 doesn't own it. */
 669         struct ieee80211_key_conf *keyconf;
 670         u8 algorithm;
 671 };
 672
 673 /* SHM offsets to the QOS data structures for the 4 different queues. */
 674 #define B43_QOS_PARAMS(queue)   (B43_SHM_SH_EDCFQ + \
 675                                  (B43_NR_QOSPARAMS * sizeof(u16) * (queue)))
 676 #define B43_QOS_BACKGROUND      B43_QOS_PARAMS(0)
 677 #define B43_QOS_BESTEFFORT      B43_QOS_PARAMS(1)
 678 #define B43_QOS_VIDEO           B43_QOS_PARAMS(2)
 679 #define B43_QOS_VOICE           B43_QOS_PARAMS(3)
 680
 681 /* QOS parameter hardware data structure offsets. */
 682 #define B43_NR_QOSPARAMS        22
 683 enum {
 684         B43_QOSPARAM_TXOP = 0,
 685         B43_QOSPARAM_CWMIN,
 686         B43_QOSPARAM_CWMAX,
 687         B43_QOSPARAM_CWCUR,
 688         B43_QOSPARAM_AIFS,
 689         B43_QOSPARAM_BSLOTS,
 690         B43_QOSPARAM_REGGAP,
 691         B43_QOSPARAM_STATUS,
 692 };
 693
 694 /* QOS parameters for a queue. */
 695 struct b43_qos_params {
 696         /* The QOS parameters */
 697         struct ieee80211_tx_queue_params p;
 698         /* Does this need to get uploaded to hardware? */
 699         bool need_hw_update;
 700 };
 701
 702 struct b43_wldev;
 703
 704 /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */
 705 struct b43_wl {
 706         /* Pointer to the active wireless device on this chip */
 707         struct b43_wldev *current_dev;
 708         /* Pointer to the ieee80211 hardware data structure */
 709         struct ieee80211_hw *hw;
 710
 711         struct mutex mutex;
 712         spinlock_t irq_lock;
 713         /* R/W lock for data transmission.
 714          * Transmissions on 2+ queues can run concurrently, but somebody else
 715          * might sync with TX by write_lock_irqsave()'ing. */
 716         rwlock_t tx_lock;
 717         /* Lock for LEDs access. */
 718         spinlock_t leds_lock;
 719         /* Lock for SHM access. */
 720         spinlock_t shm_lock;
 721
 722         /* We can only have one operating interface (802.11 core)
 723          * at a time. General information about this interface follows.
 724          */
 725
 726         struct ieee80211_vif *vif;
 727         /* The MAC address of the operating interface. */
 728         u8 mac_addr[ETH_ALEN];
 729         /* Current BSSID */
 730         u8 bssid[ETH_ALEN];
 731         /* Interface type. (IEEE80211_IF_TYPE_XXX) */
 732         int if_type;
 733         /* Is the card operating in AP, STA or IBSS mode? */
 734         bool operating;
 735         /* filter flags */
 736         unsigned int filter_flags;
 737         /* Stats about the wireless interface */
 738         struct ieee80211_low_level_stats ieee_stats;
 739
 740         struct hwrng rng;
 741         u8 rng_initialized;
 742         char rng_name[30 + 1];
 743
 744         /* The RF-kill button */
 745         struct b43_rfkill rfkill;
 746
 747         /* List of all wireless devices on this chip */
 748         struct list_head devlist;
 749         u8 nr_devs;
 750
 751         bool radiotap_enabled;
 752
 753         /* The beacon we are currently using (AP or IBSS mode).
 754          * This beacon stuff is protected by the irq_lock. */
 755         struct sk_buff *current_beacon;
 756         bool beacon0_uploaded;
 757         bool beacon1_uploaded;
 758         struct work_struct beacon_update_trigger;
 759
 760         /* The current QOS parameters for the 4 queues.
 761          * This is protected by the irq_lock. */
 762         struct b43_qos_params qos_params[4];
 763         /* Workqueue for updating QOS parameters in hardware. */
 764         struct work_struct qos_update_work;
 765 };
 766
 767 /* In-memory representation of a cached microcode file. */
 768 struct b43_firmware_file {
 769         const char *filename;
 770         const struct firmware *data;
 771 };
 772
 773 /* Pointers to the firmware data and meta information about it. */
 774 struct b43_firmware {
 775         /* Microcode */
 776         struct b43_firmware_file ucode;
 777         /* PCM code */
 778         struct b43_firmware_file pcm;
 779         /* Initial MMIO values for the firmware */
 780         struct b43_firmware_file initvals;
 781         /* Initial MMIO values for the firmware, band-specific */
 782         struct b43_firmware_file initvals_band;
 783
 784         /* Firmware revision */
 785         u16 rev;
 786         /* Firmware patchlevel */
 787         u16 patch;
 788
 789         /* Set to true, if we are using an opensource firmware. */
 790         bool opensource;
 791         /* Set to true, if the core needs a PCM firmware, but
 792          * we failed to load one. This is always false for
 793          * core rev > 10, as these don't need PCM firmware. */
 794         bool pcm_request_failed;
 795 };
 796
 797 /* Device (802.11 core) initialization status. */
 798 enum {
 799         B43_STAT_UNINIT = 0,    /* Uninitialized. */
 800         B43_STAT_INITIALIZED = 1,       /* Initialized, but not started, yet. */
 801         B43_STAT_STARTED = 2,   /* Up and running. */
 802 };
 803 #define b43_status(wldev)               atomic_read(&(wldev)->__init_status)
 804 #define b43_set_status(wldev, stat)     do {                    \
 805                 atomic_set(&(wldev)->__init_status, (stat));    \
 806                 smp_wmb();                                      \
 807                                         } while (0)
 808
 809 /* XXX---   HOW LOCKING WORKS IN B43   ---XXX
 810  *
 811  * You should always acquire both, wl->mutex and wl->irq_lock unless:
 812  * - You don't need to acquire wl->irq_lock, if the interface is stopped.
 813  * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
 814  *   and packet TX path (and _ONLY_ there.)
 815  */
 816
 817 /* Data structure for one wireless device (802.11 core) */
 818 struct b43_wldev {
 819         struct ssb_device *dev;
 820         struct b43_wl *wl;
 821
 822         /* The device initialization status.
 823          * Use b43_status() to query. */
 824         atomic_t __init_status;
 825         /* Saved init status for handling suspend. */
 826         int suspend_init_status;
 827
 828         bool bad_frames_preempt;        /* Use "Bad Frames Preemption" (default off) */
 829         bool dfq_valid;         /* Directed frame queue valid (IBSS PS mode, ATIM) */
 830         bool short_slot;        /* TRUE, if short slot timing is enabled. */
 831         bool radio_hw_enable;   /* saved state of radio hardware enabled state */
 832         bool suspend_in_progress;       /* TRUE, if we are in a suspend/resume cycle */
 833
 834         /* PHY/Radio device. */
 835         struct b43_phy phy;
 836
 837         union {
 838                 /* DMA engines. */
 839                 struct b43_dma dma;
 840                 /* PIO engines. */
 841                 struct b43_pio pio;
 842         };
 843         /* Use b43_using_pio_transfers() to check whether we are using
 844          * DMA or PIO data transfers. */
 845         bool __using_pio_transfers;
 846
 847         /* Various statistics about the physical device. */
 848         struct b43_stats stats;
 849
 850         /* The device LEDs. */
 851         struct b43_led led_tx;
 852         struct b43_led led_rx;
 853         struct b43_led led_assoc;
 854         struct b43_led led_radio;
 855
 856         /* Reason code of the last interrupt. */
 857         u32 irq_reason;
 858         u32 dma_reason[6];
 859         /* saved irq enable/disable state bitfield. */
 860         u32 irq_savedstate;
 861         /* Link Quality calculation context. */
 862         struct b43_noise_calculation noisecalc;
 863         /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
 864         int mac_suspended;
 865
 866         /* Interrupt Service Routine tasklet (bottom-half) */
 867         struct tasklet_struct isr_tasklet;
 868
 869         /* Periodic tasks */
 870         struct delayed_work periodic_work;
 871         unsigned int periodic_state;
 872
 873         struct work_struct restart_work;
 874
 875         /* encryption/decryption */
 876         u16 ktp;                /* Key table pointer */
 877         u8 max_nr_keys;
 878         struct b43_key key[58];
 879
 880         /* Firmware data */
 881         struct b43_firmware fw;
 882
 883         /* Devicelist in struct b43_wl (all 802.11 cores) */
 884         struct list_head list;
 885
 886         /* Debugging stuff follows. */
 887 #ifdef CONFIG_B43_DEBUG
 888         struct b43_dfsentry *dfsentry;
 889 #endif
 890 };
 891
 892 static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw)
 893 {
 894         return hw->priv;
 895 }
 896
 897 static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev)
 898 {
 899         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 900         return ssb_get_drvdata(ssb_dev);
 901 }
 902
 903 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
 904 static inline int b43_is_mode(struct b43_wl *wl, int type)
 905 {
 906         return (wl->operating && wl->if_type == type);
 907 }
 908
 909 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
 910 {
 911         return ssb_read16(dev->dev, offset);
 912 }
 913
 914 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
 915 {
 916         ssb_write16(dev->dev, offset, value);
 917 }
 918
 919 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
 920 {
 921         return ssb_read32(dev->dev, offset);
 922 }
 923
 924 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
 925 {
 926         ssb_write32(dev->dev, offset, value);
 927 }
 928
 929 static inline bool b43_using_pio_transfers(struct b43_wldev *dev)
 930 {
 931 #ifdef CONFIG_B43_PIO
 932         return dev->__using_pio_transfers;
 933 #else
 934         return 0;
 935 #endif
 936 }
 937
 938 #ifdef CONFIG_B43_FORCE_PIO
 939 # define B43_FORCE_PIO  1
 940 #else
 941 # define B43_FORCE_PIO  0
 942 #endif
 943
 944
 945 /* Message printing */
 946 void b43info(struct b43_wl *wl, const char *fmt, ...)
 947     __attribute__ ((format(printf, 2, 3)));
 948 void b43err(struct b43_wl *wl, const char *fmt, ...)
 949     __attribute__ ((format(printf, 2, 3)));
 950 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 951     __attribute__ ((format(printf, 2, 3)));
 952 #if B43_DEBUG
 953 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 954     __attribute__ ((format(printf, 2, 3)));
 955 #else /* DEBUG */
 956 # define b43dbg(wl, fmt...) do { /* nothing */ } while (0)
 957 #endif /* DEBUG */
 958
 959 /* A WARN_ON variant that vanishes when b43 debugging is disabled.
 960  * This _also_ evaluates the arg with debugging disabled. */
 961 #if B43_DEBUG
 962 # define B43_WARN_ON(x) WARN_ON(x)
 963 #else
 964 static inline bool __b43_warn_on_dummy(bool x) { return x; }
 965 # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x)))
 966 #endif
 967
 968 /* Convert an integer to a Q5.2 value */
 969 #define INT_TO_Q52(i)   ((i) << 2)
 970 /* Convert a Q5.2 value to an integer (precision loss!) */
 971 #define Q52_TO_INT(q52) ((q52) >> 2)
 972 /* Macros for printing a value in Q5.2 format */
 973 #define Q52_FMT         "%u.%u"
 974 #define Q52_ARG(q52)    Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4)
 975
 976 #endif /* B43_H_ */