package/ltq-dsl/src/ifxmips_atm_ppe_common.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_ppe_common.h
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM (ADSL)
   6 **
   7 ** DATE         : 1 AUG 2005
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM Driver (PPE Registers)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 **  4 AUG 2005  Xu Liang        Initiate Version
  22 ** 23 OCT 2006  Xu Liang        Add GPL header.
  23 **  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)
  24 *******************************************************************************/
  25
  26
  27
  28 #ifndef IFXMIPS_ATM_PPE_COMMON_H
  29 #define IFXMIPS_ATM_PPE_COMMON_H
  30 #if defined(CONFIG_DANUBE)
  31   #include "ifxmips_atm_ppe_danube.h"
  32 #elif defined(CONFIG_AMAZON_SE)
  33   #include "ifxmips_atm_ppe_amazon_se.h"
  34 #elif defined(CONFIG_AR9)
  35   #include "ifxmips_atm_ppe_ar9.h"
  36 #elif defined(CONFIG_VR9)
  37   #include "ifxmips_atm_ppe_vr9.h"
  38 #else
  39   #error Platform is not specified!
  40 #endif
  41
  42
  43
  44 /*
  45  *  Code/Data Memory (CDM) Interface Configuration Register
  46  */
  47 #define CDM_CFG                         PPE_REG_ADDR(0x0100)
  48
  49 #define CDM_CFG_RAM1                    GET_BITS(*CDM_CFG, 3, 2)
  50 #define CDM_CFG_RAM0                    (*CDM_CFG & (1 << 1))
  51
  52 #define CDM_CFG_RAM1_SET(value)         SET_BITS(0, 3, 2, value)
  53 #define CDM_CFG_RAM0_SET(value)         ((value) ? (1 << 1) : 0)
  54
  55 /*
  56  *  QSB Internal Cell Delay Variation Register
  57  */
  58 #define QSB_ICDV                        QSB_CONF_REG_ADDR(0x0007)
  59
  60 #define QSB_ICDV_TAU                    GET_BITS(*QSB_ICDV, 5, 0)
  61
  62 #define QSB_ICDV_TAU_SET(value)         SET_BITS(0, 5, 0, value)
  63
  64 /*
  65  *  QSB Scheduler Burst Limit Register
  66  */
  67 #define QSB_SBL                         QSB_CONF_REG_ADDR(0x0009)
  68
  69 #define QSB_SBL_SBL                     GET_BITS(*QSB_SBL, 3, 0)
  70
  71 #define QSB_SBL_SBL_SET(value)          SET_BITS(0, 3, 0, value)
  72
  73 /*
  74  *  QSB Configuration Register
  75  */
  76 #define QSB_CFG                         QSB_CONF_REG_ADDR(0x000A)
  77
  78 #define QSB_CFG_TSTEPC                  GET_BITS(*QSB_CFG, 1, 0)
  79
  80 #define QSB_CFG_TSTEPC_SET(value)       SET_BITS(0, 1, 0, value)
  81
  82 /*
  83  *  QSB RAM Transfer Table Register
  84  */
  85 #define QSB_RTM                         QSB_CONF_REG_ADDR(0x000B)
  86
  87 #define QSB_RTM_DM                      (*QSB_RTM)
  88
  89 #define QSB_RTM_DM_SET(value)           ((value) & 0xFFFFFFFF)
  90
  91 /*
  92  *  QSB RAM Transfer Data Register
  93  */
  94 #define QSB_RTD                         QSB_CONF_REG_ADDR(0x000C)
  95
  96 #define QSB_RTD_TTV                     (*QSB_RTD)
  97
  98 #define QSB_RTD_TTV_SET(value)          ((value) & 0xFFFFFFFF)
  99
 100 /*
 101  *  QSB RAM Access Register
 102  */
 103 #define QSB_RAMAC                       QSB_CONF_REG_ADDR(0x000D)
 104
 105 #define QSB_RAMAC_RW                    (*QSB_RAMAC & (1 << 31))
 106 #define QSB_RAMAC_TSEL                  GET_BITS(*QSB_RAMAC, 27, 24)
 107 #define QSB_RAMAC_LH                    (*QSB_RAMAC & (1 << 16))
 108 #define QSB_RAMAC_TESEL                 GET_BITS(*QSB_RAMAC, 9, 0)
 109
 110 #define QSB_RAMAC_RW_SET(value)         ((value) ? (1 << 31) : 0)
 111 #define QSB_RAMAC_TSEL_SET(value)       SET_BITS(0, 27, 24, value)
 112 #define QSB_RAMAC_LH_SET(value)         ((value) ? (1 << 16) : 0)
 113 #define QSB_RAMAC_TESEL_SET(value)      SET_BITS(0, 9, 0, value)
 114
 115 /*
 116  *  QSB Queue Scheduling and Shaping Definitions
 117  */
 118 #define QSB_WFQ_NONUBR_MAX              0x3f00
 119 #define QSB_WFQ_UBR_BYPASS              0x3fff
 120 #define QSB_TP_TS_MAX                   65472
 121 #define QSB_TAUS_MAX                    64512
 122 #define QSB_GCR_MIN                     18
 123
 124 /*
 125  *  QSB Constant
 126  */
 127 #define QSB_RAMAC_RW_READ               0
 128 #define QSB_RAMAC_RW_WRITE              1
 129
 130 #define QSB_RAMAC_TSEL_QPT              0x01
 131 #define QSB_RAMAC_TSEL_SCT              0x02
 132 #define QSB_RAMAC_TSEL_SPT              0x03
 133 #define QSB_RAMAC_TSEL_VBR              0x08
 134
 135 #define QSB_RAMAC_LH_LOW                0
 136 #define QSB_RAMAC_LH_HIGH               1
 137
 138 #define QSB_QPT_SET_MASK                0x0
 139 #define QSB_QVPT_SET_MASK               0x0
 140 #define QSB_SET_SCT_MASK                0x0
 141 #define QSB_SET_SPT_MASK                0x0
 142 #define QSB_SET_SPT_SBVALID_MASK        0x7FFFFFFF
 143
 144 #define QSB_SPT_SBV_VALID               (1 << 31)
 145 #define QSB_SPT_PN_SET(value)           (((value) & 0x01) ? (1 << 16) : 0)
 146 #define QSB_SPT_INTRATE_SET(value)      SET_BITS(0, 13, 0, value)
 147
 148 /*
 149  *  QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry
 150  */
 151 #if defined(__BIG_ENDIAN)
 152     union qsb_queue_parameter_table {
 153         struct {
 154             unsigned int    res1    :1;
 155             unsigned int    vbr     :1;
 156             unsigned int    wfqf    :14;
 157             unsigned int    tp      :16;
 158         }               bit;
 159         u32             dword;
 160     };
 161
 162     union qsb_queue_vbr_parameter_table {
 163         struct {
 164             unsigned int    taus    :16;
 165             unsigned int    ts      :16;
 166         }               bit;
 167         u32             dword;
 168     };
 169 #else
 170     union qsb_queue_parameter_table {
 171         struct {
 172             unsigned int    tp      :16;
 173             unsigned int    wfqf    :14;
 174             unsigned int    vbr     :1;
 175             unsigned int    res1    :1;
 176         }               bit;
 177         u32             dword;
 178     };
 179
 180     union qsb_queue_vbr_parameter_table {
 181         struct {
 182             unsigned int    ts      :16;
 183             unsigned int    taus    :16;
 184         }               bit;
 185         u32             dword;
 186     };
 187 #endif  //  defined(__BIG_ENDIAN)
 188
 189 /*
 190  *  Mailbox IGU0 Registers
 191  */
 192 #define MBOX_IGU0_ISRS                  PPE_REG_ADDR(0x0200)
 193 #define MBOX_IGU0_ISRC                  PPE_REG_ADDR(0x0201)
 194 #define MBOX_IGU0_ISR                   PPE_REG_ADDR(0x0202)
 195 #define MBOX_IGU0_IER                   PPE_REG_ADDR(0x0203)
 196
 197 #define MBOX_IGU0_ISRS_SET(n)           (1 << (n))
 198 #define MBOX_IGU0_ISRC_CLEAR(n)         (1 << (n))
 199 #define MBOX_IGU0_ISR_ISR(n)            (*MBOX_IGU0_ISR & (1 << (n)))
 200 #define MBOX_IGU0_IER_EN(n)             (*MBOX_IGU0_IER & (1 << (n)))
 201 #define MBOX_IGU0_IER_EN_SET(n)         (1 << (n))
 202
 203 /*
 204  *  Mailbox IGU1 Registers
 205  */
 206 #define MBOX_IGU1_ISRS                  PPE_REG_ADDR(0x0204)
 207 #define MBOX_IGU1_ISRC                  PPE_REG_ADDR(0x0205)
 208 #define MBOX_IGU1_ISR                   PPE_REG_ADDR(0x0206)
 209 #define MBOX_IGU1_IER                   PPE_REG_ADDR(0x0207)
 210
 211 #define MBOX_IGU1_ISRS_SET(n)           (1 << (n))
 212 #define MBOX_IGU1_ISRC_CLEAR(n)         (1 << (n))
 213 #define MBOX_IGU1_ISR_ISR(n)            (*MBOX_IGU1_ISR & (1 << (n)))
 214 #define MBOX_IGU1_IER_EN(n)             (*MBOX_IGU1_IER & (1 << (n)))
 215 #define MBOX_IGU1_IER_EN_SET(n)         (1 << (n))
 216
 217 /*
 218  *  Mailbox IGU3 Registers
 219  */
 220 #define MBOX_IGU3_ISRS                  PPE_REG_ADDR(0x0214)
 221 #define MBOX_IGU3_ISRC                  PPE_REG_ADDR(0x0215)
 222 #define MBOX_IGU3_ISR                   PPE_REG_ADDR(0x0216)
 223 #define MBOX_IGU3_IER                   PPE_REG_ADDR(0x0217)
 224
 225 #define MBOX_IGU3_ISRS_SET(n)           (1 << (n))
 226 #define MBOX_IGU3_ISRC_CLEAR(n)         (1 << (n))
 227 #define MBOX_IGU3_ISR_ISR(n)            (*MBOX_IGU3_ISR & (1 << (n)))
 228 #define MBOX_IGU3_IER_EN(n)             (*MBOX_IGU3_IER & (1 << (n)))
 229 #define MBOX_IGU3_IER_EN_SET(n)         (1 << (n))
 230
 231 /*
 232  *  RTHA/TTHA Registers
 233  */
 234 #define RFBI_CFG                        PPE_REG_ADDR(0x0400)
 235 #define RBA_CFG0                        PPE_REG_ADDR(0x0404)
 236 #define RBA_CFG1                        PPE_REG_ADDR(0x0405)
 237 #define RCA_CFG0                        PPE_REG_ADDR(0x0408)
 238 #define RCA_CFG1                        PPE_REG_ADDR(0x0409)
 239 #define RDES_CFG0                       PPE_REG_ADDR(0x040C)
 240 #define RDES_CFG1                       PPE_REG_ADDR(0x040D)
 241 #define SFSM_STATE0                     PPE_REG_ADDR(0x0410)
 242 #define SFSM_STATE1                     PPE_REG_ADDR(0x0411)
 243 #define SFSM_DBA0                       PPE_REG_ADDR(0x0412)
 244 #define SFSM_DBA1                       PPE_REG_ADDR(0x0413)
 245 #define SFSM_CBA0                       PPE_REG_ADDR(0x0414)
 246 #define SFSM_CBA1                       PPE_REG_ADDR(0x0415)
 247 #define SFSM_CFG0                       PPE_REG_ADDR(0x0416)
 248 #define SFSM_CFG1                       PPE_REG_ADDR(0x0417)
 249 #define SFSM_PGCNT0                     PPE_REG_ADDR(0x041C)
 250 #define SFSM_PGCNT1                     PPE_REG_ADDR(0x041D)
 251 #define FFSM_DBA0                       PPE_REG_ADDR(0x0508)
 252 #define FFSM_DBA1                       PPE_REG_ADDR(0x0509)
 253 #define FFSM_CFG0                       PPE_REG_ADDR(0x050A)
 254 #define FFSM_CFG1                       PPE_REG_ADDR(0x050B)
 255 #define FFSM_IDLE_HEAD_BC0              PPE_REG_ADDR(0x050E)
 256 #define FFSM_IDLE_HEAD_BC1              PPE_REG_ADDR(0x050F)
 257 #define FFSM_PGCNT0                     PPE_REG_ADDR(0x0514)
 258 #define FFSM_PGCNT1                     PPE_REG_ADDR(0x0515)
 259
 260 /*
 261  *  PPE TC Logic Registers (partial)
 262  */
 263 #define DREG_A_VERSION                  PPE_REG_ADDR(0x0D00)
 264 #define DREG_A_CFG                      PPE_REG_ADDR(0x0D01)
 265 #define DREG_AT_CTRL                    PPE_REG_ADDR(0x0D02)
 266 #define DREG_AT_CB_CFG0                 PPE_REG_ADDR(0x0D03)
 267 #define DREG_AT_CB_CFG1                 PPE_REG_ADDR(0x0D04)
 268 #define DREG_AR_CTRL                    PPE_REG_ADDR(0x0D08)
 269 #define DREG_AR_CB_CFG0                 PPE_REG_ADDR(0x0D09)
 270 #define DREG_AR_CB_CFG1                 PPE_REG_ADDR(0x0D0A)
 271 #define DREG_A_UTPCFG                   PPE_REG_ADDR(0x0D0E)
 272 #define DREG_A_STATUS                   PPE_REG_ADDR(0x0D0F)
 273 #define DREG_AT_CFG0                    PPE_REG_ADDR(0x0D20)
 274 #define DREG_AT_CFG1                    PPE_REG_ADDR(0x0D21)
 275 #define DREG_AT_FB_SIZE0                PPE_REG_ADDR(0x0D22)
 276 #define DREG_AT_FB_SIZE1                PPE_REG_ADDR(0x0D23)
 277 #define DREG_AT_CELL0                   PPE_REG_ADDR(0x0D24)
 278 #define DREG_AT_CELL1                   PPE_REG_ADDR(0x0D25)
 279 #define DREG_AT_IDLE_CNT0               PPE_REG_ADDR(0x0D26)
 280 #define DREG_AT_IDLE_CNT1               PPE_REG_ADDR(0x0D27)
 281 #define DREG_AT_IDLE0                   PPE_REG_ADDR(0x0D28)
 282 #define DREG_AT_IDLE1                   PPE_REG_ADDR(0x0D29)
 283 #define DREG_AR_CFG0                    PPE_REG_ADDR(0x0D60)
 284 #define DREG_AR_CFG1                    PPE_REG_ADDR(0x0D61)
 285 #define DREG_AR_CELL0                   PPE_REG_ADDR(0x0D68)
 286 #define DREG_AR_CELL1                   PPE_REG_ADDR(0x0D69)
 287 #define DREG_AR_IDLE_CNT0               PPE_REG_ADDR(0x0D6A)
 288 #define DREG_AR_IDLE_CNT1               PPE_REG_ADDR(0x0D6B)
 289 #define DREG_AR_AIIDLE_CNT0             PPE_REG_ADDR(0x0D6C)
 290 #define DREG_AR_AIIDLE_CNT1             PPE_REG_ADDR(0x0D6D)
 291 #define DREG_AR_BE_CNT0                 PPE_REG_ADDR(0x0D6E)
 292 #define DREG_AR_BE_CNT1                 PPE_REG_ADDR(0x0D6F)
 293 #define DREG_AR_HEC_CNT0                PPE_REG_ADDR(0x0D70)
 294 #define DREG_AR_HEC_CNT1                PPE_REG_ADDR(0x0D71)
 295 #define DREG_AR_IDLE0                   PPE_REG_ADDR(0x0D74)
 296 #define DREG_AR_IDLE1                   PPE_REG_ADDR(0x0D75)
 297 #define DREG_AR_CVN_CNT0                PPE_REG_ADDR(0x0DA4)
 298 #define DREG_AR_CVN_CNT1                PPE_REG_ADDR(0x0DA5)
 299 #define DREG_AR_CVNP_CNT0               PPE_REG_ADDR(0x0DA6)
 300 #define DREG_AR_CVNP_CNT1               PPE_REG_ADDR(0x0DA7)
 301 #define DREG_B0_LADR                    PPE_REG_ADDR(0x0DA8)
 302 #define DREG_B1_LADR                    PPE_REG_ADDR(0x0DA9)
 303
 304 #define SFSM_DBA(i)                     ( (SFSM_dba * )   PPE_REG_ADDR(0x0412 + (i)))
 305 #define SFSM_CBA(i)                     ( (SFSM_cba * )   PPE_REG_ADDR(0x0414 + (i)))
 306 #define SFSM_CFG(i)                     ( (SFSM_cfg * )   PPE_REG_ADDR(0x0416 + (i)))
 307 #define SFSM_PGCNT(i)                   ( (SFSM_pgcnt * ) PPE_REG_ADDR(0x041C + (i)))
 308
 309 #define FFSM_DBA(i)                     ( (FFSM_dba * )   PPE_REG_ADDR(0x0508 + (i)))
 310 #define FFSM_CFG(i)                     ( (FFSM_cfg * )   PPE_REG_ADDR(0x050A + (i)))
 311 #define FFSM_PGCNT(i)                   ( (FFSM_pgcnt * ) PPE_REG_ADDR(0x0514 + (i)))
 312
 313 typedef struct  {
 314     unsigned int    res     : 19;
 315     unsigned int    dbase   : 13;
 316 } SFSM_dba;
 317
 318 typedef struct  {
 319     unsigned int    res     : 19;
 320     unsigned int    cbase   : 13;
 321 } SFSM_cba;
 322
 323 typedef struct  {
 324     unsigned int    res     : 15;
 325     unsigned int    endian  : 1;
 326     unsigned int    idlekeep: 1;
 327     unsigned int    sen     : 1;
 328     unsigned int    res1    : 8;
 329     unsigned int    pnum    : 6;
 330 } SFSM_cfg;
 331
 332 typedef struct  {
 333     unsigned int    res     : 17;
 334     unsigned int    pptr    : 6;
 335     unsigned int    dcmd    : 1;
 336     unsigned int    res1    : 2;
 337     unsigned int    upage   : 6;
 338 } SFSM_pgcnt;
 339
 340 typedef struct  {
 341     unsigned int    res     : 19;
 342     unsigned int    dbase   : 13;
 343 } FFSM_dba;
 344
 345 typedef struct  {
 346     unsigned int    res     : 12;
 347     unsigned int    rstptr  : 1;
 348     unsigned int    clvpage : 1;
 349     unsigned int    fidle   : 1;
 350     unsigned int    endian  : 1;
 351     unsigned int    res1    : 10;
 352     unsigned int    pnum    : 6;
 353 } FFSM_cfg;
 354
 355 typedef struct  {
 356     unsigned int    res     : 17;
 357     unsigned int    ival    : 6;
 358     unsigned int    icmd    : 1;
 359     unsigned int    res1    : 2;
 360     unsigned int    vpage   : 6;
 361 } FFSM_pgcnt;
 362
 363
 364
 365 #endif  //  IFXMIPS_ATM_PPE_COMMON_H