package/ltq-dsl/src/ifxmips_atm_vr9.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_vr9.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <asm/delay.h>
  44
  45 /*
  46  *  Chip Specific Head File
  47  */
  48 #include <ifx_types.h>
  49 #include <ifx_regs.h>
  50 #include <common_routines.h>
  51 #include <ifx_pmu.h>
  52 #include <ifx_rcu.h>
  53 #include "ifxmips_atm_core.h"
  54 #include "ifxmips_atm_fw_vr9.h"
  55
  56
  57
  58 /*
  59  * ####################################
  60  *              Definition
  61  * ####################################
  62  */
  63
  64
  65
  66 /*
  67  * ####################################
  68  *             Declaration
  69  * ####################################
  70  */
  71
  72 /*
  73  *  Hardware Init/Uninit Functions
  74  */
  75 static inline void init_pmu(void);
  76 static inline void uninit_pmu(void);
  77 static inline void reset_ppe(void);
  78 static inline void init_pdma(void);
  79 static inline void init_mailbox(void);
  80 static inline void init_atm_tc(void);
  81 static inline void clear_share_buffer(void);
  82
  83
  84
  85 /*
  86  * ####################################
  87  *            Local Variable
  88  * ####################################
  89  */
  90
  91
  92
  93 /*
  94  * ####################################
  95  *            Local Function
  96  * ####################################
  97  */
  98
  99 static inline void init_pmu(void)
 100 {
 101     //*PMU_PWDCR &= ~((1 << 29) | (1 << 22) | (1 << 21) | (1 << 19) | (1 << 18));
 102     //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
 103     PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
 104     PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
 105     PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
 106     PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
 107     PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
 108     DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);
 109 }
 110
 111 static inline void uninit_pmu(void)
 112 {
 113     PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
 114     PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
 115     PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
 116     PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
 117     PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
 118     DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
 119     //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);
 120 }
 121
 122 static inline void reset_ppe(void)
 123 {
 124 #ifdef MODULE
 125     //  reset PPE
 126     ifx_rcu_rst(IFX_RCU_DOMAIN_DSLDFE, IFX_RCU_MODULE_ATM);
 127     udelay(1000);
 128     ifx_rcu_rst(IFX_RCU_DOMAIN_DSLTC, IFX_RCU_MODULE_ATM);
 129     udelay(1000);
 130     ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
 131     udelay(1000);
 132     *PP32_SRST &= ~0x000303CF;
 133     udelay(1000);
 134     *PP32_SRST |= 0x000303CF;
 135     udelay(1000);
 136 #endif
 137 }
 138
 139 static inline void init_pdma(void)
 140 {
 141     IFX_REG_W32(0x08,       PDMA_CFG);
 142     IFX_REG_W32(0x00203580, SAR_PDMA_RX_CMDBUF_CFG);
 143     IFX_REG_W32(0x004035A0, SAR_PDMA_RX_FW_CMDBUF_CFG);
 144 }
 145
 146 static inline void init_mailbox(void)
 147 {
 148     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 149     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 150     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 151     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 152 }
 153
 154 static inline void init_atm_tc(void)
 155 {
 156     /*  clear sync state    */
 157     *SFSM_STATE0    = 0;
 158     *SFSM_STATE1    = 0;
 159
 160     /*  enable keep IDLE    */
 161 //    *SFSM_CFG0     |= 1 << 15;
 162 //    *SFSM_CFG1     |= 1 << 15;
 163 }
 164
 165 static inline void clear_share_buffer(void)
 166 {
 167     volatile u32 *p;
 168     unsigned int i;
 169
 170     p = SB_RAM0_ADDR(0);
 171     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
 172         IFX_REG_W32(0, p++);
 173
 174     p = SB_RAM6_ADDR(0);
 175     for ( i = 0; i < SB_RAM6_DWLEN; i++ )
 176         IFX_REG_W32(0, p++);
 177 }
 178
 179 /*
 180  *  Description:
 181  *    Download PPE firmware binary code.
 182  *  Input:
 183  *    pp32      --- int, which pp32 core
 184  *    src       --- u32 *, binary code buffer
 185  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 186  *  Output:
 187  *    int       --- IFX_SUCCESS:    Success
 188  *                  else:           Error Code
 189  */
 190 static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 191 {
 192     unsigned int clr, set;
 193     volatile u32 *dest;
 194
 195     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 196         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 197         return IFX_ERROR;
 198
 199     clr = pp32 ? 0xF0 : 0x0F;
 200     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 201         set = pp32 ? (3 << 6): (2 << 2);
 202     else
 203         set = 0x00;
 204     IFX_REG_W32_MASK(clr, set, CDM_CFG);
 205
 206     /*  copy code   */
 207     dest = CDM_CODE_MEMORY(pp32, 0);
 208     while ( code_dword_len-- > 0 )
 209         IFX_REG_W32(*code_src++, dest++);
 210
 211     /*  copy data   */
 212     dest = CDM_DATA_MEMORY(pp32, 0);
 213     while ( data_dword_len-- > 0 )
 214         IFX_REG_W32(*data_src++, dest++);
 215
 216     return IFX_SUCCESS;
 217 }
 218
 219
 220
 221 /*
 222  * ####################################
 223  *           Global Function
 224  * ####################################
 225  */
 226
 227 extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor)
 228 {
 229     ASSERT(major != NULL, "pointer is NULL");
 230     ASSERT(minor != NULL, "pointer is NULL");
 231
 232 #ifdef VER_IN_FIRMWARE
 233     *major = FW_VER_ID->major;
 234     *minor = FW_VER_ID->minor;
 235 #else
 236     *major = ATM_FW_VER_MAJOR;
 237     *minor = ATM_FW_VER_MINOR;
 238 #endif
 239 }
 240
 241 void ifx_atm_init_chip(void)
 242 {
 243     init_pmu();
 244
 245     reset_ppe();
 246
 247     init_pdma();
 248
 249     init_mailbox();
 250
 251     init_atm_tc();
 252
 253     clear_share_buffer();
 254 }
 255
 256 void ifx_atm_uninit_chip(void)
 257 {
 258     uninit_pmu();
 259 }
 260
 261 /*
 262  *  Description:
 263  *    Initialize and start up PP32.
 264  *  Input:
 265  *    none
 266  *  Output:
 267  *    int  --- IFX_SUCCESS: Success
 268  *             else:        Error Code
 269  */
 270 int ifx_pp32_start(int pp32)
 271 {
 272     unsigned int mask = 1 << (pp32 << 4);
 273     int ret;
 274
 275     /*  download firmware   */
 276     ret = pp32_download_code(pp32, firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 277     if ( ret != IFX_SUCCESS )
 278         return ret;
 279
 280     /*  run PP32    */
 281     IFX_REG_W32_MASK(mask, 0, PP32_FREEZE);
 282
 283     /*  idle for a while to let PP32 init itself    */
 284     udelay(10);
 285
 286     return IFX_SUCCESS;
 287 }
 288
 289 /*
 290  *  Description:
 291  *    Halt PP32.
 292  *  Input:
 293  *    none
 294  *  Output:
 295  *    none
 296  */
 297 void ifx_pp32_stop(int pp32)
 298 {
 299     unsigned int mask = 1 << (pp32 << 4);
 300
 301     /*  halt PP32   */
 302     IFX_REG_W32_MASK(0, mask, PP32_FREEZE);
 303 }