2 * Platform driver for the Realtek RTL8366 ethernet switch
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
24 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
25 #include <linux/debugfs.h>
28 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
29 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
30 #define RTL8366_SMI_DRIVER_VER "0.1.1"
32 #define RTL8366S_PHY_NO_MAX 4
33 #define RTL8366S_PHY_PAGE_MAX 7
34 #define RTL8366S_PHY_ADDR_MAX 31
36 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
37 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
39 #define RTL8366_RESET_CTRL_REG 0x0100
40 #define RTL8366_CHIP_CTRL_RESET_HW 1
41 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
43 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
44 #define RTL8366S_CHIP_VERSION_MASK 0xf
45 #define RTL8366S_CHIP_ID_REG 0x0105
46 #define RTL8366S_CHIP_ID_8366 0x8366
48 /* PHY registers control */
49 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
50 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
52 #define RTL8366S_PHY_CTRL_READ 1
53 #define RTL8366S_PHY_CTRL_WRITE 0
55 #define RTL8366S_PHY_REG_MASK 0x1f
56 #define RTL8366S_PHY_PAGE_OFFSET 5
57 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
58 #define RTL8366S_PHY_NO_OFFSET 9
59 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
61 #define RTL8366_SMI_ACK_RETRY_COUNT 5
62 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
64 /* LED control registers */
65 #define RTL8366_LED_BLINKRATE_REG 0x0420
66 #define RTL8366_LED_BLINKRATE_BIT 0
67 #define RTL8366_LED_BLINKRATE_MASK 0x0007
69 #define RTL8366_LED_CTRL_REG 0x0421
70 #define RTL8366_LED_0_1_CTRL_REG 0x0422
71 #define RTL8366_LED_2_3_CTRL_REG 0x0423
73 #define RTL8366S_MIB_COUNT 33
74 #define RTL8366S_GLOBAL_MIB_COUNT 1
75 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
76 #define RTL8366S_MIB_COUNTER_BASE 0x1000
77 #define RTL8366S_MIB_CTRL_REG 0x11F0
78 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
79 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
80 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
82 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
83 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
84 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
87 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
88 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
89 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
90 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
91 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
94 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
95 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
97 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
99 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
100 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
101 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
103 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
106 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
107 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
108 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
109 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
110 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
111 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
112 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
115 #define RTL8366_PORT_NUM_CPU 5
116 #define RTL8366_NUM_PORTS 6
117 #define RTL8366_NUM_VLANS 16
118 #define RTL8366_NUM_LEDGROUPS 4
119 #define RTL8366_NUM_VIDS 4096
120 #define RTL8366S_PRIORITYMAX 7
121 #define RTL8366S_FIDMAX 7
124 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
125 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
126 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
127 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
129 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
130 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
132 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
136 RTL8366_PORT_UNKNOWN | \
139 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
143 RTL8366_PORT_UNKNOWN)
145 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
150 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
153 struct rtl8366s_vlanconfig
{
164 struct rtl8366s_vlan4kentry
{
174 static const char *MIBCOUNTERS
[] = {
177 "EtherStatsUnderSizePkts ",
179 "EtherStatsPkts64Octets ",
180 "EtherStatsPkts65to127Octets ",
181 "EtherStatsPkts128to255Octets ",
182 "EtherStatsPkts256to511Octets ",
183 "EtherStatsPkts512to1023Octets ",
184 "EtherStatsPkts1024to1518Octets ",
185 "EtherOversizeStats ",
186 "EtherStatsJabbers ",
188 "EtherStatsMulticastPkts ",
189 "EtherStatsBroadcastPkts ",
190 "EtherStatsDropEvents ",
191 "Dot3StatsFCSErrors ",
192 "Dot3StatsSymbolErrors ",
193 "Dot3InPauseFrames ",
194 "Dot3ControlInUnknownOpcodes ",
196 "Dot3StatsSingleCollisionFrames ",
197 "Dot3StatMultipleCollisionFrames ",
198 "Dot3sDeferredTransmissions ",
199 "Dot3StatsLateCollisions ",
200 "EtherStatsCollisions ",
201 "Dot3StatsExcessiveCollisions ",
202 "Dot3OutPauseFrames ",
203 "Dot1dBasePortDelayExceededDiscards",
204 "Dot1dTpPortInDiscards ",
206 "IfOutMulticastPkts ",
207 "IfOutBroadcastPkts ",
212 struct device
*parent
;
213 unsigned int gpio_sda
;
214 unsigned int gpio_sck
;
219 struct device
*parent
;
220 struct rtl8366_smi smi
;
221 struct mii_bus
*mii_bus
;
222 int mii_irq
[PHY_MAX_ADDR
];
223 struct switch_dev dev
;
225 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
226 struct dentry
*debugfs_root
;
230 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
234 static inline struct rtl8366s
*sw_to_rtl8366s(struct switch_dev
*sw
)
236 return container_of(sw
, struct rtl8366s
, dev
);
239 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi
*smi
)
241 ndelay(RTL8366_SMI_CLK_DELAY
);
244 static void rtl8366_smi_start(struct rtl8366_smi
*smi
)
246 unsigned int sda
= smi
->gpio_sda
;
247 unsigned int sck
= smi
->gpio_sck
;
250 * Set GPIO pins to output mode, with initial state:
253 gpio_direction_output(sck
, 0);
254 gpio_direction_output(sda
, 1);
255 rtl8366_smi_clk_delay(smi
);
257 /* CLK 1: 0 -> 1, 1 -> 0 */
258 gpio_set_value(sck
, 1);
259 rtl8366_smi_clk_delay(smi
);
260 gpio_set_value(sck
, 0);
261 rtl8366_smi_clk_delay(smi
);
264 gpio_set_value(sck
, 1);
265 rtl8366_smi_clk_delay(smi
);
266 gpio_set_value(sda
, 0);
267 rtl8366_smi_clk_delay(smi
);
268 gpio_set_value(sck
, 0);
269 rtl8366_smi_clk_delay(smi
);
270 gpio_set_value(sda
, 1);
273 static void rtl8366_smi_stop(struct rtl8366_smi
*smi
)
275 unsigned int sda
= smi
->gpio_sda
;
276 unsigned int sck
= smi
->gpio_sck
;
278 rtl8366_smi_clk_delay(smi
);
279 gpio_set_value(sda
, 0);
280 gpio_set_value(sck
, 1);
281 rtl8366_smi_clk_delay(smi
);
282 gpio_set_value(sda
, 1);
283 rtl8366_smi_clk_delay(smi
);
284 gpio_set_value(sck
, 1);
285 rtl8366_smi_clk_delay(smi
);
286 gpio_set_value(sck
, 0);
287 rtl8366_smi_clk_delay(smi
);
288 gpio_set_value(sck
, 1);
291 rtl8366_smi_clk_delay(smi
);
292 gpio_set_value(sck
, 0);
293 rtl8366_smi_clk_delay(smi
);
294 gpio_set_value(sck
, 1);
296 /* set GPIO pins to input mode */
297 gpio_direction_input(sda
);
298 gpio_direction_input(sck
);
301 static void rtl8366_smi_write_bits(struct rtl8366_smi
*smi
, u32 data
, u32 len
)
303 unsigned int sda
= smi
->gpio_sda
;
304 unsigned int sck
= smi
->gpio_sck
;
306 for (; len
> 0; len
--) {
307 rtl8366_smi_clk_delay(smi
);
310 if ( data
& ( 1 << (len
- 1)) )
311 gpio_set_value(sda
, 1);
313 gpio_set_value(sda
, 0);
314 rtl8366_smi_clk_delay(smi
);
317 gpio_set_value(sck
, 1);
318 rtl8366_smi_clk_delay(smi
);
319 gpio_set_value(sck
, 0);
323 static void rtl8366_smi_read_bits(struct rtl8366_smi
*smi
, u32 len
, u32
*data
)
325 unsigned int sda
= smi
->gpio_sda
;
326 unsigned int sck
= smi
->gpio_sck
;
328 gpio_direction_input(sda
);
330 for (*data
= 0; len
> 0; len
--) {
333 rtl8366_smi_clk_delay(smi
);
336 gpio_set_value(sck
, 1);
337 rtl8366_smi_clk_delay(smi
);
338 u
= gpio_get_value(sda
);
339 gpio_set_value(sck
, 0);
341 *data
|= (u
<< (len
- 1));
344 gpio_direction_output(sda
, 0);
347 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi
*smi
)
355 rtl8366_smi_read_bits(smi
, 1, &ack
);
359 if (++retry_cnt
> RTL8366_SMI_ACK_RETRY_COUNT
)
366 static int rtl8366_smi_write_byte(struct rtl8366_smi
*smi
, u8 data
)
368 rtl8366_smi_write_bits(smi
, data
, 8);
369 return rtl8366_smi_wait_for_ack(smi
);
372 static int rtl8366_smi_read_byte0(struct rtl8366_smi
*smi
, u8
*data
)
377 rtl8366_smi_read_bits(smi
, 8, &t
);
381 rtl8366_smi_write_bits(smi
, 0x00, 1);
386 static int rtl8366_smi_read_byte1(struct rtl8366_smi
*smi
, u8
*data
)
391 rtl8366_smi_read_bits(smi
, 8, &t
);
395 rtl8366_smi_write_bits(smi
, 0x01, 1);
400 static int rtl8366_smi_read_reg(struct rtl8366_smi
*smi
, u32 addr
, u32
*data
)
407 spin_lock_irqsave(&smi
->lock
, flags
);
409 rtl8366_smi_start(smi
);
411 /* send READ command */
412 ret
= rtl8366_smi_write_byte(smi
, 0x0a << 4 | 0x04 << 1 | 0x01);
417 ret
= rtl8366_smi_write_byte(smi
, addr
& 0xff);
422 ret
= rtl8366_smi_write_byte(smi
, addr
>> 8);
427 rtl8366_smi_read_byte0(smi
, &lo
);
428 /* read DATA[15:8] */
429 rtl8366_smi_read_byte1(smi
, &hi
);
431 *data
= ((u32
) lo
) | (((u32
) hi
) << 8);
436 rtl8366_smi_stop(smi
);
437 spin_unlock_irqrestore(&smi
->lock
, flags
);
442 static int rtl8366_smi_write_reg(struct rtl8366_smi
*smi
, u32 addr
, u32 data
)
447 spin_lock_irqsave(&smi
->lock
, flags
);
449 rtl8366_smi_start(smi
);
451 /* send WRITE command */
452 ret
= rtl8366_smi_write_byte(smi
, 0x0a << 4 | 0x04 << 1 | 0x00);
457 ret
= rtl8366_smi_write_byte(smi
, addr
& 0xff);
462 ret
= rtl8366_smi_write_byte(smi
, addr
>> 8);
466 /* write DATA[7:0] */
467 ret
= rtl8366_smi_write_byte(smi
, data
& 0xff);
471 /* write DATA[15:8] */
472 ret
= rtl8366_smi_write_byte(smi
, data
>> 8);
479 rtl8366_smi_stop(smi
);
480 spin_unlock_irqrestore(&smi
->lock
, flags
);
485 static int rtl8366_smi_read_phy_reg(struct rtl8366s
*rtl
,
486 u32 phy_no
, u32 page
, u32 addr
, u32
*data
)
488 struct rtl8366_smi
*smi
= &rtl
->smi
;
492 if (phy_no
> RTL8366S_PHY_NO_MAX
)
495 if (page
> RTL8366S_PHY_PAGE_MAX
)
498 if (addr
> RTL8366S_PHY_ADDR_MAX
)
501 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
502 RTL8366S_PHY_CTRL_READ
);
506 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
507 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
508 (addr
& RTL8366S_PHY_REG_MASK
);
510 ret
= rtl8366_smi_write_reg(smi
, reg
, 0);
514 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_PHY_ACCESS_DATA_REG
, data
);
521 static int rtl8366_smi_write_phy_reg(struct rtl8366s
*rtl
,
522 u32 phy_no
, u32 page
, u32 addr
, u32 data
)
524 struct rtl8366_smi
*smi
= &rtl
->smi
;
528 if (phy_no
> RTL8366S_PHY_NO_MAX
)
531 if (page
> RTL8366S_PHY_PAGE_MAX
)
534 if (addr
> RTL8366S_PHY_ADDR_MAX
)
537 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
538 RTL8366S_PHY_CTRL_WRITE
);
542 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
543 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
544 (addr
& RTL8366S_PHY_REG_MASK
);
546 ret
= rtl8366_smi_write_reg(smi
, reg
, data
);
553 static int rtl8366_get_mib_counter(struct rtl8366s
*rtl
, int counter
,
554 int port
, unsigned long long *val
)
556 struct rtl8366_smi
*smi
= &rtl
->smi
;
559 u32 addr
, data
, regoffset
;
562 /* address offset to MIBs counter */
563 const u16 mibLength
[RTL8366S_MIB_COUNT
] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
564 2, 2, 2, 2, 2, 2, 2, 2, 2,
565 2, 2, 4, 2, 2, 2, 2, 2, 2,
568 if (port
> RTL8366_NUM_PORTS
|| counter
>= RTL8366S_MIB_COUNT
)
571 regoffset
= RTL8366S_MIB_COUNTER_PORT_OFFSET
* (port
);
573 for (i
= 0; i
< counter
; i
++)
574 regoffset
+= mibLength
[i
];
576 addr
= RTL8366S_MIB_COUNTER_BASE
+ regoffset
;
579 * Writing access counter address first
580 * then ASIC will prepare 64bits counter wait for being retrived
582 data
= 0; /* writing data will be discard by ASIC */
583 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
587 /* read MIB control register */
588 err
= rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
592 if (data
& RTL8366S_MIB_CTRL_BUSY_MASK
)
595 if (data
& RTL8366S_MIB_CTRL_RESET_MASK
)
599 addr
= addr
+ mibLength
[counter
] - 1;
600 i
= mibLength
[counter
];
603 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
607 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
617 static int rtl8366s_get_vlan_4k_entry(struct rtl8366s
*rtl
, u32 vid
,
618 struct rtl8366s_vlan4kentry
*vlan4k
)
620 struct rtl8366_smi
*smi
= &rtl
->smi
;
625 memset(vlan4k
, '\0', sizeof(struct rtl8366s_vlan4kentry
));
628 if (vid
>= RTL8366_NUM_VIDS
)
631 tableaddr
= (u16
*)vlan4k
;
635 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
639 /* write table access control word */
640 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
641 RTL8366S_TABLE_VLAN_READ_CTRL
);
645 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
, &data
);
652 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
+ 1,
663 static int rtl8366s_set_vlan_4k_entry(struct rtl8366s
*rtl
,
664 const struct rtl8366s_vlan4kentry
*vlan4k
)
666 struct rtl8366_smi
*smi
= &rtl
->smi
;
671 if (vlan4k
->vid
>= RTL8366_NUM_VIDS
||
672 vlan4k
->member
> RTL8366_PORT_ALL
||
673 vlan4k
->untag
> RTL8366_PORT_ALL
||
674 vlan4k
->fid
> RTL8366S_FIDMAX
)
677 tableaddr
= (u16
*)vlan4k
;
681 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
689 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
+ 1,
694 /* write table access control word */
695 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
696 RTL8366S_TABLE_VLAN_WRITE_CTRL
);
701 static int rtl8366s_get_vlan_member_config(struct rtl8366s
*rtl
, u32 index
,
702 struct rtl8366s_vlanconfig
*vlanmc
)
704 struct rtl8366_smi
*smi
= &rtl
->smi
;
710 memset(vlanmc
, '\0', sizeof(struct rtl8366s_vlanconfig
));
712 if (index
>= RTL8366_NUM_VLANS
)
715 tableaddr
= (u16
*)vlanmc
;
717 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
<< 1);
718 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
725 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
<< 1);
726 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
735 static int rtl8366s_set_vlan_member_config(struct rtl8366s
*rtl
, u32 index
,
736 const struct rtl8366s_vlanconfig
739 struct rtl8366_smi
*smi
= &rtl
->smi
;
745 if (index
>= RTL8366_NUM_VLANS
||
746 vlanmc
->vid
>= RTL8366_NUM_VIDS
||
747 vlanmc
->priority
> RTL8366S_PRIORITYMAX
||
748 vlanmc
->member
> RTL8366_PORT_ALL
||
749 vlanmc
->untag
> RTL8366_PORT_ALL
||
750 vlanmc
->fid
> RTL8366S_FIDMAX
)
753 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
<< 1);
755 tableaddr
= (u16
*)vlanmc
;
758 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
762 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
<< 1);
767 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
774 static int rtl8366_get_port_vlan_index(struct rtl8366s
*rtl
, int port
,
777 struct rtl8366_smi
*smi
= &rtl
->smi
;
781 if (port
>= RTL8366_NUM_PORTS
)
784 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
789 *val
= (data
>> RTL8366S_PORT_VLAN_CTRL_SHIFT(port
)) &
790 RTL8366S_PORT_VLAN_CTRL_MASK
;
796 static int rtl8366_get_vlan_port_pvid(struct rtl8366s
*rtl
, int port
,
799 struct rtl8366s_vlanconfig vlanmc
;
803 err
= rtl8366_get_port_vlan_index(rtl
, port
, &index
);
807 err
= rtl8366s_get_vlan_member_config(rtl
, index
, &vlanmc
);
815 static int rtl8366_set_port_vlan_index(struct rtl8366s
*rtl
, int port
,
818 struct rtl8366_smi
*smi
= &rtl
->smi
;
822 if (port
>= RTL8366_NUM_PORTS
|| index
>= RTL8366_NUM_VLANS
)
825 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
830 data
&= ~(RTL8366S_PORT_VLAN_CTRL_MASK
<<
831 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
));
832 data
|= (index
& RTL8366S_PORT_VLAN_CTRL_MASK
) <<
833 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
);
835 err
= rtl8366_smi_write_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
840 static int rtl8366_set_vlan_port_pvid(struct rtl8366s
*rtl
, int port
,
844 struct rtl8366s_vlanconfig vlanmc
;
845 struct rtl8366s_vlan4kentry vlan4k
;
847 if (port
>= RTL8366_NUM_PORTS
|| val
>= RTL8366_NUM_VIDS
)
850 /* Updating the 4K entry; lookup it and change the port member set */
851 rtl8366s_get_vlan_4k_entry(rtl
, val
, &vlan4k
);
852 vlan4k
.member
|= ((1 << port
) | RTL8366_PORT_CPU
);
853 vlan4k
.untag
= RTL8366_PORT_ALL_BUT_CPU
;
854 rtl8366s_set_vlan_4k_entry(rtl
, &vlan4k
);
857 * For the 16 entries more work needs to be done. First see if such
858 * VID is already there and change it
860 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
861 rtl8366s_get_vlan_member_config(rtl
, i
, &vlanmc
);
863 /* Try to find an existing vid and update port member set */
864 if (val
== vlanmc
.vid
) {
865 vlanmc
.member
|= ((1 << port
) | RTL8366_PORT_CPU
);
866 rtl8366s_set_vlan_member_config(rtl
, i
, &vlanmc
);
868 /* Now update PVID register settings */
869 rtl8366_set_port_vlan_index(rtl
, port
, i
);
876 * PVID could not be found from vlan table. Replace unused (one that
877 * has no member ports) with new one
879 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
880 rtl8366s_get_vlan_member_config(rtl
, i
, &vlanmc
);
883 * See if this vlan member configuration is unused. It is
884 * unused if member set contains no ports or CPU port only
886 if (!vlanmc
.member
|| vlanmc
.member
== RTL8366_PORT_CPU
) {
889 vlanmc
.untag
= RTL8366_PORT_ALL_BUT_CPU
;
890 vlanmc
.member
= ((1 << port
) | RTL8366_PORT_CPU
);
893 rtl8366s_set_vlan_member_config(rtl
, i
, &vlanmc
);
895 /* Now update PVID register settings */
896 rtl8366_set_port_vlan_index(rtl
, port
, i
);
903 "All 16 vlan member configurations are in use\n");
909 static int rtl8366_vlan_set_vlan(struct rtl8366s
*rtl
, int enable
)
911 struct rtl8366_smi
*smi
= &rtl
->smi
;
914 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
917 data
|= RTL8366_CHIP_CTRL_VLAN
;
919 data
&= ~RTL8366_CHIP_CTRL_VLAN
;
921 return rtl8366_smi_write_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, data
);
924 static int rtl8366_vlan_set_4ktable(struct rtl8366s
*rtl
, int enable
)
926 struct rtl8366_smi
*smi
= &rtl
->smi
;
929 rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TB_CTRL_REG
, &data
);
936 return rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TB_CTRL_REG
, data
);
939 static int rtl8366s_reset_vlan(struct rtl8366s
*rtl
)
941 struct rtl8366s_vlan4kentry vlan4k
;
942 struct rtl8366s_vlanconfig vlanmc
;
946 /* clear 16 VLAN member configuration */
952 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
953 err
= rtl8366s_set_vlan_member_config(rtl
, i
, &vlanmc
);
958 /* Set a default VLAN with vid 1 to 4K table for all ports */
960 vlan4k
.member
= RTL8366_PORT_ALL
;
961 vlan4k
.untag
= RTL8366_PORT_ALL
;
963 err
= rtl8366s_set_vlan_4k_entry(rtl
, &vlan4k
);
967 /* Set all ports PVID to default VLAN */
968 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
969 err
= rtl8366_set_vlan_port_pvid(rtl
, i
, 0);
977 #ifdef CONFIG_RTL8366_SMI_DEBUG_FS
978 static int rtl8366_debugfs_open(struct inode
*inode
, struct file
*file
)
980 file
->private_data
= inode
->i_private
;
984 static ssize_t
rtl8366_read_debugfs_mibs(struct file
*file
,
985 char __user
*user_buf
,
986 size_t count
, loff_t
*ppos
)
988 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
990 char *buf
= rtl
->buf
;
992 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "MIB Counters:\n");
993 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "Counter"
995 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
998 for (i
= 0; i
< 33; ++i
) {
999 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "%d:%s ",
1001 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
1002 unsigned long long counter
= 0;
1004 if (!rtl8366_get_mib_counter(rtl
, i
, j
, &counter
))
1005 len
+= snprintf(buf
+ len
,
1006 sizeof(rtl
->buf
) - len
,
1009 len
+= snprintf(buf
+ len
,
1010 sizeof(rtl
->buf
) - len
,
1013 if (j
!= RTL8366_NUM_PORTS
- 1) {
1014 if (counter
< 100000)
1015 len
+= snprintf(buf
+ len
,
1016 sizeof(rtl
->buf
) - len
,
1019 len
+= snprintf(buf
+ len
,
1020 sizeof(rtl
->buf
) - len
,
1024 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
1027 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
1029 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
1032 static ssize_t
rtl8366_read_debugfs_vlan(struct file
*file
,
1033 char __user
*user_buf
,
1034 size_t count
, loff_t
*ppos
)
1036 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
1038 char *buf
= rtl
->buf
;
1040 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1041 "VLAN Member Config:\n");
1042 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1043 "\t id \t vid \t prio \t member \t untag \t fid "
1046 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
1047 struct rtl8366s_vlanconfig vlanmc
;
1049 rtl8366s_get_vlan_member_config(rtl
, i
, &vlanmc
);
1051 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1052 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1053 "\t", i
, vlanmc
.vid
, vlanmc
.priority
,
1054 vlanmc
.member
, vlanmc
.untag
, vlanmc
.fid
);
1056 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
1058 if (!rtl8366_get_port_vlan_index(rtl
, j
, &index
)) {
1060 len
+= snprintf(buf
+ len
,
1061 sizeof(rtl
->buf
) - len
,
1065 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
1068 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
1071 static ssize_t
rtl8366_read_debugfs_reg(struct file
*file
,
1072 char __user
*user_buf
,
1073 size_t count
, loff_t
*ppos
)
1075 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
1076 struct rtl8366_smi
*smi
= &rtl
->smi
;
1077 u32 t
, reg
= g_dbg_reg
;
1079 char *buf
= rtl
->buf
;
1081 memset(buf
, '\0', sizeof(rtl
->buf
));
1083 err
= rtl8366_smi_read_reg(smi
, reg
, &t
);
1085 len
+= snprintf(buf
, sizeof(rtl
->buf
),
1086 "Read failed (reg: 0x%04x)\n", reg
);
1087 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
1090 len
+= snprintf(buf
, sizeof(rtl
->buf
), "reg = 0x%04x, val = 0x%04x\n",
1093 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
1096 static ssize_t
rtl8366_write_debugfs_reg(struct file
*file
,
1097 const char __user
*user_buf
,
1098 size_t count
, loff_t
*ppos
)
1100 struct rtl8366s
*rtl
= (struct rtl8366s
*)file
->private_data
;
1101 struct rtl8366_smi
*smi
= &rtl
->smi
;
1103 u32 reg
= g_dbg_reg
;
1106 char *buf
= rtl
->buf
;
1108 len
= min(count
, sizeof(rtl
->buf
) - 1);
1109 if (copy_from_user(buf
, user_buf
, len
)) {
1110 dev_err(rtl
->parent
, "copy from user failed\n");
1115 if (len
> 0 && buf
[len
- 1] == '\n')
1116 buf
[len
- 1] = '\0';
1119 if (strict_strtoul(buf
, 16, &data
)) {
1120 dev_err(rtl
->parent
, "Invalid reg value %s\n", buf
);
1122 err
= rtl8366_smi_write_reg(smi
, reg
, data
);
1124 dev_err(rtl
->parent
,
1125 "writing reg 0x%04x val 0x%04lx failed\n",
1133 static const struct file_operations fops_rtl8366_regs
= {
1134 .read
= rtl8366_read_debugfs_reg
,
1135 .write
= rtl8366_write_debugfs_reg
,
1136 .open
= rtl8366_debugfs_open
,
1137 .owner
= THIS_MODULE
1140 static const struct file_operations fops_rtl8366_vlan
= {
1141 .read
= rtl8366_read_debugfs_vlan
,
1142 .open
= rtl8366_debugfs_open
,
1143 .owner
= THIS_MODULE
1146 static const struct file_operations fops_rtl8366_mibs
= {
1147 .read
= rtl8366_read_debugfs_mibs
,
1148 .open
= rtl8366_debugfs_open
,
1149 .owner
= THIS_MODULE
1152 static void rtl8366_debugfs_init(struct rtl8366s
*rtl
)
1154 struct dentry
*node
;
1155 struct dentry
*root
;
1157 if (!rtl
->debugfs_root
)
1158 rtl
->debugfs_root
= debugfs_create_dir("rtl8366s", NULL
);
1160 if (!rtl
->debugfs_root
) {
1161 dev_err(rtl
->parent
, "Unable to create debugfs dir\n");
1164 root
= rtl
->debugfs_root
;
1166 node
= debugfs_create_x16("reg", S_IRUGO
| S_IWUSR
, root
, &g_dbg_reg
);
1168 dev_err(rtl
->parent
, "Creating debugfs file reg failed\n");
1172 node
= debugfs_create_file("val", S_IRUGO
| S_IWUSR
, root
, rtl
,
1173 &fops_rtl8366_regs
);
1175 dev_err(rtl
->parent
, "Creating debugfs file val failed\n");
1179 node
= debugfs_create_file("vlan", S_IRUSR
, root
, rtl
,
1180 &fops_rtl8366_vlan
);
1182 dev_err(rtl
->parent
,
1183 "Creating debugfs file vlan failed\n");
1187 node
= debugfs_create_file("mibs", S_IRUSR
, root
, rtl
,
1188 &fops_rtl8366_mibs
);
1190 dev_err(rtl
->parent
,
1191 "Creating debugfs file mibs failed\n");
1196 static void rtl8366_debugfs_remove(struct rtl8366s
*rtl
)
1198 if (rtl
->debugfs_root
) {
1199 debugfs_remove_recursive(rtl
->debugfs_root
);
1200 rtl
->debugfs_root
= NULL
;
1205 static inline void rtl8366_debugfs_init(struct rtl8366s
*rtl
) {}
1206 static inline void rtl8366_debugfs_remove(struct rtl8366s
*rtl
) {}
1207 #endif /* CONFIG_RTL8366_SMI_DEBUG_FS */
1209 static int rtl8366_sw_reset_mibs(struct switch_dev
*dev
,
1210 const struct switch_attr
*attr
,
1211 struct switch_val
*val
)
1213 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1214 struct rtl8366_smi
*smi
= &rtl
->smi
;
1217 if (val
->value
.i
== 1) {
1218 rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
1220 rtl8366_smi_write_reg(smi
, RTL8366S_MIB_CTRL_REG
, data
);
1226 static int rtl8366_sw_get_vlan_enable(struct switch_dev
*dev
,
1227 const struct switch_attr
*attr
,
1228 struct switch_val
*val
)
1230 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1231 struct rtl8366_smi
*smi
= &rtl
->smi
;
1234 if (attr
->ofs
== 1) {
1235 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
1237 if (data
& RTL8366_CHIP_CTRL_VLAN
)
1241 } else if (attr
->ofs
== 2) {
1242 rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TB_CTRL_REG
, &data
);
1253 static int rtl8366_sw_get_blinkrate(struct switch_dev
*dev
,
1254 const struct switch_attr
*attr
,
1255 struct switch_val
*val
)
1257 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1258 struct rtl8366_smi
*smi
= &rtl
->smi
;
1261 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1263 val
->value
.i
= (data
& (RTL8366_LED_BLINKRATE_MASK
));
1268 static int rtl8366_sw_set_blinkrate(struct switch_dev
*dev
,
1269 const struct switch_attr
*attr
,
1270 struct switch_val
*val
)
1272 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1273 struct rtl8366_smi
*smi
= &rtl
->smi
;
1276 if (val
->value
.i
>= 6)
1279 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1281 data
&= ~RTL8366_LED_BLINKRATE_MASK
;
1282 data
|= val
->value
.i
;
1284 rtl8366_smi_write_reg(smi
, RTL8366_LED_BLINKRATE_REG
, data
);
1289 static int rtl8366_sw_set_vlan_enable(struct switch_dev
*dev
,
1290 const struct switch_attr
*attr
,
1291 struct switch_val
*val
)
1293 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1296 return rtl8366_vlan_set_vlan(rtl
, val
->value
.i
);
1298 return rtl8366_vlan_set_4ktable(rtl
, val
->value
.i
);
1301 static const char *rtl8366_speed_str(unsigned speed
)
1315 static int rtl8366_sw_get_port_link(struct switch_dev
*dev
,
1316 const struct switch_attr
*attr
,
1317 struct switch_val
*val
)
1319 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1320 struct rtl8366_smi
*smi
= &rtl
->smi
;
1321 u32 len
= 0, data
= 0;
1323 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1326 memset(rtl
->buf
, '\0', sizeof(rtl
->buf
));
1327 rtl8366_smi_read_reg(smi
, RTL8366S_PORT_LINK_STATUS_BASE
+
1328 (val
->port_vlan
/ 2), &data
);
1330 if (val
->port_vlan
% 2)
1333 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
),
1334 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1336 (data
& RTL8366S_PORT_STATUS_LINK_MASK
) ? "up" : "down",
1337 rtl8366_speed_str(data
&
1338 RTL8366S_PORT_STATUS_SPEED_MASK
),
1339 (data
& RTL8366S_PORT_STATUS_DUPLEX_MASK
) ?
1341 (data
& RTL8366S_PORT_STATUS_TXPAUSE_MASK
) ?
1343 (data
& RTL8366S_PORT_STATUS_RXPAUSE_MASK
) ?
1345 (data
& RTL8366S_PORT_STATUS_AN_MASK
) ? "nway ": "");
1347 val
->value
.s
= rtl
->buf
;
1353 static int rtl8366_sw_get_vlan_info(struct switch_dev
*dev
,
1354 const struct switch_attr
*attr
,
1355 struct switch_val
*val
)
1359 struct rtl8366s_vlanconfig vlanmc
;
1360 struct rtl8366s_vlan4kentry vlan4k
;
1361 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1362 char *buf
= rtl
->buf
;
1364 if (val
->port_vlan
>= RTL8366_NUM_VLANS
)
1367 memset(buf
, '\0', sizeof(rtl
->buf
));
1369 rtl8366s_get_vlan_member_config(rtl
, val
->port_vlan
, &vlanmc
);
1370 rtl8366s_get_vlan_4k_entry(rtl
, vlanmc
.vid
, &vlan4k
);
1372 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "VLAN %d: Ports: ",
1375 for (i
= 0; i
< RTL8366_NUM_PORTS
; ++i
) {
1377 if (!rtl8366_get_port_vlan_index(rtl
, i
, &index
) &&
1378 index
== val
->port_vlan
)
1379 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1382 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
1384 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1385 "\t\t vid \t prio \t member \t untag \t fid\n");
1386 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\tMC:\t");
1387 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1388 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1389 vlanmc
.vid
, vlanmc
.priority
, vlanmc
.member
,
1390 vlanmc
.untag
, vlanmc
.fid
);
1391 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\t4K:\t");
1392 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1393 "%d \t \t 0x%04x \t 0x%04x \t %d",
1394 vlan4k
.vid
, vlan4k
.member
, vlan4k
.untag
, vlan4k
.fid
);
1402 static int rtl8366_sw_set_port_led(struct switch_dev
*dev
,
1403 const struct switch_attr
*attr
,
1404 struct switch_val
*val
)
1406 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1407 struct rtl8366_smi
*smi
= &rtl
->smi
;
1410 if (val
->port_vlan
>= RTL8366_NUM_PORTS
||
1411 (1 << val
->port_vlan
) == RTL8366_PORT_UNKNOWN
)
1414 if (val
->port_vlan
== RTL8366_PORT_NUM_CPU
) {
1415 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1416 data
= (data
& (~(0xF << 4))) | (val
->value
.i
<< 4);
1417 rtl8366_smi_write_reg(smi
, RTL8366_LED_BLINKRATE_REG
, data
);
1419 rtl8366_smi_read_reg(smi
, RTL8366_LED_CTRL_REG
, &data
);
1420 data
= (data
& (~(0xF << (val
->port_vlan
* 4)))) |
1421 (val
->value
.i
<< (val
->port_vlan
* 4));
1422 rtl8366_smi_write_reg(smi
, RTL8366_LED_CTRL_REG
, data
);
1428 static int rtl8366_sw_get_port_led(struct switch_dev
*dev
,
1429 const struct switch_attr
*attr
,
1430 struct switch_val
*val
)
1432 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1433 struct rtl8366_smi
*smi
= &rtl
->smi
;
1436 if (val
->port_vlan
>= RTL8366_NUM_LEDGROUPS
)
1439 rtl8366_smi_read_reg(smi
, RTL8366_LED_CTRL_REG
, &data
);
1440 val
->value
.i
= (data
>> (val
->port_vlan
* 4)) & 0x000F;
1445 static int rtl8366_sw_reset_port_mibs(struct switch_dev
*dev
,
1446 const struct switch_attr
*attr
,
1447 struct switch_val
*val
)
1449 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1450 struct rtl8366_smi
*smi
= &rtl
->smi
;
1453 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1456 rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
1457 data
|= (1 << (val
->port_vlan
+ 3));
1458 rtl8366_smi_write_reg(smi
, RTL8366S_MIB_CTRL_REG
, data
);
1463 static int rtl8366_sw_get_port_mib(struct switch_dev
*dev
,
1464 const struct switch_attr
*attr
,
1465 struct switch_val
*val
)
1467 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1469 unsigned long long counter
= 0;
1470 char *buf
= rtl
->buf
;
1472 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1475 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1476 "Port %d MIB counters\n",
1479 for (i
= 0; i
< RTL8366S_MIB_COUNT
; ++i
) {
1480 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1481 "%d:%s\t", i
, MIBCOUNTERS
[i
]);
1482 if (!rtl8366_get_mib_counter(rtl
, i
, val
->port_vlan
, &counter
))
1483 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1484 "[%llu]\n", counter
);
1486 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1495 static int rtl8366_sw_get_vlan_ports(struct switch_dev
*dev
,
1496 struct switch_val
*val
)
1498 struct rtl8366s_vlanconfig vlanmc
;
1499 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1500 struct switch_port
*port
;
1503 if (val
->port_vlan
>= RTL8366_NUM_VLANS
)
1506 rtl8366s_get_vlan_member_config(rtl
, val
->port_vlan
, &vlanmc
);
1508 port
= &val
->value
.ports
[0];
1510 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
1511 if (!(vlanmc
.member
& BIT(i
)))
1515 port
->flags
= (vlanmc
.untag
& BIT(i
)) ?
1516 0 : BIT(SWITCH_PORT_FLAG_TAGGED
);
1523 static int rtl8366_sw_set_vlan_ports(struct switch_dev
*dev
,
1524 struct switch_val
*val
)
1526 struct rtl8366s_vlanconfig vlanmc
;
1527 struct rtl8366s_vlan4kentry vlan4k
;
1528 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1529 struct switch_port
*port
;
1532 if (val
->port_vlan
>= RTL8366_NUM_VLANS
)
1535 rtl8366s_get_vlan_member_config(rtl
, val
->port_vlan
, &vlanmc
);
1536 rtl8366s_get_vlan_4k_entry(rtl
, vlanmc
.vid
, &vlan4k
);
1541 port
= &val
->value
.ports
[0];
1542 for (i
= 0; i
< val
->len
; i
++, port
++) {
1543 vlanmc
.member
|= BIT(port
->id
);
1545 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)))
1546 vlanmc
.untag
|= BIT(port
->id
);
1549 vlan4k
.member
= vlanmc
.member
;
1550 vlan4k
.untag
= vlanmc
.untag
;
1552 rtl8366s_set_vlan_member_config(rtl
, val
->port_vlan
, &vlanmc
);
1553 rtl8366s_set_vlan_4k_entry(rtl
, &vlan4k
);
1557 static int rtl8366_sw_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
1559 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1560 return rtl8366_get_vlan_port_pvid(rtl
, port
, val
);
1563 static int rtl8366_sw_set_port_pvid(struct switch_dev
*dev
, int port
, int val
)
1565 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1566 return rtl8366_set_vlan_port_pvid(rtl
, port
, val
);
1569 static int rtl8366_sw_reset_switch(struct switch_dev
*dev
)
1571 struct rtl8366s
*rtl
= sw_to_rtl8366s(dev
);
1572 struct rtl8366_smi
*smi
= &rtl
->smi
;
1576 rtl8366_smi_write_reg(smi
, RTL8366_RESET_CTRL_REG
,
1577 RTL8366_CHIP_CTRL_RESET_HW
);
1580 if (rtl8366_smi_read_reg(smi
, RTL8366_RESET_CTRL_REG
, &data
))
1583 if (!(data
& RTL8366_CHIP_CTRL_RESET_HW
))
1585 } while (--timeout
);
1588 printk("Timeout waiting for the switch to reset\n");
1592 return rtl8366s_reset_vlan(rtl
);
1595 static struct switch_attr rtl8366_globals
[] = {
1597 .type
= SWITCH_TYPE_INT
,
1598 .name
= "enable_vlan",
1599 .description
= "Enable VLAN mode",
1600 .set
= rtl8366_sw_set_vlan_enable
,
1601 .get
= rtl8366_sw_get_vlan_enable
,
1605 .type
= SWITCH_TYPE_INT
,
1606 .name
= "enable_vlan4k",
1607 .description
= "Enable VLAN 4K mode",
1608 .set
= rtl8366_sw_set_vlan_enable
,
1609 .get
= rtl8366_sw_get_vlan_enable
,
1613 .type
= SWITCH_TYPE_INT
,
1614 .name
= "reset_mibs",
1615 .description
= "Reset all MIB counters",
1616 .set
= rtl8366_sw_reset_mibs
,
1620 .type
= SWITCH_TYPE_INT
,
1621 .name
= "blinkrate",
1622 .description
= "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1623 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1624 .set
= rtl8366_sw_set_blinkrate
,
1625 .get
= rtl8366_sw_get_blinkrate
,
1630 static struct switch_attr rtl8366_port
[] = {
1632 .type
= SWITCH_TYPE_STRING
,
1634 .description
= "Get port link information",
1637 .get
= rtl8366_sw_get_port_link
,
1639 .type
= SWITCH_TYPE_INT
,
1640 .name
= "reset_mib",
1641 .description
= "Reset single port MIB counters",
1643 .set
= rtl8366_sw_reset_port_mibs
,
1646 .type
= SWITCH_TYPE_STRING
,
1648 .description
= "Get MIB counters for port",
1651 .get
= rtl8366_sw_get_port_mib
,
1653 .type
= SWITCH_TYPE_INT
,
1655 .description
= "Get/Set port group (0 - 3) led mode (0 - 15)",
1657 .set
= rtl8366_sw_set_port_led
,
1658 .get
= rtl8366_sw_get_port_led
,
1662 static struct switch_attr rtl8366_vlan
[] = {
1664 .type
= SWITCH_TYPE_STRING
,
1666 .description
= "Get vlan information",
1669 .get
= rtl8366_sw_get_vlan_info
,
1675 static struct switch_dev rtldev
= {
1677 .cpu_port
= RTL8366_PORT_NUM_CPU
,
1678 .ports
= RTL8366_NUM_PORTS
,
1679 .vlans
= RTL8366_NUM_VLANS
,
1681 .attr
= rtl8366_globals
,
1682 .n_attr
= ARRAY_SIZE(rtl8366_globals
),
1685 .attr
= rtl8366_port
,
1686 .n_attr
= ARRAY_SIZE(rtl8366_port
),
1689 .attr
= rtl8366_vlan
,
1690 .n_attr
= ARRAY_SIZE(rtl8366_vlan
),
1693 .get_vlan_ports
= rtl8366_sw_get_vlan_ports
,
1694 .set_vlan_ports
= rtl8366_sw_set_vlan_ports
,
1695 .get_port_pvid
= rtl8366_sw_get_port_pvid
,
1696 .set_port_pvid
= rtl8366_sw_set_port_pvid
,
1697 .reset_switch
= rtl8366_sw_reset_switch
,
1700 static int rtl8366_smi_switch_init(struct rtl8366s
*rtl
)
1702 struct switch_dev
*dev
= &rtl
->dev
;
1705 memcpy(dev
, &rtldev
, sizeof(struct switch_dev
));
1707 dev
->devname
= dev_name(rtl
->parent
);
1709 err
= register_switch(dev
, NULL
);
1711 dev_err(rtl
->parent
, "switch registration failed\n");
1716 static void rtl8366_smi_switch_cleanup(struct rtl8366s
*rtl
)
1718 unregister_switch(&rtl
->dev
);
1721 static int rtl8366_smi_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
1723 struct rtl8366s
*rtl
= bus
->priv
;
1727 err
= rtl8366_smi_read_phy_reg(rtl
, addr
, 0, reg
, &val
);
1734 static int rtl8366_smi_mii_write(struct mii_bus
*bus
, int addr
, int reg
,
1737 struct rtl8366s
*rtl
= bus
->priv
;
1741 err
= rtl8366_smi_write_phy_reg(rtl
, addr
, 0, reg
, val
);
1743 (void) rtl8366_smi_read_phy_reg(rtl
, addr
, 0, reg
, &t
);
1748 static int rtl8366_smi_mii_init(struct rtl8366s
*rtl
)
1753 rtl
->mii_bus
= mdiobus_alloc();
1754 if (rtl
->mii_bus
== NULL
) {
1759 rtl
->mii_bus
->priv
= (void *) rtl
;
1760 rtl
->mii_bus
->name
= "rtl8366-rtl";
1761 rtl
->mii_bus
->read
= rtl8366_smi_mii_read
;
1762 rtl
->mii_bus
->write
= rtl8366_smi_mii_write
;
1763 snprintf(rtl
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s",
1764 dev_name(rtl
->parent
));
1765 rtl
->mii_bus
->parent
= rtl
->parent
;
1766 rtl
->mii_bus
->phy_mask
= ~(0x1f);
1767 rtl
->mii_bus
->irq
= rtl
->mii_irq
;
1768 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1769 rtl
->mii_irq
[i
] = PHY_POLL
;
1771 ret
= mdiobus_register(rtl
->mii_bus
);
1778 mdiobus_free(rtl
->mii_bus
);
1783 static void rtl8366_smi_mii_cleanup(struct rtl8366s
*rtl
)
1785 mdiobus_unregister(rtl
->mii_bus
);
1786 mdiobus_free(rtl
->mii_bus
);
1789 static int rtl8366_smi_mii_bus_match(struct mii_bus
*bus
)
1791 return (bus
->read
== rtl8366_smi_mii_read
&&
1792 bus
->write
== rtl8366_smi_mii_write
);
1795 static int rtl8366_smi_setup(struct rtl8366s
*rtl
)
1797 struct rtl8366_smi
*smi
= &rtl
->smi
;
1802 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_ID_REG
, &chip_id
);
1804 dev_err(rtl
->parent
, "unable to read chip id\n");
1809 case RTL8366S_CHIP_ID_8366
:
1812 dev_err(rtl
->parent
, "unknown chip id (%04x)\n", chip_id
);
1816 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_VERSION_CTRL_REG
,
1819 dev_err(rtl
->parent
, "unable to read chip version\n");
1823 dev_info(rtl
->parent
, "RTL%04x ver. %u chip found\n",
1824 chip_id
, chip_ver
& RTL8366S_CHIP_VERSION_MASK
);
1826 rtl8366_debugfs_init(rtl
);
1831 static int __init
rtl8366_smi_init(struct rtl8366_smi
*smi
)
1838 err
= gpio_request(smi
->gpio_sda
, dev_name(smi
->parent
));
1840 dev_err(smi
->parent
, "gpio_request failed for %u, err=%d\n",
1841 smi
->gpio_sda
, err
);
1845 err
= gpio_request(smi
->gpio_sck
, dev_name(smi
->parent
));
1847 dev_err(smi
->parent
, "gpio_request failed for %u, err=%d\n",
1848 smi
->gpio_sck
, err
);
1852 spin_lock_init(&smi
->lock
);
1854 dev_info(smi
->parent
, "using GPIO pins %u (SDA) and %u (SCK)\n",
1855 smi
->gpio_sda
, smi
->gpio_sck
);
1860 gpio_free(smi
->gpio_sda
);
1865 static void rtl8366_smi_cleanup(struct rtl8366_smi
*smi
)
1867 gpio_free(smi
->gpio_sck
);
1868 gpio_free(smi
->gpio_sda
);
1871 static int __init
rtl8366_smi_probe(struct platform_device
*pdev
)
1873 static int rtl8366_smi_version_printed
;
1874 struct rtl8366_smi_platform_data
*pdata
;
1875 struct rtl8366s
*rtl
;
1876 struct rtl8366_smi
*smi
;
1879 if (!rtl8366_smi_version_printed
++)
1880 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1881 " version " RTL8366_SMI_DRIVER_VER
"\n");
1883 pdata
= pdev
->dev
.platform_data
;
1885 dev_err(&pdev
->dev
, "no platform data specified\n");
1890 rtl
= kzalloc(sizeof(*rtl
), GFP_KERNEL
);
1892 dev_err(&pdev
->dev
, "no memory for private data\n");
1897 rtl
->parent
= &pdev
->dev
;
1900 smi
->parent
= &pdev
->dev
;
1901 smi
->gpio_sda
= pdata
->gpio_sda
;
1902 smi
->gpio_sck
= pdata
->gpio_sck
;
1904 err
= rtl8366_smi_init(smi
);
1908 platform_set_drvdata(pdev
, rtl
);
1910 err
= rtl8366_smi_setup(rtl
);
1912 goto err_clear_drvdata
;
1914 err
= rtl8366_smi_mii_init(rtl
);
1916 goto err_clear_drvdata
;
1918 err
= rtl8366_smi_switch_init(rtl
);
1920 goto err_mii_cleanup
;
1925 rtl8366_smi_mii_cleanup(rtl
);
1927 platform_set_drvdata(pdev
, NULL
);
1928 rtl8366_smi_cleanup(smi
);
1935 static int rtl8366_phy_config_init(struct phy_device
*phydev
)
1937 if (!rtl8366_smi_mii_bus_match(phydev
->bus
))
1943 static int rtl8366_phy_config_aneg(struct phy_device
*phydev
)
1948 static struct phy_driver rtl8366_smi_phy_driver
= {
1949 .phy_id
= 0x001cc960,
1950 .name
= "Realtek RTL8366",
1951 .phy_id_mask
= 0x1ffffff0,
1952 .features
= PHY_GBIT_FEATURES
,
1953 .config_aneg
= rtl8366_phy_config_aneg
,
1954 .config_init
= rtl8366_phy_config_init
,
1955 .read_status
= genphy_read_status
,
1957 .owner
= THIS_MODULE
,
1961 static int __devexit
rtl8366_smi_remove(struct platform_device
*pdev
)
1963 struct rtl8366s
*rtl
= platform_get_drvdata(pdev
);
1966 rtl8366_smi_switch_cleanup(rtl
);
1967 rtl8366_debugfs_remove(rtl
);
1968 rtl8366_smi_mii_cleanup(rtl
);
1969 platform_set_drvdata(pdev
, NULL
);
1970 rtl8366_smi_cleanup(&rtl
->smi
);
1977 static struct platform_driver rtl8366_smi_driver
= {
1979 .name
= RTL8366_SMI_DRIVER_NAME
,
1980 .owner
= THIS_MODULE
,
1982 .probe
= rtl8366_smi_probe
,
1983 .remove
= __devexit_p(rtl8366_smi_remove
),
1986 static int __init
rtl8366_smi_module_init(void)
1989 ret
= platform_driver_register(&rtl8366_smi_driver
);
1993 ret
= phy_driver_register(&rtl8366_smi_phy_driver
);
1995 goto err_platform_unregister
;
1999 err_platform_unregister
:
2000 platform_driver_unregister(&rtl8366_smi_driver
);
2003 module_init(rtl8366_smi_module_init
);
2005 static void __exit
rtl8366_smi_exit(void)
2007 phy_driver_unregister(&rtl8366_smi_phy_driver
);
2008 platform_driver_unregister(&rtl8366_smi_driver
);
2010 module_exit(rtl8366_smi_exit
);
2012 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC
);
2013 MODULE_VERSION(RTL8366_SMI_DRIVER_VER
);
2014 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
2015 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
2016 MODULE_LICENSE("GPL v2");
2017 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME
);