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This patch is for broadcom 96348GW-11 boards, to get USB and Ethernet working. Also...
[openwrt.git] / package / uboot-ifxmips / files / cpu / mips / danube / au1x00_usb_ohci.c
1 /*
2 * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
3 *
4 * (C) Copyright 2003
5 * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 * Note: Part of this code has been derived from linux
26 *
27 */
28 /*
29 * IMPORTANT NOTES
30 * 1 - you MUST define LITTLEENDIAN in the configuration file for the
31 * board or this driver will NOT work!
32 * 2 - this driver is intended for use with USB Mass Storage Devices
33 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
34 */
35
36 #include <config.h>
37
38 #if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
39
40 /* #include <pci.h> no PCI on the AU1x00 */
41
42 #include <common.h>
43 #include <malloc.h>
44 #include <asm/io.h>
45 #include <asm/au1x00.h>
46 #include <usb.h>
47 #include "au1x00_usb_ohci.h"
48
49 #define OHCI_USE_NPS /* force NoPowerSwitching mode */
50 #define OHCI_VERBOSE_DEBUG /* not always helpful */
51 #define OHCI_FILL_TRACE
52
53 #define USBH_ENABLE_BE (1<<0)
54 #define USBH_ENABLE_C (1<<1)
55 #define USBH_ENABLE_E (1<<2)
56 #define USBH_ENABLE_CE (1<<3)
57 #define USBH_ENABLE_RD (1<<4)
58
59 #ifdef LITTLEENDIAN
60 #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
61 #else
62 #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
63 #endif
64
65
66 /* For initializing controller (mask in an HCFS mode too) */
67 #define OHCI_CONTROL_INIT \
68 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
69
70 #undef readl
71 #undef writel
72
73 #define readl(a) au_readl((long)(a))
74 #define writel(v,a) au_writel((v),(int)(a))
75
76 #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
77
78 #define DEBUG
79 #ifdef DEBUG
80 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
81 #else
82 #define dbg(format, arg...) do {} while(0)
83 #endif /* DEBUG */
84 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
85 #define SHOW_INFO
86 #ifdef SHOW_INFO
87 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
88 #else
89 #define info(format, arg...) do {} while(0)
90 #endif
91
92 #define m16_swap(x) swap_16(x)
93 #define m32_swap(x) swap_32(x)
94
95 /* global ohci_t */
96 static ohci_t gohci;
97 /* this must be aligned to a 256 byte boundary */
98 struct ohci_hcca ghcca[1];
99 /* a pointer to the aligned storage */
100 struct ohci_hcca *phcca;
101 /* this allocates EDs for all possible endpoints */
102 struct ohci_device ohci_dev;
103 /* urb_priv */
104 urb_priv_t urb_priv;
105 /* RHSC flag */
106 int got_rhsc;
107 /* device which was disconnected */
108 struct usb_device *devgone;
109
110 /*-------------------------------------------------------------------------*/
111
112 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
113 * The erratum (#4) description is incorrect. AMD's workaround waits
114 * till some bits (mostly reserved) are clear; ok for all revs.
115 */
116 #define OHCI_QUIRK_AMD756 0xabcd
117 #define read_roothub(hc, register, mask) ({ \
118 u32 temp = readl (&hc->regs->roothub.register); \
119 if (hc->flags & OHCI_QUIRK_AMD756) \
120 while (temp & mask) \
121 temp = readl (&hc->regs->roothub.register); \
122 temp; })
123
124 static u32 roothub_a (struct ohci *hc)
125 { return read_roothub (hc, a, 0xfc0fe000); }
126 static inline u32 roothub_b (struct ohci *hc)
127 { return readl (&hc->regs->roothub.b); }
128 static inline u32 roothub_status (struct ohci *hc)
129 { return readl (&hc->regs->roothub.status); }
130 static u32 roothub_portstatus (struct ohci *hc, int i)
131 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
132
133
134 /* forward declaration */
135 static int hc_interrupt (void);
136 static void
137 td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
138 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
139
140 /*-------------------------------------------------------------------------*
141 * URB support functions
142 *-------------------------------------------------------------------------*/
143
144 /* free HCD-private data associated with this URB */
145
146 static void urb_free_priv (urb_priv_t * urb)
147 {
148 int i;
149 int last;
150 struct td * td;
151
152 last = urb->length - 1;
153 if (last >= 0) {
154 for (i = 0; i <= last; i++) {
155 td = urb->td[i];
156 if (td) {
157 td->usb_dev = NULL;
158 urb->td[i] = NULL;
159 }
160 }
161 }
162 }
163
164 /*-------------------------------------------------------------------------*/
165
166 #ifdef DEBUG
167 static int sohci_get_current_frame_number (struct usb_device * dev);
168
169 /* debug| print the main components of an URB
170 * small: 0) header + data packets 1) just header */
171
172 static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
173 int transfer_len, struct devrequest * setup, char * str, int small)
174 {
175 urb_priv_t * purb = &urb_priv;
176
177 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
178 str,
179 sohci_get_current_frame_number (dev),
180 usb_pipedevice (pipe),
181 usb_pipeendpoint (pipe),
182 usb_pipeout (pipe)? 'O': 'I',
183 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
184 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
185 purb->actual_length,
186 transfer_len, dev->status);
187 #ifdef OHCI_VERBOSE_DEBUG
188 if (!small) {
189 int i, len;
190
191 if (usb_pipecontrol (pipe)) {
192 printf (__FILE__ ": cmd(8):");
193 for (i = 0; i < 8 ; i++)
194 printf (" %02x", ((__u8 *) setup) [i]);
195 printf ("\n");
196 }
197 if (transfer_len > 0 && buffer) {
198 printf (__FILE__ ": data(%d/%d):",
199 purb->actual_length,
200 transfer_len);
201 len = usb_pipeout (pipe)?
202 transfer_len: purb->actual_length;
203 for (i = 0; i < 16 && i < len; i++)
204 printf (" %02x", ((__u8 *) buffer) [i]);
205 printf ("%s\n", i < len? "...": "");
206 }
207 }
208 #endif
209 }
210
211 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
212 void ep_print_int_eds (ohci_t *ohci, char * str) {
213 int i, j;
214 __u32 * ed_p;
215 for (i= 0; i < 32; i++) {
216 j = 5;
217 ed_p = &(ohci->hcca->int_table [i]);
218 if (*ed_p == 0)
219 continue;
220 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
221 while (*ed_p != 0 && j--) {
222 ed_t *ed = (ed_t *)m32_swap(ed_p);
223 printf (" ed: %4x;", ed->hwINFO);
224 ed_p = &ed->hwNextED;
225 }
226 printf ("\n");
227 }
228 }
229
230 static void ohci_dump_intr_mask (char *label, __u32 mask)
231 {
232 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
233 label,
234 mask,
235 (mask & OHCI_INTR_MIE) ? " MIE" : "",
236 (mask & OHCI_INTR_OC) ? " OC" : "",
237 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
238 (mask & OHCI_INTR_FNO) ? " FNO" : "",
239 (mask & OHCI_INTR_UE) ? " UE" : "",
240 (mask & OHCI_INTR_RD) ? " RD" : "",
241 (mask & OHCI_INTR_SF) ? " SF" : "",
242 (mask & OHCI_INTR_WDH) ? " WDH" : "",
243 (mask & OHCI_INTR_SO) ? " SO" : ""
244 );
245 }
246
247 static void maybe_print_eds (char *label, __u32 value)
248 {
249 ed_t *edp = (ed_t *)value;
250
251 if (value) {
252 dbg ("%s %08x", label, value);
253 dbg ("%08x", edp->hwINFO);
254 dbg ("%08x", edp->hwTailP);
255 dbg ("%08x", edp->hwHeadP);
256 dbg ("%08x", edp->hwNextED);
257 }
258 }
259
260 static char * hcfs2string (int state)
261 {
262 switch (state) {
263 case OHCI_USB_RESET: return "reset";
264 case OHCI_USB_RESUME: return "resume";
265 case OHCI_USB_OPER: return "operational";
266 case OHCI_USB_SUSPEND: return "suspend";
267 }
268 return "?";
269 }
270
271 /* dump control and status registers */
272 static void ohci_dump_status (ohci_t *controller)
273 {
274 struct ohci_regs *regs = controller->regs;
275 __u32 temp;
276
277 temp = readl (&regs->revision) & 0xff;
278 if (temp != 0x10)
279 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
280
281 temp = readl (&regs->control);
282 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
283 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
284 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
285 (temp & OHCI_CTRL_IR) ? " IR" : "",
286 hcfs2string (temp & OHCI_CTRL_HCFS),
287 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
288 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
289 (temp & OHCI_CTRL_IE) ? " IE" : "",
290 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
291 temp & OHCI_CTRL_CBSR
292 );
293
294 temp = readl (&regs->cmdstatus);
295 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
296 (temp & OHCI_SOC) >> 16,
297 (temp & OHCI_OCR) ? " OCR" : "",
298 (temp & OHCI_BLF) ? " BLF" : "",
299 (temp & OHCI_CLF) ? " CLF" : "",
300 (temp & OHCI_HCR) ? " HCR" : ""
301 );
302
303 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
304 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
305
306 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
307
308 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
309 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
310
311 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
312 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
313
314 maybe_print_eds ("donehead", readl (&regs->donehead));
315 }
316
317 static void ohci_dump_roothub (ohci_t *controller, int verbose)
318 {
319 __u32 temp, ndp, i;
320
321 temp = roothub_a (controller);
322 ndp = (temp & RH_A_NDP);
323
324 if (verbose) {
325 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
326 ((temp & RH_A_POTPGT) >> 24) & 0xff,
327 (temp & RH_A_NOCP) ? " NOCP" : "",
328 (temp & RH_A_OCPM) ? " OCPM" : "",
329 (temp & RH_A_DT) ? " DT" : "",
330 (temp & RH_A_NPS) ? " NPS" : "",
331 (temp & RH_A_PSM) ? " PSM" : "",
332 ndp
333 );
334 temp = roothub_b (controller);
335 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
336 temp,
337 (temp & RH_B_PPCM) >> 16,
338 (temp & RH_B_DR)
339 );
340 temp = roothub_status (controller);
341 dbg ("roothub.status: %08x%s%s%s%s%s%s",
342 temp,
343 (temp & RH_HS_CRWE) ? " CRWE" : "",
344 (temp & RH_HS_OCIC) ? " OCIC" : "",
345 (temp & RH_HS_LPSC) ? " LPSC" : "",
346 (temp & RH_HS_DRWE) ? " DRWE" : "",
347 (temp & RH_HS_OCI) ? " OCI" : "",
348 (temp & RH_HS_LPS) ? " LPS" : ""
349 );
350 }
351
352 for (i = 0; i < ndp; i++) {
353 temp = roothub_portstatus (controller, i);
354 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
355 i,
356 temp,
357 (temp & RH_PS_PRSC) ? " PRSC" : "",
358 (temp & RH_PS_OCIC) ? " OCIC" : "",
359 (temp & RH_PS_PSSC) ? " PSSC" : "",
360 (temp & RH_PS_PESC) ? " PESC" : "",
361 (temp & RH_PS_CSC) ? " CSC" : "",
362
363 (temp & RH_PS_LSDA) ? " LSDA" : "",
364 (temp & RH_PS_PPS) ? " PPS" : "",
365 (temp & RH_PS_PRS) ? " PRS" : "",
366 (temp & RH_PS_POCI) ? " POCI" : "",
367 (temp & RH_PS_PSS) ? " PSS" : "",
368
369 (temp & RH_PS_PES) ? " PES" : "",
370 (temp & RH_PS_CCS) ? " CCS" : ""
371 );
372 }
373 }
374
375 static void ohci_dump (ohci_t *controller, int verbose)
376 {
377 dbg ("OHCI controller usb-%s state", controller->slot_name);
378
379 /* dumps some of the state we know about */
380 ohci_dump_status (controller);
381 if (verbose)
382 ep_print_int_eds (controller, "hcca");
383 dbg ("hcca frame #%04x", controller->hcca->frame_no);
384 ohci_dump_roothub (controller, 1);
385 }
386
387
388 #endif /* DEBUG */
389
390 /*-------------------------------------------------------------------------*
391 * Interface functions (URB)
392 *-------------------------------------------------------------------------*/
393
394 /* get a transfer request */
395
396 int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
397 int transfer_len, struct devrequest *setup, int interval)
398 {
399 ohci_t *ohci;
400 ed_t * ed;
401 urb_priv_t *purb_priv;
402 int i, size = 0;
403
404 ohci = &gohci;
405
406 /* when controller's hung, permit only roothub cleanup attempts
407 * such as powering down ports */
408 if (ohci->disabled) {
409 err("sohci_submit_job: EPIPE");
410 return -1;
411 }
412
413 /* every endpoint has a ed, locate and fill it */
414 if (!(ed = ep_add_ed (dev, pipe))) {
415 err("sohci_submit_job: ENOMEM");
416 return -1;
417 }
418
419 /* for the private part of the URB we need the number of TDs (size) */
420 switch (usb_pipetype (pipe)) {
421 case PIPE_BULK: /* one TD for every 4096 Byte */
422 size = (transfer_len - 1) / 4096 + 1;
423 break;
424 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
425 size = (transfer_len == 0)? 2:
426 (transfer_len - 1) / 4096 + 3;
427 break;
428 }
429
430 if (size >= (N_URB_TD - 1)) {
431 err("need %d TDs, only have %d", size, N_URB_TD);
432 return -1;
433 }
434 purb_priv = &urb_priv;
435 purb_priv->pipe = pipe;
436
437 /* fill the private part of the URB */
438 purb_priv->length = size;
439 purb_priv->ed = ed;
440 purb_priv->actual_length = 0;
441
442 /* allocate the TDs */
443 /* note that td[0] was allocated in ep_add_ed */
444 for (i = 0; i < size; i++) {
445 purb_priv->td[i] = td_alloc (dev);
446 if (!purb_priv->td[i]) {
447 purb_priv->length = i;
448 urb_free_priv (purb_priv);
449 err("sohci_submit_job: ENOMEM");
450 return -1;
451 }
452 }
453
454 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
455 urb_free_priv (purb_priv);
456 err("sohci_submit_job: EINVAL");
457 return -1;
458 }
459
460 /* link the ed into a chain if is not already */
461 if (ed->state != ED_OPER)
462 ep_link (ohci, ed);
463
464 /* fill the TDs and link it to the ed */
465 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
466
467 return 0;
468 }
469
470 /*-------------------------------------------------------------------------*/
471
472 #ifdef DEBUG
473 /* tell us the current USB frame number */
474
475 static int sohci_get_current_frame_number (struct usb_device *usb_dev)
476 {
477 ohci_t *ohci = &gohci;
478
479 return m16_swap (ohci->hcca->frame_no);
480 }
481 #endif
482
483 /*-------------------------------------------------------------------------*
484 * ED handling functions
485 *-------------------------------------------------------------------------*/
486
487 /* link an ed into one of the HC chains */
488
489 static int ep_link (ohci_t *ohci, ed_t *edi)
490 {
491 volatile ed_t *ed = edi;
492
493 ed->state = ED_OPER;
494
495 switch (ed->type) {
496 case PIPE_CONTROL:
497 ed->hwNextED = 0;
498 if (ohci->ed_controltail == NULL) {
499 writel ((long)ed, &ohci->regs->ed_controlhead);
500 } else {
501 ohci->ed_controltail->hwNextED = m32_swap (ed);
502 }
503 ed->ed_prev = ohci->ed_controltail;
504 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
505 !ohci->ed_rm_list[1] && !ohci->sleeping) {
506 ohci->hc_control |= OHCI_CTRL_CLE;
507 writel (ohci->hc_control, &ohci->regs->control);
508 }
509 ohci->ed_controltail = edi;
510 break;
511
512 case PIPE_BULK:
513 ed->hwNextED = 0;
514 if (ohci->ed_bulktail == NULL) {
515 writel ((long)ed, &ohci->regs->ed_bulkhead);
516 } else {
517 ohci->ed_bulktail->hwNextED = m32_swap (ed);
518 }
519 ed->ed_prev = ohci->ed_bulktail;
520 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
521 !ohci->ed_rm_list[1] && !ohci->sleeping) {
522 ohci->hc_control |= OHCI_CTRL_BLE;
523 writel (ohci->hc_control, &ohci->regs->control);
524 }
525 ohci->ed_bulktail = edi;
526 break;
527 }
528 return 0;
529 }
530
531 /*-------------------------------------------------------------------------*/
532
533 /* unlink an ed from one of the HC chains.
534 * just the link to the ed is unlinked.
535 * the link from the ed still points to another operational ed or 0
536 * so the HC can eventually finish the processing of the unlinked ed */
537
538 static int ep_unlink (ohci_t *ohci, ed_t *ed)
539 {
540 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
541
542 switch (ed->type) {
543 case PIPE_CONTROL:
544 if (ed->ed_prev == NULL) {
545 if (!ed->hwNextED) {
546 ohci->hc_control &= ~OHCI_CTRL_CLE;
547 writel (ohci->hc_control, &ohci->regs->control);
548 }
549 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
550 } else {
551 ed->ed_prev->hwNextED = ed->hwNextED;
552 }
553 if (ohci->ed_controltail == ed) {
554 ohci->ed_controltail = ed->ed_prev;
555 } else {
556 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
557 }
558 break;
559
560 case PIPE_BULK:
561 if (ed->ed_prev == NULL) {
562 if (!ed->hwNextED) {
563 ohci->hc_control &= ~OHCI_CTRL_BLE;
564 writel (ohci->hc_control, &ohci->regs->control);
565 }
566 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
567 } else {
568 ed->ed_prev->hwNextED = ed->hwNextED;
569 }
570 if (ohci->ed_bulktail == ed) {
571 ohci->ed_bulktail = ed->ed_prev;
572 } else {
573 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
574 }
575 break;
576 }
577 ed->state = ED_UNLINK;
578 return 0;
579 }
580
581
582 /*-------------------------------------------------------------------------*/
583
584 /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
585 * but the USB stack is a little bit stateless so we do it at every transaction
586 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
587 * in all other cases the state is left unchanged
588 * the ed info fields are setted anyway even though most of them should not change */
589
590 static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
591 {
592 td_t *td;
593 ed_t *ed_ret;
594 volatile ed_t *ed;
595
596 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
597 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
598
599 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
600 err("ep_add_ed: pending delete");
601 /* pending delete request */
602 return NULL;
603 }
604
605 if (ed->state == ED_NEW) {
606 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
607 /* dummy td; end of td list for ed */
608 td = td_alloc (usb_dev);
609 ed->hwTailP = m32_swap (td);
610 ed->hwHeadP = ed->hwTailP;
611 ed->state = ED_UNLINK;
612 ed->type = usb_pipetype (pipe);
613 ohci_dev.ed_cnt++;
614 }
615
616 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
617 | usb_pipeendpoint (pipe) << 7
618 | (usb_pipeisoc (pipe)? 0x8000: 0)
619 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
620 | usb_pipeslow (pipe) << 13
621 | usb_maxpacket (usb_dev, pipe) << 16);
622
623 return ed_ret;
624 }
625
626 /*-------------------------------------------------------------------------*
627 * TD handling functions
628 *-------------------------------------------------------------------------*/
629
630 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
631
632 static void td_fill (ohci_t *ohci, unsigned int info,
633 void *data, int len,
634 struct usb_device *dev, int index, urb_priv_t *urb_priv)
635 {
636 volatile td_t *td, *td_pt;
637 #ifdef OHCI_FILL_TRACE
638 int i;
639 #endif
640
641 if (index > urb_priv->length) {
642 err("index > length");
643 return;
644 }
645 /* use this td as the next dummy */
646 td_pt = urb_priv->td [index];
647 td_pt->hwNextTD = 0;
648
649 /* fill the old dummy TD */
650 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
651
652 td->ed = urb_priv->ed;
653 td->next_dl_td = NULL;
654 td->index = index;
655 td->data = (__u32)data;
656 #ifdef OHCI_FILL_TRACE
657 if (1 || ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe))) {
658 for (i = 0; i < len; i++)
659 printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
660 }
661 #endif
662 if (!len)
663 data = 0;
664
665 td->hwINFO = m32_swap (info);
666 td->hwCBP = m32_swap (data);
667 if (data)
668 td->hwBE = m32_swap (data + len - 1);
669 else
670 td->hwBE = 0;
671 td->hwNextTD = m32_swap (td_pt);
672 td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
673
674 /* append to queue */
675 td->ed->hwTailP = td->hwNextTD;
676 }
677
678 /*-------------------------------------------------------------------------*/
679
680 /* prepare all TDs of a transfer */
681
682 #define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000))
683
684 static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
685 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
686 {
687 ohci_t *ohci = &gohci;
688 int data_len = transfer_len;
689 void *data;
690 int cnt = 0;
691 __u32 info = 0;
692 unsigned int toggle = 0;
693
694 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
695 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
696 toggle = TD_T_TOGGLE;
697 } else {
698 toggle = TD_T_DATA0;
699 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
700 }
701 urb->td_cnt = 0;
702 if (data_len)
703 data = kseg_to_phys(buffer);
704 else
705 data = 0;
706
707 switch (usb_pipetype (pipe)) {
708 case PIPE_BULK:
709 info = usb_pipeout (pipe)?
710 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
711 while(data_len > 4096) {
712 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
713 data += 4096; data_len -= 4096; cnt++;
714 }
715 info = usb_pipeout (pipe)?
716 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
717 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
718 cnt++;
719
720 if (!ohci->sleeping)
721 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
722 break;
723
724 case PIPE_CONTROL:
725 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
726 td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
727 if (data_len > 0) {
728 info = usb_pipeout (pipe)?
729 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
730 /* NOTE: mishandles transfers >8K, some >4K */
731 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
732 }
733 info = usb_pipeout (pipe)?
734 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
735 td_fill (ohci, info, data, 0, dev, cnt++, urb);
736 if (!ohci->sleeping)
737 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
738 break;
739 }
740 if (urb->length != cnt)
741 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
742 }
743
744 /*-------------------------------------------------------------------------*
745 * Done List handling functions
746 *-------------------------------------------------------------------------*/
747
748
749 /* calculate the transfer length and update the urb */
750
751 static void dl_transfer_length(td_t * td)
752 {
753 __u32 tdINFO, tdBE, tdCBP;
754 urb_priv_t *lurb_priv = &urb_priv;
755
756 tdINFO = m32_swap (td->hwINFO);
757 tdBE = m32_swap (td->hwBE);
758 tdCBP = m32_swap (td->hwCBP);
759
760
761 if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
762 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
763 if (tdBE != 0) {
764 if (td->hwCBP == 0)
765 lurb_priv->actual_length += tdBE - td->data + 1;
766 else
767 lurb_priv->actual_length += tdCBP - td->data;
768 }
769 }
770 }
771
772 /*-------------------------------------------------------------------------*/
773
774 /* replies to the request have to be on a FIFO basis so
775 * we reverse the reversed done-list */
776
777 static td_t * dl_reverse_done_list (ohci_t *ohci)
778 {
779 __u32 td_list_hc;
780 td_t *td_rev = NULL;
781 td_t *td_list = NULL;
782 urb_priv_t *lurb_priv = NULL;
783
784 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
785 ohci->hcca->done_head = 0;
786
787 while (td_list_hc) {
788 td_list = (td_t *)td_list_hc;
789
790 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
791 lurb_priv = &urb_priv;
792 dbg(" USB-error/status: %x : %p",
793 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
794 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
795 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
796 td_list->ed->hwHeadP =
797 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
798 (td_list->ed->hwHeadP & m32_swap (0x2));
799 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
800 } else
801 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
802 }
803 }
804
805 td_list->next_dl_td = td_rev;
806 td_rev = td_list;
807 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
808 }
809 return td_list;
810 }
811
812 /*-------------------------------------------------------------------------*/
813
814 /* td done list */
815 static int dl_done_list (ohci_t *ohci, td_t *td_list)
816 {
817 td_t *td_list_next = NULL;
818 ed_t *ed;
819 int cc = 0;
820 int stat = 0;
821 /* urb_t *urb; */
822 urb_priv_t *lurb_priv;
823 __u32 tdINFO, edHeadP, edTailP;
824
825 while (td_list) {
826 td_list_next = td_list->next_dl_td;
827
828 lurb_priv = &urb_priv;
829 tdINFO = m32_swap (td_list->hwINFO);
830
831 ed = td_list->ed;
832
833 dl_transfer_length(td_list);
834
835 /* error code of transfer */
836 cc = TD_CC_GET (tdINFO);
837 if (cc != 0) {
838 dbg("ConditionCode %#x", cc);
839 stat = cc_to_error[cc];
840 }
841
842 if (ed->state != ED_NEW) {
843 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
844 edTailP = m32_swap (ed->hwTailP);
845
846 /* unlink eds if they are not busy */
847 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
848 ep_unlink (ohci, ed);
849 }
850
851 td_list = td_list_next;
852 }
853 return stat;
854 }
855
856 /*-------------------------------------------------------------------------*
857 * Virtual Root Hub
858 *-------------------------------------------------------------------------*/
859
860 /* Device descriptor */
861 static __u8 root_hub_dev_des[] =
862 {
863 0x12, /* __u8 bLength; */
864 0x01, /* __u8 bDescriptorType; Device */
865 0x10, /* __u16 bcdUSB; v1.1 */
866 0x01,
867 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
868 0x00, /* __u8 bDeviceSubClass; */
869 0x00, /* __u8 bDeviceProtocol; */
870 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
871 0x00, /* __u16 idVendor; */
872 0x00,
873 0x00, /* __u16 idProduct; */
874 0x00,
875 0x00, /* __u16 bcdDevice; */
876 0x00,
877 0x00, /* __u8 iManufacturer; */
878 0x01, /* __u8 iProduct; */
879 0x00, /* __u8 iSerialNumber; */
880 0x01 /* __u8 bNumConfigurations; */
881 };
882
883
884 /* Configuration descriptor */
885 static __u8 root_hub_config_des[] =
886 {
887 0x09, /* __u8 bLength; */
888 0x02, /* __u8 bDescriptorType; Configuration */
889 0x19, /* __u16 wTotalLength; */
890 0x00,
891 0x01, /* __u8 bNumInterfaces; */
892 0x01, /* __u8 bConfigurationValue; */
893 0x00, /* __u8 iConfiguration; */
894 0x40, /* __u8 bmAttributes;
895 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
896 0x00, /* __u8 MaxPower; */
897
898 /* interface */
899 0x09, /* __u8 if_bLength; */
900 0x04, /* __u8 if_bDescriptorType; Interface */
901 0x00, /* __u8 if_bInterfaceNumber; */
902 0x00, /* __u8 if_bAlternateSetting; */
903 0x01, /* __u8 if_bNumEndpoints; */
904 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
905 0x00, /* __u8 if_bInterfaceSubClass; */
906 0x00, /* __u8 if_bInterfaceProtocol; */
907 0x00, /* __u8 if_iInterface; */
908
909 /* endpoint */
910 0x07, /* __u8 ep_bLength; */
911 0x05, /* __u8 ep_bDescriptorType; Endpoint */
912 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
913 0x03, /* __u8 ep_bmAttributes; Interrupt */
914 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
915 0x00,
916 0xff /* __u8 ep_bInterval; 255 ms */
917 };
918
919 static unsigned char root_hub_str_index0[] =
920 {
921 0x04, /* __u8 bLength; */
922 0x03, /* __u8 bDescriptorType; String-descriptor */
923 0x09, /* __u8 lang ID */
924 0x04, /* __u8 lang ID */
925 };
926
927 static unsigned char root_hub_str_index1[] =
928 {
929 28, /* __u8 bLength; */
930 0x03, /* __u8 bDescriptorType; String-descriptor */
931 'O', /* __u8 Unicode */
932 0, /* __u8 Unicode */
933 'H', /* __u8 Unicode */
934 0, /* __u8 Unicode */
935 'C', /* __u8 Unicode */
936 0, /* __u8 Unicode */
937 'I', /* __u8 Unicode */
938 0, /* __u8 Unicode */
939 ' ', /* __u8 Unicode */
940 0, /* __u8 Unicode */
941 'R', /* __u8 Unicode */
942 0, /* __u8 Unicode */
943 'o', /* __u8 Unicode */
944 0, /* __u8 Unicode */
945 'o', /* __u8 Unicode */
946 0, /* __u8 Unicode */
947 't', /* __u8 Unicode */
948 0, /* __u8 Unicode */
949 ' ', /* __u8 Unicode */
950 0, /* __u8 Unicode */
951 'H', /* __u8 Unicode */
952 0, /* __u8 Unicode */
953 'u', /* __u8 Unicode */
954 0, /* __u8 Unicode */
955 'b', /* __u8 Unicode */
956 0, /* __u8 Unicode */
957 };
958
959 /* Hub class-specific descriptor is constructed dynamically */
960
961
962 /*-------------------------------------------------------------------------*/
963
964 #define OK(x) len = (x); break
965 #ifdef DEBUG
966 #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
967 #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
968 #else
969 #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
970 #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
971 #endif
972 #define RD_RH_STAT roothub_status(&gohci)
973 #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
974
975 /* request to virtual root hub */
976
977 int rh_check_port_status(ohci_t *controller)
978 {
979 __u32 temp, ndp, i;
980 int res;
981
982 res = -1;
983 temp = roothub_a (controller);
984 ndp = (temp & RH_A_NDP);
985 for (i = 0; i < ndp; i++) {
986 temp = roothub_portstatus (controller, i);
987 /* check for a device disconnect */
988 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
989 (RH_PS_PESC | RH_PS_CSC)) &&
990 ((temp & RH_PS_CCS) == 0)) {
991 res = i;
992 break;
993 }
994 }
995 return res;
996 }
997
998 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
999 void *buffer, int transfer_len, struct devrequest *cmd)
1000 {
1001 void * data = buffer;
1002 int leni = transfer_len;
1003 int len = 0;
1004 int stat = 0;
1005 __u32 datab[4];
1006 __u8 *data_buf = (__u8 *)datab;
1007 __u16 bmRType_bReq;
1008 __u16 wValue;
1009 __u16 wIndex;
1010 __u16 wLength;
1011
1012 #ifdef DEBUG
1013 urb_priv.actual_length = 0;
1014 pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
1015 #else
1016 wait_ms(1);
1017 #endif
1018 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1019 info("Root-Hub submit IRQ: NOT implemented");
1020 return 0;
1021 }
1022
1023 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1024 wValue = m16_swap (cmd->value);
1025 wIndex = m16_swap (cmd->index);
1026 wLength = m16_swap (cmd->length);
1027
1028 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1029 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1030
1031 switch (bmRType_bReq) {
1032 /* Request Destination:
1033 without flags: Device,
1034 RH_INTERFACE: interface,
1035 RH_ENDPOINT: endpoint,
1036 RH_CLASS means HUB here,
1037 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1038 */
1039
1040 case RH_GET_STATUS:
1041 *(__u16 *) data_buf = m16_swap (1); OK (2);
1042 case RH_GET_STATUS | RH_INTERFACE:
1043 *(__u16 *) data_buf = m16_swap (0); OK (2);
1044 case RH_GET_STATUS | RH_ENDPOINT:
1045 *(__u16 *) data_buf = m16_swap (0); OK (2);
1046 case RH_GET_STATUS | RH_CLASS:
1047 *(__u32 *) data_buf = m32_swap (
1048 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1049 OK (4);
1050 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1051 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1052
1053 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1054 switch (wValue) {
1055 case (RH_ENDPOINT_STALL): OK (0);
1056 }
1057 break;
1058
1059 case RH_CLEAR_FEATURE | RH_CLASS:
1060 switch (wValue) {
1061 case RH_C_HUB_LOCAL_POWER:
1062 OK(0);
1063 case (RH_C_HUB_OVER_CURRENT):
1064 WR_RH_STAT(RH_HS_OCIC); OK (0);
1065 }
1066 break;
1067
1068 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1069 switch (wValue) {
1070 case (RH_PORT_ENABLE):
1071 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1072 case (RH_PORT_SUSPEND):
1073 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1074 case (RH_PORT_POWER):
1075 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1076 case (RH_C_PORT_CONNECTION):
1077 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1078 case (RH_C_PORT_ENABLE):
1079 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1080 case (RH_C_PORT_SUSPEND):
1081 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1082 case (RH_C_PORT_OVER_CURRENT):
1083 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1084 case (RH_C_PORT_RESET):
1085 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1086 }
1087 break;
1088
1089 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1090 switch (wValue) {
1091 case (RH_PORT_SUSPEND):
1092 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1093 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1094 if (RD_RH_PORTSTAT & RH_PS_CCS)
1095 WR_RH_PORTSTAT (RH_PS_PRS);
1096 OK (0);
1097 case (RH_PORT_POWER):
1098 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1099 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1100 if (RD_RH_PORTSTAT & RH_PS_CCS)
1101 WR_RH_PORTSTAT (RH_PS_PES );
1102 OK (0);
1103 }
1104 break;
1105
1106 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1107
1108 case RH_GET_DESCRIPTOR:
1109 switch ((wValue & 0xff00) >> 8) {
1110 case (0x01): /* device descriptor */
1111 len = min_t(unsigned int,
1112 leni,
1113 min_t(unsigned int,
1114 sizeof (root_hub_dev_des),
1115 wLength));
1116 data_buf = root_hub_dev_des; OK(len);
1117 case (0x02): /* configuration descriptor */
1118 len = min_t(unsigned int,
1119 leni,
1120 min_t(unsigned int,
1121 sizeof (root_hub_config_des),
1122 wLength));
1123 data_buf = root_hub_config_des; OK(len);
1124 case (0x03): /* string descriptors */
1125 if(wValue==0x0300) {
1126 len = min_t(unsigned int,
1127 leni,
1128 min_t(unsigned int,
1129 sizeof (root_hub_str_index0),
1130 wLength));
1131 data_buf = root_hub_str_index0;
1132 OK(len);
1133 }
1134 if(wValue==0x0301) {
1135 len = min_t(unsigned int,
1136 leni,
1137 min_t(unsigned int,
1138 sizeof (root_hub_str_index1),
1139 wLength));
1140 data_buf = root_hub_str_index1;
1141 OK(len);
1142 }
1143 default:
1144 stat = USB_ST_STALLED;
1145 }
1146 break;
1147
1148 case RH_GET_DESCRIPTOR | RH_CLASS:
1149 {
1150 __u32 temp = roothub_a (&gohci);
1151
1152 data_buf [0] = 9; /* min length; */
1153 data_buf [1] = 0x29;
1154 data_buf [2] = temp & RH_A_NDP;
1155 data_buf [3] = 0;
1156 if (temp & RH_A_PSM) /* per-port power switching? */
1157 data_buf [3] |= 0x1;
1158 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1159 data_buf [3] |= 0x10;
1160 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1161 data_buf [3] |= 0x8;
1162
1163 /* corresponds to data_buf[4-7] */
1164 datab [1] = 0;
1165 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1166 temp = roothub_b (&gohci);
1167 data_buf [7] = temp & RH_B_DR;
1168 if (data_buf [2] < 7) {
1169 data_buf [8] = 0xff;
1170 } else {
1171 data_buf [0] += 2;
1172 data_buf [8] = (temp & RH_B_DR) >> 8;
1173 data_buf [10] = data_buf [9] = 0xff;
1174 }
1175
1176 len = min_t(unsigned int, leni,
1177 min_t(unsigned int, data_buf [0], wLength));
1178 OK (len);
1179 }
1180
1181 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1182
1183 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1184
1185 default:
1186 dbg ("unsupported root hub command");
1187 stat = USB_ST_STALLED;
1188 }
1189
1190 #ifdef DEBUG
1191 ohci_dump_roothub (&gohci, 1);
1192 #else
1193 wait_ms(1);
1194 #endif
1195
1196 len = min_t(int, len, leni);
1197 if (data != data_buf)
1198 memcpy (data, data_buf, len);
1199 dev->act_len = len;
1200 dev->status = stat;
1201
1202 #ifdef DEBUG
1203 if (transfer_len)
1204 urb_priv.actual_length = transfer_len;
1205 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1206 #else
1207 wait_ms(1);
1208 #endif
1209
1210 return stat;
1211 }
1212
1213 /*-------------------------------------------------------------------------*/
1214
1215 /* common code for handling submit messages - used for all but root hub */
1216 /* accesses. */
1217 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1218 int transfer_len, struct devrequest *setup, int interval)
1219 {
1220 int stat = 0;
1221 int maxsize = usb_maxpacket(dev, pipe);
1222 int timeout;
1223
1224 /* device pulled? Shortcut the action. */
1225 if (devgone == dev) {
1226 dev->status = USB_ST_CRC_ERR;
1227 return 0;
1228 }
1229
1230 #ifdef DEBUG
1231 urb_priv.actual_length = 0;
1232 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1233 #else
1234 wait_ms(1);
1235 #endif
1236 if (!maxsize) {
1237 err("submit_common_message: pipesize for pipe %lx is zero",
1238 pipe);
1239 return -1;
1240 }
1241
1242 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1243 err("sohci_submit_job failed");
1244 return -1;
1245 }
1246
1247 wait_ms(10);
1248 /* ohci_dump_status(&gohci); */
1249
1250 /* allow more time for a BULK device to react - some are slow */
1251 #define BULK_TO 5000 /* timeout in milliseconds */
1252 if (usb_pipetype (pipe) == PIPE_BULK)
1253 timeout = BULK_TO;
1254 else
1255 timeout = 100;
1256
1257 timeout *= 4;
1258 /* wait for it to complete */
1259 for (;;) {
1260 /* check whether the controller is done */
1261 stat = hc_interrupt();
1262 if (stat < 0) {
1263 stat = USB_ST_CRC_ERR;
1264 break;
1265 }
1266 if (stat >= 0 && stat != 0xff) {
1267 /* 0xff is returned for an SF-interrupt */
1268 break;
1269 }
1270 if (--timeout) {
1271 udelay(250); /* wait_ms(1); */
1272 } else {
1273 err("CTL:TIMEOUT ");
1274 stat = USB_ST_CRC_ERR;
1275 break;
1276 }
1277 }
1278 /* we got an Root Hub Status Change interrupt */
1279 if (got_rhsc) {
1280 #ifdef DEBUG
1281 ohci_dump_roothub (&gohci, 1);
1282 #endif
1283 got_rhsc = 0;
1284 /* abuse timeout */
1285 timeout = rh_check_port_status(&gohci);
1286 if (timeout >= 0) {
1287 #if 0 /* this does nothing useful, but leave it here in case that changes */
1288 /* the called routine adds 1 to the passed value */
1289 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1290 #endif
1291 /*
1292 * XXX
1293 * This is potentially dangerous because it assumes
1294 * that only one device is ever plugged in!
1295 */
1296 devgone = dev;
1297 }
1298 }
1299
1300 dev->status = stat;
1301 dev->act_len = transfer_len;
1302
1303 #ifdef DEBUG
1304 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1305 #else
1306 wait_ms(1);
1307 #endif
1308
1309 /* free TDs in urb_priv */
1310 urb_free_priv (&urb_priv);
1311 return 0;
1312 }
1313
1314 /* submit routines called from usb.c */
1315 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1316 int transfer_len)
1317 {
1318 info("submit_bulk_msg");
1319 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1320 }
1321
1322 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1323 int transfer_len, struct devrequest *setup)
1324 {
1325 int maxsize = usb_maxpacket(dev, pipe);
1326
1327 info("submit_control_msg");
1328 #ifdef DEBUG
1329 urb_priv.actual_length = 0;
1330 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1331 #else
1332 wait_ms(1);
1333 #endif
1334 if (!maxsize) {
1335 err("submit_control_message: pipesize for pipe %lx is zero",
1336 pipe);
1337 return -1;
1338 }
1339 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1340 gohci.rh.dev = dev;
1341 /* root hub - redirect */
1342 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1343 setup);
1344 }
1345
1346 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1347 }
1348
1349 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1350 int transfer_len, int interval)
1351 {
1352 info("submit_int_msg");
1353 return -1;
1354 }
1355
1356 /*-------------------------------------------------------------------------*
1357 * HC functions
1358 *-------------------------------------------------------------------------*/
1359
1360 /* reset the HC and BUS */
1361
1362 static int hc_reset (ohci_t *ohci)
1363 {
1364 int timeout = 30;
1365 int smm_timeout = 50; /* 0,5 sec */
1366
1367 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1368 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1369 info("USB HC TakeOver from SMM");
1370 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1371 wait_ms (10);
1372 if (--smm_timeout == 0) {
1373 err("USB HC TakeOver failed!");
1374 return -1;
1375 }
1376 }
1377 }
1378
1379 /* Disable HC interrupts */
1380 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1381
1382 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1383 ohci->slot_name,
1384 readl (&ohci->regs->control));
1385
1386 /* Reset USB (needed by some controllers) */
1387 writel (0, &ohci->regs->control);
1388
1389 /* HC Reset requires max 10 us delay */
1390 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1391 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1392 if (--timeout == 0) {
1393 err("USB HC reset timed out!");
1394 return -1;
1395 }
1396 udelay (1);
1397 }
1398 return 0;
1399 }
1400
1401 /*-------------------------------------------------------------------------*/
1402
1403 /* Start an OHCI controller, set the BUS operational
1404 * enable interrupts
1405 * connect the virtual root hub */
1406
1407 static int hc_start (ohci_t * ohci)
1408 {
1409 __u32 mask;
1410 unsigned int fminterval;
1411
1412 ohci->disabled = 1;
1413
1414 /* Tell the controller where the control and bulk lists are
1415 * The lists are empty now. */
1416
1417 writel (0, &ohci->regs->ed_controlhead);
1418 writel (0, &ohci->regs->ed_bulkhead);
1419
1420 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1421
1422 fminterval = 0x2edf;
1423 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1424 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1425 writel (fminterval, &ohci->regs->fminterval);
1426 writel (0x628, &ohci->regs->lsthresh);
1427
1428 /* start controller operations */
1429 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1430 ohci->disabled = 0;
1431 writel (ohci->hc_control, &ohci->regs->control);
1432
1433 /* disable all interrupts */
1434 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1435 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1436 OHCI_INTR_OC | OHCI_INTR_MIE);
1437 writel (mask, &ohci->regs->intrdisable);
1438 /* clear all interrupts */
1439 mask &= ~OHCI_INTR_MIE;
1440 writel (mask, &ohci->regs->intrstatus);
1441 /* Choose the interrupts we care about now - but w/o MIE */
1442 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1443 writel (mask, &ohci->regs->intrenable);
1444
1445 #ifdef OHCI_USE_NPS
1446 /* required for AMD-756 and some Mac platforms */
1447 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1448 &ohci->regs->roothub.a);
1449 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1450 #endif /* OHCI_USE_NPS */
1451
1452 #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1453 /* POTPGT delay is bits 24-31, in 2 ms units. */
1454 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1455
1456 /* connect the virtual root hub */
1457 ohci->rh.devnum = 0;
1458
1459 return 0;
1460 }
1461
1462 /*-------------------------------------------------------------------------*/
1463
1464 /* an interrupt happens */
1465
1466 static int
1467 hc_interrupt (void)
1468 {
1469 ohci_t *ohci = &gohci;
1470 struct ohci_regs *regs = ohci->regs;
1471 int ints;
1472 int stat = -1;
1473
1474 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1475 ints = OHCI_INTR_WDH;
1476 } else {
1477 ints = readl (&regs->intrstatus);
1478 }
1479
1480 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1481
1482 if (ints & OHCI_INTR_RHSC) {
1483 got_rhsc = 1;
1484 }
1485
1486 if (ints & OHCI_INTR_UE) {
1487 ohci->disabled++;
1488 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1489 ohci->slot_name);
1490 /* e.g. due to PCI Master/Target Abort */
1491
1492 #ifdef DEBUG
1493 ohci_dump (ohci, 1);
1494 #else
1495 wait_ms(1);
1496 #endif
1497 /* FIXME: be optimistic, hope that bug won't repeat often. */
1498 /* Make some non-interrupt context restart the controller. */
1499 /* Count and limit the retries though; either hardware or */
1500 /* software errors can go forever... */
1501 hc_reset (ohci);
1502 return -1;
1503 }
1504
1505 if (ints & OHCI_INTR_WDH) {
1506 wait_ms(1);
1507 writel (OHCI_INTR_WDH, &regs->intrdisable);
1508 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1509 writel (OHCI_INTR_WDH, &regs->intrenable);
1510 }
1511
1512 if (ints & OHCI_INTR_SO) {
1513 dbg("USB Schedule overrun\n");
1514 writel (OHCI_INTR_SO, &regs->intrenable);
1515 stat = -1;
1516 }
1517
1518 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1519 if (ints & OHCI_INTR_SF) {
1520 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1521 wait_ms(1);
1522 writel (OHCI_INTR_SF, &regs->intrdisable);
1523 if (ohci->ed_rm_list[frame] != NULL)
1524 writel (OHCI_INTR_SF, &regs->intrenable);
1525 stat = 0xff;
1526 }
1527
1528 writel (ints, &regs->intrstatus);
1529 return stat;
1530 }
1531
1532 /*-------------------------------------------------------------------------*/
1533
1534 /*-------------------------------------------------------------------------*/
1535
1536 /* De-allocate all resources.. */
1537
1538 static void hc_release_ohci (ohci_t *ohci)
1539 {
1540 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1541
1542 if (!ohci->disabled)
1543 hc_reset (ohci);
1544 }
1545
1546 /*-------------------------------------------------------------------------*/
1547
1548 #define __read_32bit_c0_register(source, sel) \
1549 ({ int __res; \
1550 if (sel == 0) \
1551 __asm__ __volatile__( \
1552 "mfc0\t%0, " #source "\n\t" \
1553 : "=r" (__res)); \
1554 else \
1555 __asm__ __volatile__( \
1556 ".set\tmips32\n\t" \
1557 "mfc0\t%0, " #source ", " #sel "\n\t" \
1558 ".set\tmips0\n\t" \
1559 : "=r" (__res)); \
1560 __res; \
1561 })
1562
1563 #define read_c0_prid() __read_32bit_c0_register($15, 0)
1564
1565 /*
1566 * low level initalisation routine, called from usb.c
1567 */
1568 static char ohci_inited = 0;
1569
1570 int usb_lowlevel_init(void)
1571 {
1572 u32 pin_func;
1573 u32 sys_freqctrl, sys_clksrc;
1574 u32 prid = read_c0_prid();
1575
1576 dbg("in usb_lowlevel_init\n");
1577
1578 /* zero and disable FREQ2 */
1579 sys_freqctrl = au_readl(SYS_FREQCTRL0);
1580 sys_freqctrl &= ~0xFFF00000;
1581 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1582
1583 /* zero and disable USBH/USBD clocks */
1584 sys_clksrc = au_readl(SYS_CLKSRC);
1585 sys_clksrc &= ~0x00007FE0;
1586 au_writel(sys_clksrc, SYS_CLKSRC);
1587
1588 sys_freqctrl = au_readl(SYS_FREQCTRL0);
1589 sys_freqctrl &= ~0xFFF00000;
1590
1591 sys_clksrc = au_readl(SYS_CLKSRC);
1592 sys_clksrc &= ~0x00007FE0;
1593
1594 switch (prid & 0x000000FF) {
1595 case 0x00: /* DA */
1596 case 0x01: /* HA */
1597 case 0x02: /* HB */
1598 /* CPU core freq to 48MHz to slow it way down... */
1599 au_writel(4, SYS_CPUPLL);
1600
1601 /*
1602 * Setup 48MHz FREQ2 from CPUPLL for USB Host
1603 */
1604 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
1605 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
1606 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1607
1608 /* CPU core freq to 384MHz */
1609 au_writel(0x20, SYS_CPUPLL);
1610
1611 printf("Au1000: 48MHz OHCI workaround enabled\n");
1612 break;
1613
1614 default: /* HC and newer */
1615 /* FREQ2 = aux/2 = 48 MHz */
1616 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
1617 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1618 break;
1619 }
1620
1621 /*
1622 * Route 48MHz FREQ2 into USB Host and/or Device
1623 */
1624 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
1625 au_writel(sys_clksrc, SYS_CLKSRC);
1626
1627 /* configure pins GPIO[14:9] as GPIO */
1628 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
1629
1630 au_writel(pin_func, SYS_PINFUNC);
1631 au_writel(0x2800, SYS_TRIOUTCLR);
1632 au_writel(0x0030, SYS_OUTPUTCLR);
1633
1634 dbg("OHCI board setup complete\n");
1635
1636 /* enable host controller */
1637 au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
1638 udelay(1000);
1639 au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
1640 udelay(1000);
1641
1642 /* wait for reset complete (read register twice; see au1500 errata) */
1643 while (au_readl(USB_HOST_CONFIG),
1644 !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
1645 udelay(1000);
1646
1647 dbg("OHCI clock running\n");
1648
1649 memset (&gohci, 0, sizeof (ohci_t));
1650 memset (&urb_priv, 0, sizeof (urb_priv_t));
1651
1652 /* align the storage */
1653 if ((__u32)&ghcca[0] & 0xff) {
1654 err("HCCA not aligned!!");
1655 return -1;
1656 }
1657 phcca = &ghcca[0];
1658 info("aligned ghcca %p", phcca);
1659 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1660 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1661 err("EDs not aligned!!");
1662 return -1;
1663 }
1664 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1665 if ((__u32)gtd & 0x7) {
1666 err("TDs not aligned!!");
1667 return -1;
1668 }
1669 ptd = gtd;
1670 gohci.hcca = phcca;
1671 memset (phcca, 0, sizeof (struct ohci_hcca));
1672
1673 gohci.disabled = 1;
1674 gohci.sleeping = 0;
1675 gohci.irq = -1;
1676 gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
1677
1678 gohci.flags = 0;
1679 gohci.slot_name = "au1x00";
1680
1681 dbg("OHCI revision: 0x%08x\n"
1682 " RH: a: 0x%08x b: 0x%08x\n",
1683 readl(&gohci.regs->revision),
1684 readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
1685
1686 if (hc_reset (&gohci) < 0)
1687 goto errout;
1688
1689 /* FIXME this is a second HC reset; why?? */
1690 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1691 wait_ms (10);
1692
1693 if (hc_start (&gohci) < 0)
1694 goto errout;
1695
1696 #ifdef DEBUG
1697 ohci_dump (&gohci, 1);
1698 #else
1699 wait_ms(1);
1700 #endif
1701 ohci_inited = 1;
1702 return 0;
1703
1704 errout:
1705 err("OHCI initialization error\n");
1706 hc_release_ohci (&gohci);
1707 /* Initialization failed */
1708 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1709 return -1;
1710 }
1711
1712 int usb_lowlevel_stop(void)
1713 {
1714 /* this gets called really early - before the controller has */
1715 /* even been initialized! */
1716 if (!ohci_inited)
1717 return 0;
1718 /* TODO release any interrupts, etc. */
1719 /* call hc_release_ohci() here ? */
1720 hc_reset (&gohci);
1721 /* may not want to do this */
1722 /* Disable clock */
1723 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1724 return 0;
1725 }
1726
1727 #endif /* CONFIG_USB_OHCI */
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