package/uboot-ifxmips/files/cpu/mips/danube/ifx_cgu.c

   1 /*
   2  * ########################################################################
   3  *
   4  *  This program is free software; you can distribute it and/or modify it
   5  *  under the terms of the GNU General Public License (Version 2) as
   6  *  published by the Free Software Foundation.
   7  *
   8  *  This program is distributed in the hope it will be useful, but WITHOUT
   9  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  11  *  for more details.
  12  *
  13  *  You should have received a copy of the GNU General Public License along
  14  *  with this program; if not, write to the Free Software Foundation, Inc.,
  15  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  16  *
  17  * ########################################################################
  18  *
  19  * danube_cgu.c
  20  *
  21  *  Description:
  22  *    device driver of clock generation unit of Danube chip
  23  *  Author:
  24  *    Samuels Xu Liang
  25  *  Created:
  26  *    19 Jul 2005
  27  *  History & Modification Tag:
  28  *  ___________________________________________________________________________
  29  *  |  Tag   |                  Comments                   | Modifier & Time  |
  30  *  |--------+---------------------------------------------+------------------|
  31  *  |  S0.0  | First version of this driver and the tag is | Samuels Xu Liang |
  32  *  |        | implied.                                    |   19 Jul 2005    |
  33  *  ---------------------------------------------------------------------------
  34  *
  35  */
  36
  37
  38 /*
  39  * ####################################
  40  *              Head File
  41  * ####################################
  42  */
  43
  44 /*
  45  *  Common Head File
  46  */
  47 #include <linux/config.h>
  48 #include <linux/kernel.h>
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/types.h>
  52 #include <linux/fs.h>
  53 #include <linux/miscdevice.h>
  54 #include <linux/init.h>
  55 #include <asm/uaccess.h>
  56 #include <asm/unistd.h>
  57 #include <asm/irq.h>
  58 #include <linux/errno.h>
  59
  60 /*
  61  *  Chip Specific Head File
  62  */
  63 #include "ifx_cgu.h"
  64
  65
  66 /*
  67  * ####################################
  68  *              Definition
  69  * ####################################
  70  */
  71
  72 #define DEBUG_ON_AMAZON                 1
  73 #define DEBUG_PRINT_INFO                1
  74
  75 /*
  76  *  Frequency of Clock Direct Feed from The Analog Line Driver Chip
  77  */
  78 #define BASIC_INPUT_CLOCK_FREQUENCY     35328000
  79
  80 /*
  81  *  Bits Operation
  82  */
  83 #define GET_BITS(x, msb, lsb)           (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
  84 #define SET_BITS(x, msb, lsb, value)    (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
  85
  86 /*
  87  *  CGU Register Mapping
  88  */
  89 #define DANUBE_CGU                      (KSEG1 + 0x1F103000)
  90 #define DANUBE_CGU_DIV                  ((volatile u32*)(DANUBE_CGU + 0x0000))
  91 #define DANUBE_CGU_PLL_NMK0             ((volatile u32*)(DANUBE_CGU + 0x0004))
  92 #define DANUBE_CGU_PLL_SR0              ((volatile u32*)(DANUBE_CGU + 0x0008))
  93 #define DANUBE_CGU_PLL_NMK1             ((volatile u32*)(DANUBE_CGU + 0x000C))
  94 #define DANUBE_CGU_PLL_SR1              ((volatile u32*)(DANUBE_CGU + 0x0010))
  95 #define DANUBE_CGU_PLL_SR2              ((volatile u32*)(DANUBE_CGU + 0x0014))
  96 #define DANUBE_CGU_IF_CLK               ((volatile u32*)(DANUBE_CGU + 0x0018))
  97 #define DANUBE_CGU_OSC_CTRL             ((volatile u32*)(DANUBE_CGU + 0x001C))
  98 #define DANUBE_CGU_SMD                  ((volatile u32*)(DANUBE_CGU + 0x0020))
  99 #define DANUBE_CGU_CRD                  ((volatile u32*)(DANUBE_CGU + 0x0024))
 100 #define DANUBE_CGU_CT1SR                ((volatile u32*)(DANUBE_CGU + 0x0028))
 101 #define DANUBE_CGU_CT2SR                ((volatile u32*)(DANUBE_CGU + 0x002C))
 102 #define DANUBE_CGU_PCMCR                ((volatile u32*)(DANUBE_CGU + 0x0030))
 103 #define DANUBE_CGU_MUX                  ((volatile u32*)(DANUBE_CGU + 0x0034))
 104
 105 /*
 106  *  CGU Divider Register
 107  */
 108 #define CGU_DIV_SFTR                    (*DANUBE_CGU_DIV & (1 << 31))
 109 #define CGU_DIV_DIVE                    (*DANUBE_CGU_DIV & (1 << 16))
 110 #define CGU_DIV_IOR                     GET_BITS(*DANUBE_CGU_DIV, 5, 4)
 111 #define CGU_DIV_FKS                     GET_BITS(*DANUBE_CGU_DIV, 3, 2)
 112 #define CGU_DIV_FBS                     GET_BITS(*DANUBE_CGU_DIV, 1, 0)
 113
 114 /*
 115  *  CGU PLL0 NMK Register
 116  */
 117 #define CGU_PLL_NMK0_PLLN               ((*DANUBE_CGU_PLL_NMK0 & (0xFFFFFFFF ^ ((1 << 24) - 1))) >> 24)
 118 #define CGU_PLL_NMK0_PLLM               GET_BITS(*DANUBE_CGU_PLL_NMK0, 23, 20)
 119 #define CGU_PLL_NMK0_PLLK               GET_BITS(*DANUBE_CGU_PLL_NMK0, 19, 0)
 120
 121 /*
 122  *  CGU PLL0 Status Register
 123  */
 124 #define CGU_PLL_SR0_PLLDIV              ((*DANUBE_CGU_PLL_SR0 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)
 125 #define CGU_PLL_SR0_PLLDEN              (*DANUBE_CGU_PLL_SR0 & (1 << 26))
 126 #define CGU_PLL_SR0_PLLPSE              GET_BITS(*DANUBE_CGU_PLL_SR0, 5, 4)
 127 #define CGU_PLL_SR0_PLLB                (*DANUBE_CGU_PLL_SR0 & (1 << 2))
 128 #define CGU_PLL_SR0_PLLL                (*DANUBE_CGU_PLL_SR0 & (1 << 1))
 129 #define CGU_PLL_SR0_PLLEN               (*DANUBE_CGU_PLL_SR0 & (1 << 0))
 130
 131 #define CGU_PLL_SR0_DSMSEL              1
 132 #define CGU_PLL_SR0_PHASE_DIV_EN        1
 133
 134 /*
 135  *  CGU PLL1 NMK Register
 136  */
 137 #define CGU_PLL_NMK1_PLLN               ((*DANUBE_CGU_PLL_NMK1 & (0xFFFFFFFF ^ ((1 << 24) - 1))) >> 24)
 138 #define CGU_PLL_NMK1_PLLM               GET_BITS(*DANUBE_CGU_PLL_NMK1, 23, 20)
 139 #define CGU_PLL_NMK1_PLLK               GET_BITS(*DANUBE_CGU_PLL_NMK1, 19, 0)
 140
 141 /*
 142  *  CGU PLL1 Status Register
 143  */
 144 #define CGU_PLL_SR1_PLLDIV              ((*DANUBE_CGU_PLL_SR1 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)
 145 #define CGU_PLL_SR1_PLLDEN              (*DANUBE_CGU_PLL_SR1 & (1 << 26))
 146 #define CGU_PLL_SR1_PLLPSE              GET_BITS(*DANUBE_CGU_PLL_SR1, 5, 4)
 147 #define CGU_PLL_SR1_PLLB                (*DANUBE_CGU_PLL_SR1 & (1 << 2))
 148 #define CGU_PLL_SR1_PLLL                (*DANUBE_CGU_PLL_SR1 & (1 << 1))
 149 #define CGU_PLL_SR1_PLLEN               (*DANUBE_CGU_PLL_SR1 & (1 << 0))
 150
 151 #define CGU_PLL_SR1_DSMSEL              1
 152 #define CGU_PLL_SR1_PHASE_DIV_EN        1
 153
 154 /*
 155  *  CGU PLL2 Status Register
 156  */
 157 #define CGU_PLL_SR2_PLLDIV              ((*DANUBE_CGU_PLL_SR2 & (0xFFFFFFFF ^ ((1 << 28) - 1))) >> 28)
 158 #define CGU_PLL_SR2_PLLDEN              (*DANUBE_CGU_PLL_SR2 & (1 << 27))
 159 #define CGU_PLL_SR2_PLLN                GET_BITS(*DANUBE_CGU_PLL_SR2, 25, 20)
 160 #define CGU_PLL_SR2_PLLM                GET_BITS(*DANUBE_CGU_PLL_SR2, 19, 16)
 161 #define CGU_PLL_SR2_PLLPS               (*DANUBE_CGU_PLL_SR2 & (1 << 5))
 162 #define CGU_PLL_SR2_PLLPE               (*DANUBE_CGU_PLL_SR2 & (1 << 4))
 163 #define CGU_PLL_SR2_PLLB                (*DANUBE_CGU_PLL_SR2 & (1 << 2))
 164 #define CGU_PLL_SR2_PLLL                (*DANUBE_CGU_PLL_SR2 & (1 << 1))
 165 #define CGU_PLL_SR2_PLLEN               (*DANUBE_CGU_PLL_SR2 & (1 << 0))
 166
 167 /*
 168  *  CGU Interface Clock Register
 169  */
 170 #define CGU_IF_CLK_CLKOD0               GET_BITS(*DANUBE_CGU_IF_CLK, 27, 26)
 171 #define CGU_IF_CLK_CLKOD1               GET_BITS(*DANUBE_CGU_IF_CLK, 25, 24)
 172 #define CGU_IF_CLK_CLKOD2               GET_BITS(*DANUBE_CGU_IF_CLK, 23, 22)
 173 #define CGU_IF_CLK_CLKOD3               GET_BITS(*DANUBE_CGU_IF_CLK, 21, 20)
 174 #define CGU_IF_CLK_PDA                  (*DANUBE_CGU_IF_CLK & (1 << 18))
 175 #define CGU_IF_CLK_PCI_B                (*DANUBE_CGU_IF_CLK & (1 << 17))
 176 #define CGU_IF_CLK_PCIBM                (*DANUBE_CGU_IF_CLK & (1 << 16))
 177 #define CGU_IF_CLK_MIICS                (*DANUBE_CGU_IF_CLK & (1 << 3))
 178 #define CGU_IF_CLK_USBCS                (*DANUBE_CGU_IF_CLK & (1 << 2))
 179 #define CGU_IF_CLK_PCIF                 (*DANUBE_CGU_IF_CLK & (1 << 1))
 180 #define CGU_IF_CLK_PCIS                 (*DANUBE_CGU_IF_CLK & (1 << 0))
 181
 182 /*
 183  *  CGU Oscillator Control Register
 184  */
 185 #define CGU_OSC_CTRL                    GET_BITS(*DANUBE_CGU_OSC_CTRL, 1, 0)
 186
 187 /*
 188  *  CGU SDRAM Memory Delay Register
 189  */
 190 #define CGU_SMD_CLKI                    (*DANUBE_CGU_SMD & (1 << 31))
 191 #define CGU_SMD_MIDS                    GET_BITS(*DANUBE_CGU_SMD, 17, 12)
 192 #define CGU_SMD_MODS                    GET_BITS(*DANUBE_CGU_SMD, 11, 6)
 193 #define CGU_SMD_MDSEL                   GET_BITS(*DANUBE_CGU_SMD, 5, 0)
 194
 195 /*
 196  *  CGU CPU Clock Reduction Register
 197  */
 198 #define CGU_CRD_SFTR                    (*DANUBE_CGU_CRD & (1 << 31))
 199 #define CGU_CRD_DIVE                    (*DANUBE_CGU_CRD & (1 << 16))
 200 #define CGU_CRD_CRD1                    GET_BITS(*DANUBE_CGU_CRD, 3, 2)
 201 #define CGU_CRD_CRD                     GET_BITS(*DANUBE_CGU_CRD, 1, 0)
 202
 203 /*
 204  *  CGU CT Status Register 1
 205  */
 206 #define CGU_CT1SR_PDOUT                 GET_BITS(*DANUBE_CGU_CT1SR, 13, 0)
 207
 208 /*
 209  *  CGU CT Status Register 2
 210  */
 211 #define CGU_CT2SR_PLL1K                 GET_BITS(*DANUBE_CGU_CT2SR, 9, 0)
 212
 213 /*
 214  *  CGU PCM Control Register
 215  */
 216 #define CGU_PCMCR_DCL1                  GET_BITS(*DANUBE_CGU_PCMCR, 27, 25)
 217 #define CGU_PCMCR_MUXDCL                (*DANUBE_CGU_PCMCR & (1 << 22))
 218 #define CGU_PCMCR_MUXFSC                (*DANUBE_CGU_PCMCR & (1 << 18))
 219 #define CGU_PCMCR_PCM_SL                (*DANUBE_CGU_PCMCR & (1 << 13))
 220 #define CGU_PCMCR_DNTR                  (*DANUBE_CGU_PCMCR & (1 << 12))
 221
 222 /*
 223  *  CGU Clock Mux Register
 224  */
 225 #define CGU_MUX_MII_CLK                 (*DANUBE_CGU_MUX & (1 << 6))
 226 #define CGU_MUX_SUB_SYS                 GET_BITS(*DANUBE_CGU_MUX, 5, 3)
 227 #define CGU_MUX_PP32                    GET_BITS(*DANUBE_CGU_MUX, 1, 0)
 228
 229
 230 /*
 231  * ####################################
 232  * Preparation of Debug on Amazon Chip
 233  * ####################################
 234  */
 235
 236 /*
 237  *  If try module on Amazon chip, prepare some tricks to prevent invalid memory write.
 238  */
 239 #if defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON
 240     u32 g_pFakeRegisters[0x0100];
 241
 242     #undef  DANUBE_CGU
 243     #define DANUBE_CGU                  ((u32)g_pFakeRegisters)
 244 #endif  //  defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON
 245
 246
 247 /*
 248  * ####################################
 249  *              Data Type
 250  * ####################################
 251  */
 252
 253
 254 /*
 255  * ####################################
 256  *             Declaration
 257  * ####################################
 258  */
 259
 260 /*
 261  *  Pre-declaration of File Operations
 262  */
 263 static ssize_t cgu_read(struct file *, char *, size_t, loff_t *);
 264 static ssize_t cgu_write(struct file *, const char *, size_t, loff_t *);
 265 static int cgu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
 266 static int cgu_open(struct inode *, struct file *);
 267 static int cgu_release(struct inode *, struct file *);
 268
 269 /*
 270  *  Pre-declaration of 64-bit Unsigned Integer Operation
 271  */
 272 static inline void uint64_multiply(unsigned int, unsigned int, unsigned int *);
 273 static inline void uint64_divide(unsigned int *, unsigned int, unsigned int *, unsigned int *);
 274
 275 /*
 276  *  Calculate PLL Frequency
 277  */
 278 static inline u32 cal_dsm(u32, u32);
 279 static inline u32 mash_dsm(u32, u32, u32);
 280 static inline u32 ssff_dsm_1(u32, u32, u32);
 281 static inline u32 ssff_dsm_2(u32, u32, u32);
 282 static inline u32 dsm(u32 M, u32, u32, int, int);
 283 static inline u32 cgu_get_pll0_fosc(void);
 284 static inline u32 cgu_get_pll0_fps(void);
 285 static inline u32 cgu_get_pll0_fdiv(void);
 286 static inline u32 cgu_get_pll1_fosc(void);
 287 static inline u32 cgu_get_pll1_fps(void);
 288 static inline u32 cgu_get_pll1_fdiv(void);
 289 static inline u32 cgu_get_pll2_fosc(void);
 290 static inline u32 cgu_get_pll2_fps(void);
 291
 292 /*
 293  *  Export Functions
 294  */
 295 u32 cgu_get_mips_clock(int);
 296 u32 cgu_get_cpu_clock(void);
 297 u32 cgu_get_io_region_clock(void);
 298 u32 cgu_get_fpi_bus_clock(int);
 299 u32 cgu_get_pp32_clock(void);
 300 u32 cgu_get_pci_clock(void);
 301 u32 cgu_get_ethernet_clock(void);
 302 u32 cgu_get_usb_clock(void);
 303 u32 cgu_get_clockout(int);
 304
 305
 306 /*
 307  * ####################################
 308  *            Local Variable
 309  * ####################################
 310  */
 311
 312 static struct file_operations cgu_fops = {
 313     owner:      THIS_MODULE,
 314     llseek:     no_llseek,
 315     read:       cgu_read,
 316     write:      cgu_write,
 317     ioctl:      cgu_ioctl,
 318     open:       cgu_open,
 319     release:    cgu_release
 320 };
 321
 322 static struct miscdevice cgu_miscdev = {
 323     MISC_DYNAMIC_MINOR,
 324     "danube_cgu_dev",
 325     &cgu_fops
 326 };
 327
 328
 329 /*
 330  * ####################################
 331  *           Global Variable
 332  * ####################################
 333  */
 334
 335
 336 /*
 337  * ####################################
 338  *            Local Function
 339  * ####################################
 340  */
 341
 342 static ssize_t cgu_read(struct file *file, char *buf, size_t count, loff_t *ppos)
 343 {
 344     return -EPERM;
 345 }
 346
 347 static ssize_t cgu_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
 348 {
 349     return -EPERM;
 350 }
 351
 352 static int cgu_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
 353 {
 354     int ret = 0;
 355     struct cgu_clock_rates rates;
 356
 357     if ( _IOC_TYPE(cmd) != CGU_IOC_MAGIC
 358         || _IOC_NR(cmd) >= CGU_IOC_MAXNR )
 359         return -ENOTTY;
 360
 361     if ( _IOC_DIR(cmd) & _IOC_READ )
 362         ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
 363     else if ( _IOC_DIR(cmd) & _IOC_WRITE )
 364         ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
 365     if ( ret )
 366         return -EFAULT;
 367
 368     switch ( cmd )
 369     {
 370     case CGU_GET_CLOCK_RATES:
 371         /*  Calculate Clock Rates   */
 372         rates.mips0     = cgu_get_mips_clock(0);
 373         rates.mips1     = cgu_get_mips_clock(1);
 374         rates.cpu       = cgu_get_cpu_clock();
 375         rates.io_region = cgu_get_io_region_clock();
 376         rates.fpi_bus1  = cgu_get_fpi_bus_clock(1);
 377         rates.fpi_bus2  = cgu_get_fpi_bus_clock(2);
 378         rates.pp32      = cgu_get_pp32_clock();
 379         rates.pci       = cgu_get_pci_clock();
 380         rates.ethernet  = cgu_get_ethernet_clock();
 381         rates.usb       = cgu_get_usb_clock();
 382         rates.clockout0 = cgu_get_clockout(0);
 383         rates.clockout1 = cgu_get_clockout(1);
 384         rates.clockout2 = cgu_get_clockout(2);
 385         rates.clockout3 = cgu_get_clockout(3);
 386         /*  Copy to User Space      */
 387         copy_to_user((char*)arg, (char*)&rates, sizeof(rates));
 388
 389         ret = 0;
 390         break;
 391     default:
 392         ret = -ENOTTY;
 393     }
 394
 395     return ret;
 396 }
 397
 398 static int cgu_open(struct inode *inode, struct file *file)
 399 {
 400     return 0;
 401 }
 402
 403 static int cgu_release(struct inode *inode, struct file *file)
 404 {
 405     return 0;
 406 }
 407
 408 /*
 409  *  Description:
 410  *    calculate 64-bit multiplication result of two 32-bit unsigned integer
 411  *  Input:
 412  *    u32Multiplier1 --- u32 (32-bit), one of the multipliers
 413  *    u32Multiplier2 --- u32 (32-bit), the other multiplier
 414  *    u32Result      --- u32[2], array to retrieve the multiplication result,
 415  *                       index 0 is high word, index 1 is low word
 416  *  Output:
 417 *    none
 418  */
 419 static inline void uint64_multiply(u32 u32Multiplier1, u32 u32Multiplier2, u32 u32Result[2])
 420 {
 421         u32 u32Multiplier1LowWord = u32Multiplier1 & 0xFFFF;
 422         u32 u32Multiplier1HighWord = u32Multiplier1 >> 16;
 423         u32 u32Multiplier2LowWord = u32Multiplier2 & 0xFFFF;
 424         u32 u32Multiplier2HighWord = u32Multiplier2 >> 16;
 425         u32 u32Combo1, u32Combo2, u32Combo3, u32Combo4;
 426         u32 u32Word1, u32Word2, u32Word3, u32Word4;
 427
 428         u32Combo1 = u32Multiplier1LowWord * u32Multiplier2LowWord;
 429         u32Combo2 = u32Multiplier1HighWord * u32Multiplier2LowWord;
 430         u32Combo3 = u32Multiplier1LowWord * u32Multiplier2HighWord;
 431         u32Combo4 = u32Multiplier1HighWord * u32Multiplier2HighWord;
 432
 433         u32Word1 = u32Combo1 & 0xFFFF;
 434         u32Word2 = (u32Combo1 >> 16) + (u32Combo2 & 0xFFFF) + (u32Combo3 & 0xFFFF);
 435         u32Word3 = (u32Combo2 >> 16) + (u32Combo3 >> 16) + (u32Combo4 & 0xFFFF) + (u32Word2 >> 16);
 436         u32Word4 = (u32Combo4 >> 16) + (u32Word3 >> 16);
 437
 438         u32Result[0] = (u32Word4 << 16) | u32Word3;
 439         u32Result[1] = (u32Word2 << 16) | u32Word1;
 440 }
 441
 442 /*
 443  *  Description:
 444  *    divide 64-bit unsigned integer with 32-bit unsigned integer
 445  *  Input:
 446  *    u32Numerator   --- u32[2], index 0 is high word of numerator, while
 447  *                       index 1 is low word of numerator
 448  *    u32Denominator --- u32 (32-bit), the denominator in division, this
 449  *                       parameter can not be zero, or lead to unpredictable
 450  *                       result
 451  *    pu32Quotient   --- u32 *, the pointer to retrieve 32-bit quotient, null
 452  *                       pointer means ignore quotient
 453  *    pu32Residue    --- u32 *, the pointer to retrieve 32-bit residue null
 454  *                       pointer means ignore residue
 455  *  Output:
 456  *    none
 457  */
 458 static inline void uint64_divide(u32 u32Numerator[2], u32 u32Denominator, u32 *pu32Quotient, u32 *pu32Residue)
 459 {
 460         u32 u32DWord1, u32DWord2, u32DWord3;
 461         u32 u32Quotient;
 462         int i;
 463
 464         u32DWord3 = 0;
 465         u32DWord2 = u32Numerator[0];
 466         u32DWord1 = u32Numerator[1];
 467
 468         u32Quotient = 0;
 469
 470         for ( i = 0; i < 64; i++ )
 471         {
 472                 u32DWord3 = (u32DWord3 << 1) | (u32DWord2 >> 31);
 473                 u32DWord2 = (u32DWord2 << 1) | (u32DWord1 >> 31);
 474                 u32DWord1 <<= 1;
 475                 u32Quotient <<= 1;
 476                 if ( u32DWord3 >= u32Denominator )
 477                 {
 478                         u32DWord3 -= u32Denominator;
 479                         u32Quotient |= 1;
 480                 }
 481         }
 482         if ( pu32Quotient )
 483             *pu32Quotient = u32Quotient;
 484         if ( pu32Residue )
 485             *pu32Residue = u32DWord3;
 486 }
 487
 488 /*
 489  *  Description:
 490  *    common routine to calculate PLL frequency
 491  *  Input:
 492  *    num --- u32, numerator
 493  *    den --- u32, denominator
 494  *  Output:
 495  *    u32 --- frequency the PLL output
 496  */
 497 static inline u32 cal_dsm(u32 num, u32 den)
 498 {
 499     u32 ret;
 500     u32 temp[2];
 501     u32 residue;
 502
 503     uint64_multiply(num, BASIC_INPUT_CLOCK_FREQUENCY, temp);
 504     uint64_divide(temp, den, &ret, &residue);
 505     if ( (residue << 1) >= den )
 506         ret++;
 507
 508     return ret;
 509 }
 510
 511 /*
 512  *  Description:
 513  *    calculate PLL frequency following MASH-DSM
 514  *  Input:
 515  *    M   --- u32, denominator coefficient
 516  *    N   --- u32, numerator integer coefficient
 517  *    K   --- u32, numerator fraction coefficient
 518  *  Output:
 519  *    u32 --- frequency the PLL output
 520  */
 521 static inline u32 mash_dsm(u32 M, u32 N, u32 K)
 522 {
 523     u32 num = ((N + 1) << 10) + K;
 524     u32 den = (M + 1) << 10;
 525
 526     return cal_dsm(num, den);
 527 }
 528
 529 /*
 530  *  Description:
 531  *    calculate PLL frequency following SSFF-DSM (0.25 < fraction < 0.75)
 532  *  Input:
 533  *    M   --- u32, denominator coefficient
 534  *    N   --- u32, numerator integer coefficient
 535  *    K   --- u32, numerator fraction coefficient
 536  *  Output:
 537  *    u32 --- frequency the PLL output
 538  */
 539 static inline u32 ssff_dsm_1(u32 M, u32 N, u32 K)
 540 {
 541     u32 num = ((N + 1) << 11) + K + 512;
 542     u32 den = (M + 1) << 11;
 543
 544     return cal_dsm(num, den);
 545 }
 546
 547 /*
 548  *  Description:
 549  *    calculate PLL frequency following SSFF-DSM
 550  *    (fraction < 0.125 || fraction > 0.875)
 551  *  Input:
 552  *    M   --- u32, denominator coefficient
 553  *    N   --- u32, numerator integer coefficient
 554  *    K   --- u32, numerator fraction coefficient
 555  *  Output:
 556  *    u32 --- frequency the PLL output
 557  */
 558 static inline u32 ssff_dsm_2(u32 M, u32 N, u32 K)
 559 {
 560     u32 num = K >= 512 ? ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
 561     u32 den = (M + 1) << 12;
 562
 563     return cal_dsm(num, den);
 564 }
 565
 566 /*
 567  *  Description:
 568  *    calculate PLL frequency
 569  *  Input:
 570  *    M            --- u32, denominator coefficient
 571  *    N            --- u32, numerator integer coefficient
 572  *    K            --- u32, numerator fraction coefficient
 573  *    dsmsel       --- int, 0: MASH-DSM, 1: SSFF-DSM
 574  *    phase_div_en --- int, 0: 0.25 < fraction < 0.75
 575  *                          1: fraction < 0.125 || fraction > 0.875
 576  *  Output:
 577  *    u32          --- frequency the PLL output
 578  */
 579 static inline u32 dsm(u32 M, u32 N, u32 K, int dsmsel, int phase_div_en)
 580 {
 581     if ( !dsmsel )
 582         return mash_dsm(M, N, K);
 583     else
 584         if ( !phase_div_en )
 585             return ssff_dsm_1(M, N, K);
 586         else
 587             return ssff_dsm_2(M, N, K);
 588 }
 589
 590 /*
 591  *  Description:
 592  *    get oscillate frequency of PLL0
 593  *  Input:
 594  *    none
 595  *  Output:
 596  *    u32 --- frequency of PLL0 Fosc
 597  */
 598 static inline u32 cgu_get_pll0_fosc(void)
 599 {
 600     return CGU_PLL_SR0_PLLB ? BASIC_INPUT_CLOCK_FREQUENCY : dsm(CGU_PLL_NMK0_PLLM, CGU_PLL_NMK0_PLLN, CGU_PLL_NMK0_PLLK, CGU_PLL_SR0_DSMSEL, CGU_PLL_SR0_PHASE_DIV_EN);
 601 }
 602
 603 /*
 604  *  Description:
 605  *    get output frequency of PLL0 phase shifter
 606  *  Input:
 607  *    none
 608  *  Output:
 609  *    u32 --- frequency of PLL0 Fps
 610  */
 611 static inline u32 cgu_get_pll0_fps(void)
 612 {
 613     register u32 fps = cgu_get_pll0_fosc();
 614
 615     switch ( CGU_PLL_SR0_PLLPSE )
 616     {
 617     case 1:
 618         /*  1.5     */
 619         fps = ((fps << 1) + 1) / 3; break;
 620     case 2:
 621         /*  1.25    */
 622         fps = ((fps << 2) + 2) / 5; break;
 623     case 3:
 624         /*  3.5     */
 625         fps = ((fps << 1) + 3) / 7;
 626     }
 627     return fps;
 628 }
 629
 630 /*
 631  *  Description:
 632  *    get output frequency of PLL0 output divider
 633  *  Input:
 634  *    none
 635  *  Output:
 636  *    u32 --- frequency of PLL0 Fdiv
 637  */
 638 static inline u32 cgu_get_pll0_fdiv(void)
 639 {
 640     register u32 fdiv = cgu_get_pll0_fosc();
 641
 642     if ( CGU_PLL_SR0_PLLDEN )
 643         fdiv = (fdiv + (CGU_PLL_SR0_PLLDIV + 1) / 2) / (CGU_PLL_SR0_PLLDIV + 1);
 644     return fdiv;
 645 }
 646
 647 /*
 648  *  Description:
 649  *    get oscillate frequency of PLL1
 650  *  Input:
 651  *    none
 652  *  Output:
 653  *    u32 --- frequency of PLL1 Fosc
 654  */
 655 static inline u32 cgu_get_pll1_fosc(void)
 656 {
 657     return CGU_PLL_SR1_PLLB ? BASIC_INPUT_CLOCK_FREQUENCY : dsm(CGU_PLL_NMK1_PLLM, CGU_PLL_NMK1_PLLN, CGU_PLL_NMK1_PLLK, CGU_PLL_SR1_DSMSEL, CGU_PLL_SR1_PHASE_DIV_EN);
 658 }
 659
 660 /*
 661  *  Description:
 662  *    get output frequency of PLL1 phase shifter
 663  *  Input:
 664  *    none
 665  *  Output:
 666  *    u32 --- frequency of PLL1 Fps
 667  */
 668 static inline u32 cgu_get_pll1_fps(void)
 669 {
 670     register u32 fps = cgu_get_pll1_fosc();
 671
 672     switch ( CGU_PLL_SR1_PLLPSE )
 673     {
 674     case 1:
 675         /*  1.5     */
 676         fps = ((fps << 1) + 1) / 3; break;
 677     case 2:
 678         /*  1.25    */
 679         fps = ((fps << 2) + 2) / 5; break;
 680     case 3:
 681         /*  3.5     */
 682         fps = ((fps << 1) + 3) / 7;
 683     }
 684     return fps;
 685 }
 686
 687 /*
 688  *  Description:
 689  *    get output frequency of PLL1 output divider
 690  *  Input:
 691  *    none
 692  *  Output:
 693  *    u32 --- frequency of PLL1 Fdiv
 694  */
 695 static inline u32 cgu_get_pll1_fdiv(void)
 696 {
 697     register u32 fdiv = cgu_get_pll1_fosc();
 698
 699     if ( CGU_PLL_SR1_PLLDEN )
 700         fdiv = (fdiv + (CGU_PLL_SR1_PLLDIV + 1) / 2) / (CGU_PLL_SR1_PLLDIV + 1);
 701     return fdiv;
 702 }
 703
 704 /*
 705  *  Description:
 706  *    get oscillate frequency of PLL2
 707  *  Input:
 708  *    none
 709  *  Output:
 710  *    u32 --- frequency of PLL2 Fosc
 711  */
 712 static inline u32 cgu_get_pll2_fosc(void)
 713 {
 714     u32 ret;
 715     u32 temp[2];
 716     u32 residue;
 717
 718     uint64_multiply((CGU_PLL_SR2_PLLN + 1) * 8, cgu_get_pll0_fdiv(), temp);
 719     uint64_divide(temp, CGU_PLL_SR2_PLLM + 1, &ret, &residue);
 720     if ( (residue << 1) >= CGU_PLL_SR2_PLLM )
 721         ret++;
 722
 723     return ret;
 724 }
 725
 726 /*
 727  *  Description:
 728  *    get output frequency of PLL2 phase shifter
 729  *  Input:
 730  *    none
 731  *  Output:
 732  *    u32 --- frequency of PLL2 Fps
 733  */
 734 static inline u32 cgu_get_pll2_fps(void)
 735 {
 736     register u32 fps = cgu_get_pll2_fosc();
 737
 738     if ( CGU_PLL_SR2_PLLPE )
 739     {
 740         if ( CGU_PLL_SR2_PLLPS )
 741             /*  1.25    */
 742             fps = ((fps << 3) + 4) / 9;
 743         else
 744             /*  1.125   */
 745             fps = ((fps << 2) + 2) / 5;
 746     }
 747
 748     return fps;
 749 }
 750
 751
 752 /*
 753  * ####################################
 754  *           Global Function
 755  * ####################################
 756  */
 757
 758 /*
 759  *  Description:
 760  *    get frequency of MIPS (0: core, 1: DSP)
 761  *  Input:
 762  *    cpu --- int, 0: core, 1: DSP
 763  *  Output:
 764  *    u32 --- frequency of MIPS coprocessor (0: core, 1: DSP)
 765  */
 766 u32 cgu_get_mips_clock(int cpu)
 767 {
 768     register u32 ret = cgu_get_pll0_fosc();
 769
 770     if ( CGU_CRD_CRD )
 771         ret = (ret + (CGU_CRD_CRD >> 1)) / (CGU_CRD_CRD + 1);
 772     if ( cpu == 0 && CGU_CRD_CRD1 )
 773         ret >>= CGU_CRD_CRD1;
 774     return ret;
 775 }
 776
 777 /*
 778  *  Description:
 779  *    get frequency of MIPS core
 780  *  Input:
 781  *    none
 782  *  Output:
 783  *    u32 --- frequency of MIPS core
 784  */
 785 u32 cgu_get_cpu_clock(void)
 786 {
 787     return cgu_get_mips_clock(0);
 788 }
 789
 790 /*
 791  *  Description:
 792  *    get frequency of sub-system and memory controller
 793  *  Input:
 794  *    none
 795  *  Output:
 796  *    u32 --- frequency of sub-system and memory controller
 797  */
 798 u32 cgu_get_io_region_clock(void)
 799 {
 800     register u32 ret = (CGU_MUX_SUB_SYS > 4) ? cgu_get_pll0_fosc() : cgu_get_mips_clock(1);
 801
 802     switch ( CGU_MUX_SUB_SYS )
 803     {
 804     case 0:
 805         break;
 806     case 1:
 807     default:
 808         ret = (ret + 1) >> 1; break;
 809     case 2:
 810         ret = (ret + 1) / 3; break;
 811     case 3:
 812         ret = (ret + 2) >> 2; break;
 813     case 5:
 814         ret = ((ret << 1) + 1) / 3; break;
 815     case 6:
 816         ret = ((ret << 1) + 2) / 5;
 817     }
 818
 819     return ret;
 820 }
 821
 822 /*
 823  *  Description:
 824  *    get frequency of FPI bus
 825  *  Input:
 826  *    fpi --- int, 1: FPI bus 1 (FBS1/Fast FPI Bus), 2: FPI bus 2 (FBS2)
 827  *  Output:
 828  *    u32 --- frequency of FPI bus
 829  */
 830 u32 cgu_get_fpi_bus_clock(int fpi)
 831 {
 832     register u32 ret = cgu_get_io_region_clock();
 833
 834     if ( fpi == 2 )
 835         ret >>= 1;
 836     return ret;
 837 }
 838
 839 /*
 840  *  Description:
 841  *    get frequency of PP32 processor
 842  *  Input:
 843  *    none
 844  *  Output:
 845  *    u32 --- frequency of PP32 processor
 846  */
 847 u32 cgu_get_pp32_clock(void)
 848 {
 849     register u32 ret;
 850
 851     switch ( CGU_MUX_PP32 )
 852     {
 853     case 0:
 854     default:
 855         ret = ((cgu_get_pll2_fosc() << 2) + 2) / 5; break;
 856     case 1:
 857         ret = ((cgu_get_pll2_fosc() << 3) + 4) / 9; break;
 858     case 2:
 859         ret = cgu_get_fpi_bus_clock(1); break;
 860     case 3:
 861         ret = cgu_get_mips_clock(1);
 862     }
 863
 864     return ret;
 865 }
 866
 867 /*
 868  *  Description:
 869  *    get frequency of PCI bus
 870  *  Input:
 871  *    none
 872  *  Output:
 873  *    u32 --- frequency of PCI bus
 874  */
 875 u32 cgu_get_pci_clock(void)
 876 {
 877     register u32 ret = 0;
 878
 879     if ( !CGU_IF_CLK_PCIS )
 880     {
 881         ret = cgu_get_pll2_fosc();
 882         if ( CGU_IF_CLK_PCIF )
 883             ret = (ret + 2) / 5;
 884         else
 885             ret = (ret + 4) / 9;
 886     }
 887
 888     return ret;
 889 }
 890
 891 /*
 892  *  Description:
 893  *    get frequency of ethernet module (MII)
 894  *  Input:
 895  *    none
 896  *  Output:
 897  *    u32 --- frequency of ethernet module
 898  */
 899 u32 cgu_get_ethernet_clock(void)
 900 {
 901     register u32 ret = 0;
 902
 903     if ( !CGU_IF_CLK_MIICS )
 904     {
 905         ret = cgu_get_pll2_fosc();
 906         if ( CGU_MUX_MII_CLK )
 907             ret = (ret + 3) / 6;
 908         else
 909             ret = (ret + 6) / 12;
 910     }
 911
 912     return ret;
 913 }
 914
 915 /*
 916  *  Description:
 917  *    get frequency of USB
 918  *  Input:
 919  *    none
 920  *  Output:
 921  *    u32 --- frequency of USB
 922  */
 923 u32 cgu_get_usb_clock(void)
 924 {
 925     return CGU_IF_CLK_USBCS ? 12000000 : (cgu_get_pll2_fosc() + 12) / 25;
 926 }
 927
 928 /*
 929  *  Description:
 930  *    get frequency of CLK_OUT pin
 931  *  Input:
 932  *    clkout --- int, clock out pin number
 933  *  Output:
 934  *    u32    --- frequency of CLK_OUT pin
 935  */
 936 u32 cgu_get_clockout(int clkout)
 937 {
 938     u32 fosc1 = cgu_get_pll1_fosc();
 939     u32 fosc2 = cgu_get_pll2_fosc();
 940
 941     if ( clkout > 3 || clkout < 0 )
 942         return 0;
 943
 944     switch ( ((u32)clkout << 2) | GET_BITS(*DANUBE_CGU_IF_CLK, 21 + clkout * 2, 20 + clkout * 2) )
 945     {
 946     case 0: /*  32.768KHz   */
 947     case 14:
 948         return (fosc1 + 6000) / 12000;
 949     case 1: /*  1.536MHz    */
 950         return (fosc1 + 128) / 256;
 951     case 2: /*  2.5MHz      */
 952         return (fosc2 + 60) / 120;
 953     case 3: /*  12MHz       */
 954     case 5:
 955     case 12:
 956         return (fosc2 + 12) / 25;
 957     case 4: /*  40MHz       */
 958         return (fosc2 * 2 + 7) / 15;
 959     case 6: /*  24MHz       */
 960         return (fosc2 * 2 + 12) / 25;
 961     case 7: /*  48MHz       */
 962         return (fosc2 * 4 + 12) / 25;
 963     case 8: /*  25MHz       */
 964     case 15:
 965         return (fosc2 + 6) / 12;
 966     case 9: /*  50MHz       */
 967     case 13:
 968         return (fosc2 + 3) / 6;
 969     case 10:/*  30MHz       */
 970         return (fosc2 + 5) / 10;
 971     case 11:/*  60MHz       */
 972         return (fosc2 + 2) / 5;
 973     }
 974
 975     return 0;
 976 }
 977
 978
 979 /*
 980  * ####################################
 981  *           Init/Cleanup API
 982  * ####################################
 983  */
 984
 985 /*
 986  *  Description:
 987  *    register device
 988  *  Input:
 989  *    none
 990  *  Output:
 991  *    0    --- successful
 992  *    else --- failure, usually it is negative value of error code
 993  */
 994 int __init danube_cgu_init(void)
 995 {
 996     int ret;
 997
 998     ret = misc_register(&cgu_miscdev);
 999     if ( ret )
1000     {
1001         printk(KERN_ERR "cgu: can't misc_register\n");
1002         return ret;
1003     }
1004     else
1005         printk(KERN_INFO "cgu: misc_register on minor = %d\n", cgu_miscdev.minor);
1006
1007     /*
1008      *  initialize fake registers to do testing on Amazon
1009      */
1010 #if defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON
1011     #ifdef  DEBUG_PRINT_INFO
1012     #undef  DEBUG_PRINT_INFO
1013     #endif
1014     #define DEBUG_PRINT_INFO    1
1015
1016     *DANUBE_CGU_DIV         = 0x00010019;
1017     *DANUBE_CGU_PLL_NMK0    = 0x416002C3;
1018     *DANUBE_CGU_PLL_SR0     = 0x74000013;
1019     *DANUBE_CGU_PLL_NMK1    = 0x4C60009C;
1020     *DANUBE_CGU_PLL_SR1     = 0x54000013;
1021     *DANUBE_CGU_PLL_SR2     = 0x58890013;
1022     *DANUBE_CGU_IF_CLK      = 0x00000000;
1023     *DANUBE_CGU_OSC_CTRL    = 0x00000000;
1024     *DANUBE_CGU_SMD         = 0x00000000;
1025     *DANUBE_CGU_CRD         = 0x00010000;
1026     *DANUBE_CGU_CT1SR       = 0x00000000;
1027     *DANUBE_CGU_CT2SR       = CGU_PLL_NMK1_PLLK;
1028     *DANUBE_CGU_PCMCR       = 0x00000000;
1029     *DANUBE_CGU_MUX         = 0x00000008;
1030 #endif  //  defined(DEBUG_ON_AMAZON) && DEBUG_ON_AMAZON
1031
1032     /*
1033      *  for testing only
1034      */
1035 #if defined(DEBUG_PRINT_INFO) && DEBUG_PRINT_INFO
1036     printk("pll0 N = %d, M = %d, K = %d, DIV = %d\n", CGU_PLL_NMK0_PLLN, CGU_PLL_NMK0_PLLM, CGU_PLL_NMK0_PLLK, CGU_PLL_SR0_PLLDIV);
1037     printk("pll1 N = %d, M = %d, K = %d, DIV = %d\n", CGU_PLL_NMK1_PLLN, CGU_PLL_NMK1_PLLM, CGU_PLL_NMK1_PLLK, CGU_PLL_SR1_PLLDIV);
1038     printk("pll2 N = %d, M = %d, DIV = %d\n", CGU_PLL_SR2_PLLN, CGU_PLL_SR2_PLLM, CGU_PLL_SR2_PLLDIV);
1039     printk("pll0_fosc    = %d\n", cgu_get_pll0_fosc());
1040     printk("pll0_fps     = %d\n", cgu_get_pll0_fps());
1041     printk("pll0_fdiv    = %d\n", cgu_get_pll0_fdiv());
1042     printk("pll1_fosc    = %d\n", cgu_get_pll1_fosc());
1043     printk("pll1_fps     = %d\n", cgu_get_pll1_fps());
1044     printk("pll1_fdiv    = %d\n", cgu_get_pll1_fdiv());
1045     printk("pll2_fosc    = %d\n", cgu_get_pll2_fosc());
1046     printk("pll2_fps     = %d\n", cgu_get_pll2_fps());
1047     printk("mips0 clock  = %d\n", cgu_get_mips_clock(0));
1048     printk("mips1 clock  = %d\n", cgu_get_mips_clock(1));
1049     printk("cpu clock    = %d\n", cgu_get_cpu_clock());
1050     printk("IO region    = %d\n", cgu_get_io_region_clock());
1051     printk("FPI bus 1    = %d\n", cgu_get_fpi_bus_clock(1));
1052     printk("FPI bus 2    = %d\n", cgu_get_fpi_bus_clock(2));
1053     printk("PP32 clock   = %d\n", cgu_get_pp32_clock());
1054     printk("PCI clock    = %d\n", cgu_get_pci_clock());
1055     printk("Ethernet     = %d\n", cgu_get_ethernet_clock());
1056     printk("USB clock    = %d\n", cgu_get_usb_clock());
1057     printk("Clockout0    = %d\n", cgu_get_clockout(0));
1058     printk("Clockout1    = %d\n", cgu_get_clockout(1));
1059     printk("Clockout2    = %d\n", cgu_get_clockout(2));
1060     printk("Clockout3    = %d\n", cgu_get_clockout(3));
1061 #endif  //  defined(DEBUG_PRINT_INFO) && DEBUG_PRINT_INFO
1062
1063     return 0;
1064 }
1065
1066 /*
1067  *  Description:
1068  *    deregister device
1069  *  Input:
1070  *    none
1071  *  Output:
1072  *    none
1073  */
1074 void __exit danube_cgu_exit(void)
1075 {
1076     int ret;
1077
1078     ret = misc_deregister(&cgu_miscdev);
1079     if ( ret )
1080         printk(KERN_ERR "cgu: can't misc_deregister, get error number %d\n", -ret);
1081     else
1082         printk(KERN_INFO "cgu: misc_deregister successfully\n");
1083 }
1084
1085 module_init(danube_cgu_init);
1086 module_exit(danube_cgu_exit);