package/uboot-ifxmips/files/cpu/mips/danube/start_bootstrap.S

   1 /*
   2  *  Startup Code for MIPS32 CPU-core
   3  *
   4  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25
  26 #include <config.h>
  27 #include <version.h>
  28 #include <asm/regdef.h>
  29 #include <asm/mipsregs.h>
  30
  31
  32 #define RVECENT(f,n) \
  33    b f; nop
  34 #define XVECENT(f,bev) \
  35    b f     ;           \
  36    li k0,bev
  37
  38         .set noreorder
  39
  40         .globl _start_bootstrap
  41         .text
  42 _start_bootstrap:
  43         RVECENT(reset,0)        /* U-boot entry point */
  44         RVECENT(reset,1)        /* software reboot */
  45 #if defined(CONFIG_INCA_IP) || defined(CONFIG_INCA_IP2)
  46         .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
  47         .word 0x00000000           /* phase of the flash                    */
  48 #elif defined(CONFIG_PURPLE)
  49         .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
  50         .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
  51 #elif defined(CONFIG_DANUBE)
  52
  53         .org 0x10
  54         .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
  55         .word 0x00000000           /* phase of the flash                    */
  56
  57         .org 0x18
  58         .word 0x312E3000           /* version x.x                           */
  59         .word 0x00000000           /* phase of the flash                    */
  60 #else
  61         RVECENT(romReserved,2)
  62 #endif
  63         RVECENT(romReserved,3)
  64         RVECENT(romReserved,4)
  65         RVECENT(romReserved,5)
  66         RVECENT(romReserved,6)
  67         RVECENT(romReserved,7)
  68         RVECENT(romReserved,8)
  69         RVECENT(romReserved,9)
  70         RVECENT(romReserved,10)
  71         RVECENT(romReserved,11)
  72         RVECENT(romReserved,12)
  73         RVECENT(romReserved,13)
  74         RVECENT(romReserved,14)
  75         RVECENT(romReserved,15)
  76         RVECENT(romReserved,16)
  77         RVECENT(romReserved,17)
  78         RVECENT(romReserved,18)
  79         RVECENT(romReserved,19)
  80         RVECENT(romReserved,20)
  81         RVECENT(romReserved,21)
  82         RVECENT(romReserved,22)
  83         RVECENT(romReserved,23)
  84         RVECENT(romReserved,24)
  85         RVECENT(romReserved,25)
  86         RVECENT(romReserved,26)
  87         RVECENT(romReserved,27)
  88         RVECENT(romReserved,28)
  89         RVECENT(romReserved,29)
  90         RVECENT(romReserved,30)
  91         RVECENT(romReserved,31)
  92         RVECENT(romReserved,32)
  93         RVECENT(romReserved,33)
  94         RVECENT(romReserved,34)
  95         RVECENT(romReserved,35)
  96         RVECENT(romReserved,36)
  97         RVECENT(romReserved,37)
  98         RVECENT(romReserved,38)
  99         RVECENT(romReserved,39)
 100         RVECENT(romReserved,40)
 101         RVECENT(romReserved,41)
 102         RVECENT(romReserved,42)
 103         RVECENT(romReserved,43)
 104         RVECENT(romReserved,44)
 105         RVECENT(romReserved,45)
 106         RVECENT(romReserved,46)
 107         RVECENT(romReserved,47)
 108         RVECENT(romReserved,48)
 109         RVECENT(romReserved,49)
 110         RVECENT(romReserved,50)
 111         RVECENT(romReserved,51)
 112         RVECENT(romReserved,52)
 113         RVECENT(romReserved,53)
 114         RVECENT(romReserved,54)
 115         RVECENT(romReserved,55)
 116         RVECENT(romReserved,56)
 117         RVECENT(romReserved,57)
 118         RVECENT(romReserved,58)
 119         RVECENT(romReserved,59)
 120         RVECENT(romReserved,60)
 121         RVECENT(romReserved,61)
 122         RVECENT(romReserved,62)
 123         RVECENT(romReserved,63)
 124         XVECENT(romExcHandle,0x200)     /* bfc00200: R4000 tlbmiss vector */
 125         RVECENT(romReserved,65)
 126         RVECENT(romReserved,66)
 127         RVECENT(romReserved,67)
 128         RVECENT(romReserved,68)
 129         RVECENT(romReserved,69)
 130         RVECENT(romReserved,70)
 131         RVECENT(romReserved,71)
 132         RVECENT(romReserved,72)
 133         RVECENT(romReserved,73)
 134         RVECENT(romReserved,74)
 135         RVECENT(romReserved,75)
 136         RVECENT(romReserved,76)
 137         RVECENT(romReserved,77)
 138         RVECENT(romReserved,78)
 139         RVECENT(romReserved,79)
 140         XVECENT(romExcHandle,0x280)     /* bfc00280: R4000 xtlbmiss vector */
 141         RVECENT(romReserved,81)
 142         RVECENT(romReserved,82)
 143         RVECENT(romReserved,83)
 144         RVECENT(romReserved,84)
 145         RVECENT(romReserved,85)
 146         RVECENT(romReserved,86)
 147         RVECENT(romReserved,87)
 148         RVECENT(romReserved,88)
 149         RVECENT(romReserved,89)
 150         RVECENT(romReserved,90)
 151         RVECENT(romReserved,91)
 152         RVECENT(romReserved,92)
 153         RVECENT(romReserved,93)
 154         RVECENT(romReserved,94)
 155         RVECENT(romReserved,95)
 156         XVECENT(romExcHandle,0x300)     /* bfc00300: R4000 cache vector */
 157         RVECENT(romReserved,97)
 158         RVECENT(romReserved,98)
 159         RVECENT(romReserved,99)
 160         RVECENT(romReserved,100)
 161         RVECENT(romReserved,101)
 162         RVECENT(romReserved,102)
 163         RVECENT(romReserved,103)
 164         RVECENT(romReserved,104)
 165         RVECENT(romReserved,105)
 166         RVECENT(romReserved,106)
 167         RVECENT(romReserved,107)
 168         RVECENT(romReserved,108)
 169         RVECENT(romReserved,109)
 170         RVECENT(romReserved,110)
 171         RVECENT(romReserved,111)
 172         XVECENT(romExcHandle,0x380)     /* bfc00380: R4000 general vector */
 173         RVECENT(romReserved,113)
 174         RVECENT(romReserved,114)
 175         RVECENT(romReserved,115)
 176         RVECENT(romReserved,116)
 177         RVECENT(romReserved,116)
 178         RVECENT(romReserved,118)
 179         RVECENT(romReserved,119)
 180         RVECENT(romReserved,120)
 181         RVECENT(romReserved,121)
 182         RVECENT(romReserved,122)
 183         RVECENT(romReserved,123)
 184         RVECENT(romReserved,124)
 185         RVECENT(romReserved,125)
 186         RVECENT(romReserved,126)
 187         RVECENT(romReserved,127)
 188
 189         /* We hope there are no more reserved vectors!
 190          * 128 * 8 == 1024 == 0x400
 191          * so this is address R_VEC+0x400 == 0xbfc00400
 192          */
 193 #ifdef CONFIG_PURPLE
 194 /* 0xbfc00400 */
 195         .word   0xdc870000
 196         .word   0xfca70000
 197         .word   0x20840008
 198         .word   0x20a50008
 199         .word   0x20c6ffff
 200         .word   0x14c0fffa
 201         .word   0x00000000
 202         .word   0x03e00008
 203         .word   0x00000000
 204         .word   0x00000000
 205 /* 0xbfc00428 */
 206         .word   0xdc870000
 207         .word   0xfca70000
 208         .word   0x20840008
 209         .word   0x20a50008
 210         .word   0x20c6ffff
 211         .word   0x14c0fffa
 212         .word   0x00000000
 213         .word   0x03e00008
 214         .word   0x00000000
 215         .word   0x00000000
 216 #endif /* CONFIG_PURPLE */
 217         .align 4
 218 reset:
 219 #ifdef CONFIG_INCA_IP2
 220         /* Check for Host or Voice CPU */
 221
 222         mfc0    k0, CP0_EBASE
 223         and     k0, EBASEF_CPUNUM
 224         srl     k0, EBASEB_CPUNUM
 225         subu    k0, EBASE_CPU_HOST
 226         bne     k0, zero, voice_reset_handler
 227         nop
 228
 229 #endif
 230
 231         /* Clear watch registers.
 232          */
 233         mtc0    zero, CP0_WATCHLO
 234         mtc0    zero, CP0_WATCHHI
 235
 236         /* STATUS register */
 237 #ifdef  CONFIG_TB0229
 238         li      k0, ST0_CU0
 239 #else
 240         mfc0    k0, CP0_STATUS
 241 #endif
 242         li      k1, ~ST0_IE
 243         and     k0, k1
 244         mtc0    k0, CP0_STATUS
 245
 246         /* CAUSE register */
 247         mtc0    zero, CP0_CAUSE
 248
 249 #ifdef CONFIG_INCA_IP2
 250         /* CONFIG7 register */
 251         mfc0    k0, CP0_CONFIG, 7
 252         li      k1, 4 /* Disable RPS due to E83 bug of 24KEC */
 253         or      k0, k1
 254         mtc0    k0, CP0_CONFIG, 7
 255 #endif
 256         /* Init Timer */
 257         mtc0    zero, CP0_COUNT
 258         mtc0    zero, CP0_COMPARE
 259
 260         /* CONFIG0 register */
 261         li      t0, CONF_CM_UNCACHED
 262         mtc0    t0, CP0_CONFIG
 263
 264         /* Initialize GOT pointer.
 265         */
 266         bal     1f
 267         nop
 268         .word   _GLOBAL_OFFSET_TABLE_
 269         1:
 270         move    gp, ra
 271         lw      t1, 0(ra)
 272         move    gp, t1
 273
 274 #ifdef CONFIG_INCA_IP
 275         /* Disable INCA-IP Watchdog.
 276          */
 277         la      t9, disable_incaip_wdt
 278         jalr    t9
 279         nop
 280 #endif
 281
 282         /* Initialize any external memory.
 283          */
 284         la      t9, lowlevel_init
 285         jalr    t9
 286         nop
 287
 288         /* Initialize caches...
 289          */
 290         la      t9, mips_cache_reset
 291         jalr    t9
 292         nop
 293
 294         /* ... and enable them.
 295          */
 296 #ifdef CONFIG_MIPS_FORCE_CACHE_WRITE_THROUGH
 297         li      t0, CONF_CM_CACHABLE_NO_WA
 298 #else
 299         li      t0, CONF_CM_CACHABLE_NONCOHERENT
 300 #endif
 301         mtc0    t0, CP0_CONFIG
 302
 303
 304         /* Set up temporary stack.
 305          */
 306         li      a0, CFG_INIT_SP_OFFSET
 307         la      t9, mips_cache_lock
 308         jalr    t9
 309         nop
 310
 311         li      t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
 312         la      sp, 0(t0)
 313
 314         la      t9, bootstrap_board_init_f
 315         j       t9
 316         nop
 317
 318
 319 /*
 320  * void bootstrap_relocate_code (addr_sp, gd, addr_moni)
 321  *
 322  * This "function" does not return, instead it continues in RAM
 323  * after relocating the monitor code.
 324  *
 325  * a0 = addr_sp
 326  * a1 = gd
 327  * a2 = destination address
 328  */
 329         .globl  bootstrap_relocate_code
 330         .ent    bootstrap_relocate_code
 331 bootstrap_relocate_code:
 332         move    sp, a0          /* Set new stack pointer                */
 333
 334         li      t0, BOOTSTRAP_CFG_MONITOR_BASE
 335         la      t3, in_ram
 336         lw      t2, -12(t3)     /* t2 <-- uboot_end_data_bootsrap       */
 337         move    t1, a2
 338
 339         /*
 340          * Fix GOT pointer:
 341          *
 342          * New GOT-PTR = (old GOT-PTR - BOOTSTRAP_CFG_MONITOR_BASE) + Destination Address
 343          */
 344         move    t6, gp
 345         sub     gp, BOOTSTRAP_CFG_MONITOR_BASE
 346         add     gp, a2                  /* gp now adjusted              */
 347         sub     t6, gp, t6              /* t6 <-- relocation offset     */
 348
 349         /*
 350          * t0 = source address
 351          * t1 = target address
 352          * t2 = source end address
 353          */
 354         /* On the purple board we copy the code earlier in a special way
 355          * in order to solve flash problems
 356          */
 357 #ifndef CONFIG_PURPLE
 358 1:
 359         lw      t3, 0(t0)
 360         sw      t3, 0(t1)
 361         addu    t0, 4
 362         ble     t0, t2, 1b
 363         addu    t1, 4                   /* delay slot                   */
 364 #endif
 365
 366         /* If caches were enabled, we would have to flush them here.
 367          */
 368
 369         /* Jump to where we've relocated ourselves.
 370          */
 371         addi    t0, a2, in_ram - _start_bootstrap
 372         j       t0
 373         nop
 374
 375         .word   uboot_end_data_bootstrap
 376         .word   uboot_end_bootstrap
 377         .word   num_got_entries
 378
 379 in_ram:
 380         /* Now we want to update GOT.
 381          */
 382         lw      t3, -4(t0)      /* t3 <-- num_got_entries       */
 383         addi    t4, gp, 8       /* Skipping first two entries.  */
 384         li      t2, 2
 385 1:
 386         lw      t1, 0(t4)
 387         beqz    t1, 2f
 388         add     t1, t6
 389         sw      t1, 0(t4)
 390 2:
 391         addi    t2, 1
 392         blt     t2, t3, 1b
 393         addi    t4, 4           /* delay slot                   */
 394
 395         /* Clear BSS.
 396          */
 397         lw      t1, -12(t0)     /* t1 <-- uboot_end_data_bootstrap      */
 398         lw      t2, -8(t0)      /* t2 <-- uboot_end_bootstrap           */
 399         add     t1, t6          /* adjust pointers              */
 400         add     t2, t6
 401
 402         sub     t1, 4
 403 1:      addi    t1, 4
 404         bltl    t1, t2, 1b
 405         sw      zero, 0(t1)     /* delay slot                   */
 406
 407         move    a0, a1
 408         la      t9, bootstrap_board_init_r
 409         j       t9
 410         move    a1, a2          /* delay slot                   */
 411
 412         .end    bootstrap_relocate_code
 413
 414
 415         /* Exception handlers.
 416          */
 417 romReserved:
 418         b romReserved
 419
 420 romExcHandle:
 421         b romExcHandle
 422
 423 #ifdef CONFIG_INCA_IP2
 424 voice_reset_handler:
 425         wait
 426         b voice_reset_handler
 427         nop
 428 #endif