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[ppc44x] refresh kernel patches
[openwrt.git] / target / linux / ifxmips / files / drivers / char / ifxmips_ssc.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright (C) 2006 infineon
17 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
18 *
19 */
20
21 // ### TO DO: general issues:
22 // - power management
23 // - interrupt handling (direct/indirect)
24 // - pin/mux-handling (just overall concept due to project dependency)
25 // - multiple instances capability
26 // - slave functionality
27
28 #include <linux/module.h>
29 #include <linux/errno.h>
30 #include <linux/signal.h>
31 #include <linux/sched.h>
32 #include <linux/timer.h>
33 #include <linux/interrupt.h>
34 #include <linux/major.h>
35 #include <linux/string.h>
36 #include <linux/fs.h>
37 #include <linux/fcntl.h>
38 #include <linux/ptrace.h>
39 #include <linux/mm.h>
40 #include <linux/ioport.h>
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/spinlock.h>
44 #include <linux/slab.h>
45
46 #include <asm/system.h>
47 #include <asm/io.h>
48 #include <asm/irq.h>
49 #include <asm/uaccess.h>
50 #include <asm/bitops.h>
51
52 #include <linux/types.h>
53 #include <linux/kernel.h>
54 #include <linux/version.h>
55
56 #include <asm/ifxmips/ifxmips.h>
57 #include <asm/ifxmips/ifxmips_irq.h>
58 #include <asm/ifxmips/ifx_ssc_defines.h>
59 #include <asm/ifxmips/ifx_ssc.h>
60
61 /* allow the user to set the major device number */
62 static int maj = 0;
63
64 /*
65 * This is the per-channel data structure containing pointers, flags
66 * and variables for the port. This driver supports a maximum of PORT_CNT.
67 * isp is allocated in ifx_ssc_init() based on the chip version.
68 */
69 static struct ifx_ssc_port *isp;
70
71 /* other forward declarations */
72 static unsigned int ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info);
73 static void tx_int (struct ifx_ssc_port *);
74
75 extern unsigned int ifxmips_get_fpi_hz (void);
76 extern void mask_and_ack_ifxmips_irq (unsigned int irq_nr);
77
78 static inline unsigned int
79 ifx_ssc_get_kernel_clk (struct ifx_ssc_port *info)
80 {
81 unsigned int rmc;
82
83 rmc = (readl(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
84 if (rmc == 0)
85 {
86 printk ("ifx_ssc_get_kernel_clk rmc==0 \n");
87 return 0;
88 }
89 return ifxmips_get_fpi_hz () / rmc;
90 }
91
92 inline static void
93 rx_int (struct ifx_ssc_port *info)
94 {
95 int fifo_fill_lev, bytes_in_buf, i;
96 unsigned long tmp_val;
97 unsigned long *tmp_ptr;
98 unsigned int rx_valid_cnt;
99 /* number of words waiting in the RX FIFO */
100 fifo_fill_lev = (readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
101 bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
102 // transfer with 32 bits per entry
103 while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
104 tmp_ptr = (unsigned long *) info->rxbuf_ptr;
105 *tmp_ptr = readl(IFXMIPS_SSC_RB);
106 info->rxbuf_ptr += 4;
107 info->stats.rxBytes += 4;
108 fifo_fill_lev--;
109 bytes_in_buf -= 4;
110 }
111
112 // now do the rest as mentioned in STATE.RXBV
113 while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
114 rx_valid_cnt = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
115 if (rx_valid_cnt == 0)
116 break;
117
118 if (rx_valid_cnt > bytes_in_buf)
119 rx_valid_cnt = bytes_in_buf;
120
121 tmp_val = readl(IFXMIPS_SSC_RB);
122
123 for (i = 0; i < rx_valid_cnt; i++)
124 {
125 *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff;
126 bytes_in_buf--;
127 info->rxbuf_ptr++;
128 }
129 info->stats.rxBytes += rx_valid_cnt;
130 }
131
132 // check if transfer is complete
133 if (info->rxbuf_ptr >= info->rxbuf_end)
134 {
135 disable_irq(IFXMIPS_SSC_RIR);
136 wake_up_interruptible (&info->rwait);
137 } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (readl(IFXMIPS_SSC_RXCNT) == 0))
138 {
139 if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
140 writel((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
141 else
142 writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
143 }
144 }
145
146 inline static void
147 tx_int (struct ifx_ssc_port *info)
148 {
149
150 int fifo_space, fill, i;
151 fifo_space = ((readl(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
152 - ((readl(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
153
154 if (fifo_space == 0)
155 return;
156
157 fill = info->txbuf_end - info->txbuf_ptr;
158
159 if (fill > fifo_space * 4)
160 fill = fifo_space * 4;
161
162 for (i = 0; i < fill / 4; i++)
163 {
164 // at first 32 bit access
165 writel(*(UINT32 *) info->txbuf_ptr, IFXMIPS_SSC_TB);
166 info->txbuf_ptr += 4;
167 }
168
169 fifo_space -= fill / 4;
170 info->stats.txBytes += fill & ~0x3;
171 fill &= 0x3;
172 if ((fifo_space > 0) & (fill > 1))
173 {
174 // trailing 16 bit access
175 WRITE_PERIPHERAL_REGISTER_16 (*(UINT16 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
176 info->txbuf_ptr += 2;
177 info->stats.txBytes += 2;
178 fifo_space--;
179 fill -= 2;
180 }
181
182 if ((fifo_space > 0) & (fill > 0))
183 {
184 // trailing 8 bit access
185 WRITE_PERIPHERAL_REGISTER_8 (*(UINT8 *) info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
186 info->txbuf_ptr++;
187 info->stats.txBytes++;
188 }
189
190 // check if transmission complete
191 if (info->txbuf_ptr >= info->txbuf_end)
192 {
193 disable_irq(IFXMIPS_SSC_TIR);
194 kfree (info->txbuf);
195 info->txbuf = NULL;
196 }
197
198 }
199
200 irqreturn_t
201 ifx_ssc_rx_int (int irq, void *dev_id)
202 {
203 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
204 rx_int (info);
205
206 return IRQ_HANDLED;
207 }
208
209 irqreturn_t
210 ifx_ssc_tx_int (int irq, void *dev_id)
211 {
212 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
213 tx_int (info);
214
215 return IRQ_HANDLED;
216 }
217
218 irqreturn_t
219 ifx_ssc_err_int (int irq, void *dev_id)
220 {
221 struct ifx_ssc_port *info = (struct ifx_ssc_port *) dev_id;
222 unsigned int state;
223 unsigned int write_back = 0;
224 unsigned long flags;
225
226 local_irq_save (flags);
227 state = readl(IFXMIPS_SSC_STATE);
228
229 if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
230 info->stats.rxUnErr++;
231 write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
232 }
233
234 if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
235 info->stats.rxOvErr++;
236 write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
237 }
238
239 if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
240 info->stats.txOvErr++;
241 write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
242 }
243
244 if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
245 info->stats.txUnErr++;
246 write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
247 }
248
249 if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
250 info->stats.modeErr++;
251 write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
252 }
253
254 if (write_back)
255 writel(write_back, IFXMIPS_SSC_WHBSTATE);
256
257 local_irq_restore (flags);
258
259 return IRQ_HANDLED;
260 }
261
262 static void
263 ifx_ssc_abort (struct ifx_ssc_port *info)
264 {
265 unsigned long flags;
266 bool enabled;
267
268 local_irq_save (flags);
269
270 disable_irq(IFXMIPS_SSC_RIR);
271 disable_irq(IFXMIPS_SSC_TIR);
272 disable_irq(IFXMIPS_SSC_EIR);
273
274 local_irq_restore (flags);
275
276 // disable SSC (also aborts a receive request!)
277 // ### TO DO: Perhaps it's better to abort after the receiption of a
278 // complete word. The disable cuts the transmission immediatly and
279 // releases the chip selects. This could result in unpredictable
280 // behavior of connected external devices!
281 enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
282 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
283
284 // flush fifos
285 writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
286 writel(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
287
288 // free txbuf
289 if (info->txbuf != NULL)
290 {
291 kfree (info->txbuf);
292 info->txbuf = NULL;
293 }
294
295 // wakeup read process
296 if (info->rxbuf != NULL)
297 wake_up_interruptible (&info->rwait);
298
299 // clear pending int's
300 mask_and_ack_ifxmips_irq(IFXMIPS_SSC_RIR);
301 mask_and_ack_ifxmips_irq(IFXMIPS_SSC_TIR);
302 mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
303
304 // clear error flags
305 writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
306
307 if (enabled)
308 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
309
310 }
311
312 /*
313 * This routine is called whenever a port is opened. It enforces
314 * exclusive opening of a port and enables interrupts, etc.
315 */
316 int
317 ifx_ssc_open (struct inode *inode, struct file *filp)
318 {
319 struct ifx_ssc_port *info;
320 int line;
321 int from_kernel = 0;
322
323 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1)) {
324 from_kernel = 1;
325 line = (int) inode;
326 } else {
327 line = MINOR (filp->f_dentry->d_inode->i_rdev);
328 }
329
330 /* don't open more minor devices than we can support */
331 if (line < 0 || line >= PORT_CNT)
332 return -ENXIO;
333
334 info = &isp[line];
335
336 /* exclusive open */
337 if (info->port_is_open != 0)
338 return -EBUSY;
339 info->port_is_open++;
340
341 disable_irq(IFXMIPS_SSC_RIR);
342 disable_irq(IFXMIPS_SSC_TIR);
343 disable_irq(IFXMIPS_SSC_EIR);
344
345 /* Flush and enable TX/RX FIFO */
346 writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
347 writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
348
349 /* logically flush the software FIFOs */
350 info->rxbuf_ptr = 0;
351 info->txbuf_ptr = 0;
352
353 /* clear all error bits */
354 writel(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
355
356 // clear pending interrupts
357 mask_and_ack_ifxmips_irq(IFXMIPS_SSC_RIR);
358 mask_and_ack_ifxmips_irq(IFXMIPS_SSC_TIR);
359 mask_and_ack_ifxmips_irq(IFXMIPS_SSC_EIR);
360
361 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
362
363 return 0;
364 }
365 EXPORT_SYMBOL(ifx_ssc_open);
366
367 int
368 ifx_ssc_close (struct inode *inode, struct file *filp)
369 {
370 struct ifx_ssc_port *info;
371 int idx;
372
373 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
374 idx = (int) inode;
375 else
376 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
377
378 if (idx < 0 || idx >= PORT_CNT)
379 return -ENXIO;
380
381 info = &isp[idx];
382 if (!info)
383 return -ENXIO;
384
385 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
386
387 ifx_ssc_abort(info);
388
389 info->port_is_open--;
390
391 return 0;
392 }
393 EXPORT_SYMBOL(ifx_ssc_close);
394
395 static ssize_t
396 ifx_ssc_read_helper_poll (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
397 {
398 ssize_t ret_val;
399 unsigned long flags;
400
401 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
402 return -EFAULT;
403 local_irq_save (flags);
404 info->rxbuf_ptr = info->rxbuf;
405 info->rxbuf_end = info->rxbuf + len;
406 local_irq_restore (flags);
407 /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
408 /* TXRX in poll mode */
409 while (info->rxbuf_ptr < info->rxbuf_end)
410 {
411 if (info->txbuf_ptr < info->txbuf_end)
412 tx_int (info);
413
414 rx_int (info);
415 };
416
417 ret_val = info->rxbuf_ptr - info->rxbuf;
418
419 return ret_val;
420 }
421
422 static ssize_t
423 ifx_ssc_read_helper (struct ifx_ssc_port *info, char *buf, size_t len, int from_kernel)
424 {
425 ssize_t ret_val;
426 unsigned long flags;
427 DECLARE_WAITQUEUE (wait, current);
428
429 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
430 return -EFAULT;
431
432 local_irq_save (flags);
433 info->rxbuf_ptr = info->rxbuf;
434 info->rxbuf_end = info->rxbuf + len;
435
436 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX)
437 {
438 if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf))
439 {
440 local_irq_restore (flags);
441 printk ("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__);
442 return -EFAULT;
443 }
444
445 local_irq_restore(flags);
446 tx_int (info);
447
448 if (info->txbuf_ptr < info->txbuf_end)
449 enable_irq(IFXMIPS_SSC_TIR);
450
451 enable_irq(IFXMIPS_SSC_RIR);
452 } else {
453 local_irq_restore(flags);
454 if (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
455 return -EBUSY;
456 enable_irq(IFXMIPS_SSC_RIR);
457 if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
458 writel(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
459 else
460 writel(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
461 }
462
463 __add_wait_queue (&info->rwait, &wait);
464 set_current_state (TASK_INTERRUPTIBLE);
465
466 do {
467 local_irq_save (flags);
468 if (info->rxbuf_ptr >= info->rxbuf_end)
469 break;
470
471 local_irq_restore (flags);
472
473 if (signal_pending (current))
474 {
475 ret_val = -ERESTARTSYS;
476 goto out;
477 }
478 schedule();
479 } while (1);
480
481 ret_val = info->rxbuf_ptr - info->rxbuf;
482 local_irq_restore (flags);
483
484 out:
485 current->state = TASK_RUNNING;
486 __remove_wait_queue (&info->rwait, &wait);
487
488 return (ret_val);
489 }
490
491 static ssize_t
492 ifx_ssc_write_helper (struct ifx_ssc_port *info, const char *buf,
493 size_t len, int from_kernel)
494 {
495 if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
496 return -EFAULT;
497
498 info->txbuf_ptr = info->txbuf;
499 info->txbuf_end = len + info->txbuf;
500 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
501 {
502 tx_int (info);
503 if (info->txbuf_ptr < info->txbuf_end)
504 {
505 enable_irq(IFXMIPS_SSC_TIR);
506 }
507 }
508
509 return len;
510 }
511
512 ssize_t
513 ifx_ssc_kread (int port, char *kbuf, size_t len)
514 {
515 struct ifx_ssc_port *info;
516 ssize_t ret_val;
517
518 if (port < 0 || port >= PORT_CNT)
519 return -ENXIO;
520
521 if (len == 0)
522 return 0;
523
524 info = &isp[port];
525
526 if (info->rxbuf != NULL)
527 {
528 printk ("SSC device busy\n");
529 return -EBUSY;
530 }
531
532 info->rxbuf = kbuf;
533 if (info->rxbuf == NULL)
534 {
535 printk ("SSC device error\n");
536 return -EINVAL;
537 }
538
539 ret_val = ifx_ssc_read_helper_poll (info, kbuf, len, 1);
540 info->rxbuf = NULL;
541
542 disable_irq(IFXMIPS_SSC_RIR);
543
544 return ret_val;
545 }
546 EXPORT_SYMBOL(ifx_ssc_kread);
547
548 ssize_t
549 ifx_ssc_kwrite (int port, const char *kbuf, size_t len)
550 {
551 struct ifx_ssc_port *info;
552 ssize_t ret_val;
553
554 if (port < 0 || port >= PORT_CNT)
555 return -ENXIO;
556
557 if (len == 0)
558 return 0;
559
560 info = &isp[port];
561
562 // check if transmission in progress
563 if (info->txbuf != NULL)
564 return -EBUSY;
565
566 info->txbuf = (char *) kbuf;
567
568 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 1);
569
570 if (ret_val < 0)
571 info->txbuf = NULL;
572
573 return ret_val;
574 }
575 EXPORT_SYMBOL(ifx_ssc_kwrite);
576
577 static ssize_t
578 ifx_ssc_read (struct file *filp, char *ubuf, size_t len, loff_t * off)
579 {
580 ssize_t ret_val;
581 int idx;
582 struct ifx_ssc_port *info;
583
584 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
585 info = &isp[idx];
586
587 if (info->rxbuf != NULL)
588 return -EBUSY;
589
590 info->rxbuf = kmalloc (len + 3, GFP_KERNEL);
591 if (info->rxbuf == NULL)
592 return -ENOMEM;
593
594 ret_val = ifx_ssc_read_helper (info, info->rxbuf, len, 0);
595 if (copy_to_user ((void *) ubuf, info->rxbuf, ret_val) != 0)
596 ret_val = -EFAULT;
597
598 disable_irq(IFXMIPS_SSC_RIR);
599
600 kfree (info->rxbuf);
601 info->rxbuf = NULL;
602
603 return (ret_val);
604 }
605
606 static ssize_t
607 ifx_ssc_write (struct file *filp, const char *ubuf, size_t len, loff_t * off)
608 {
609 int idx;
610 struct ifx_ssc_port *info;
611 int ret_val;
612
613 if (len == 0)
614 return (0);
615
616 idx = MINOR (filp->f_dentry->d_inode->i_rdev);
617 info = &isp[idx];
618
619 if (info->txbuf != NULL)
620 return -EBUSY;
621
622 info->txbuf = kmalloc (len + 3, GFP_KERNEL);
623 if (info->txbuf == NULL)
624 return -ENOMEM;
625
626 ret_val = copy_from_user (info->txbuf, ubuf, len);
627 if (ret_val == 0)
628 ret_val = ifx_ssc_write_helper (info, info->txbuf, len, 0);
629 else
630 ret_val = -EFAULT;
631
632 if (ret_val < 0)
633 {
634 kfree (info->txbuf);
635 info->txbuf = NULL;
636 }
637
638 return (ret_val);
639 }
640
641 static struct ifx_ssc_frm_status *
642 ifx_ssc_frm_status_get (struct ifx_ssc_port *info)
643 {
644 unsigned long tmp;
645
646 tmp = readl(IFXMIPS_SSC_SFSTAT);
647 info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
648 info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
649 info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
650 info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
651 tmp = readl(IFXMIPS_SSC_SFCON);
652 info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
653 info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
654
655 return &info->frm_status;
656 }
657
658
659 static struct ifx_ssc_frm_opts *
660 ifx_ssc_frm_control_get (struct ifx_ssc_port *info)
661 {
662 unsigned long tmp;
663
664 tmp = readl(IFXMIPS_SSC_SFCON);
665 info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
666 info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
667 info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
668 info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
669 info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
670 info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
671
672 return &info->frm_opts;
673 }
674
675 static int
676 ifx_ssc_frm_control_set (struct ifx_ssc_port *info)
677 {
678 unsigned long tmp;
679
680 if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX)
681 || (info->frm_opts.DataLength < 1)
682 || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX)
683 || (info->frm_opts.PauseLength < 1)
684 || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET))
685 || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)))
686 return -EINVAL;
687
688 // read interrupt bits (they're not changed here)
689 tmp = readl(IFXMIPS_SSC_SFCON) &
690 (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
691
692 // set all values with respect to it's bit position (for data and pause
693 // length set N-1)
694 tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
695 tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
696 tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
697 tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
698 tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
699 tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
700
701 writel(tmp, IFXMIPS_SSC_SFCON);
702
703 return 0;
704 }
705
706 static int
707 ifx_ssc_rxtx_mode_set (struct ifx_ssc_port *info, unsigned int val)
708 {
709 unsigned long tmp;
710
711 if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
712 return -EINVAL;
713
714 if ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
715 || (readl(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
716 return -EBUSY;
717
718 tmp = (readl(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
719 writel(tmp, IFXMIPS_SSC_SFCON);
720 info->opts.modeRxTx = val;
721
722 return 0;
723 }
724
725 static int
726 ifx_ssc_sethwopts (struct ifx_ssc_port *info)
727 {
728 unsigned long flags, bits;
729 struct ifx_ssc_hwopts *opts = &info->opts;
730
731 if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH)
732 || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH))
733 return -EINVAL;
734
735 bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
736 bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
737
738 if (opts->rxOvErrDetect)
739 bits |= IFX_SSC_CON_RX_OFL_CHECK;
740 if (opts->rxUndErrDetect)
741 bits |= IFX_SSC_CON_RX_UFL_CHECK;
742 if (opts->txOvErrDetect)
743 bits |= IFX_SSC_CON_TX_OFL_CHECK;
744 if (opts->txUndErrDetect)
745 bits |= IFX_SSC_CON_TX_UFL_CHECK;
746 if (opts->loopBack)
747 bits |= IFX_SSC_CON_LOOPBACK_MODE;
748 if (opts->echoMode)
749 bits |= IFX_SSC_CON_ECHO_MODE_ON;
750 if (opts->headingControl)
751 bits |= IFX_SSC_CON_MSB_FIRST;
752 if (opts->clockPhase)
753 bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
754 if (opts->clockPolarity)
755 bits |= IFX_SSC_CON_CLOCK_FALL;
756
757 switch (opts->modeRxTx)
758 {
759 case IFX_SSC_MODE_TX:
760 bits |= IFX_SSC_CON_RX_OFF;
761 break;
762 case IFX_SSC_MODE_RX:
763 bits |= IFX_SSC_CON_TX_OFF;
764 break;
765 }
766
767 local_irq_save (flags);
768
769 writel(bits, IFXMIPS_SSC_CON);
770 writel((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
771 (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON);
772
773 writel(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
774
775 //master mode
776 if (opts->masterSelect)
777 writel(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
778 else
779 writel(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
780
781 // init serial framing
782 writel(0, IFXMIPS_SSC_SFCON);
783 /* set up the port pins */
784 //check for general requirements to switch (external) pad/pin characteristics
785 /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
786 /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
787 /* Set p0.15 to alternative 01, others to 00 (In/OUT) */
788 *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
789 *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
790 *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
791 *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
792
793 /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
794 *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
795 *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
796 *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
797 *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
798
799 /*CS3 */
800 /*TODO: CS4 CS5 CS6 */
801 *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
802
803 local_irq_restore (flags);
804
805 return 0;
806 }
807
808 static int
809 ifx_ssc_set_baud (struct ifx_ssc_port *info, unsigned int baud)
810 {
811 unsigned int ifx_ssc_clock;
812 unsigned int br;
813 unsigned long flags;
814 bool enabled;
815 int retval = 0;
816
817 ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
818 if (ifx_ssc_clock == 0)
819 {
820 retval = -EINVAL;
821 goto out;
822 }
823
824 local_irq_save (flags);
825
826 enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
827 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
828
829 br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
830 wmb();
831
832 if (br > 0xffff || ((br == 0) &&
833 ((readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
834 local_irq_restore (flags);
835 printk ("%s: invalid baudrate %u\n", __func__, baud);
836 return -EINVAL;
837 }
838
839 writel(br, IFXMIPS_SSC_BR);
840
841 if (enabled)
842 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
843
844 local_irq_restore(flags);
845
846 out:
847 return retval;
848 }
849
850 static int
851 ifx_ssc_hwinit (struct ifx_ssc_port *info)
852 {
853 unsigned long flags;
854 bool enabled;
855
856 enabled = (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
857 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
858
859 if (ifx_ssc_sethwopts (info) < 0)
860 {
861 printk ("%s: setting the hardware options failed\n", __func__);
862 return -EINVAL;
863 }
864
865 if (ifx_ssc_set_baud (info, info->baud) < 0)
866 {
867 printk ("%s: setting the baud rate failed\n", __func__);
868 return -EINVAL;
869 }
870
871 local_irq_save (flags);
872
873 /* TX FIFO */
874 writel((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
875 /* RX FIFO */
876 writel((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
877
878 local_irq_restore (flags);
879
880 if (enabled)
881 writel(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
882
883 return 0;
884 }
885
886 int
887 ifx_ssc_ioctl (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long data)
888 {
889 struct ifx_ssc_port *info;
890 int line, ret_val = 0;
891 unsigned long flags;
892 unsigned long tmp;
893 int from_kernel = 0;
894
895 if ((inode == (struct inode *) 0) || (inode == (struct inode *) 1))
896 {
897 from_kernel = 1;
898 line = (int) inode;
899 } else {
900 line = MINOR (filp->f_dentry->d_inode->i_rdev);
901 }
902
903 if (line < 0 || line >= PORT_CNT)
904 return -ENXIO;
905
906 info = &isp[line];
907
908 switch (cmd)
909 {
910 case IFX_SSC_STATS_READ:
911 /* data must be a pointer to a struct ifx_ssc_statistics */
912 if (from_kernel)
913 memcpy ((void *) data, (void *) &info->stats,
914 sizeof (struct ifx_ssc_statistics));
915 else if (copy_to_user ((void *) data,
916 (void *) &info->stats,
917 sizeof (struct ifx_ssc_statistics)))
918 ret_val = -EFAULT;
919 break;
920 case IFX_SSC_STATS_RESET:
921 /* just resets the statistics counters */
922 memset ((void *) &info->stats, 0,
923 sizeof (struct ifx_ssc_statistics));
924 break;
925 case IFX_SSC_BAUD_SET:
926 /* if the buffers are not empty then the port is */
927 /* busy and we shouldn't change things on-the-fly! */
928 if (!info->txbuf || !info->rxbuf ||
929 (readl(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
930 ret_val = -EBUSY;
931 break;
932 }
933 /* misuse flags */
934 if (from_kernel)
935 flags = *((unsigned long *) data);
936 else if (copy_from_user ((void *) &flags,
937 (void *) data, sizeof (flags))) {
938 ret_val = -EFAULT;
939 break;
940 }
941 if (flags == 0) {
942 ret_val = -EINVAL;
943 break;
944 }
945 if (ifx_ssc_set_baud (info, flags) < 0) {
946 ret_val = -EINVAL;
947 break;
948 }
949 info->baud = flags;
950 break;
951 case IFX_SSC_BAUD_GET:
952 if (from_kernel)
953 *((unsigned int *) data) = info->baud;
954 else if (copy_to_user ((void *) data,
955 (void *) &info->baud,
956 sizeof (unsigned long)))
957 ret_val = -EFAULT;
958 break;
959 case IFX_SSC_RXTX_MODE_SET:
960 if (from_kernel)
961 tmp = *((unsigned long *) data);
962 else if (copy_from_user ((void *) &tmp,
963 (void *) data, sizeof (tmp))) {
964 ret_val = -EFAULT;
965 break;
966 }
967 ret_val = ifx_ssc_rxtx_mode_set (info, tmp);
968 break;
969 case IFX_SSC_RXTX_MODE_GET:
970 tmp = readl(IFXMIPS_SSC_CON) &
971 (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
972 if (from_kernel)
973 *((unsigned int *) data) = tmp;
974 else if (copy_to_user ((void *) data,
975 (void *) &tmp, sizeof (tmp)))
976 ret_val = -EFAULT;
977 break;
978
979 case IFX_SSC_ABORT:
980 ifx_ssc_abort (info);
981 break;
982
983 case IFX_SSC_GPO_OUT_SET:
984 if (from_kernel)
985 tmp = *((unsigned long *) data);
986 else if (copy_from_user ((void *) &tmp,
987 (void *) data, sizeof (tmp))) {
988 ret_val = -EFAULT;
989 break;
990 }
991 if (tmp > IFX_SSC_MAX_GPO_OUT)
992 ret_val = -EINVAL;
993 else
994 writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
995 IFXMIPS_SSC_WHBGPOSTAT);
996 break;
997 case IFX_SSC_GPO_OUT_CLR:
998 if (from_kernel)
999 tmp = *((unsigned long *) data);
1000 else if (copy_from_user ((void *) &tmp, (void *) data, sizeof (tmp))) {
1001 ret_val = -EFAULT;
1002 break;
1003 }
1004 if (tmp > IFX_SSC_MAX_GPO_OUT)
1005 ret_val = -EINVAL;
1006 else {
1007 writel(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
1008 IFXMIPS_SSC_WHBGPOSTAT);
1009 }
1010 break;
1011 case IFX_SSC_GPO_OUT_GET:
1012 tmp = readl(IFXMIPS_SSC_GPOSTAT);
1013 if (from_kernel)
1014 *((unsigned int *) data) = tmp;
1015 else if (copy_to_user ((void *) data,
1016 (void *) &tmp, sizeof (tmp)))
1017 ret_val = -EFAULT;
1018 break;
1019 case IFX_SSC_FRM_STATUS_GET:
1020 ifx_ssc_frm_status_get (info);
1021 if (from_kernel)
1022 memcpy ((void *) data, (void *) &info->frm_status,
1023 sizeof (struct ifx_ssc_frm_status));
1024 else if (copy_to_user ((void *) data,
1025 (void *) &info->frm_status,
1026 sizeof (struct ifx_ssc_frm_status)))
1027 ret_val = -EFAULT;
1028 break;
1029 case IFX_SSC_FRM_CONTROL_GET:
1030 ifx_ssc_frm_control_get (info);
1031 if (from_kernel)
1032 memcpy ((void *) data, (void *) &info->frm_opts,
1033 sizeof (struct ifx_ssc_frm_opts));
1034 else if (copy_to_user ((void *) data,
1035 (void *) &info->frm_opts,
1036 sizeof (struct ifx_ssc_frm_opts)))
1037 ret_val = -EFAULT;
1038 break;
1039 case IFX_SSC_FRM_CONTROL_SET:
1040 if (from_kernel)
1041 memcpy ((void *) &info->frm_opts, (void *) data,
1042 sizeof (struct ifx_ssc_frm_opts));
1043 else if (copy_to_user ((void *) &info->frm_opts,
1044 (void *) data,
1045 sizeof (struct ifx_ssc_frm_opts))) {
1046 ret_val = -EFAULT;
1047 break;
1048 }
1049 ret_val = ifx_ssc_frm_control_set (info);
1050 break;
1051 case IFX_SSC_HWOPTS_SET:
1052 /* data must be a pointer to a struct ifx_ssc_hwopts */
1053 /* if the buffers are not empty then the port is */
1054 /* busy and we shouldn't change things on-the-fly! */
1055 if (!info->txbuf || !info->rxbuf ||
1056 (readl(IFXMIPS_SSC_STATE)
1057 & IFX_SSC_STATE_BUSY)) {
1058 ret_val = -EBUSY;
1059 break;
1060 }
1061 if (from_kernel)
1062 memcpy ((void *) &info->opts, (void *) data,
1063 sizeof (struct ifx_ssc_hwopts));
1064 else if (copy_from_user ((void *) &info->opts,
1065 (void *) data, sizeof(struct ifx_ssc_hwopts))) {
1066 ret_val = -EFAULT;
1067 break;
1068 }
1069 if (ifx_ssc_hwinit (info) < 0) {
1070 ret_val = -EIO;
1071 }
1072 break;
1073 case IFX_SSC_HWOPTS_GET:
1074 /* data must be a pointer to a struct ifx_ssc_hwopts */
1075 if (from_kernel)
1076 memcpy ((void *) data, (void *) &info->opts,
1077 sizeof (struct ifx_ssc_hwopts));
1078 else if (copy_to_user ((void *) data,
1079 (void *) &info->opts,
1080 sizeof (struct ifx_ssc_hwopts)))
1081 ret_val = -EFAULT;
1082 break;
1083 default:
1084 ret_val = -ENOIOCTLCMD;
1085 }
1086
1087 return ret_val;
1088 }
1089 EXPORT_SYMBOL(ifx_ssc_ioctl);
1090
1091 static struct file_operations ifx_ssc_fops = {
1092 .owner = THIS_MODULE,
1093 .read = ifx_ssc_read,
1094 .write = ifx_ssc_write,
1095 .ioctl = ifx_ssc_ioctl,
1096 .open = ifx_ssc_open,
1097 .release = ifx_ssc_close,
1098 };
1099
1100 int __init
1101 ifx_ssc_init (void)
1102 {
1103 struct ifx_ssc_port *info;
1104 int i, nbytes;
1105 unsigned long flags;
1106 int ret_val;
1107
1108 ret_val = -ENOMEM;
1109 nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
1110 isp = (struct ifx_ssc_port*)kmalloc(nbytes, GFP_KERNEL);
1111
1112 if (isp == NULL)
1113 {
1114 printk("%s: no memory for isp\n", __func__);
1115 return (ret_val);
1116 }
1117 memset(isp, 0, nbytes);
1118
1119 ret_val = -ENXIO;
1120 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1121 {
1122 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1123 if (maj == 0)
1124 {
1125 goto errout;
1126 } else {
1127 maj = 0;
1128 if ((i = register_chrdev (maj, "ssc", &ifx_ssc_fops)) < 0)
1129 {
1130 printk ("Unable to register major %d for the Infineon SSC\n", maj);
1131 goto errout;
1132 }
1133 }
1134 }
1135
1136 if (maj == 0)
1137 maj = i;
1138
1139 /* set default values in ifx_ssc_port */
1140 for (i = 0; i < PORT_CNT; i++) {
1141 info = &isp[i];
1142 info->port_nr = i;
1143 /* default values for the HwOpts */
1144 info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
1145 info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
1146 info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
1147 info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
1148 info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
1149 info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
1150 info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
1151 info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
1152 info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
1153 info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
1154 info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
1155 info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
1156 info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
1157 info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
1158 info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
1159 info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
1160 info->baud = IFX_SSC_DEF_BAUDRATE;
1161 info->rxbuf = NULL;
1162 info->txbuf = NULL;
1163 /* values specific to SSC1 */
1164 if (i == 0) {
1165 info->mapbase = IFXMIPS_SSC_BASE_ADDR;
1166 }
1167
1168 writel(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
1169
1170 init_waitqueue_head (&info->rwait);
1171
1172 local_irq_save (flags);
1173
1174 // init serial framing register
1175 writel(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
1176
1177 ret_val = request_irq(IFXMIPS_SSC_TIR, ifx_ssc_tx_int, IRQF_DISABLED, "ifx_ssc_tx", info);
1178 if (ret_val)
1179 {
1180 printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_TIR);
1181 local_irq_restore(flags);
1182 goto errout;
1183 }
1184
1185 ret_val = request_irq(IFXMIPS_SSC_RIR, ifx_ssc_rx_int, IRQF_DISABLED, "ifx_ssc_rx", info);
1186 if (ret_val)
1187 {
1188 printk ("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_RIR);
1189 local_irq_restore (flags);
1190 goto irqerr;
1191 }
1192
1193 ret_val = request_irq(IFXMIPS_SSC_EIR, ifx_ssc_err_int, IRQF_DISABLED, "ifx_ssc_err", info);
1194 if (ret_val)
1195 {
1196 printk ("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_EIR);
1197 local_irq_restore (flags);
1198 goto irqerr;
1199 }
1200 writel(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
1201
1202 //enable_irq(IFXMIPS_SSC_TIR);
1203 //enable_irq(IFXMIPS_SSC_RIR);
1204 //enable_irq(IFXMIPS_SSC_EIR);
1205
1206 local_irq_restore (flags);
1207 }
1208
1209 for (i = 0; i < PORT_CNT; i++) {
1210 info = &isp[i];
1211 if (ifx_ssc_hwinit (info) < 0)
1212 {
1213 printk ("%s: hardware init failed for port %d\n", __func__, i);
1214 goto irqerr;
1215 }
1216 }
1217
1218
1219 return 0;
1220
1221 irqerr:
1222 free_irq(IFXMIPS_SSC_TIR, &isp[0]);
1223 free_irq(IFXMIPS_SSC_RIR, &isp[0]);
1224 free_irq(IFXMIPS_SSC_EIR, &isp[0]);
1225 errout:
1226 kfree (isp);
1227 return (ret_val);
1228 }
1229
1230 void
1231 ifx_ssc_cleanup_module (void)
1232 {
1233 int i;
1234
1235 for (i = 0; i < PORT_CNT; i++) {
1236 writel(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
1237 free_irq(IFXMIPS_SSC_TIR, &isp[i]);
1238 free_irq(IFXMIPS_SSC_RIR, &isp[i]);
1239 free_irq(IFXMIPS_SSC_EIR, &isp[i]);
1240 }
1241 kfree (isp);
1242 }
1243
1244 module_init(ifx_ssc_init);
1245 module_exit(ifx_ssc_cleanup_module);
1246
1247
1248 inline int
1249 ifx_ssc_cs_low (u32 pin)
1250 {
1251 int ret = 0;
1252 if ((ret = ifx_ssc_ioctl ((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin)))
1253 printk ("clear CS %d fails\n", pin);
1254 wmb ();
1255
1256 return ret;
1257 }
1258 EXPORT_SYMBOL(ifx_ssc_cs_low);
1259
1260 inline int
1261 ifx_ssc_cs_high (u32 pin)
1262 {
1263 int ret = 0;
1264 if ((ret = ifx_ssc_ioctl((struct inode *) 0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin)))
1265 printk ("set CS %d fails\n", pin);
1266 wmb ();
1267
1268 return ret;
1269 }
1270 EXPORT_SYMBOL(ifx_ssc_cs_high);
1271
1272 static int
1273 ssc_session (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1274 {
1275 int ret = 0;
1276
1277 char *ssc_tx_buf = NULL;
1278 char *ssc_rx_buf = NULL;
1279 int eff_size = 0;
1280 u8 mode = 0;
1281
1282 if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
1283 printk ("invalid parameters\n");
1284 ret = -EINVAL;
1285 goto ssc_session_exit;
1286 }
1287 else if (tx_buf == NULL || tx_len == 0) {
1288 if (rx_buf != NULL && rx_len != 0) {
1289 mode = IFX_SSC_MODE_RX;
1290 }
1291 else {
1292 printk ("invalid parameters\n");
1293 ret = -EINVAL;
1294 goto ssc_session_exit;
1295 }
1296 }
1297 else if (rx_buf == NULL || rx_len == 0) {
1298 if (tx_buf != NULL && tx_len != 0) {
1299 mode = IFX_SSC_MODE_TX;
1300 }
1301 else {
1302 printk ("invalid parameters\n");
1303 ret = -EINVAL;
1304 goto ssc_session_exit;
1305 }
1306 }
1307 else {
1308 mode = IFX_SSC_MODE_RXTX;
1309 }
1310
1311 if (mode == IFX_SSC_MODE_RXTX) {
1312 eff_size = tx_len + rx_len;
1313 }
1314 else if (mode == IFX_SSC_MODE_RX) {
1315 eff_size = rx_len;
1316 }
1317 else {
1318 eff_size = tx_len;
1319 }
1320
1321 //4 bytes alignment, required by driver
1322 /* change by TaiCheng */
1323 //if (in_irq()){
1324 if (1) {
1325 ssc_tx_buf =
1326 (char *) kmalloc (sizeof (char) *
1327 ((eff_size + 3) & (~3)),
1328 GFP_ATOMIC);
1329 ssc_rx_buf =
1330 (char *) kmalloc (sizeof (char) *
1331 ((eff_size + 3) & (~3)),
1332 GFP_ATOMIC);
1333 }
1334 else {
1335 ssc_tx_buf =
1336 (char *) kmalloc (sizeof (char) *
1337 ((eff_size + 3) & (~3)),
1338 GFP_KERNEL);
1339 ssc_rx_buf =
1340 (char *) kmalloc (sizeof (char) *
1341 ((eff_size + 3) & (~3)),
1342 GFP_KERNEL);
1343 }
1344 if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
1345 printk ("no memory for size of %d\n", eff_size);
1346 ret = -ENOMEM;
1347 goto ssc_session_exit;
1348 }
1349 memset ((void *) ssc_tx_buf, 0, eff_size);
1350 memset ((void *) ssc_rx_buf, 0, eff_size);
1351
1352 if (tx_len > 0) {
1353 memcpy (ssc_tx_buf, tx_buf, tx_len);
1354 }
1355
1356 ret = ifx_ssc_kwrite (0, ssc_tx_buf, eff_size);
1357
1358 if (ret > 0) {
1359 ssc_tx_buf = NULL; //should be freed by ifx_ssc_kwrite
1360 }
1361
1362 if (ret != eff_size) {
1363 printk ("ifx_ssc_write return %d\n", ret);
1364 goto ssc_session_exit;
1365 }
1366 ret = ifx_ssc_kread (0, ssc_rx_buf, eff_size);
1367 if (ret != eff_size) {
1368 printk ("ifx_ssc_read return %d\n", ret);
1369 goto ssc_session_exit;
1370 }
1371
1372 memcpy (rx_buf, ssc_rx_buf + tx_len, rx_len);
1373
1374 if (mode == IFX_SSC_MODE_TX) {
1375 ret = tx_len;
1376 }
1377 else {
1378 ret = rx_len;
1379 }
1380 ssc_session_exit:
1381
1382 if (ssc_tx_buf != NULL)
1383 kfree (ssc_tx_buf);
1384 if (ssc_rx_buf != NULL)
1385 kfree (ssc_rx_buf);
1386
1387 if (ret < 0) {
1388 printk ("ssc session fails\n");
1389 }
1390 return ret;
1391 }
1392
1393 int
1394 ifx_ssc_txrx (char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1395 {
1396 return ssc_session(tx_buf, tx_len, rx_buf, rx_len);
1397 }
1398 EXPORT_SYMBOL(ifx_ssc_txrx);
1399
1400 int
1401 ifx_ssc_tx (char *tx_buf, u32 tx_len)
1402 {
1403 return ssc_session(tx_buf, tx_len, NULL, 0);
1404 }
1405 EXPORT_SYMBOL(ifx_ssc_tx);
1406
1407 int
1408 ifx_ssc_rx (char *rx_buf, u32 rx_len)
1409 {
1410 return ssc_session(NULL, 0, rx_buf, rx_len);
1411 }
1412 EXPORT_SYMBOL(ifx_ssc_rx);
1413
1414 MODULE_LICENSE("GPL");
1415 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1416 MODULE_DESCRIPTION("ifxmips ssc driver");
1417
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