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Add support for WRT600N and WRT600N v1.1 (#3535)
[openwrt.git] / package / b43 / src / dma.c
1 /*
2
3 Broadcom B43 wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41 #include <asm/div64.h>
42
43
44 /* 32bit DMA ops. */
45 static
46 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
47 int slot,
48 struct b43_dmadesc_meta **meta)
49 {
50 struct b43_dmadesc32 *desc;
51
52 *meta = &(ring->meta[slot]);
53 desc = ring->descbase;
54 desc = &(desc[slot]);
55
56 return (struct b43_dmadesc_generic *)desc;
57 }
58
59 static void op32_fill_descriptor(struct b43_dmaring *ring,
60 struct b43_dmadesc_generic *desc,
61 dma_addr_t dmaaddr, u16 bufsize,
62 int start, int end, int irq)
63 {
64 struct b43_dmadesc32 *descbase = ring->descbase;
65 int slot;
66 u32 ctl;
67 u32 addr;
68 u32 addrext;
69
70 slot = (int)(&(desc->dma32) - descbase);
71 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
72
73 addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
74 addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
75 >> SSB_DMA_TRANSLATION_SHIFT;
76 addr |= ssb_dma_translation(ring->dev->dev);
77 ctl = (bufsize - ring->frameoffset)
78 & B43_DMA32_DCTL_BYTECNT;
79 if (slot == ring->nr_slots - 1)
80 ctl |= B43_DMA32_DCTL_DTABLEEND;
81 if (start)
82 ctl |= B43_DMA32_DCTL_FRAMESTART;
83 if (end)
84 ctl |= B43_DMA32_DCTL_FRAMEEND;
85 if (irq)
86 ctl |= B43_DMA32_DCTL_IRQ;
87 ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
88 & B43_DMA32_DCTL_ADDREXT_MASK;
89
90 desc->dma32.control = cpu_to_le32(ctl);
91 desc->dma32.address = cpu_to_le32(addr);
92 }
93
94 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
95 {
96 b43_dma_write(ring, B43_DMA32_TXINDEX,
97 (u32) (slot * sizeof(struct b43_dmadesc32)));
98 }
99
100 static void op32_tx_suspend(struct b43_dmaring *ring)
101 {
102 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
103 | B43_DMA32_TXSUSPEND);
104 }
105
106 static void op32_tx_resume(struct b43_dmaring *ring)
107 {
108 b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
109 & ~B43_DMA32_TXSUSPEND);
110 }
111
112 static int op32_get_current_rxslot(struct b43_dmaring *ring)
113 {
114 u32 val;
115
116 val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
117 val &= B43_DMA32_RXDPTR;
118
119 return (val / sizeof(struct b43_dmadesc32));
120 }
121
122 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
123 {
124 b43_dma_write(ring, B43_DMA32_RXINDEX,
125 (u32) (slot * sizeof(struct b43_dmadesc32)));
126 }
127
128 static const struct b43_dma_ops dma32_ops = {
129 .idx2desc = op32_idx2desc,
130 .fill_descriptor = op32_fill_descriptor,
131 .poke_tx = op32_poke_tx,
132 .tx_suspend = op32_tx_suspend,
133 .tx_resume = op32_tx_resume,
134 .get_current_rxslot = op32_get_current_rxslot,
135 .set_current_rxslot = op32_set_current_rxslot,
136 };
137
138 /* 64bit DMA ops. */
139 static
140 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
141 int slot,
142 struct b43_dmadesc_meta **meta)
143 {
144 struct b43_dmadesc64 *desc;
145
146 *meta = &(ring->meta[slot]);
147 desc = ring->descbase;
148 desc = &(desc[slot]);
149
150 return (struct b43_dmadesc_generic *)desc;
151 }
152
153 static void op64_fill_descriptor(struct b43_dmaring *ring,
154 struct b43_dmadesc_generic *desc,
155 dma_addr_t dmaaddr, u16 bufsize,
156 int start, int end, int irq)
157 {
158 struct b43_dmadesc64 *descbase = ring->descbase;
159 int slot;
160 u32 ctl0 = 0, ctl1 = 0;
161 u32 addrlo, addrhi;
162 u32 addrext;
163
164 slot = (int)(&(desc->dma64) - descbase);
165 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
166
167 addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
168 addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
169 addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
170 >> SSB_DMA_TRANSLATION_SHIFT;
171 addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
172 if (slot == ring->nr_slots - 1)
173 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
174 if (start)
175 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
176 if (end)
177 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
178 if (irq)
179 ctl0 |= B43_DMA64_DCTL0_IRQ;
180 ctl1 |= (bufsize - ring->frameoffset)
181 & B43_DMA64_DCTL1_BYTECNT;
182 ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
183 & B43_DMA64_DCTL1_ADDREXT_MASK;
184
185 desc->dma64.control0 = cpu_to_le32(ctl0);
186 desc->dma64.control1 = cpu_to_le32(ctl1);
187 desc->dma64.address_low = cpu_to_le32(addrlo);
188 desc->dma64.address_high = cpu_to_le32(addrhi);
189 }
190
191 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
192 {
193 b43_dma_write(ring, B43_DMA64_TXINDEX,
194 (u32) (slot * sizeof(struct b43_dmadesc64)));
195 }
196
197 static void op64_tx_suspend(struct b43_dmaring *ring)
198 {
199 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
200 | B43_DMA64_TXSUSPEND);
201 }
202
203 static void op64_tx_resume(struct b43_dmaring *ring)
204 {
205 b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
206 & ~B43_DMA64_TXSUSPEND);
207 }
208
209 static int op64_get_current_rxslot(struct b43_dmaring *ring)
210 {
211 u32 val;
212
213 val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
214 val &= B43_DMA64_RXSTATDPTR;
215
216 return (val / sizeof(struct b43_dmadesc64));
217 }
218
219 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
220 {
221 b43_dma_write(ring, B43_DMA64_RXINDEX,
222 (u32) (slot * sizeof(struct b43_dmadesc64)));
223 }
224
225 static const struct b43_dma_ops dma64_ops = {
226 .idx2desc = op64_idx2desc,
227 .fill_descriptor = op64_fill_descriptor,
228 .poke_tx = op64_poke_tx,
229 .tx_suspend = op64_tx_suspend,
230 .tx_resume = op64_tx_resume,
231 .get_current_rxslot = op64_get_current_rxslot,
232 .set_current_rxslot = op64_set_current_rxslot,
233 };
234
235 static inline int free_slots(struct b43_dmaring *ring)
236 {
237 return (ring->nr_slots - ring->used_slots);
238 }
239
240 static inline int next_slot(struct b43_dmaring *ring, int slot)
241 {
242 B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
243 if (slot == ring->nr_slots - 1)
244 return 0;
245 return slot + 1;
246 }
247
248 static inline int prev_slot(struct b43_dmaring *ring, int slot)
249 {
250 B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
251 if (slot == 0)
252 return ring->nr_slots - 1;
253 return slot - 1;
254 }
255
256 #ifdef CONFIG_B43_DEBUG
257 static void update_max_used_slots(struct b43_dmaring *ring,
258 int current_used_slots)
259 {
260 if (current_used_slots <= ring->max_used_slots)
261 return;
262 ring->max_used_slots = current_used_slots;
263 if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
264 b43dbg(ring->dev->wl,
265 "max_used_slots increased to %d on %s ring %d\n",
266 ring->max_used_slots,
267 ring->tx ? "TX" : "RX", ring->index);
268 }
269 }
270 #else
271 static inline
272 void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
273 {
274 }
275 #endif /* DEBUG */
276
277 /* Request a slot for usage. */
278 static inline int request_slot(struct b43_dmaring *ring)
279 {
280 int slot;
281
282 B43_WARN_ON(!ring->tx);
283 B43_WARN_ON(ring->stopped);
284 B43_WARN_ON(free_slots(ring) == 0);
285
286 slot = next_slot(ring, ring->current_slot);
287 ring->current_slot = slot;
288 ring->used_slots++;
289
290 update_max_used_slots(ring, ring->used_slots);
291
292 return slot;
293 }
294
295 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
296 {
297 static const u16 map64[] = {
298 B43_MMIO_DMA64_BASE0,
299 B43_MMIO_DMA64_BASE1,
300 B43_MMIO_DMA64_BASE2,
301 B43_MMIO_DMA64_BASE3,
302 B43_MMIO_DMA64_BASE4,
303 B43_MMIO_DMA64_BASE5,
304 };
305 static const u16 map32[] = {
306 B43_MMIO_DMA32_BASE0,
307 B43_MMIO_DMA32_BASE1,
308 B43_MMIO_DMA32_BASE2,
309 B43_MMIO_DMA32_BASE3,
310 B43_MMIO_DMA32_BASE4,
311 B43_MMIO_DMA32_BASE5,
312 };
313
314 if (type == B43_DMA_64BIT) {
315 B43_WARN_ON(!(controller_idx >= 0 &&
316 controller_idx < ARRAY_SIZE(map64)));
317 return map64[controller_idx];
318 }
319 B43_WARN_ON(!(controller_idx >= 0 &&
320 controller_idx < ARRAY_SIZE(map32)));
321 return map32[controller_idx];
322 }
323
324 static inline
325 dma_addr_t map_descbuffer(struct b43_dmaring *ring,
326 unsigned char *buf, size_t len, int tx)
327 {
328 dma_addr_t dmaaddr;
329
330 if (tx) {
331 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
332 buf, len, DMA_TO_DEVICE);
333 } else {
334 dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
335 buf, len, DMA_FROM_DEVICE);
336 }
337
338 return dmaaddr;
339 }
340
341 static inline
342 void unmap_descbuffer(struct b43_dmaring *ring,
343 dma_addr_t addr, size_t len, int tx)
344 {
345 if (tx) {
346 dma_unmap_single(ring->dev->dev->dma_dev,
347 addr, len, DMA_TO_DEVICE);
348 } else {
349 dma_unmap_single(ring->dev->dev->dma_dev,
350 addr, len, DMA_FROM_DEVICE);
351 }
352 }
353
354 static inline
355 void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
356 dma_addr_t addr, size_t len)
357 {
358 B43_WARN_ON(ring->tx);
359 dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
360 addr, len, DMA_FROM_DEVICE);
361 }
362
363 static inline
364 void sync_descbuffer_for_device(struct b43_dmaring *ring,
365 dma_addr_t addr, size_t len)
366 {
367 B43_WARN_ON(ring->tx);
368 dma_sync_single_for_device(ring->dev->dev->dma_dev,
369 addr, len, DMA_FROM_DEVICE);
370 }
371
372 static inline
373 void free_descriptor_buffer(struct b43_dmaring *ring,
374 struct b43_dmadesc_meta *meta)
375 {
376 if (meta->skb) {
377 dev_kfree_skb_any(meta->skb);
378 meta->skb = NULL;
379 }
380 }
381
382 static int alloc_ringmemory(struct b43_dmaring *ring)
383 {
384 struct device *dma_dev = ring->dev->dev->dma_dev;
385 gfp_t flags = GFP_KERNEL;
386
387 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
388 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
389 * has shown that 4K is sufficient for the latter as long as the buffer
390 * does not cross an 8K boundary.
391 *
392 * For unknown reasons - possibly a hardware error - the BCM4311 rev
393 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
394 * which accounts for the GFP_DMA flag below.
395 */
396 if (ring->type == B43_DMA_64BIT)
397 flags |= GFP_DMA;
398 ring->descbase = dma_alloc_coherent(dma_dev, B43_DMA_RINGMEMSIZE,
399 &(ring->dmabase), flags);
400 if (!ring->descbase) {
401 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
402 return -ENOMEM;
403 }
404 memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
405
406 return 0;
407 }
408
409 static void free_ringmemory(struct b43_dmaring *ring)
410 {
411 struct device *dma_dev = ring->dev->dev->dma_dev;
412
413 dma_free_coherent(dma_dev, B43_DMA_RINGMEMSIZE,
414 ring->descbase, ring->dmabase);
415 }
416
417 /* Reset the RX DMA channel */
418 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
419 enum b43_dmatype type)
420 {
421 int i;
422 u32 value;
423 u16 offset;
424
425 might_sleep();
426
427 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
428 b43_write32(dev, mmio_base + offset, 0);
429 for (i = 0; i < 10; i++) {
430 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
431 B43_DMA32_RXSTATUS;
432 value = b43_read32(dev, mmio_base + offset);
433 if (type == B43_DMA_64BIT) {
434 value &= B43_DMA64_RXSTAT;
435 if (value == B43_DMA64_RXSTAT_DISABLED) {
436 i = -1;
437 break;
438 }
439 } else {
440 value &= B43_DMA32_RXSTATE;
441 if (value == B43_DMA32_RXSTAT_DISABLED) {
442 i = -1;
443 break;
444 }
445 }
446 msleep(1);
447 }
448 if (i != -1) {
449 b43err(dev->wl, "DMA RX reset timed out\n");
450 return -ENODEV;
451 }
452
453 return 0;
454 }
455
456 /* Reset the TX DMA channel */
457 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
458 enum b43_dmatype type)
459 {
460 int i;
461 u32 value;
462 u16 offset;
463
464 might_sleep();
465
466 for (i = 0; i < 10; i++) {
467 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
468 B43_DMA32_TXSTATUS;
469 value = b43_read32(dev, mmio_base + offset);
470 if (type == B43_DMA_64BIT) {
471 value &= B43_DMA64_TXSTAT;
472 if (value == B43_DMA64_TXSTAT_DISABLED ||
473 value == B43_DMA64_TXSTAT_IDLEWAIT ||
474 value == B43_DMA64_TXSTAT_STOPPED)
475 break;
476 } else {
477 value &= B43_DMA32_TXSTATE;
478 if (value == B43_DMA32_TXSTAT_DISABLED ||
479 value == B43_DMA32_TXSTAT_IDLEWAIT ||
480 value == B43_DMA32_TXSTAT_STOPPED)
481 break;
482 }
483 msleep(1);
484 }
485 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
486 b43_write32(dev, mmio_base + offset, 0);
487 for (i = 0; i < 10; i++) {
488 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
489 B43_DMA32_TXSTATUS;
490 value = b43_read32(dev, mmio_base + offset);
491 if (type == B43_DMA_64BIT) {
492 value &= B43_DMA64_TXSTAT;
493 if (value == B43_DMA64_TXSTAT_DISABLED) {
494 i = -1;
495 break;
496 }
497 } else {
498 value &= B43_DMA32_TXSTATE;
499 if (value == B43_DMA32_TXSTAT_DISABLED) {
500 i = -1;
501 break;
502 }
503 }
504 msleep(1);
505 }
506 if (i != -1) {
507 b43err(dev->wl, "DMA TX reset timed out\n");
508 return -ENODEV;
509 }
510 /* ensure the reset is completed. */
511 msleep(1);
512
513 return 0;
514 }
515
516 /* Check if a DMA mapping address is invalid. */
517 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
518 dma_addr_t addr,
519 size_t buffersize, bool dma_to_device)
520 {
521 if (unlikely(dma_mapping_error(addr)))
522 return 1;
523
524 switch (ring->type) {
525 case B43_DMA_30BIT:
526 if ((u64)addr + buffersize > (1ULL << 30))
527 goto address_error;
528 break;
529 case B43_DMA_32BIT:
530 if ((u64)addr + buffersize > (1ULL << 32))
531 goto address_error;
532 break;
533 case B43_DMA_64BIT:
534 /* Currently we can't have addresses beyond
535 * 64bit in the kernel. */
536 break;
537 }
538
539 /* The address is OK. */
540 return 0;
541
542 address_error:
543 /* We can't support this address. Unmap it again. */
544 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
545
546 return 1;
547 }
548
549 static int setup_rx_descbuffer(struct b43_dmaring *ring,
550 struct b43_dmadesc_generic *desc,
551 struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
552 {
553 struct b43_rxhdr_fw4 *rxhdr;
554 dma_addr_t dmaaddr;
555 struct sk_buff *skb;
556
557 B43_WARN_ON(ring->tx);
558
559 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
560 if (unlikely(!skb))
561 return -ENOMEM;
562 dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
563 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
564 /* ugh. try to realloc in zone_dma */
565 gfp_flags |= GFP_DMA;
566
567 dev_kfree_skb_any(skb);
568
569 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
570 if (unlikely(!skb))
571 return -ENOMEM;
572 dmaaddr = map_descbuffer(ring, skb->data,
573 ring->rx_buffersize, 0);
574 }
575
576 if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
577 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
578 dev_kfree_skb_any(skb);
579 return -EIO;
580 }
581
582 meta->skb = skb;
583 meta->dmaaddr = dmaaddr;
584 ring->ops->fill_descriptor(ring, desc, dmaaddr,
585 ring->rx_buffersize, 0, 0, 0);
586
587 rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
588 rxhdr->frame_len = 0;
589
590 return 0;
591 }
592
593 /* Allocate the initial descbuffers.
594 * This is used for an RX ring only.
595 */
596 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
597 {
598 int i, err = -ENOMEM;
599 struct b43_dmadesc_generic *desc;
600 struct b43_dmadesc_meta *meta;
601
602 for (i = 0; i < ring->nr_slots; i++) {
603 desc = ring->ops->idx2desc(ring, i, &meta);
604
605 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
606 if (err) {
607 b43err(ring->dev->wl,
608 "Failed to allocate initial descbuffers\n");
609 goto err_unwind;
610 }
611 }
612 mb();
613 ring->used_slots = ring->nr_slots;
614 err = 0;
615 out:
616 return err;
617
618 err_unwind:
619 for (i--; i >= 0; i--) {
620 desc = ring->ops->idx2desc(ring, i, &meta);
621
622 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
623 dev_kfree_skb(meta->skb);
624 }
625 goto out;
626 }
627
628 /* Do initial setup of the DMA controller.
629 * Reset the controller, write the ring busaddress
630 * and switch the "enable" bit on.
631 */
632 static int dmacontroller_setup(struct b43_dmaring *ring)
633 {
634 int err = 0;
635 u32 value;
636 u32 addrext;
637 u32 trans = ssb_dma_translation(ring->dev->dev);
638
639 if (ring->tx) {
640 if (ring->type == B43_DMA_64BIT) {
641 u64 ringbase = (u64) (ring->dmabase);
642
643 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
644 >> SSB_DMA_TRANSLATION_SHIFT;
645 value = B43_DMA64_TXENABLE;
646 value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
647 & B43_DMA64_TXADDREXT_MASK;
648 b43_dma_write(ring, B43_DMA64_TXCTL, value);
649 b43_dma_write(ring, B43_DMA64_TXRINGLO,
650 (ringbase & 0xFFFFFFFF));
651 b43_dma_write(ring, B43_DMA64_TXRINGHI,
652 ((ringbase >> 32) &
653 ~SSB_DMA_TRANSLATION_MASK)
654 | (trans << 1));
655 } else {
656 u32 ringbase = (u32) (ring->dmabase);
657
658 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
659 >> SSB_DMA_TRANSLATION_SHIFT;
660 value = B43_DMA32_TXENABLE;
661 value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
662 & B43_DMA32_TXADDREXT_MASK;
663 b43_dma_write(ring, B43_DMA32_TXCTL, value);
664 b43_dma_write(ring, B43_DMA32_TXRING,
665 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
666 | trans);
667 }
668 } else {
669 err = alloc_initial_descbuffers(ring);
670 if (err)
671 goto out;
672 if (ring->type == B43_DMA_64BIT) {
673 u64 ringbase = (u64) (ring->dmabase);
674
675 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
676 >> SSB_DMA_TRANSLATION_SHIFT;
677 value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
678 value |= B43_DMA64_RXENABLE;
679 value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
680 & B43_DMA64_RXADDREXT_MASK;
681 b43_dma_write(ring, B43_DMA64_RXCTL, value);
682 b43_dma_write(ring, B43_DMA64_RXRINGLO,
683 (ringbase & 0xFFFFFFFF));
684 b43_dma_write(ring, B43_DMA64_RXRINGHI,
685 ((ringbase >> 32) &
686 ~SSB_DMA_TRANSLATION_MASK)
687 | (trans << 1));
688 b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
689 sizeof(struct b43_dmadesc64));
690 } else {
691 u32 ringbase = (u32) (ring->dmabase);
692
693 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
694 >> SSB_DMA_TRANSLATION_SHIFT;
695 value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
696 value |= B43_DMA32_RXENABLE;
697 value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
698 & B43_DMA32_RXADDREXT_MASK;
699 b43_dma_write(ring, B43_DMA32_RXCTL, value);
700 b43_dma_write(ring, B43_DMA32_RXRING,
701 (ringbase & ~SSB_DMA_TRANSLATION_MASK)
702 | trans);
703 b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
704 sizeof(struct b43_dmadesc32));
705 }
706 }
707
708 out:
709 return err;
710 }
711
712 /* Shutdown the DMA controller. */
713 static void dmacontroller_cleanup(struct b43_dmaring *ring)
714 {
715 if (ring->tx) {
716 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
717 ring->type);
718 if (ring->type == B43_DMA_64BIT) {
719 b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
720 b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
721 } else
722 b43_dma_write(ring, B43_DMA32_TXRING, 0);
723 } else {
724 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
725 ring->type);
726 if (ring->type == B43_DMA_64BIT) {
727 b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
728 b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
729 } else
730 b43_dma_write(ring, B43_DMA32_RXRING, 0);
731 }
732 }
733
734 static void free_all_descbuffers(struct b43_dmaring *ring)
735 {
736 struct b43_dmadesc_generic *desc;
737 struct b43_dmadesc_meta *meta;
738 int i;
739
740 if (!ring->used_slots)
741 return;
742 for (i = 0; i < ring->nr_slots; i++) {
743 desc = ring->ops->idx2desc(ring, i, &meta);
744
745 if (!meta->skb) {
746 B43_WARN_ON(!ring->tx);
747 continue;
748 }
749 if (ring->tx) {
750 unmap_descbuffer(ring, meta->dmaaddr,
751 meta->skb->len, 1);
752 } else {
753 unmap_descbuffer(ring, meta->dmaaddr,
754 ring->rx_buffersize, 0);
755 }
756 free_descriptor_buffer(ring, meta);
757 }
758 }
759
760 static u64 supported_dma_mask(struct b43_wldev *dev)
761 {
762 u32 tmp;
763 u16 mmio_base;
764
765 tmp = b43_read32(dev, SSB_TMSHIGH);
766 if (tmp & SSB_TMSHIGH_DMA64)
767 return DMA_64BIT_MASK;
768 mmio_base = b43_dmacontroller_base(0, 0);
769 b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
770 tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
771 if (tmp & B43_DMA32_TXADDREXT_MASK)
772 return DMA_32BIT_MASK;
773
774 return DMA_30BIT_MASK;
775 }
776
777 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
778 {
779 if (dmamask == DMA_30BIT_MASK)
780 return B43_DMA_30BIT;
781 if (dmamask == DMA_32BIT_MASK)
782 return B43_DMA_32BIT;
783 if (dmamask == DMA_64BIT_MASK)
784 return B43_DMA_64BIT;
785 B43_WARN_ON(1);
786 return B43_DMA_30BIT;
787 }
788
789 /* Main initialization function. */
790 static
791 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
792 int controller_index,
793 int for_tx,
794 enum b43_dmatype type)
795 {
796 struct b43_dmaring *ring;
797 int err;
798 int nr_slots;
799 dma_addr_t dma_test;
800
801 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
802 if (!ring)
803 goto out;
804 ring->type = type;
805
806 nr_slots = B43_RXRING_SLOTS;
807 if (for_tx)
808 nr_slots = B43_TXRING_SLOTS;
809
810 ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta),
811 GFP_KERNEL);
812 if (!ring->meta)
813 goto err_kfree_ring;
814 if (for_tx) {
815 ring->txhdr_cache = kcalloc(nr_slots,
816 b43_txhdr_size(dev),
817 GFP_KERNEL);
818 if (!ring->txhdr_cache)
819 goto err_kfree_meta;
820
821 /* test for ability to dma to txhdr_cache */
822 dma_test = dma_map_single(dev->dev->dma_dev,
823 ring->txhdr_cache,
824 b43_txhdr_size(dev),
825 DMA_TO_DEVICE);
826
827 if (b43_dma_mapping_error(ring, dma_test,
828 b43_txhdr_size(dev), 1)) {
829 /* ugh realloc */
830 kfree(ring->txhdr_cache);
831 ring->txhdr_cache = kcalloc(nr_slots,
832 b43_txhdr_size(dev),
833 GFP_KERNEL | GFP_DMA);
834 if (!ring->txhdr_cache)
835 goto err_kfree_meta;
836
837 dma_test = dma_map_single(dev->dev->dma_dev,
838 ring->txhdr_cache,
839 b43_txhdr_size(dev),
840 DMA_TO_DEVICE);
841
842 if (b43_dma_mapping_error(ring, dma_test,
843 b43_txhdr_size(dev), 1)) {
844
845 b43err(dev->wl,
846 "TXHDR DMA allocation failed\n");
847 goto err_kfree_txhdr_cache;
848 }
849 }
850
851 dma_unmap_single(dev->dev->dma_dev,
852 dma_test, b43_txhdr_size(dev),
853 DMA_TO_DEVICE);
854 }
855
856 ring->dev = dev;
857 ring->nr_slots = nr_slots;
858 ring->mmio_base = b43_dmacontroller_base(type, controller_index);
859 ring->index = controller_index;
860 if (type == B43_DMA_64BIT)
861 ring->ops = &dma64_ops;
862 else
863 ring->ops = &dma32_ops;
864 if (for_tx) {
865 ring->tx = 1;
866 ring->current_slot = -1;
867 } else {
868 if (ring->index == 0) {
869 ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
870 ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
871 } else if (ring->index == 3) {
872 ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
873 ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
874 } else
875 B43_WARN_ON(1);
876 }
877 spin_lock_init(&ring->lock);
878 #ifdef CONFIG_B43_DEBUG
879 ring->last_injected_overflow = jiffies;
880 #endif
881
882 err = alloc_ringmemory(ring);
883 if (err)
884 goto err_kfree_txhdr_cache;
885 err = dmacontroller_setup(ring);
886 if (err)
887 goto err_free_ringmemory;
888
889 out:
890 return ring;
891
892 err_free_ringmemory:
893 free_ringmemory(ring);
894 err_kfree_txhdr_cache:
895 kfree(ring->txhdr_cache);
896 err_kfree_meta:
897 kfree(ring->meta);
898 err_kfree_ring:
899 kfree(ring);
900 ring = NULL;
901 goto out;
902 }
903
904 #define divide(a, b) ({ \
905 typeof(a) __a = a; \
906 do_div(__a, b); \
907 __a; \
908 })
909
910 #define modulo(a, b) ({ \
911 typeof(a) __a = a; \
912 do_div(__a, b); \
913 })
914
915 /* Main cleanup function. */
916 static void b43_destroy_dmaring(struct b43_dmaring *ring,
917 const char *ringname)
918 {
919 if (!ring)
920 return;
921
922 #ifdef CONFIG_B43_DEBUG
923 {
924 /* Print some statistics. */
925 u64 failed_packets = ring->nr_failed_tx_packets;
926 u64 succeed_packets = ring->nr_succeed_tx_packets;
927 u64 nr_packets = failed_packets + succeed_packets;
928 u64 permille_failed = 0, average_tries = 0;
929
930 if (nr_packets)
931 permille_failed = divide(failed_packets * 1000, nr_packets);
932 if (nr_packets)
933 average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
934
935 b43dbg(ring->dev->wl, "DMA-%u %s: "
936 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
937 "Average tries %llu.%02llu\n",
938 (unsigned int)(ring->type), ringname,
939 ring->max_used_slots,
940 ring->nr_slots,
941 (unsigned long long)failed_packets,
942 (unsigned long long)nr_packets,
943 (unsigned long long)divide(permille_failed, 10),
944 (unsigned long long)modulo(permille_failed, 10),
945 (unsigned long long)divide(average_tries, 100),
946 (unsigned long long)modulo(average_tries, 100));
947 }
948 #endif /* DEBUG */
949
950 /* Device IRQs are disabled prior entering this function,
951 * so no need to take care of concurrency with rx handler stuff.
952 */
953 dmacontroller_cleanup(ring);
954 free_all_descbuffers(ring);
955 free_ringmemory(ring);
956
957 kfree(ring->txhdr_cache);
958 kfree(ring->meta);
959 kfree(ring);
960 }
961
962 #define destroy_ring(dma, ring) do { \
963 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
964 (dma)->ring = NULL; \
965 } while (0)
966
967 void b43_dma_free(struct b43_wldev *dev)
968 {
969 struct b43_dma *dma;
970
971 if (b43_using_pio_transfers(dev))
972 return;
973 dma = &dev->dma;
974
975 destroy_ring(dma, rx_ring);
976 destroy_ring(dma, tx_ring_AC_BK);
977 destroy_ring(dma, tx_ring_AC_BE);
978 destroy_ring(dma, tx_ring_AC_VI);
979 destroy_ring(dma, tx_ring_AC_VO);
980 destroy_ring(dma, tx_ring_mcast);
981 }
982
983 static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask)
984 {
985 u64 orig_mask = mask;
986 bool fallback = 0;
987 int err;
988
989 /* Try to set the DMA mask. If it fails, try falling back to a
990 * lower mask, as we can always also support a lower one. */
991 while (1) {
992 err = ssb_dma_set_mask(dev->dev, mask);
993 if (!err)
994 break;
995 if (mask == DMA_64BIT_MASK) {
996 mask = DMA_32BIT_MASK;
997 fallback = 1;
998 continue;
999 }
1000 if (mask == DMA_32BIT_MASK) {
1001 mask = DMA_30BIT_MASK;
1002 fallback = 1;
1003 continue;
1004 }
1005 b43err(dev->wl, "The machine/kernel does not support "
1006 "the required %u-bit DMA mask\n",
1007 (unsigned int)dma_mask_to_engine_type(orig_mask));
1008 return -EOPNOTSUPP;
1009 }
1010 if (fallback) {
1011 b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n",
1012 (unsigned int)dma_mask_to_engine_type(orig_mask),
1013 (unsigned int)dma_mask_to_engine_type(mask));
1014 }
1015
1016 return 0;
1017 }
1018
1019 int b43_dma_init(struct b43_wldev *dev)
1020 {
1021 struct b43_dma *dma = &dev->dma;
1022 int err;
1023 u64 dmamask;
1024 enum b43_dmatype type;
1025
1026 dmamask = supported_dma_mask(dev);
1027 type = dma_mask_to_engine_type(dmamask);
1028 err = b43_dma_set_mask(dev, dmamask);
1029 if (err)
1030 return err;
1031
1032 err = -ENOMEM;
1033 /* setup TX DMA channels. */
1034 dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1035 if (!dma->tx_ring_AC_BK)
1036 goto out;
1037
1038 dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1039 if (!dma->tx_ring_AC_BE)
1040 goto err_destroy_bk;
1041
1042 dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1043 if (!dma->tx_ring_AC_VI)
1044 goto err_destroy_be;
1045
1046 dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1047 if (!dma->tx_ring_AC_VO)
1048 goto err_destroy_vi;
1049
1050 dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1051 if (!dma->tx_ring_mcast)
1052 goto err_destroy_vo;
1053
1054 /* setup RX DMA channel. */
1055 dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1056 if (!dma->rx_ring)
1057 goto err_destroy_mcast;
1058
1059 /* No support for the TX status DMA ring. */
1060 B43_WARN_ON(dev->dev->id.revision < 5);
1061
1062 b43dbg(dev->wl, "%u-bit DMA initialized\n",
1063 (unsigned int)type);
1064 err = 0;
1065 out:
1066 return err;
1067
1068 err_destroy_mcast:
1069 destroy_ring(dma, tx_ring_mcast);
1070 err_destroy_vo:
1071 destroy_ring(dma, tx_ring_AC_VO);
1072 err_destroy_vi:
1073 destroy_ring(dma, tx_ring_AC_VI);
1074 err_destroy_be:
1075 destroy_ring(dma, tx_ring_AC_BE);
1076 err_destroy_bk:
1077 destroy_ring(dma, tx_ring_AC_BK);
1078 return err;
1079 }
1080
1081 /* Generate a cookie for the TX header. */
1082 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1083 {
1084 u16 cookie;
1085
1086 /* Use the upper 4 bits of the cookie as
1087 * DMA controller ID and store the slot number
1088 * in the lower 12 bits.
1089 * Note that the cookie must never be 0, as this
1090 * is a special value used in RX path.
1091 * It can also not be 0xFFFF because that is special
1092 * for multicast frames.
1093 */
1094 cookie = (((u16)ring->index + 1) << 12);
1095 B43_WARN_ON(slot & ~0x0FFF);
1096 cookie |= (u16)slot;
1097
1098 return cookie;
1099 }
1100
1101 /* Inspect a cookie and find out to which controller/slot it belongs. */
1102 static
1103 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1104 {
1105 struct b43_dma *dma = &dev->dma;
1106 struct b43_dmaring *ring = NULL;
1107
1108 switch (cookie & 0xF000) {
1109 case 0x1000:
1110 ring = dma->tx_ring_AC_BK;
1111 break;
1112 case 0x2000:
1113 ring = dma->tx_ring_AC_BE;
1114 break;
1115 case 0x3000:
1116 ring = dma->tx_ring_AC_VI;
1117 break;
1118 case 0x4000:
1119 ring = dma->tx_ring_AC_VO;
1120 break;
1121 case 0x5000:
1122 ring = dma->tx_ring_mcast;
1123 break;
1124 default:
1125 B43_WARN_ON(1);
1126 }
1127 *slot = (cookie & 0x0FFF);
1128 B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1129
1130 return ring;
1131 }
1132
1133 static int dma_tx_fragment(struct b43_dmaring *ring,
1134 struct sk_buff *skb)
1135 {
1136 const struct b43_dma_ops *ops = ring->ops;
1137 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1138 u8 *header;
1139 int slot, old_top_slot, old_used_slots;
1140 int err;
1141 struct b43_dmadesc_generic *desc;
1142 struct b43_dmadesc_meta *meta;
1143 struct b43_dmadesc_meta *meta_hdr;
1144 struct sk_buff *bounce_skb;
1145 u16 cookie;
1146 size_t hdrsize = b43_txhdr_size(ring->dev);
1147
1148 #define SLOTS_PER_PACKET 2
1149
1150 old_top_slot = ring->current_slot;
1151 old_used_slots = ring->used_slots;
1152
1153 /* Get a slot for the header. */
1154 slot = request_slot(ring);
1155 desc = ops->idx2desc(ring, slot, &meta_hdr);
1156 memset(meta_hdr, 0, sizeof(*meta_hdr));
1157
1158 header = &(ring->txhdr_cache[slot * hdrsize]);
1159 cookie = generate_cookie(ring, slot);
1160 err = b43_generate_txhdr(ring->dev, header,
1161 skb->data, skb->len, info, cookie);
1162 if (unlikely(err)) {
1163 ring->current_slot = old_top_slot;
1164 ring->used_slots = old_used_slots;
1165 return err;
1166 }
1167
1168 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1169 hdrsize, 1);
1170 if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1171 ring->current_slot = old_top_slot;
1172 ring->used_slots = old_used_slots;
1173 return -EIO;
1174 }
1175 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1176 hdrsize, 1, 0, 0);
1177
1178 /* Get a slot for the payload. */
1179 slot = request_slot(ring);
1180 desc = ops->idx2desc(ring, slot, &meta);
1181 memset(meta, 0, sizeof(*meta));
1182
1183 meta->skb = skb;
1184 meta->is_last_fragment = 1;
1185
1186 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1187 /* create a bounce buffer in zone_dma on mapping failure. */
1188 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1189 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1190 if (!bounce_skb) {
1191 ring->current_slot = old_top_slot;
1192 ring->used_slots = old_used_slots;
1193 err = -ENOMEM;
1194 goto out_unmap_hdr;
1195 }
1196
1197 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1198 dev_kfree_skb_any(skb);
1199 skb = bounce_skb;
1200 meta->skb = skb;
1201 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1202 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1203 ring->current_slot = old_top_slot;
1204 ring->used_slots = old_used_slots;
1205 err = -EIO;
1206 goto out_free_bounce;
1207 }
1208 }
1209
1210 ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1211
1212 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1213 /* Tell the firmware about the cookie of the last
1214 * mcast frame, so it can clear the more-data bit in it. */
1215 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1216 B43_SHM_SH_MCASTCOOKIE, cookie);
1217 }
1218 /* Now transfer the whole frame. */
1219 wmb();
1220 ops->poke_tx(ring, next_slot(ring, slot));
1221 return 0;
1222
1223 out_free_bounce:
1224 dev_kfree_skb_any(skb);
1225 out_unmap_hdr:
1226 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1227 hdrsize, 1);
1228 return err;
1229 }
1230
1231 static inline int should_inject_overflow(struct b43_dmaring *ring)
1232 {
1233 #ifdef CONFIG_B43_DEBUG
1234 if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1235 /* Check if we should inject another ringbuffer overflow
1236 * to test handling of this situation in the stack. */
1237 unsigned long next_overflow;
1238
1239 next_overflow = ring->last_injected_overflow + HZ;
1240 if (time_after(jiffies, next_overflow)) {
1241 ring->last_injected_overflow = jiffies;
1242 b43dbg(ring->dev->wl,
1243 "Injecting TX ring overflow on "
1244 "DMA controller %d\n", ring->index);
1245 return 1;
1246 }
1247 }
1248 #endif /* CONFIG_B43_DEBUG */
1249 return 0;
1250 }
1251
1252 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1253 static struct b43_dmaring * select_ring_by_priority(struct b43_wldev *dev,
1254 u8 queue_prio)
1255 {
1256 struct b43_dmaring *ring;
1257
1258 if (b43_modparam_qos) {
1259 /* 0 = highest priority */
1260 switch (queue_prio) {
1261 default:
1262 B43_WARN_ON(1);
1263 /* fallthrough */
1264 case 0:
1265 ring = dev->dma.tx_ring_AC_VO;
1266 break;
1267 case 1:
1268 ring = dev->dma.tx_ring_AC_VI;
1269 break;
1270 case 2:
1271 ring = dev->dma.tx_ring_AC_BE;
1272 break;
1273 case 3:
1274 ring = dev->dma.tx_ring_AC_BK;
1275 break;
1276 }
1277 } else
1278 ring = dev->dma.tx_ring_AC_BE;
1279
1280 return ring;
1281 }
1282
1283 int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb)
1284 {
1285 struct b43_dmaring *ring;
1286 struct ieee80211_hdr *hdr;
1287 int err = 0;
1288 unsigned long flags;
1289 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1290
1291 hdr = (struct ieee80211_hdr *)skb->data;
1292 if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) {
1293 /* The multicast ring will be sent after the DTIM */
1294 ring = dev->dma.tx_ring_mcast;
1295 /* Set the more-data bit. Ucode will clear it on
1296 * the last frame for us. */
1297 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1298 } else {
1299 /* Decide by priority where to put this frame. */
1300 ring = select_ring_by_priority(
1301 dev, skb_get_queue_mapping(skb));
1302 }
1303
1304 spin_lock_irqsave(&ring->lock, flags);
1305 B43_WARN_ON(!ring->tx);
1306 if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1307 b43warn(dev->wl, "DMA queue overflow\n");
1308 err = -ENOSPC;
1309 goto out_unlock;
1310 }
1311 /* Check if the queue was stopped in mac80211,
1312 * but we got called nevertheless.
1313 * That would be a mac80211 bug. */
1314 B43_WARN_ON(ring->stopped);
1315
1316 /* Assign the queue number to the ring (if not already done before)
1317 * so TX status handling can use it. The queue to ring mapping is
1318 * static, so we don't need to store it per frame. */
1319 ring->queue_prio = skb_get_queue_mapping(skb);
1320
1321 err = dma_tx_fragment(ring, skb);
1322 if (unlikely(err == -ENOKEY)) {
1323 /* Drop this packet, as we don't have the encryption key
1324 * anymore and must not transmit it unencrypted. */
1325 dev_kfree_skb_any(skb);
1326 err = 0;
1327 goto out_unlock;
1328 }
1329 if (unlikely(err)) {
1330 b43err(dev->wl, "DMA tx mapping failure\n");
1331 goto out_unlock;
1332 }
1333 ring->nr_tx_packets++;
1334 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1335 should_inject_overflow(ring)) {
1336 /* This TX ring is full. */
1337 ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb));
1338 ring->stopped = 1;
1339 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1340 b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1341 }
1342 }
1343 out_unlock:
1344 spin_unlock_irqrestore(&ring->lock, flags);
1345
1346 return err;
1347 }
1348
1349 /* Called with IRQs disabled. */
1350 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1351 const struct b43_txstatus *status)
1352 {
1353 const struct b43_dma_ops *ops;
1354 struct b43_dmaring *ring;
1355 struct b43_dmadesc_generic *desc;
1356 struct b43_dmadesc_meta *meta;
1357 int slot;
1358 bool frame_succeed;
1359
1360 ring = parse_cookie(dev, status->cookie, &slot);
1361 if (unlikely(!ring))
1362 return;
1363
1364 spin_lock(&ring->lock); /* IRQs are already disabled. */
1365
1366 B43_WARN_ON(!ring->tx);
1367 ops = ring->ops;
1368 while (1) {
1369 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1370 desc = ops->idx2desc(ring, slot, &meta);
1371
1372 if (meta->skb)
1373 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
1374 1);
1375 else
1376 unmap_descbuffer(ring, meta->dmaaddr,
1377 b43_txhdr_size(dev), 1);
1378
1379 if (meta->is_last_fragment) {
1380 struct ieee80211_tx_info *info;
1381
1382 BUG_ON(!meta->skb);
1383
1384 info = IEEE80211_SKB_CB(meta->skb);
1385
1386 memset(&info->status, 0, sizeof(info->status));
1387
1388 /*
1389 * Call back to inform the ieee80211 subsystem about
1390 * the status of the transmission.
1391 */
1392 frame_succeed = b43_fill_txstatus_report(info, status);
1393 #ifdef CONFIG_B43_DEBUG
1394 if (frame_succeed)
1395 ring->nr_succeed_tx_packets++;
1396 else
1397 ring->nr_failed_tx_packets++;
1398 ring->nr_total_packet_tries += status->frame_count;
1399 #endif /* DEBUG */
1400 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1401
1402 /* skb is freed by ieee80211_tx_status_irqsafe() */
1403 meta->skb = NULL;
1404 } else {
1405 /* No need to call free_descriptor_buffer here, as
1406 * this is only the txhdr, which is not allocated.
1407 */
1408 B43_WARN_ON(meta->skb);
1409 }
1410
1411 /* Everything unmapped and free'd. So it's not used anymore. */
1412 ring->used_slots--;
1413
1414 if (meta->is_last_fragment)
1415 break;
1416 slot = next_slot(ring, slot);
1417 }
1418 dev->stats.last_tx = jiffies;
1419 if (ring->stopped) {
1420 B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1421 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1422 ring->stopped = 0;
1423 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1424 b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1425 }
1426 }
1427
1428 spin_unlock(&ring->lock);
1429 }
1430
1431 void b43_dma_get_tx_stats(struct b43_wldev *dev,
1432 struct ieee80211_tx_queue_stats *stats)
1433 {
1434 const int nr_queues = dev->wl->hw->queues;
1435 struct b43_dmaring *ring;
1436 unsigned long flags;
1437 int i;
1438
1439 for (i = 0; i < nr_queues; i++) {
1440 ring = select_ring_by_priority(dev, i);
1441
1442 spin_lock_irqsave(&ring->lock, flags);
1443 stats[i].len = ring->used_slots / SLOTS_PER_PACKET;
1444 stats[i].limit = ring->nr_slots / SLOTS_PER_PACKET;
1445 stats[i].count = ring->nr_tx_packets;
1446 spin_unlock_irqrestore(&ring->lock, flags);
1447 }
1448 }
1449
1450 static void dma_rx(struct b43_dmaring *ring, int *slot)
1451 {
1452 const struct b43_dma_ops *ops = ring->ops;
1453 struct b43_dmadesc_generic *desc;
1454 struct b43_dmadesc_meta *meta;
1455 struct b43_rxhdr_fw4 *rxhdr;
1456 struct sk_buff *skb;
1457 u16 len;
1458 int err;
1459 dma_addr_t dmaaddr;
1460
1461 desc = ops->idx2desc(ring, *slot, &meta);
1462
1463 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1464 skb = meta->skb;
1465
1466 rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1467 len = le16_to_cpu(rxhdr->frame_len);
1468 if (len == 0) {
1469 int i = 0;
1470
1471 do {
1472 udelay(2);
1473 barrier();
1474 len = le16_to_cpu(rxhdr->frame_len);
1475 } while (len == 0 && i++ < 5);
1476 if (unlikely(len == 0)) {
1477 /* recycle the descriptor buffer. */
1478 sync_descbuffer_for_device(ring, meta->dmaaddr,
1479 ring->rx_buffersize);
1480 goto drop;
1481 }
1482 }
1483 if (unlikely(len > ring->rx_buffersize)) {
1484 /* The data did not fit into one descriptor buffer
1485 * and is split over multiple buffers.
1486 * This should never happen, as we try to allocate buffers
1487 * big enough. So simply ignore this packet.
1488 */
1489 int cnt = 0;
1490 s32 tmp = len;
1491
1492 while (1) {
1493 desc = ops->idx2desc(ring, *slot, &meta);
1494 /* recycle the descriptor buffer. */
1495 sync_descbuffer_for_device(ring, meta->dmaaddr,
1496 ring->rx_buffersize);
1497 *slot = next_slot(ring, *slot);
1498 cnt++;
1499 tmp -= ring->rx_buffersize;
1500 if (tmp <= 0)
1501 break;
1502 }
1503 b43err(ring->dev->wl, "DMA RX buffer too small "
1504 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1505 len, ring->rx_buffersize, cnt);
1506 goto drop;
1507 }
1508
1509 dmaaddr = meta->dmaaddr;
1510 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1511 if (unlikely(err)) {
1512 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1513 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1514 goto drop;
1515 }
1516
1517 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1518 skb_put(skb, len + ring->frameoffset);
1519 skb_pull(skb, ring->frameoffset);
1520
1521 b43_rx(ring->dev, skb, rxhdr);
1522 drop:
1523 return;
1524 }
1525
1526 void b43_dma_rx(struct b43_dmaring *ring)
1527 {
1528 const struct b43_dma_ops *ops = ring->ops;
1529 int slot, current_slot;
1530 int used_slots = 0;
1531
1532 B43_WARN_ON(ring->tx);
1533 current_slot = ops->get_current_rxslot(ring);
1534 B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1535
1536 slot = ring->current_slot;
1537 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1538 dma_rx(ring, &slot);
1539 update_max_used_slots(ring, ++used_slots);
1540 }
1541 ops->set_current_rxslot(ring, slot);
1542 ring->current_slot = slot;
1543 }
1544
1545 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1546 {
1547 unsigned long flags;
1548
1549 spin_lock_irqsave(&ring->lock, flags);
1550 B43_WARN_ON(!ring->tx);
1551 ring->ops->tx_suspend(ring);
1552 spin_unlock_irqrestore(&ring->lock, flags);
1553 }
1554
1555 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1556 {
1557 unsigned long flags;
1558
1559 spin_lock_irqsave(&ring->lock, flags);
1560 B43_WARN_ON(!ring->tx);
1561 ring->ops->tx_resume(ring);
1562 spin_unlock_irqrestore(&ring->lock, flags);
1563 }
1564
1565 void b43_dma_tx_suspend(struct b43_wldev *dev)
1566 {
1567 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1568 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1569 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1570 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1571 b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1572 b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1573 }
1574
1575 void b43_dma_tx_resume(struct b43_wldev *dev)
1576 {
1577 b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1578 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1579 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1580 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1581 b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1582 b43_power_saving_ctl_bits(dev, 0);
1583 }
1584
1585 #ifdef CONFIG_B43_PIO
1586 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1587 u16 mmio_base, bool enable)
1588 {
1589 u32 ctl;
1590
1591 if (type == B43_DMA_64BIT) {
1592 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1593 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1594 if (enable)
1595 ctl |= B43_DMA64_RXDIRECTFIFO;
1596 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1597 } else {
1598 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1599 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1600 if (enable)
1601 ctl |= B43_DMA32_RXDIRECTFIFO;
1602 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1603 }
1604 }
1605
1606 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1607 * This is called from PIO code, so DMA structures are not available. */
1608 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1609 unsigned int engine_index, bool enable)
1610 {
1611 enum b43_dmatype type;
1612 u16 mmio_base;
1613
1614 type = dma_mask_to_engine_type(supported_dma_mask(dev));
1615
1616 mmio_base = b43_dmacontroller_base(type, engine_index);
1617 direct_fifo_rx(dev, type, mmio_base, enable);
1618 }
1619 #endif /* CONFIG_B43_PIO */
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