package/linux/kernel-source/include/sbchipc.h

   1 /*
   2  * SiliconBackplane Chipcommon core hardware definitions.
   3  *
   4  * The chipcommon core provides chip identification, SB control,
   5  * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
   6  * gpio interface, extbus, and support for serial and parallel flashes.
   7  *
   8  * $Id$
   9  * Copyright 2004, Broadcom Corporation
  10  * All Rights Reserved.
  11  *
  12  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
  13  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  14  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  15  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  16  *
  17  */
  18
  19 #ifndef _SBCHIPC_H
  20 #define _SBCHIPC_H
  21
  22
  23 #ifndef _LANGUAGE_ASSEMBLY
  24
  25 /* cpp contortions to concatenate w/arg prescan */
  26 #ifndef PAD
  27 #define _PADLINE(line)  pad ## line
  28 #define _XSTR(line)     _PADLINE(line)
  29 #define PAD             _XSTR(__LINE__)
  30 #endif  /* PAD */
  31
  32 typedef volatile struct {
  33         uint32  chipid;                 /* 0x0 */
  34         uint32  capabilities;
  35         uint32  corecontrol;            /* corerev >= 1 */
  36         uint32  bist;
  37
  38         /* OTP */
  39         uint32  otpstatus;              /* 0x10, corerev >= 10 */
  40         uint32  otpcontrol;
  41         uint32  otpprog;
  42         uint32  PAD;
  43
  44         /* Interrupt control */
  45         uint32  intstatus;              /* 0x20 */
  46         uint32  intmask;
  47         uint32  PAD[2];
  48
  49         /* Jtag Master */
  50         uint32  jtagcmd;                /* 0x30, rev >= 10 */
  51         uint32  jtagir;
  52         uint32  jtagdr;
  53         uint32  jtagctrl;
  54
  55         /* serial flash interface registers */
  56         uint32  flashcontrol;           /* 0x40 */
  57         uint32  flashaddress;
  58         uint32  flashdata;
  59         uint32  PAD[1];
  60
  61         /* Silicon backplane configuration broadcast control */
  62         uint32  broadcastaddress;       /* 0x50 */
  63         uint32  broadcastdata;
  64         uint32  PAD[2];
  65
  66         /* gpio - cleared only by power-on-reset */
  67         uint32  gpioin;                 /* 0x60 */
  68         uint32  gpioout;
  69         uint32  gpioouten;
  70         uint32  gpiocontrol;
  71         uint32  gpiointpolarity;
  72         uint32  gpiointmask;
  73         uint32  PAD[2];
  74
  75         /* Watchdog timer */
  76         uint32  watchdog;               /* 0x80 */
  77         uint32  PAD[3];
  78
  79         /* clock control */
  80         uint32  clockcontrol_n;         /* 0x90 */
  81         uint32  clockcontrol_sb;        /* aka m0 */
  82         uint32  clockcontrol_pci;       /* aka m1 */
  83         uint32  clockcontrol_m2;        /* mii/uart/mipsref */
  84         uint32  clockcontrol_mips;      /* aka m3 */
  85         uint32  clkdiv;                 /* corerev >= 3 */
  86         uint32  PAD[2];
  87
  88         /* pll delay registers (corerev >= 4) */
  89         uint32  pll_on_delay;           /* 0xb0 */
  90         uint32  fref_sel_delay;
  91         uint32  slow_clk_ctl;           /* 5 < corerev < 10 */
  92         uint32  PAD[1];
  93
  94         /* Instaclock registers (corerev >= 10) */
  95         uint32  system_clk_ctl;         /* 0xc0 */
  96         uint32  clkstatestretch;
  97         uint32  PAD[14];
  98
  99         /* ExtBus control registers (corerev >= 3) */
 100         uint32  pcmcia_config;          /* 0x100 */
 101         uint32  pcmcia_memwait;
 102         uint32  pcmcia_attrwait;
 103         uint32  pcmcia_iowait;
 104         uint32  ide_config;
 105         uint32  ide_memwait;
 106         uint32  ide_attrwait;
 107         uint32  ide_iowait;
 108         uint32  prog_config;
 109         uint32  prog_waitcount;
 110         uint32  flash_config;
 111         uint32  flash_waitcount;
 112         uint32  PAD[116];
 113
 114         /* uarts */
 115         uint8   uart0data;              /* 0x300 */
 116         uint8   uart0imr;
 117         uint8   uart0fcr;
 118         uint8   uart0lcr;
 119         uint8   uart0mcr;
 120         uint8   uart0lsr;
 121         uint8   uart0msr;
 122         uint8   uart0scratch;
 123         uint8   PAD[248];               /* corerev >= 1 */
 124
 125         uint8   uart1data;              /* 0x400 */
 126         uint8   uart1imr;
 127         uint8   uart1fcr;
 128         uint8   uart1lcr;
 129         uint8   uart1mcr;
 130         uint8   uart1lsr;
 131         uint8   uart1msr;
 132         uint8   uart1scratch;
 133 } chipcregs_t;
 134
 135 #endif /* _LANGUAGE_ASSEMBLY */
 136
 137 #define CC_CHIPID               0
 138 #define CC_CAPABILITIES         4
 139 #define CC_JTAGCMD              0x30
 140 #define CC_JTAGIR               0x34
 141 #define CC_JTAGDR               0x38
 142 #define CC_JTAGCTRL             0x3c
 143 #define CC_CLKDIV               0xa4
 144
 145 /* chipid */
 146 #define CID_ID_MASK             0x0000ffff              /* Chip Id mask */
 147 #define CID_REV_MASK            0x000f0000              /* Chip Revision mask */
 148 #define CID_REV_SHIFT           16                      /* Chip Revision shift */
 149 #define CID_PKG_MASK            0x00f00000              /* Package Option mask */
 150 #define CID_PKG_SHIFT           20                      /* Package Option shift */
 151 #define CID_CC_MASK             0x0f000000              /* CoreCount (corerev >= 4) */
 152 #define CID_CC_SHIFT            24
 153
 154 /* capabilities */
 155 #define CAP_UARTS_MASK          0x00000003              /* Number of uarts */
 156 #define CAP_MIPSEB              0x00000004              /* MIPS is in big-endian mode */
 157 #define CAP_UCLKSEL             0x00000018              /* UARTs clock select */
 158 #define CAP_UINTCLK             0x00000008              /* UARTs are driven by internal divided clock */
 159 #define CAP_UARTGPIO            0x00000020              /* UARTs own Gpio's 15:12 */
 160 #define CAP_EXTBUS              0x00000040              /* External bus present */
 161 #define CAP_FLASH_MASK          0x00000700              /* Type of flash */
 162 #define CAP_PLL_MASK            0x00038000              /* Type of PLL */
 163 #define CAP_PWR_CTL             0x00040000              /* Power control */
 164 #define CAP_OTPSIZE             0x00380000              /* OTP Size (0 = none) */
 165 #define CAP_JTAGP               0x00400000              /* JTAG Master Present */
 166 #define CAP_ROM                 0x00800000              /* Internal boot rom active */
 167
 168 /* PLL type */
 169 #define PLL_NONE                0x00000000
 170 #define PLL_TYPE1               0x00010000              /* 48Mhz base, 3 dividers */
 171 #define PLL_TYPE2               0x00020000              /* 48Mhz, 4 dividers */
 172 #define PLL_TYPE3               0x00030000              /* 25Mhz, 2 dividers */
 173 #define PLL_TYPE4               0x00008000              /* 48Mhz, 4 dividers */
 174
 175 /* corecontrol */
 176 #define CC_UARTCLKO             0x00000001              /* Drive UART with internal clock */
 177 #define CC_SE                   0x00000002              /* sync clk out enable (corerev >= 3) */
 178
 179 /* jtagcmd */
 180 #define JCMD_START              0x80000000
 181 #define JCMD_BUSY               0x80000000
 182 #define JCMD_PAUSE              0x40000000
 183 #define JCMD0_ACC_MASK          0x0000f000
 184 #define JCMD0_ACC_IRDR          0x00000000
 185 #define JCMD0_ACC_DR            0x00001000
 186 #define JCMD0_ACC_IR            0x00002000
 187 #define JCMD0_ACC_RESET         0x00003000
 188 #define JCMD0_ACC_IRPDR         0x00004000
 189 #define JCMD0_ACC_PDR           0x00005000
 190 #define JCMD0_IRW_MASK          0x00000f00
 191 #define JCMD_ACC_MASK           0x000f0000              /* Changes for corerev 11 */
 192 #define JCMD_ACC_IRDR           0x00000000
 193 #define JCMD_ACC_DR             0x00010000
 194 #define JCMD_ACC_IR             0x00020000
 195 #define JCMD_ACC_RESET          0x00030000
 196 #define JCMD_ACC_IRPDR          0x00040000
 197 #define JCMD_ACC_PDR            0x00050000
 198 #define JCMD_IRW_MASK           0x00001f00
 199 #define JCMD_IRW_SHIFT          8
 200 #define JCMD_DRW_MASK           0x0000003f
 201
 202 /* jtagctrl */
 203 #define JCTRL_FORCE_CLK         4                       /* Force clock */
 204 #define JCTRL_EXT_EN            2                       /* Enable external targets */
 205 #define JCTRL_EN                1                       /* Enable Jtag master */
 206
 207 /* Fields in clkdiv */
 208 #define CLKD_SFLASH             0x0f000000
 209 #define CLKD_SFLASH_SHIFT               24
 210 #define CLKD_OTP                0x000f0000
 211 #define CLKD_OTP_SHIFT          16
 212 #define CLKD_JTAG               0x00000f00
 213 #define CLKD_JTAG_SHIFT         8
 214 #define CLKD_UART               0x000000ff
 215
 216 /* intstatus/intmask */
 217 #define CI_GPIO                 0x00000001              /* gpio intr */
 218 #define CI_EI                   0x00000002              /* ro: ext intr pin (corerev >= 3) */
 219 #define CI_WDREST               0x80000000              /* watchdog reset occurred */
 220
 221 /* slow_clk_ctl */
 222 #define SCC_SS_MASK             0x00000007              /* slow clock source mask */
 223 #define SCC_SS_LPO              0x00000000              /* source of slow clock is LPO */
 224 #define SCC_SS_XTAL             0x00000001              /* source of slow clock is crystal */
 225 #define SCC_SS_PCI              0x00000002              /* source of slow clock is PCI */
 226 #define SCC_LF                  0x00000200              /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
 227 #define SCC_LP                  0x00000400              /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
 228 #define SCC_FS                  0x00000800              /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
 229 #define SCC_IP                  0x00001000              /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
 230 #define SCC_XC                  0x00002000              /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
 231 #define SCC_XP                  0x00004000              /* XtalPU (RO), 1/0: crystal running/disabled */
 232 #define SCC_CD_MASK             0xffff0000              /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
 233 #define SCC_CD_SHF              16                      /* CLockDivider shift */
 234
 235 /* sys_clk_ctl */
 236 #define SYCC_IE                 0x00000001              /* ILPen: Enable Idle Low Power */
 237 #define SYCC_AE                 0x00000002              /* ALPen: Enable Active Low Power */
 238 #define SYCC_FP                 0x00000004              /* ForcePLLOn */
 239 #define SYCC_AR                 0x00000008              /* Force ALP (or HT if ALPen is not set */
 240 #define SYCC_HR                 0x00000010              /* Force HT */
 241 #define SYCC_CD_MASK            0xffff0000              /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
 242 #define SYCC_CD_SHF             16                      /* CLockDivider shift */
 243
 244 /* clockcontrol_n */
 245 #define CN_N1_MASK              0x3f                    /* n1 control */
 246 #define CN_N2_MASK              0x3f00                  /* n2 control */
 247 #define CN_N2_SHIFT             8
 248
 249 /* clockcontrol_sb/pci/uart */
 250 #define CC_M1_MASK              0x3f                    /* m1 control */
 251 #define CC_M2_MASK              0x3f00                  /* m2 control */
 252 #define CC_M2_SHIFT             8
 253 #define CC_M3_MASK              0x3f0000                /* m3 control */
 254 #define CC_M3_SHIFT             16
 255 #define CC_MC_MASK              0x1f000000              /* mux control */
 256 #define CC_MC_SHIFT             24
 257
 258 /* N3M Clock control values for 125Mhz */
 259 #define CC_125_N                0x0802                  /* Default values for bcm4310 */
 260 #define CC_125_M                0x04020009
 261 #define CC_125_M25              0x11090009
 262 #define CC_125_M33              0x11090005
 263
 264 /* N3M Clock control magic field values */
 265 #define CC_F6_2                 0x02                    /* A factor of 2 in */
 266 #define CC_F6_3                 0x03                    /* 6-bit fields like */
 267 #define CC_F6_4                 0x05                    /* N1, M1 or M3 */
 268 #define CC_F6_5                 0x09
 269 #define CC_F6_6                 0x11
 270 #define CC_F6_7                 0x21
 271
 272 #define CC_F5_BIAS              5                       /* 5-bit fields get this added */
 273
 274 #define CC_MC_BYPASS            0x08
 275 #define CC_MC_M1                0x04
 276 #define CC_MC_M1M2              0x02
 277 #define CC_MC_M1M2M3            0x01
 278 #define CC_MC_M1M3              0x11
 279
 280 /* Type 2 Clock control magic field values */
 281 #define CC_T2_BIAS              2                       /* n1, n2, m1 & m3 bias */
 282 #define CC_T2M2_BIAS            3                       /* m2 bias */
 283
 284 #define CC_T2MC_M1BYP           1
 285 #define CC_T2MC_M2BYP           2
 286 #define CC_T2MC_M3BYP           4
 287
 288 /* Common clock base */
 289 #define CC_CLOCK_BASE           24000000                /* Half the clock freq */
 290
 291
 292 /* Flash types in the chipcommon capabilities register */
 293 #define FLASH_NONE              0x000           /* No flash */
 294 #define SFLASH_ST               0x100           /* ST serial flash */
 295 #define SFLASH_AT               0x200           /* Atmel serial flash */
 296 #define PFLASH                  0x700           /* Parallel flash */
 297
 298 /* Prefered flash window in chipcommon */
 299 #define CC_FLASH_BASE           0xbc000000      /* Chips with chipcommon cores */
 300 #define CC_FLASH_MAX            0x02000000      /* Maximum flash size with chipc */
 301
 302
 303 /* Bits in the config registers */
 304 #define CC_CFG_EN               0x0001          /* Enable */
 305 #define CC_CFG_EM_MASK          0x000e          /* Extif Mode */
 306 #define CC_CFG_EM_ASYNC         0x0002          /*   Async/Parallel flash */
 307 #define CC_CFG_EM_SYNC          0x0004          /*   Synchronous */
 308 #define CC_CFG_EM_PCMCIA        0x0008          /*   PCMCIA */
 309 #define CC_CFG_EM_IDE           0x000a          /*   IDE */
 310 #define CC_CFG_DS               0x0010          /* Data size, 0=8bit, 1=16bit */
 311 #define CC_CFG_CD_MASK          0x0060          /* Sync: Clock divisor */
 312 #define CC_CFG_CE               0x0080          /* Sync: Clock enable */
 313 #define CC_CFG_SB               0x0100          /* Sync: Size/Bytestrobe */
 314
 315 /* Start/busy bit in flashcontrol */
 316 #define SFLASH_START            0x80000000
 317 #define SFLASH_BUSY             SFLASH_START
 318
 319 /* flashcontrol opcodes for ST flashes */
 320 #define SFLASH_ST_WREN          0x0006          /* Write Enable */
 321 #define SFLASH_ST_WRDIS         0x0004          /* Write Disable */
 322 #define SFLASH_ST_RDSR          0x0105          /* Read Status Register */
 323 #define SFLASH_ST_WRSR          0x0101          /* Write Status Register */
 324 #define SFLASH_ST_READ          0x0303          /* Read Data Bytes */
 325 #define SFLASH_ST_PP            0x0302          /* Page Program */
 326 #define SFLASH_ST_SE            0x02d8          /* Sector Erase */
 327 #define SFLASH_ST_BE            0x00c7          /* Bulk Erase */
 328 #define SFLASH_ST_DP            0x00b9          /* Deep Power-down */
 329 #define SFLASH_ST_RES           0x03ab          /* Read Electronic Signature */
 330
 331 /* Status register bits for ST flashes */
 332 #define SFLASH_ST_WIP           0x01            /* Write In Progress */
 333 #define SFLASH_ST_WEL           0x02            /* Write Enable Latch */
 334 #define SFLASH_ST_BP_MASK       0x1c            /* Block Protect */
 335 #define SFLASH_ST_BP_SHIFT      2
 336 #define SFLASH_ST_SRWD          0x80            /* Status Register Write Disable */
 337
 338 /* flashcontrol opcodes for Atmel flashes */
 339 #define SFLASH_AT_READ                          0x07e8
 340 #define SFLASH_AT_PAGE_READ                     0x07d2
 341 #define SFLASH_AT_BUF1_READ
 342 #define SFLASH_AT_BUF2_READ
 343 #define SFLASH_AT_STATUS                        0x01d7
 344 #define SFLASH_AT_BUF1_WRITE                    0x0384
 345 #define SFLASH_AT_BUF2_WRITE                    0x0387
 346 #define SFLASH_AT_BUF1_ERASE_PROGRAM            0x0283
 347 #define SFLASH_AT_BUF2_ERASE_PROGRAM            0x0286
 348 #define SFLASH_AT_BUF1_PROGRAM                  0x0288
 349 #define SFLASH_AT_BUF2_PROGRAM                  0x0289
 350 #define SFLASH_AT_PAGE_ERASE                    0x0281
 351 #define SFLASH_AT_BLOCK_ERASE                   0x0250
 352 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM      0x0382
 353 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM      0x0385
 354 #define SFLASH_AT_BUF1_LOAD                     0x0253
 355 #define SFLASH_AT_BUF2_LOAD                     0x0255
 356 #define SFLASH_AT_BUF1_COMPARE                  0x0260
 357 #define SFLASH_AT_BUF2_COMPARE                  0x0261
 358 #define SFLASH_AT_BUF1_REPROGRAM                0x0258
 359 #define SFLASH_AT_BUF2_REPROGRAM                0x0259
 360
 361 /* Status register bits for Atmel flashes */
 362 #define SFLASH_AT_READY                         0x80
 363 #define SFLASH_AT_MISMATCH                      0x40
 364 #define SFLASH_AT_ID_MASK                       0x38
 365 #define SFLASH_AT_ID_SHIFT                      3
 366
 367 #endif  /* _SBCHIPC_H */