target/linux/ar7-2.6/files/arch/mips/ar7/clock.c

   1 /*
   2  * $Id$
   3  *
   4  * Copyright (C) 2007 OpenWrt.org
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/types.h>
  23 #include <linux/module.h>
  24 #include <linux/delay.h>
  25 #include <asm/addrspace.h>
  26 #include <asm/io.h>
  27 #include <asm/ar7/ar7.h>
  28
  29 #define BOOT_PLL_SOURCE_MASK 0x3
  30 #define CPU_PLL_SOURCE_SHIFT 16
  31 #define BUS_PLL_SOURCE_SHIFT 14
  32 #define USB_PLL_SOURCE_SHIFT 18
  33 #define DSP_PLL_SOURCE_SHIFT 22
  34 #define BOOT_PLL_SOURCE_AFE 0
  35 #define BOOT_PLL_SOURCE_BUS 0
  36 #define BOOT_PLL_SOURCE_REF 1
  37 #define BOOT_PLL_SOURCE_XTAL 2
  38 #define BOOT_PLL_SOURCE_CPU 3
  39 #define BOOT_PLL_BYPASS 0x00000020
  40 #define BOOT_PLL_ASYNC_MODE 0x02000000
  41 #define BOOT_PLL_2TO1_MODE 0x00008000
  42
  43 #define TNETD7200_CLOCK_ID_CPU 0
  44 #define TNETD7200_CLOCK_ID_DSP 1
  45 #define TNETD7200_CLOCK_ID_USB 2
  46
  47 #define TNETD7200_DEF_CPU_CLK 211000000
  48 #define TNETD7200_DEF_DSP_CLK 125000000
  49 #define TNETD7200_DEF_USB_CLK 48000000
  50
  51 struct tnetd7300_clock {
  52         volatile u32 ctrl;
  53 #define PREDIV_MASK 0x001f0000
  54 #define PREDIV_SHIFT 16
  55 #define POSTDIV_MASK 0x0000001f
  56         u32 unused1[3];
  57         volatile u32 pll;
  58 #define MUL_MASK 0x0000f000
  59 #define MUL_SHIFT 12
  60 #define PLL_MODE_MASK 0x00000001
  61 #define PLL_NDIV 0x00000800
  62 #define PLL_DIV 0x00000002
  63 #define PLL_STATUS 0x00000001
  64         u32 unused2[3];
  65 } __attribute__ ((packed));
  66
  67 struct tnetd7300_clocks {
  68         struct tnetd7300_clock bus;
  69         struct tnetd7300_clock cpu;
  70         struct tnetd7300_clock usb;
  71         struct tnetd7300_clock dsp;
  72 } __attribute__ ((packed));
  73
  74 struct tnetd7200_clock {
  75         volatile u32 ctrl;
  76         u32 unused1[3];
  77 #define DIVISOR_ENABLE_MASK 0x00008000
  78         volatile u32 mul;
  79         volatile u32 prediv;
  80         volatile u32 postdiv;
  81         volatile u32 postdiv2;
  82         u32 unused2[6];
  83         volatile u32 cmd;
  84         volatile u32 status;
  85         volatile u32 cmden;
  86         u32 padding[15];
  87 } __attribute__ ((packed));
  88
  89 struct tnetd7200_clocks {
  90         struct tnetd7200_clock cpu;
  91         struct tnetd7200_clock dsp;
  92         struct tnetd7200_clock usb;
  93 } __attribute__ ((packed));
  94
  95 int ar7_afe_clock = 35328000;
  96 int ar7_ref_clock = 25000000;
  97 int ar7_xtal_clock = 24000000;
  98
  99 int ar7_cpu_clock = 150000000;
 100 EXPORT_SYMBOL(ar7_cpu_clock);
 101 int ar7_bus_clock = 125000000;
 102 EXPORT_SYMBOL(ar7_bus_clock);
 103 int ar7_dsp_clock = 0;
 104 EXPORT_SYMBOL(ar7_dsp_clock);
 105
 106 static int gcd(int x, int y)
 107 {
 108         if (x > y)
 109                 return (x % y) ? gcd(y, x % y) : y;
 110         return (y % x) ? gcd(x, y % x) : x;
 111 }
 112
 113 static inline int ABS(int x)
 114 {
 115         return (x >= 0) ? x : -x;
 116 }
 117
 118 static void approximate(int base, int target, int *prediv,
 119                         int *postdiv, int *mul)
 120 {
 121         int i, j, k, freq, res = target;
 122         for (i = 1; i <= 16; i++) {
 123                 for (j = 1; j <= 32; j++) {
 124                         for (k = 1; k <= 32; k++) {
 125                                 freq = ABS(base / j * i / k - target);
 126                                 if (freq < res) {
 127                                         res = freq;
 128                                         *mul = i;
 129                                         *prediv = j;
 130                                         *postdiv = k;
 131                                 }
 132                         }
 133                 }
 134         }
 135 }
 136
 137 static void calculate(int base, int target, int *prediv, int *postdiv,
 138                       int *mul)
 139 {
 140         int tmp_gcd, tmp_base, tmp_freq;
 141
 142         for (*prediv = 1; *prediv <= 32; (*prediv)++) {
 143                 tmp_base = base / *prediv;
 144                 tmp_gcd = gcd(target, tmp_base);
 145                 *mul = target / tmp_gcd;
 146                 *postdiv = tmp_base / tmp_gcd;
 147                 if ((*mul < 1) || (*mul >= 16))
 148                         continue;
 149                 if ((*postdiv > 0) & (*postdiv <= 32))
 150                         break;
 151         }
 152
 153         if (base / (*prediv) * (*mul) / (*postdiv) != target) {
 154                 approximate(base, target, prediv, postdiv, mul);
 155                 tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
 156                 printk(KERN_WARNING
 157                        "Adjusted requested frequency %d to %d\n",
 158                        target, tmp_freq);
 159         }
 160
 161         printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
 162                *prediv, *postdiv, *mul);
 163 }
 164
 165 static int tnetd7300_dsp_clock(void)
 166 {
 167         u32 didr1, didr2;
 168         u8 rev = ar7_chip_rev();
 169         didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
 170         didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
 171         if (didr2 & (1 << 23))
 172                 return 0;
 173         if ((rev >= 0x23) && (rev != 0x57))
 174                 return 250000000;
 175         if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
 176             > 4208000)
 177                 return 250000000;
 178         return 0;
 179 }
 180
 181 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
 182                                u32 *bootcr, u32 bus_clock)
 183 {
 184         int product;
 185         int base_clock = ar7_ref_clock;
 186         u32 ctrl = clock->ctrl;
 187         u32 pll = clock->pll;
 188         int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
 189         int postdiv = (ctrl & POSTDIV_MASK) + 1;
 190         int divisor = prediv * postdiv;
 191         int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
 192
 193         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 194         case BOOT_PLL_SOURCE_BUS:
 195                 base_clock = bus_clock;
 196                 break;
 197         case BOOT_PLL_SOURCE_REF:
 198                 base_clock = ar7_ref_clock;
 199                 break;
 200         case BOOT_PLL_SOURCE_XTAL:
 201                 base_clock = ar7_xtal_clock;
 202                 break;
 203         case BOOT_PLL_SOURCE_CPU:
 204                 base_clock = ar7_cpu_clock;
 205                 break;
 206         }
 207
 208         if (*bootcr & BOOT_PLL_BYPASS)
 209                 return base_clock / divisor;
 210
 211         if ((pll & PLL_MODE_MASK) == 0)
 212                 return (base_clock >> (mul / 16 + 1)) / divisor;
 213
 214         if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
 215                 product = (mul & 1) ?
 216                         (base_clock * mul) >> 1 :
 217                         (base_clock * (mul - 1)) >> 2;
 218                 return product / divisor;
 219         }
 220
 221         if (mul == 16)
 222                 return base_clock / divisor;
 223
 224         return base_clock * mul / divisor;
 225 }
 226
 227 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
 228                                 u32 *bootcr, u32 frequency)
 229 {
 230         u32 status;
 231         int prediv, postdiv, mul;
 232         int base_clock = ar7_bus_clock;
 233
 234         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
 235         case BOOT_PLL_SOURCE_BUS:
 236                 base_clock = ar7_bus_clock;
 237                 break;
 238         case BOOT_PLL_SOURCE_REF:
 239                 base_clock = ar7_ref_clock;
 240                 break;
 241         case BOOT_PLL_SOURCE_XTAL:
 242                 base_clock = ar7_xtal_clock;
 243                 break;
 244         case BOOT_PLL_SOURCE_CPU:
 245                 base_clock = ar7_cpu_clock;
 246                 break;
 247         }
 248
 249         calculate(base_clock, frequency, &prediv, &postdiv, &mul);
 250
 251         clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
 252         mdelay(1);
 253         clock->pll = 4;
 254         do {
 255                 status = clock->pll;
 256         } while (status & PLL_STATUS);
 257         clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
 258         mdelay(75);
 259 }
 260
 261 static void __init tnetd7300_init_clocks(void)
 262 {
 263         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 264         struct tnetd7300_clocks *clocks = (struct tnetd7300_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x20, sizeof(struct tnetd7300_clocks));
 265
 266         ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
 267                                             &clocks->bus, bootcr,
 268                                             ar7_afe_clock);
 269
 270         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 271                 ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
 272                                                     &clocks->cpu,
 273                                                     bootcr, ar7_afe_clock);
 274         } else {
 275                 ar7_cpu_clock = ar7_bus_clock;
 276         }
 277
 278         tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
 279                             bootcr, 48000000);
 280
 281         if (ar7_dsp_clock == 250000000)
 282                 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
 283                                     bootcr, ar7_dsp_clock);
 284
 285         iounmap(clocks);
 286         iounmap(bootcr);
 287 }
 288
 289 static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
 290                                u32 *bootcr, u32 bus_clock)
 291 {
 292         int divisor = ((clock->prediv & 0x1f) + 1) *
 293                 ((clock->postdiv & 0x1f) + 1);
 294
 295         if (*bootcr & BOOT_PLL_BYPASS)
 296                 return base / divisor;
 297
 298         return base * ((clock->mul & 0xf) + 1) / divisor;
 299 }
 300
 301
 302 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
 303                                 int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
 304 {
 305     printk("Clocks: base = %d, frequency = %u, prediv = %d, postdiv = %d, postdiv2 = %d, mul = %d\n",
 306         base, frequency, prediv, postdiv, postdiv2, mul);
 307
 308     clock->ctrl = 0;
 309         clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
 310     clock->mul = ((mul - 1) & 0xF);
 311
 312     for(mul = 0; mul < 2000; mul++) /* nop */;
 313
 314     while(clock->status & 0x1) /* nop */;
 315
 316     clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
 317
 318     clock->cmden |= 1;
 319     clock->cmd |= 1;
 320
 321     while(clock->status & 0x1) /* nop */;
 322
 323     clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
 324
 325     clock->cmden |= 1;
 326     clock->cmd |= 1;
 327
 328     while(clock->status & 0x1) /* nop */;
 329
 330     clock->ctrl |= 1;
 331 }
 332
 333 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
 334 {
 335     if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 336         // Async
 337         switch (clock_id) {
 338         case TNETD7200_CLOCK_ID_DSP:
 339             return ar7_ref_clock;
 340         default:
 341             return ar7_afe_clock;
 342         }
 343     } else {
 344         // Sync
 345                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
 346             // 2:1
 347             switch (clock_id) {
 348             case TNETD7200_CLOCK_ID_DSP:
 349                 return ar7_ref_clock;
 350             default:
 351                 return ar7_afe_clock;
 352             }
 353         } else {
 354             // 1:1
 355             return ar7_ref_clock;
 356         }
 357     }
 358 }
 359
 360
 361 static void __init tnetd7200_init_clocks(void)
 362 {
 363         u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
 364         struct tnetd7200_clocks *clocks = (struct tnetd7200_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x80, sizeof(struct tnetd7200_clocks));
 365     int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
 366     int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
 367     int usb_base, usb_mul, usb_prediv, usb_postdiv;
 368
 369     /*
 370         Log from Fritz!Box 7170 Annex B:
 371
 372         CPU revision is: 00018448
 373         Clocks: Async mode
 374         Clocks: Setting DSP clock
 375         Clocks: prediv: 1, postdiv: 1, mul: 5
 376         Clocks: base = 25000000, frequency = 125000000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
 377         Clocks: Setting CPU clock
 378         Adjusted requested frequency 211000000 to 211968000
 379         Clocks: prediv: 1, postdiv: 1, mul: 6
 380         Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
 381         Clocks: Setting USB clock
 382         Adjusted requested frequency 48000000 to 48076920
 383         Clocks: prediv: 13, postdiv: 1, mul: 5
 384         Clocks: base = 125000000, frequency = 48000000, prediv = 13, postdiv = 1, postdiv2 = -1, mul = 5
 385
 386         DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination, driver hung on startup.
 387         Haven't tested this on a synchronous board, neither do i know what to do with ar7_dsp_clock
 388     */
 389
 390     cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
 391     dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
 392
 393         if (*bootcr & BOOT_PLL_ASYNC_MODE) {
 394         printk("Clocks: Async mode\n");
 395
 396         printk("Clocks: Setting DSP clock\n");
 397         calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
 398         ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
 399         tnetd7200_set_clock(dsp_base, &clocks->dsp,
 400             dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 401             ar7_bus_clock);
 402
 403         printk("Clocks: Setting CPU clock\n");
 404         calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
 405         ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
 406         tnetd7200_set_clock(cpu_base, &clocks->cpu,
 407             cpu_prediv, cpu_postdiv, -1, cpu_mul,
 408             ar7_cpu_clock);
 409
 410         } else {
 411                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
 412             printk("Clocks: Sync 2:1 mode\n");
 413
 414             printk("Clocks: Setting CPU clock\n");
 415             calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
 416             ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
 417             tnetd7200_set_clock(cpu_base, &clocks->cpu,
 418                 cpu_prediv, cpu_postdiv, -1, cpu_mul,
 419                 ar7_cpu_clock);
 420
 421             printk("Clocks: Setting DSP clock\n");
 422             calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
 423             ar7_bus_clock = ar7_cpu_clock / 2;
 424             tnetd7200_set_clock(dsp_base, &clocks->dsp,
 425                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 426                 ar7_bus_clock);
 427                 } else {
 428             printk("Clocks: Sync 1:1 mode\n");
 429
 430             printk("Clocks: Setting DSP clock\n");
 431             calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
 432             ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
 433             tnetd7200_set_clock(dsp_base, &clocks->dsp,
 434                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
 435                 ar7_bus_clock);
 436
 437             ar7_cpu_clock = ar7_bus_clock;
 438                 }
 439         }
 440
 441     printk("Clocks: Setting USB clock\n");
 442     usb_base = ar7_bus_clock;
 443     calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, &usb_postdiv, &usb_mul);
 444     tnetd7200_set_clock(usb_base, &clocks->usb,
 445         usb_prediv, usb_postdiv, -1, usb_mul,
 446         TNETD7200_DEF_USB_CLK);
 447
 448 #warning FIXME: ????! Hrmm
 449     ar7_dsp_clock = ar7_cpu_clock;
 450
 451         iounmap(clocks);
 452         iounmap(bootcr);
 453 }
 454
 455 void __init ar7_init_clocks(void)
 456 {
 457         switch (ar7_chip_id()) {
 458         case AR7_CHIP_7100:
 459 #warning FIXME: Check if the new 7200 clock init works for 7100
 460                 tnetd7200_init_clocks();
 461                 break;
 462         case AR7_CHIP_7200:
 463                 tnetd7200_init_clocks();
 464                 break;
 465         case AR7_CHIP_7300:
 466                 ar7_dsp_clock = tnetd7300_dsp_clock();
 467                 tnetd7300_init_clocks();
 468                 break;
 469         default:
 470                 break;
 471         }
 472 }