projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
atheros: add kernel workaround for bringing up eth1 on devices with a micrel switch...
[openwrt.git] / target / linux / storm / patches / 005-gmac_napi_mask_intrs.patch
1 --- a/drivers/net/sl351x_gmac.c
2 +++ b/drivers/net/sl351x_gmac.c
3 @@ -127,6 +127,7 @@ static char _debug_prefetch_buf[_DEBUG_P
4 static int gmac_initialized = 0;
5 TOE_INFO_T toe_private_data;
6 static int do_again = 0;
7 +static int rx_poll_enabled;
8 spinlock_t gmac_fq_lock;
9 unsigned int FLAG_SWITCH;
10
11 @@ -1065,7 +1066,8 @@ static void toe_init_gmac(struct net_dev
12 tp->intr3_enabled = 0xffffffff;
13 tp->intr4_selected = GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
14 HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
15 - tp->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
16 + tp->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT| GMAC0_RX_OVERRUN_INT_BIT;
17 + // GMAC0_TX_PAUSE_OFF_INT_BIT| GMAC0_MIB_INT_BIT;
18
19 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
20 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
21 @@ -1115,7 +1117,7 @@ static void toe_init_gmac(struct net_dev
22 tp->intr3_enabled |= 0xffffffff;
23 tp->intr4_selected |= CLASS_RX_FULL_INT_BITS |
24 HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
25 - tp->intr4_enabled |= SWFQ_EMPTY_INT_BIT;
26 + tp->intr4_enabled |= SWFQ_EMPTY_INT_BIT | GMAC1_RX_OVERRUN_INT_BIT;
27 }
28 data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) | tp->intr0_selected;
29 writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
30 @@ -2408,7 +2410,7 @@ static inline void toe_gmac_fill_free_q(
31 // unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
32
33 fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
34 - spin_lock_irqsave(&gmac_fq_lock, flags);
35 + // spin_lock_irqsave(&gmac_fq_lock, flags);
36 //while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
37 // TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
38 while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
39 @@ -2428,10 +2430,47 @@ static inline void toe_gmac_fill_free_q(
40 SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
41 toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
42 }
43 - spin_unlock_irqrestore(&gmac_fq_lock, flags);
44 + // spin_unlock_irqrestore(&gmac_fq_lock, flags);
45 }
46 // EXPORT_SYMBOL(toe_gmac_fill_free_q);
47
48 +static void gmac_registers(const char *message)
49 +{
50 + unsigned int status0;
51 + unsigned int status1;
52 + unsigned int status2;
53 + unsigned int status3;
54 + unsigned int status4;
55 +
56 + printk("%s\n", message);
57 +
58 + status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
59 + status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
60 + status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
61 + status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
62 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
63 +
64 + printk("status: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
65 + status0, status1, status2, status3, status4);
66 +
67 + status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_0_REG);
68 + status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
69 + status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_2_REG);
70 + status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_3_REG);
71 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
72 +
73 + printk("mask : s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
74 + status0, status1, status2, status3, status4);
75 +
76 + status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
77 + status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
78 + status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
79 + status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
80 + status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
81 +
82 + printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
83 + status0, status1, status2, status3, status4);
84 +}
85 /*----------------------------------------------------------------------
86 * toe_gmac_interrupt
87 *----------------------------------------------------------------------*/
88 @@ -2492,6 +2531,7 @@ if (1)
89 writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
90 if (status4)
91 writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
92 +
93 #if 0
94 /* handle freeq interrupt first */
95 if (status4 & tp->intr4_enabled) {
96 @@ -2536,10 +2576,31 @@ if (1)
97 }
98 if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
99 {
100 - if (likely(netif_rx_schedule_prep(dev)))
101 + if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
102 {
103 - // unsigned int data32;
104 - // disable GMAC-0 rx interrupt
105 + unsigned int data32;
106 +
107 + if (rx_poll_enabled)
108 + gmac_registers("check #1");
109 +
110 + BUG_ON(rx_poll_enabled == 1);
111 +
112 +#if 0
113 + /* Masks GMAC-0 rx interrupt */
114 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
115 + data32 &= ~(DEFAULT_Q0_INT_BIT);
116 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
117 +
118 + /* Masks GMAC-0 queue empty interrupt */
119 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
120 + data32 &= ~DEFAULT_Q0_INT_BIT;
121 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
122 +
123 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
124 + data32 &= ~DEFAULT_Q0_INT_BIT;
125 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
126 +#endif
127 +
128 // class-Q & TOE-Q are implemented in future
129 //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
130 //data32 &= ~DEFAULT_Q0_INT_BIT;
131 @@ -2549,7 +2610,8 @@ if (1)
132 //tp->total_q_cnt_napi=0;
133 //rx_time = jiffies;
134 //rx_old_bytes = isPtr->rx_bytes;
135 - __netif_rx_schedule(dev);
136 + __netif_rx_schedule(dev);
137 + rx_poll_enabled = 1;
138 }
139 }
140 }
141 @@ -2569,9 +2631,31 @@ if (1)
142
143 if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
144 {
145 - if (likely(netif_rx_schedule_prep(dev)))
146 + if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
147 {
148 - // unsigned int data32;
149 + unsigned int data32;
150 +
151 + if (rx_poll_enabled)
152 + gmac_registers("check #2");
153 +
154 + BUG_ON(rx_poll_enabled == 1);
155 +
156 +#if 0
157 + /* Masks GMAC-1 rx interrupt */
158 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
159 + data32 &= ~(DEFAULT_Q1_INT_BIT);
160 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
161 +
162 + /* Masks GMAC-1 queue empty interrupt */
163 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
164 + data32 &= ~DEFAULT_Q1_INT_BIT;
165 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
166 +
167 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
168 + data32 &= ~DEFAULT_Q1_INT_BIT;
169 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
170 +#endif
171 +
172 // disable GMAC-0 rx interrupt
173 // class-Q & TOE-Q are implemented in future
174 //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
175 @@ -2583,9 +2667,13 @@ if (1)
176 //rx_time = jiffies;
177 //rx_old_bytes = isPtr->rx_bytes;
178 __netif_rx_schedule(dev);
179 + rx_poll_enabled = 1;
180 }
181 }
182 }
183 + } else {
184 +
185 + gmac_registers("check #3");
186 }
187
188 // Interrupt Status 0
189 @@ -3306,8 +3394,10 @@ next_rx:
190 SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
191 tp->rx_rwptr.bits32 = rwptr.bits32;
192
193 - toe_gmac_fill_free_q();
194 }
195 +
196 + /* Handles first available packets only then refill the queue. */
197 + toe_gmac_fill_free_q();
198 }
199
200 /*----------------------------------------------------------------------
201 @@ -4217,6 +4307,7 @@ static int gmac_rx_poll(struct net_devic
202 GMAC_RXDESC_T *curr_desc;
203 struct sk_buff *skb;
204 DMA_RWPTR_T rwptr;
205 + unsigned int data32;
206 unsigned int pkt_size;
207 unsigned int desc_count;
208 unsigned int good_frame, chksum_status, rx_status;
209 @@ -4231,7 +4322,7 @@ static int gmac_rx_poll(struct net_devic
210 //unsigned long long rx_time;
211
212
213 -
214 + BUG_ON(rx_poll_enabled == 0);
215 #if 1
216 if (do_again)
217 {
218 @@ -4516,6 +4607,30 @@ static int gmac_rx_poll(struct net_devic
219 #endif
220 //toe_gmac_fill_free_q();
221 netif_rx_complete(dev);
222 +
223 + rx_poll_enabled = 0;
224 +
225 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
226 + if (tp->port_id == 0)
227 + data32 |= DEFAULT_Q0_INT_BIT;
228 + else
229 + data32 |= DEFAULT_Q1_INT_BIT;
230 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
231 +
232 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
233 + if (tp->port_id == 0)
234 + data32 |= DEFAULT_Q0_INT_BIT;
235 + else
236 + data32 |= DEFAULT_Q1_INT_BIT;
237 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
238 +
239 + data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
240 + if (tp->port_id == 0)
241 + data32 |= DEFAULT_Q0_INT_BIT;
242 + else
243 + data32 |= DEFAULT_Q1_INT_BIT;
244 + writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
245 +
246 // enable GMAC-0 rx interrupt
247 // class-Q & TOE-Q are implemented in future
248 //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
Personal OpenWRT clone
This page took 0.067881 seconds and 5 git commands to generate.