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ar71xx: move micrel PHY driver to the generic linux target
[openwrt.git] / target / linux / generic / patches-2.6.32 / 975-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -3,7 +3,7 @@
4 * Broadcom ChipCommon core driver
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
13 if (!ccdev)
14 return;
15 bus = ccdev->bus;
16 +
17 + /* We support SLOW only on 6..9 */
18 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
19 + mode = SSB_CLKMODE_DYNAMIC;
20 +
21 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
22 + return; /* PMU controls clockmode, separated function needed */
23 + SSB_WARN_ON(ccdev->id.revision >= 20);
24 +
25 /* chipcommon cores prior to rev6 don't support dynamic clock control */
26 if (ccdev->id.revision < 6)
27 return;
28 - /* chipcommon cores rev10 are a whole new ball game */
29 +
30 + /* ChipCommon cores rev10+ need testing */
31 if (ccdev->id.revision >= 10)
32 return;
33 +
34 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
35 return;
36
37 switch (mode) {
38 - case SSB_CLKMODE_SLOW:
39 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
40 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
41 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
42 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
43 break;
44 case SSB_CLKMODE_FAST:
45 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
46 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
47 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
48 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
49 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
50 + if (ccdev->id.revision < 10) {
51 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
52 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
53 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
54 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
55 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
56 + } else {
57 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
58 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
59 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
60 + /* udelay(150); TODO: not available in early init */
61 + }
62 break;
63 case SSB_CLKMODE_DYNAMIC:
64 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
65 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
66 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
67 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
68 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
69 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
70 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
71 -
72 - /* for dynamic control, we have to release our xtal_pu "force on" */
73 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
74 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
75 + if (ccdev->id.revision < 10) {
76 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
77 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
78 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
79 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
80 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
81 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
82 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
83 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
84 +
85 + /* For dynamic control, we have to release our xtal_pu
86 + * "force on" */
87 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
88 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
89 + } else {
90 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
91 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
92 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
93 + }
94 break;
95 default:
96 SSB_WARN_ON(1);
97 @@ -209,6 +235,24 @@ static void chipco_powercontrol_init(str
98 }
99 }
100
101 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
102 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
103 +{
104 + struct ssb_bus *bus = cc->dev->bus;
105 +
106 + switch (bus->chip_id) {
107 + case 0x4312:
108 + case 0x4322:
109 + case 0x4328:
110 + return 7000;
111 + case 0x4325:
112 + /* TODO: */
113 + default:
114 + return 15000;
115 + }
116 +}
117 +
118 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
119 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
120 {
121 struct ssb_bus *bus = cc->dev->bus;
122 @@ -218,6 +262,12 @@ static void calc_fast_powerup_delay(stru
123
124 if (bus->bustype != SSB_BUSTYPE_PCI)
125 return;
126 +
127 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
128 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
129 + return;
130 + }
131 +
132 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
133 return;
134
135 @@ -236,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
136 if (cc->dev->id.revision >= 11)
137 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
138 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
139 +
140 + if (cc->dev->id.revision >= 20) {
141 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
142 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
143 + }
144 +
145 ssb_pmu_init(cc);
146 chipco_powercontrol_init(cc);
147 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
148 @@ -373,6 +429,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
149 {
150 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
151 }
152 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
153
154 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
155 {
156 --- a/drivers/ssb/driver_chipcommon_pmu.c
157 +++ b/drivers/ssb/driver_chipcommon_pmu.c
158 @@ -2,7 +2,7 @@
159 * Sonics Silicon Backplane
160 * Broadcom ChipCommon Power Management Unit driver
161 *
162 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
163 + * Copyright 2009, Michael Buesch <m@bues.ch>
164 * Copyright 2007, Broadcom Corporation
165 *
166 * Licensed under the GNU/GPL. See COPYING for details.
167 @@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
168 case 0x5354:
169 ssb_pmu0_pllinit_r0(cc, crystalfreq);
170 break;
171 + case 0x4322:
172 + if (cc->pmu.rev == 2) {
173 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
174 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
175 + }
176 + break;
177 default:
178 ssb_printk(KERN_ERR PFX
179 "ERROR: PLL init unknown for device %04X\n",
180 @@ -411,12 +417,15 @@ static void ssb_pmu_resources_init(struc
181 u32 min_msk = 0, max_msk = 0;
182 unsigned int i;
183 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
184 - unsigned int updown_tab_size;
185 + unsigned int updown_tab_size = 0;
186 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
187 - unsigned int depend_tab_size;
188 + unsigned int depend_tab_size = 0;
189
190 switch (bus->chip_id) {
191 case 0x4312:
192 + min_msk = 0xCBB;
193 + break;
194 + case 0x4322:
195 /* We keep the default settings:
196 * min_msk = 0xCBB
197 * max_msk = 0x7FFFF
198 @@ -495,9 +504,9 @@ static void ssb_pmu_resources_init(struc
199 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
200 }
201
202 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
203 void ssb_pmu_init(struct ssb_chipcommon *cc)
204 {
205 - struct ssb_bus *bus = cc->dev->bus;
206 u32 pmucap;
207
208 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
209 @@ -509,15 +518,12 @@ void ssb_pmu_init(struct ssb_chipcommon
210 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
211 cc->pmu.rev, pmucap);
212
213 - if (cc->pmu.rev >= 1) {
214 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
215 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
216 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
217 - } else {
218 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
219 - SSB_CHIPCO_PMU_CTL_NOILPONW);
220 - }
221 - }
222 + if (cc->pmu.rev == 1)
223 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
224 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
225 + else
226 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
227 + SSB_CHIPCO_PMU_CTL_NOILPONW);
228 ssb_pmu_pll_init(cc);
229 ssb_pmu_resources_init(cc);
230 }
231 --- a/drivers/ssb/driver_gige.c
232 +++ b/drivers/ssb/driver_gige.c
233 @@ -3,7 +3,7 @@
234 * Broadcom Gigabit Ethernet core driver
235 *
236 * Copyright 2008, Broadcom Corporation
237 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
238 + * Copyright 2008, Michael Buesch <m@bues.ch>
239 *
240 * Licensed under the GNU/GPL. See COPYING for details.
241 */
242 @@ -12,6 +12,7 @@
243 #include <linux/ssb/ssb_driver_gige.h>
244 #include <linux/pci.h>
245 #include <linux/pci_regs.h>
246 +#include <linux/slab.h>
247
248
249 /*
250 @@ -105,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
251 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
252 }
253
254 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
255 - int reg, int size, u32 *val)
256 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
257 + unsigned int devfn, int reg,
258 + int size, u32 *val)
259 {
260 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
261 unsigned long flags;
262 @@ -135,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
263 return PCIBIOS_SUCCESSFUL;
264 }
265
266 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
267 - int reg, int size, u32 val)
268 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
269 + unsigned int devfn, int reg,
270 + int size, u32 val)
271 {
272 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
273 unsigned long flags;
274 @@ -165,7 +168,8 @@ static int ssb_gige_pci_write_config(str
275 return PCIBIOS_SUCCESSFUL;
276 }
277
278 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
279 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
280 + const struct ssb_device_id *id)
281 {
282 struct ssb_gige *dev;
283 u32 base, tmslow, tmshigh;
284 --- a/drivers/ssb/driver_mipscore.c
285 +++ b/drivers/ssb/driver_mipscore.c
286 @@ -3,7 +3,7 @@
287 * Broadcom MIPS core driver
288 *
289 * Copyright 2005, Broadcom Corporation
290 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
291 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
292 *
293 * Licensed under the GNU/GPL. See COPYING for details.
294 */
295 @@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco
296 set_irq(dev, irq++);
297 }
298 break;
299 - /* fallthrough */
300 case SSB_DEV_PCI:
301 case SSB_DEV_ETHERNET:
302 case SSB_DEV_ETHERNET_GBIT:
303 @@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco
304 set_irq(dev, irq++);
305 break;
306 }
307 + /* fallthrough */
308 + case SSB_DEV_EXTIF:
309 + set_irq(dev, 0);
310 + break;
311 }
312 }
313 ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
314 --- a/drivers/ssb/driver_pcicore.c
315 +++ b/drivers/ssb/driver_pcicore.c
316 @@ -3,7 +3,7 @@
317 * Broadcom PCI-core driver
318 *
319 * Copyright 2005, Broadcom Corporation
320 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
321 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
322 *
323 * Licensed under the GNU/GPL. See COPYING for details.
324 */
325 @@ -15,6 +15,11 @@
326
327 #include "ssb_private.h"
328
329 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
330 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
331 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
332 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
333 + u8 address, u16 data);
334
335 static inline
336 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
337 @@ -246,20 +251,12 @@ static struct pci_controller ssb_pcicore
338 .pci_ops = &ssb_pcicore_pciops,
339 .io_resource = &ssb_pcicore_io_resource,
340 .mem_resource = &ssb_pcicore_mem_resource,
341 - .mem_offset = 0x24000000,
342 };
343
344 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
345 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
346 -
347 /* This function is called when doing a pci_enable_device().
348 * We must first check if the device is a device on the PCI-core bridge. */
349 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
350 {
351 - struct resource *res;
352 - int pos, size;
353 - u32 *base;
354 -
355 if (d->bus->ops != &ssb_pcicore_pciops) {
356 /* This is not a device on the PCI-core bridge. */
357 return -ENODEV;
358 @@ -268,27 +265,6 @@ int ssb_pcicore_plat_dev_init(struct pci
359 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
360 pci_name(d));
361
362 - /* Fix up resource bases */
363 - for (pos = 0; pos < 6; pos++) {
364 - res = &d->resource[pos];
365 - if (res->flags & IORESOURCE_IO)
366 - base = &ssb_pcicore_pcibus_iobase;
367 - else
368 - base = &ssb_pcicore_pcibus_membase;
369 - res->flags |= IORESOURCE_PCI_FIXED;
370 - if (res->end) {
371 - size = res->end - res->start + 1;
372 - if (*base & (size - 1))
373 - *base = (*base + size) & ~(size - 1);
374 - res->start = *base;
375 - res->end = res->start + size - 1;
376 - *base += size;
377 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
378 - }
379 - /* Fix up PCI bridge BAR0 only */
380 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
381 - break;
382 - }
383 /* Fix up interrupt lines */
384 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
385 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
386 @@ -338,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
387 return ssb_mips_irq(extpci_core->dev) + 2;
388 }
389
390 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
391 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
392 {
393 u32 val;
394
395 @@ -403,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
396 register_pci_controller(&ssb_pcicore_controller);
397 }
398
399 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
400 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
401 {
402 struct ssb_bus *bus = pc->dev->bus;
403 u16 chipid_top;
404 @@ -432,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
405 }
406 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
407
408 +/**************************************************
409 + * Workarounds.
410 + **************************************************/
411 +
412 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
413 +{
414 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
415 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
416 + tmp &= ~0xF000;
417 + tmp |= (pc->dev->core_index << 12);
418 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
419 + }
420 +}
421 +
422 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
423 +{
424 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
425 +}
426 +
427 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
428 +{
429 + const u8 serdes_pll_device = 0x1D;
430 + const u8 serdes_rx_device = 0x1F;
431 + u16 tmp;
432 +
433 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
434 + ssb_pcicore_polarity_workaround(pc));
435 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
436 + if (tmp & 0x4000)
437 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
438 +}
439 +
440 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
441 +{
442 + struct ssb_device *pdev = pc->dev;
443 + struct ssb_bus *bus = pdev->bus;
444 + u32 tmp;
445 +
446 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
447 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
448 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
449 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
450 +
451 + if (pdev->id.revision < 5) {
452 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
453 + tmp &= ~SSB_IMCFGLO_SERTO;
454 + tmp |= 2;
455 + tmp &= ~SSB_IMCFGLO_REQTO;
456 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
457 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
458 + ssb_commit_settings(bus);
459 + } else if (pdev->id.revision >= 11) {
460 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
461 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
462 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
463 + }
464 +}
465 +
466 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
467 +{
468 + u32 tmp;
469 + u8 rev = pc->dev->id.revision;
470 +
471 + if (rev == 0 || rev == 1) {
472 + /* TLP Workaround register. */
473 + tmp = ssb_pcie_read(pc, 0x4);
474 + tmp |= 0x8;
475 + ssb_pcie_write(pc, 0x4, tmp);
476 + }
477 + if (rev == 1) {
478 + /* DLLP Link Control register. */
479 + tmp = ssb_pcie_read(pc, 0x100);
480 + tmp |= 0x40;
481 + ssb_pcie_write(pc, 0x100, tmp);
482 + }
483 +
484 + if (rev == 0) {
485 + const u8 serdes_rx_device = 0x1F;
486 +
487 + ssb_pcie_mdio_write(pc, serdes_rx_device,
488 + 2 /* Timer */, 0x8128);
489 + ssb_pcie_mdio_write(pc, serdes_rx_device,
490 + 6 /* CDR */, 0x0100);
491 + ssb_pcie_mdio_write(pc, serdes_rx_device,
492 + 7 /* CDR BW */, 0x1466);
493 + } else if (rev == 3 || rev == 4 || rev == 5) {
494 + /* TODO: DLLP Power Management Threshold */
495 + ssb_pcicore_serdes_workaround(pc);
496 + /* TODO: ASPM */
497 + } else if (rev == 7) {
498 + /* TODO: No PLL down */
499 + }
500 +
501 + if (rev >= 6) {
502 + /* Miscellaneous Configuration Fixup */
503 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
504 + if (!(tmp & 0x8000))
505 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
506 + tmp | 0x8000);
507 + }
508 +}
509
510 /**************************************************
511 * Generic and Clientmode operation code.
512 **************************************************/
513
514 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
515 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
516 {
517 + struct ssb_device *pdev = pc->dev;
518 + struct ssb_bus *bus = pdev->bus;
519 +
520 + if (bus->bustype == SSB_BUSTYPE_PCI)
521 + ssb_pcicore_fix_sprom_core_index(pc);
522 +
523 /* Disable PCI interrupts. */
524 - ssb_write32(pc->dev, SSB_INTVEC, 0);
525 + ssb_write32(pdev, SSB_INTVEC, 0);
526 +
527 + /* Additional PCIe always once-executed workarounds */
528 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
529 + ssb_pcicore_serdes_workaround(pc);
530 + /* TODO: ASPM */
531 + /* TODO: Clock Request Update */
532 + }
533 }
534
535 -void ssb_pcicore_init(struct ssb_pcicore *pc)
536 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
537 {
538 struct ssb_device *dev = pc->dev;
539 - struct ssb_bus *bus;
540
541 if (!dev)
542 return;
543 - bus = dev->bus;
544 if (!ssb_device_is_enabled(dev))
545 ssb_device_enable(dev, 0);
546
547 @@ -475,58 +563,104 @@ static void ssb_pcie_write(struct ssb_pc
548 pcicore_write32(pc, 0x134, data);
549 }
550
551 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
552 - u8 address, u16 data)
553 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
554 {
555 const u16 mdio_control = 0x128;
556 const u16 mdio_data = 0x12C;
557 u32 v;
558 int i;
559
560 + v = (1 << 30); /* Start of Transaction */
561 + v |= (1 << 28); /* Write Transaction */
562 + v |= (1 << 17); /* Turnaround */
563 + v |= (0x1F << 18);
564 + v |= (phy << 4);
565 + pcicore_write32(pc, mdio_data, v);
566 +
567 + udelay(10);
568 + for (i = 0; i < 200; i++) {
569 + v = pcicore_read32(pc, mdio_control);
570 + if (v & 0x100 /* Trans complete */)
571 + break;
572 + msleep(1);
573 + }
574 +}
575 +
576 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
577 +{
578 + const u16 mdio_control = 0x128;
579 + const u16 mdio_data = 0x12C;
580 + int max_retries = 10;
581 + u16 ret = 0;
582 + u32 v;
583 + int i;
584 +
585 v = 0x80; /* Enable Preamble Sequence */
586 v |= 0x2; /* MDIO Clock Divisor */
587 pcicore_write32(pc, mdio_control, v);
588
589 + if (pc->dev->id.revision >= 10) {
590 + max_retries = 200;
591 + ssb_pcie_mdio_set_phy(pc, device);
592 + }
593 +
594 v = (1 << 30); /* Start of Transaction */
595 - v |= (1 << 28); /* Write Transaction */
596 + v |= (1 << 29); /* Read Transaction */
597 v |= (1 << 17); /* Turnaround */
598 - v |= (u32)device << 22;
599 + if (pc->dev->id.revision < 10)
600 + v |= (u32)device << 22;
601 v |= (u32)address << 18;
602 - v |= data;
603 pcicore_write32(pc, mdio_data, v);
604 /* Wait for the device to complete the transaction */
605 udelay(10);
606 - for (i = 0; i < 10; i++) {
607 + for (i = 0; i < max_retries; i++) {
608 v = pcicore_read32(pc, mdio_control);
609 - if (v & 0x100 /* Trans complete */)
610 + if (v & 0x100 /* Trans complete */) {
611 + udelay(10);
612 + ret = pcicore_read32(pc, mdio_data);
613 break;
614 + }
615 msleep(1);
616 }
617 pcicore_write32(pc, mdio_control, 0);
618 + return ret;
619 }
620
621 -static void ssb_broadcast_value(struct ssb_device *dev,
622 - u32 address, u32 data)
623 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
624 + u8 address, u16 data)
625 {
626 - /* This is used for both, PCI and ChipCommon core, so be careful. */
627 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
628 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
629 + const u16 mdio_control = 0x128;
630 + const u16 mdio_data = 0x12C;
631 + int max_retries = 10;
632 + u32 v;
633 + int i;
634
635 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
636 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
637 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
638 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
639 -}
640 + v = 0x80; /* Enable Preamble Sequence */
641 + v |= 0x2; /* MDIO Clock Divisor */
642 + pcicore_write32(pc, mdio_control, v);
643
644 -static void ssb_commit_settings(struct ssb_bus *bus)
645 -{
646 - struct ssb_device *dev;
647 + if (pc->dev->id.revision >= 10) {
648 + max_retries = 200;
649 + ssb_pcie_mdio_set_phy(pc, device);
650 + }
651
652 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
653 - if (WARN_ON(!dev))
654 - return;
655 - /* This forces an update of the cached registers. */
656 - ssb_broadcast_value(dev, 0xFD8, 0);
657 + v = (1 << 30); /* Start of Transaction */
658 + v |= (1 << 28); /* Write Transaction */
659 + v |= (1 << 17); /* Turnaround */
660 + if (pc->dev->id.revision < 10)
661 + v |= (u32)device << 22;
662 + v |= (u32)address << 18;
663 + v |= data;
664 + pcicore_write32(pc, mdio_data, v);
665 + /* Wait for the device to complete the transaction */
666 + udelay(10);
667 + for (i = 0; i < max_retries; i++) {
668 + v = pcicore_read32(pc, mdio_control);
669 + if (v & 0x100 /* Trans complete */)
670 + break;
671 + msleep(1);
672 + }
673 + pcicore_write32(pc, mdio_control, 0);
674 }
675
676 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
677 @@ -551,13 +685,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
678 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
679
680 /* Enable interrupts for this device. */
681 - if (bus->host_pci &&
682 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
683 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
684 u32 coremask;
685
686 /* Calculate the "coremask" for the device. */
687 coremask = (1 << dev->core_index);
688
689 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
690 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
691 if (err)
692 goto out;
693 @@ -579,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
694 if (pc->setup_done)
695 goto out;
696 if (pdev->id.coreid == SSB_DEV_PCI) {
697 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
698 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
699 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
700 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
701 -
702 - if (pdev->id.revision < 5) {
703 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
704 - tmp &= ~SSB_IMCFGLO_SERTO;
705 - tmp |= 2;
706 - tmp &= ~SSB_IMCFGLO_REQTO;
707 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
708 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
709 - ssb_commit_settings(bus);
710 - } else if (pdev->id.revision >= 11) {
711 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
712 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
713 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
714 - }
715 + ssb_pcicore_pci_setup_workarounds(pc);
716 } else {
717 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
718 - //TODO: Better make defines for all these magic PCIE values.
719 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
720 - /* TLP Workaround register. */
721 - tmp = ssb_pcie_read(pc, 0x4);
722 - tmp |= 0x8;
723 - ssb_pcie_write(pc, 0x4, tmp);
724 - }
725 - if (pdev->id.revision == 0) {
726 - const u8 serdes_rx_device = 0x1F;
727 -
728 - ssb_pcie_mdio_write(pc, serdes_rx_device,
729 - 2 /* Timer */, 0x8128);
730 - ssb_pcie_mdio_write(pc, serdes_rx_device,
731 - 6 /* CDR */, 0x0100);
732 - ssb_pcie_mdio_write(pc, serdes_rx_device,
733 - 7 /* CDR BW */, 0x1466);
734 - } else if (pdev->id.revision == 1) {
735 - /* DLLP Link Control register. */
736 - tmp = ssb_pcie_read(pc, 0x100);
737 - tmp |= 0x40;
738 - ssb_pcie_write(pc, 0x100, tmp);
739 - }
740 + ssb_pcicore_pcie_setup_workarounds(pc);
741 }
742 pc->setup_done = 1;
743 out:
744 --- a/drivers/ssb/main.c
745 +++ b/drivers/ssb/main.c
746 @@ -3,7 +3,7 @@
747 * Subsystem core
748 *
749 * Copyright 2005, Broadcom Corporation
750 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
751 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
752 *
753 * Licensed under the GNU/GPL. See COPYING for details.
754 */
755 @@ -12,12 +12,14 @@
756
757 #include <linux/delay.h>
758 #include <linux/io.h>
759 +#include <linux/module.h>
760 #include <linux/ssb/ssb.h>
761 #include <linux/ssb/ssb_regs.h>
762 #include <linux/ssb/ssb_driver_gige.h>
763 #include <linux/dma-mapping.h>
764 #include <linux/pci.h>
765 #include <linux/mmc/sdio_func.h>
766 +#include <linux/slab.h>
767
768 #include <pcmcia/cs_types.h>
769 #include <pcmcia/cs.h>
770 @@ -140,6 +142,19 @@ static void ssb_device_put(struct ssb_de
771 put_device(dev->dev);
772 }
773
774 +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
775 +{
776 + if (drv)
777 + get_driver(&drv->drv);
778 + return drv;
779 +}
780 +
781 +static inline void ssb_driver_put(struct ssb_driver *drv)
782 +{
783 + if (drv)
784 + put_driver(&drv->drv);
785 +}
786 +
787 static int ssb_device_resume(struct device *dev)
788 {
789 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
790 @@ -210,90 +225,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
791 EXPORT_SYMBOL(ssb_bus_suspend);
792
793 #ifdef CONFIG_SSB_SPROM
794 -int ssb_devices_freeze(struct ssb_bus *bus)
795 +/** ssb_devices_freeze - Freeze all devices on the bus.
796 + *
797 + * After freezing no device driver will be handling a device
798 + * on this bus anymore. ssb_devices_thaw() must be called after
799 + * a successful freeze to reactivate the devices.
800 + *
801 + * @bus: The bus.
802 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
803 + */
804 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
805 {
806 - struct ssb_device *dev;
807 - struct ssb_driver *drv;
808 - int err = 0;
809 - int i;
810 - pm_message_t state = PMSG_FREEZE;
811 + struct ssb_device *sdev;
812 + struct ssb_driver *sdrv;
813 + unsigned int i;
814 +
815 + memset(ctx, 0, sizeof(*ctx));
816 + ctx->bus = bus;
817 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
818
819 - /* First check that we are capable to freeze all devices. */
820 for (i = 0; i < bus->nr_devices; i++) {
821 - dev = &(bus->devices[i]);
822 - if (!dev->dev ||
823 - !dev->dev->driver ||
824 - !device_is_registered(dev->dev))
825 - continue;
826 - drv = drv_to_ssb_drv(dev->dev->driver);
827 - if (!drv)
828 + sdev = ssb_device_get(&bus->devices[i]);
829 +
830 + if (!sdev->dev || !sdev->dev->driver ||
831 + !device_is_registered(sdev->dev)) {
832 + ssb_device_put(sdev);
833 continue;
834 - if (!drv->suspend) {
835 - /* Nope, can't suspend this one. */
836 - return -EOPNOTSUPP;
837 }
838 - }
839 - /* Now suspend all devices */
840 - for (i = 0; i < bus->nr_devices; i++) {
841 - dev = &(bus->devices[i]);
842 - if (!dev->dev ||
843 - !dev->dev->driver ||
844 - !device_is_registered(dev->dev))
845 + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
846 + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
847 + ssb_device_put(sdev);
848 continue;
849 - drv = drv_to_ssb_drv(dev->dev->driver);
850 - if (!drv)
851 - continue;
852 - err = drv->suspend(dev, state);
853 - if (err) {
854 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
855 - dev_name(dev->dev));
856 - goto err_unwind;
857 }
858 + sdrv->remove(sdev);
859 + ctx->device_frozen[i] = 1;
860 }
861
862 return 0;
863 -err_unwind:
864 - for (i--; i >= 0; i--) {
865 - dev = &(bus->devices[i]);
866 - if (!dev->dev ||
867 - !dev->dev->driver ||
868 - !device_is_registered(dev->dev))
869 - continue;
870 - drv = drv_to_ssb_drv(dev->dev->driver);
871 - if (!drv)
872 - continue;
873 - if (drv->resume)
874 - drv->resume(dev);
875 - }
876 - return err;
877 }
878
879 -int ssb_devices_thaw(struct ssb_bus *bus)
880 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
881 + *
882 + * This will re-attach the device drivers and re-init the devices.
883 + *
884 + * @ctx: The context structure from ssb_devices_freeze()
885 + */
886 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
887 {
888 - struct ssb_device *dev;
889 - struct ssb_driver *drv;
890 - int err;
891 - int i;
892 + struct ssb_bus *bus = ctx->bus;
893 + struct ssb_device *sdev;
894 + struct ssb_driver *sdrv;
895 + unsigned int i;
896 + int err, result = 0;
897
898 for (i = 0; i < bus->nr_devices; i++) {
899 - dev = &(bus->devices[i]);
900 - if (!dev->dev ||
901 - !dev->dev->driver ||
902 - !device_is_registered(dev->dev))
903 + if (!ctx->device_frozen[i])
904 continue;
905 - drv = drv_to_ssb_drv(dev->dev->driver);
906 - if (!drv)
907 + sdev = &bus->devices[i];
908 +
909 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
910 continue;
911 - if (SSB_WARN_ON(!drv->resume))
912 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
913 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
914 continue;
915 - err = drv->resume(dev);
916 +
917 + err = sdrv->probe(sdev, &sdev->id);
918 if (err) {
919 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
920 - dev_name(dev->dev));
921 + dev_name(sdev->dev));
922 + result = err;
923 }
924 + ssb_driver_put(sdrv);
925 + ssb_device_put(sdev);
926 }
927
928 - return 0;
929 + return result;
930 }
931 #endif /* CONFIG_SSB_SPROM */
932
933 @@ -380,6 +386,35 @@ static int ssb_device_uevent(struct devi
934 ssb_dev->id.revision);
935 }
936
937 +#define ssb_config_attr(attrib, field, format_string) \
938 +static ssize_t \
939 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
940 +{ \
941 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
942 +}
943 +
944 +ssb_config_attr(core_num, core_index, "%u\n")
945 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
946 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
947 +ssb_config_attr(revision, id.revision, "%u\n")
948 +ssb_config_attr(irq, irq, "%u\n")
949 +static ssize_t
950 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
951 +{
952 + return sprintf(buf, "%s\n",
953 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
954 +}
955 +
956 +static struct device_attribute ssb_device_attrs[] = {
957 + __ATTR_RO(name),
958 + __ATTR_RO(core_num),
959 + __ATTR_RO(coreid),
960 + __ATTR_RO(vendor),
961 + __ATTR_RO(revision),
962 + __ATTR_RO(irq),
963 + __ATTR_NULL,
964 +};
965 +
966 static struct bus_type ssb_bustype = {
967 .name = "ssb",
968 .match = ssb_bus_match,
969 @@ -389,6 +424,7 @@ static struct bus_type ssb_bustype = {
970 .suspend = ssb_device_suspend,
971 .resume = ssb_device_resume,
972 .uevent = ssb_device_uevent,
973 + .dev_attrs = ssb_device_attrs,
974 };
975
976 static void ssb_buses_lock(void)
977 @@ -481,6 +517,7 @@ static int ssb_devices_register(struct s
978 #ifdef CONFIG_SSB_PCIHOST
979 sdev->irq = bus->host_pci->irq;
980 dev->parent = &bus->host_pci->dev;
981 + sdev->dma_dev = dev->parent;
982 #endif
983 break;
984 case SSB_BUSTYPE_PCMCIA:
985 @@ -490,13 +527,13 @@ static int ssb_devices_register(struct s
986 #endif
987 break;
988 case SSB_BUSTYPE_SDIO:
989 -#ifdef CONFIG_SSB_SDIO
990 - sdev->irq = bus->host_sdio->dev.irq;
991 +#ifdef CONFIG_SSB_SDIOHOST
992 dev->parent = &bus->host_sdio->dev;
993 #endif
994 break;
995 case SSB_BUSTYPE_SSB:
996 dev->dma_mask = &dev->coherent_dma_mask;
997 + sdev->dma_dev = dev;
998 break;
999 }
1000
1001 @@ -523,7 +560,7 @@ error:
1002 }
1003
1004 /* Needs ssb_buses_lock() */
1005 -static int ssb_attach_queued_buses(void)
1006 +static int __devinit ssb_attach_queued_buses(void)
1007 {
1008 struct ssb_bus *bus, *n;
1009 int err = 0;
1010 @@ -734,9 +771,9 @@ out:
1011 return err;
1012 }
1013
1014 -static int ssb_bus_register(struct ssb_bus *bus,
1015 - ssb_invariants_func_t get_invariants,
1016 - unsigned long baseaddr)
1017 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
1018 + ssb_invariants_func_t get_invariants,
1019 + unsigned long baseaddr)
1020 {
1021 int err;
1022
1023 @@ -817,8 +854,8 @@ err_disable_xtal:
1024 }
1025
1026 #ifdef CONFIG_SSB_PCIHOST
1027 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
1028 - struct pci_dev *host_pci)
1029 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
1030 + struct pci_dev *host_pci)
1031 {
1032 int err;
1033
1034 @@ -830,6 +867,9 @@ int ssb_bus_pcibus_register(struct ssb_b
1035 if (!err) {
1036 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1037 "PCI device %s\n", dev_name(&host_pci->dev));
1038 + } else {
1039 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1040 + " of SSB with error %d\n", err);
1041 }
1042
1043 return err;
1044 @@ -838,9 +878,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
1045 #endif /* CONFIG_SSB_PCIHOST */
1046
1047 #ifdef CONFIG_SSB_PCMCIAHOST
1048 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1049 - struct pcmcia_device *pcmcia_dev,
1050 - unsigned long baseaddr)
1051 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1052 + struct pcmcia_device *pcmcia_dev,
1053 + unsigned long baseaddr)
1054 {
1055 int err;
1056
1057 @@ -860,8 +900,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
1058 #endif /* CONFIG_SSB_PCMCIAHOST */
1059
1060 #ifdef CONFIG_SSB_SDIOHOST
1061 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
1062 - unsigned int quirks)
1063 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
1064 + struct sdio_func *func,
1065 + unsigned int quirks)
1066 {
1067 int err;
1068
1069 @@ -881,9 +922,9 @@ int ssb_bus_sdiobus_register(struct ssb_
1070 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
1071 #endif /* CONFIG_SSB_PCMCIAHOST */
1072
1073 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
1074 - unsigned long baseaddr,
1075 - ssb_invariants_func_t get_invariants)
1076 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
1077 + unsigned long baseaddr,
1078 + ssb_invariants_func_t get_invariants)
1079 {
1080 int err;
1081
1082 @@ -964,8 +1005,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
1083 switch (plltype) {
1084 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1085 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1086 - return SSB_CHIPCO_CLK_T6_M0;
1087 - return SSB_CHIPCO_CLK_T6_M1;
1088 + return SSB_CHIPCO_CLK_T6_M1;
1089 + return SSB_CHIPCO_CLK_T6_M0;
1090 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1091 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1092 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1093 @@ -1080,23 +1121,22 @@ static u32 ssb_tmslow_reject_bitmask(str
1094 {
1095 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1096
1097 - /* The REJECT bit changed position in TMSLOW between
1098 - * Backplane revisions. */
1099 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
1100 switch (rev) {
1101 case SSB_IDLOW_SSBREV_22:
1102 - return SSB_TMSLOW_REJECT_22;
1103 + case SSB_IDLOW_SSBREV_24:
1104 + case SSB_IDLOW_SSBREV_26:
1105 + return SSB_TMSLOW_REJECT;
1106 case SSB_IDLOW_SSBREV_23:
1107 return SSB_TMSLOW_REJECT_23;
1108 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
1109 - case SSB_IDLOW_SSBREV_25: /* same here */
1110 - case SSB_IDLOW_SSBREV_26: /* same here */
1111 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1112 case SSB_IDLOW_SSBREV_27: /* same here */
1113 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
1114 + return SSB_TMSLOW_REJECT; /* this is a guess */
1115 default:
1116 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1117 WARN_ON(1);
1118 }
1119 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
1120 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1121 }
1122
1123 int ssb_device_is_enabled(struct ssb_device *dev)
1124 @@ -1155,10 +1195,10 @@ void ssb_device_enable(struct ssb_device
1125 }
1126 EXPORT_SYMBOL(ssb_device_enable);
1127
1128 -/* Wait for a bit in a register to get set or unset.
1129 +/* Wait for bitmask in a register to get set or cleared.
1130 * timeout is in units of ten-microseconds */
1131 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1132 - int timeout, int set)
1133 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1134 + int timeout, int set)
1135 {
1136 int i;
1137 u32 val;
1138 @@ -1166,7 +1206,7 @@ static int ssb_wait_bit(struct ssb_devic
1139 for (i = 0; i < timeout; i++) {
1140 val = ssb_read32(dev, reg);
1141 if (set) {
1142 - if (val & bitmask)
1143 + if ((val & bitmask) == bitmask)
1144 return 0;
1145 } else {
1146 if (!(val & bitmask))
1147 @@ -1183,20 +1223,38 @@ static int ssb_wait_bit(struct ssb_devic
1148
1149 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1150 {
1151 - u32 reject;
1152 + u32 reject, val;
1153
1154 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1155 return;
1156
1157 reject = ssb_tmslow_reject_bitmask(dev);
1158 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1159 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1160 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1161 - ssb_write32(dev, SSB_TMSLOW,
1162 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1163 - reject | SSB_TMSLOW_RESET |
1164 - core_specific_flags);
1165 - ssb_flush_tmslow(dev);
1166 +
1167 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1168 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1169 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1170 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1171 +
1172 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1173 + val = ssb_read32(dev, SSB_IMSTATE);
1174 + val |= SSB_IMSTATE_REJECT;
1175 + ssb_write32(dev, SSB_IMSTATE, val);
1176 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1177 + 0);
1178 + }
1179 +
1180 + ssb_write32(dev, SSB_TMSLOW,
1181 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1182 + reject | SSB_TMSLOW_RESET |
1183 + core_specific_flags);
1184 + ssb_flush_tmslow(dev);
1185 +
1186 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1187 + val = ssb_read32(dev, SSB_IMSTATE);
1188 + val &= ~SSB_IMSTATE_REJECT;
1189 + ssb_write32(dev, SSB_IMSTATE, val);
1190 + }
1191 + }
1192
1193 ssb_write32(dev, SSB_TMSLOW,
1194 reject | SSB_TMSLOW_RESET |
1195 @@ -1205,13 +1263,34 @@ void ssb_device_disable(struct ssb_devic
1196 }
1197 EXPORT_SYMBOL(ssb_device_disable);
1198
1199 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
1200 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1201 +{
1202 + u16 chip_id = dev->bus->chip_id;
1203 +
1204 + if (dev->id.coreid == SSB_DEV_80211) {
1205 + return (chip_id == 0x4322 || chip_id == 43221 ||
1206 + chip_id == 43231 || chip_id == 43222);
1207 + }
1208 +
1209 + return 0;
1210 +}
1211 +
1212 u32 ssb_dma_translation(struct ssb_device *dev)
1213 {
1214 switch (dev->bus->bustype) {
1215 case SSB_BUSTYPE_SSB:
1216 return 0;
1217 case SSB_BUSTYPE_PCI:
1218 - return SSB_PCI_DMA;
1219 + if (dev->bus->host_pci->is_pcie &&
1220 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1221 + return SSB_PCIE_DMA_H32;
1222 + } else {
1223 + if (ssb_dma_translation_special_bit(dev))
1224 + return SSB_PCIE_DMA_H32;
1225 + else
1226 + return SSB_PCI_DMA;
1227 + }
1228 default:
1229 __ssb_dma_not_implemented(dev);
1230 }
1231 @@ -1328,20 +1407,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
1232
1233 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1234 {
1235 - struct ssb_chipcommon *cc;
1236 int err;
1237 enum ssb_clkmode mode;
1238
1239 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1240 if (err)
1241 goto error;
1242 - cc = &bus->chipco;
1243 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1244 - ssb_chipco_set_clockmode(cc, mode);
1245
1246 #ifdef CONFIG_SSB_DEBUG
1247 bus->powered_up = 1;
1248 #endif
1249 +
1250 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1251 + ssb_chipco_set_clockmode(&bus->chipco, mode);
1252 +
1253 return 0;
1254 error:
1255 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1256 @@ -1349,6 +1428,37 @@ error:
1257 }
1258 EXPORT_SYMBOL(ssb_bus_powerup);
1259
1260 +static void ssb_broadcast_value(struct ssb_device *dev,
1261 + u32 address, u32 data)
1262 +{
1263 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1264 + /* This is used for both, PCI and ChipCommon core, so be careful. */
1265 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1266 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1267 +#endif
1268 +
1269 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1270 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1271 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1272 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1273 +}
1274 +
1275 +void ssb_commit_settings(struct ssb_bus *bus)
1276 +{
1277 + struct ssb_device *dev;
1278 +
1279 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1280 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1281 +#else
1282 + dev = bus->chipco.dev;
1283 +#endif
1284 + if (WARN_ON(!dev))
1285 + return;
1286 + /* This forces an update of the cached registers. */
1287 + ssb_broadcast_value(dev, 0xFD8, 0);
1288 +}
1289 +EXPORT_SYMBOL(ssb_commit_settings);
1290 +
1291 u32 ssb_admatch_base(u32 adm)
1292 {
1293 u32 base = 0;
1294 --- a/drivers/ssb/pci.c
1295 +++ b/drivers/ssb/pci.c
1296 @@ -1,7 +1,7 @@
1297 /*
1298 * Sonics Silicon Backplane PCI-Hostbus related functions.
1299 *
1300 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
1301 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
1302 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1303 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1304 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1305 @@ -17,6 +17,7 @@
1306
1307 #include <linux/ssb/ssb.h>
1308 #include <linux/ssb/ssb_regs.h>
1309 +#include <linux/slab.h>
1310 #include <linux/pci.h>
1311 #include <linux/delay.h>
1312
1313 @@ -167,7 +168,7 @@ err_pci:
1314 }
1315
1316 /* Get the word-offset for a SSB_SPROM_XXX define. */
1317 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
1318 +#define SPOFF(offset) ((offset) / sizeof(u16))
1319 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
1320 #define SPEX16(_outvar, _offset, _mask, _shift) \
1321 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
1322 @@ -405,6 +406,46 @@ static void sprom_extract_r123(struct ss
1323 out->antenna_gain.ghz5.a3 = gain;
1324 }
1325
1326 +/* Revs 4 5 and 8 have partially shared layout */
1327 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
1328 +{
1329 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
1330 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
1331 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
1332 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
1333 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
1334 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
1335 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
1336 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
1337 +
1338 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
1339 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
1340 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
1341 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
1342 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
1343 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
1344 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
1345 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
1346 +
1347 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
1348 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
1349 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
1350 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
1351 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
1352 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
1353 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
1354 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
1355 +
1356 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
1357 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
1358 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
1359 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
1360 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
1361 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
1362 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
1363 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
1364 +}
1365 +
1366 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1367 {
1368 int i;
1369 @@ -427,10 +468,14 @@ static void sprom_extract_r45(struct ssb
1370 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1371 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1372 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1373 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1374 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1375 } else {
1376 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1377 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1378 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1379 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1380 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
1381 }
1382 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
1383 SSB_SPROM4_ANTAVAIL_A_SHIFT);
1384 @@ -470,13 +515,21 @@ static void sprom_extract_r45(struct ssb
1385 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1386 sizeof(out->antenna_gain.ghz5));
1387
1388 + sprom_extract_r458(out, in);
1389 +
1390 /* TODO - get remaining rev 4 stuff needed */
1391 }
1392
1393 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1394 {
1395 int i;
1396 - u16 v;
1397 + u16 v, o;
1398 + u16 pwr_info_offset[] = {
1399 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1400 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1401 + };
1402 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1403 + ARRAY_SIZE(out->core_pwr_info));
1404
1405 /* extract the MAC address */
1406 for (i = 0; i < 3; i++) {
1407 @@ -560,6 +613,63 @@ static void sprom_extract_r8(struct ssb_
1408 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1409 sizeof(out->antenna_gain.ghz5));
1410
1411 + /* Extract cores power info info */
1412 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1413 + o = pwr_info_offset[i];
1414 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1415 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1416 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1417 + SSB_SPROM8_2G_MAXP, 0);
1418 +
1419 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1420 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1421 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1422 +
1423 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1424 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1425 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1426 + SSB_SPROM8_5G_MAXP, 0);
1427 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1428 + SSB_SPROM8_5GH_MAXP, 0);
1429 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1430 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1431 +
1432 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1433 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1434 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1435 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1436 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1437 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1438 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1439 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1440 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1441 + }
1442 +
1443 + /* Extract FEM info */
1444 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1445 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1446 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
1447 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1448 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
1449 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1450 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
1451 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1452 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
1453 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1454 +
1455 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
1456 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1457 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
1458 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1459 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
1460 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1461 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
1462 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1463 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1464 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1465 +
1466 + sprom_extract_r458(out, in);
1467 +
1468 /* TODO - get remaining rev 8 stuff needed */
1469 }
1470
1471 @@ -572,37 +682,34 @@ static int sprom_extract(struct ssb_bus
1472 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1473 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1474 memset(out->et1mac, 0xFF, 6);
1475 +
1476 if ((bus->chip_id & 0xFF00) == 0x4400) {
1477 /* Workaround: The BCM44XX chip has a stupid revision
1478 * number stored in the SPROM.
1479 * Always extract r1. */
1480 out->revision = 1;
1481 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1482 + }
1483 +
1484 + switch (out->revision) {
1485 + case 1:
1486 + case 2:
1487 + case 3:
1488 sprom_extract_r123(out, in);
1489 - } else if (bus->chip_id == 0x4321) {
1490 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
1491 - out->revision = 4;
1492 + break;
1493 + case 4:
1494 + case 5:
1495 sprom_extract_r45(out, in);
1496 - } else {
1497 - switch (out->revision) {
1498 - case 1:
1499 - case 2:
1500 - case 3:
1501 - sprom_extract_r123(out, in);
1502 - break;
1503 - case 4:
1504 - case 5:
1505 - sprom_extract_r45(out, in);
1506 - break;
1507 - case 8:
1508 - sprom_extract_r8(out, in);
1509 - break;
1510 - default:
1511 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1512 - " revision %d detected. Will extract"
1513 - " v1\n", out->revision);
1514 - out->revision = 1;
1515 - sprom_extract_r123(out, in);
1516 - }
1517 + break;
1518 + case 8:
1519 + sprom_extract_r8(out, in);
1520 + break;
1521 + default:
1522 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1523 + " revision %d detected. Will extract"
1524 + " v1\n", out->revision);
1525 + out->revision = 1;
1526 + sprom_extract_r123(out, in);
1527 }
1528
1529 if (out->boardflags_lo == 0xFFFF)
1530 @@ -616,15 +723,14 @@ static int sprom_extract(struct ssb_bus
1531 static int ssb_pci_sprom_get(struct ssb_bus *bus,
1532 struct ssb_sprom *sprom)
1533 {
1534 - const struct ssb_sprom *fallback;
1535 - int err = -ENOMEM;
1536 + int err;
1537 u16 *buf;
1538
1539 if (!ssb_is_sprom_available(bus)) {
1540 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
1541 return -ENODEV;
1542 }
1543 - if (bus->chipco.dev) { /* can be unavailible! */
1544 + if (bus->chipco.dev) { /* can be unavailable! */
1545 /*
1546 * get SPROM offset: SSB_SPROM_BASE1 except for
1547 * chipcommon rev >= 31 or chip ID is 0x4312 and
1548 @@ -644,7 +750,7 @@ static int ssb_pci_sprom_get(struct ssb_
1549
1550 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
1551 if (!buf)
1552 - goto out;
1553 + return -ENOMEM;
1554 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
1555 sprom_do_read(bus, buf);
1556 err = sprom_check_crc(buf, bus->sprom_size);
1557 @@ -654,17 +760,24 @@ static int ssb_pci_sprom_get(struct ssb_
1558 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1559 GFP_KERNEL);
1560 if (!buf)
1561 - goto out;
1562 + return -ENOMEM;
1563 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
1564 sprom_do_read(bus, buf);
1565 err = sprom_check_crc(buf, bus->sprom_size);
1566 if (err) {
1567 /* All CRC attempts failed.
1568 * Maybe there is no SPROM on the device?
1569 - * If we have a fallback, use that. */
1570 - fallback = ssb_get_fallback_sprom();
1571 - if (fallback) {
1572 - memcpy(sprom, fallback, sizeof(*sprom));
1573 + * Now we ask the arch code if there is some sprom
1574 + * available for this device in some other storage */
1575 + err = ssb_fill_sprom_with_fallback(bus, sprom);
1576 + if (err) {
1577 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
1578 + " fallback SPROM failed (err %d)\n",
1579 + err);
1580 + } else {
1581 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1582 + " revision %d provided by"
1583 + " platform.\n", sprom->revision);
1584 err = 0;
1585 goto out_free;
1586 }
1587 @@ -676,19 +789,15 @@ static int ssb_pci_sprom_get(struct ssb_
1588
1589 out_free:
1590 kfree(buf);
1591 -out:
1592 return err;
1593 }
1594
1595 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
1596 struct ssb_boardinfo *bi)
1597 {
1598 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
1599 - &bi->vendor);
1600 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
1601 - &bi->type);
1602 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1603 - &bi->rev);
1604 + bi->vendor = bus->host_pci->subsystem_vendor;
1605 + bi->type = bus->host_pci->subsystem_device;
1606 + bi->rev = bus->host_pci->revision;
1607 }
1608
1609 int ssb_pci_get_invariants(struct ssb_bus *bus,
1610 --- a/drivers/ssb/pcihost_wrapper.c
1611 +++ b/drivers/ssb/pcihost_wrapper.c
1612 @@ -6,12 +6,13 @@
1613 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
1614 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
1615 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
1616 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
1617 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
1618 *
1619 * Licensed under the GNU/GPL. See COPYING for details.
1620 */
1621
1622 #include <linux/pci.h>
1623 +#include <linux/slab.h>
1624 #include <linux/ssb/ssb.h>
1625
1626
1627 @@ -52,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
1628 # define ssb_pcihost_resume NULL
1629 #endif /* CONFIG_PM */
1630
1631 -static int ssb_pcihost_probe(struct pci_dev *dev,
1632 - const struct pci_device_id *id)
1633 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
1634 + const struct pci_device_id *id)
1635 {
1636 struct ssb_bus *ssb;
1637 int err = -ENOMEM;
1638 const char *name;
1639 + u32 val;
1640
1641 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
1642 if (!ssb)
1643 @@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
1644 goto err_pci_disable;
1645 pci_set_master(dev);
1646
1647 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
1648 + * PCI Tx retries from interfering with C3 CPU state */
1649 + pci_read_config_dword(dev, 0x40, &val);
1650 + if ((val & 0x0000ff00) != 0)
1651 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
1652 +
1653 err = ssb_bus_pcibus_register(ssb, dev);
1654 if (err)
1655 goto err_pci_release_regions;
1656 @@ -102,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
1657 pci_set_drvdata(dev, NULL);
1658 }
1659
1660 -int ssb_pcihost_register(struct pci_driver *driver)
1661 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
1662 {
1663 driver->probe = ssb_pcihost_probe;
1664 driver->remove = ssb_pcihost_remove;
1665 --- a/drivers/ssb/pcmcia.c
1666 +++ b/drivers/ssb/pcmcia.c
1667 @@ -3,7 +3,7 @@
1668 * PCMCIA-Hostbus related functions
1669 *
1670 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1671 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1672 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1673 *
1674 * Licensed under the GNU/GPL. See COPYING for details.
1675 */
1676 @@ -617,136 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
1677 } \
1678 } while (0)
1679
1680 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
1681 - struct ssb_init_invariants *iv)
1682 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
1683 + tuple_t *tuple,
1684 + void *priv)
1685 +{
1686 + struct ssb_sprom *sprom = priv;
1687 +
1688 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
1689 + return -EINVAL;
1690 + if (tuple->TupleDataLen != ETH_ALEN + 2)
1691 + return -EINVAL;
1692 + if (tuple->TupleData[1] != ETH_ALEN)
1693 + return -EINVAL;
1694 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
1695 + return 0;
1696 +};
1697 +
1698 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
1699 + tuple_t *tuple,
1700 + void *priv)
1701 {
1702 - tuple_t tuple;
1703 - int res;
1704 - unsigned char buf[32];
1705 + struct ssb_init_invariants *iv = priv;
1706 struct ssb_sprom *sprom = &iv->sprom;
1707 struct ssb_boardinfo *bi = &iv->boardinfo;
1708 const char *error_description;
1709
1710 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
1711 + switch (tuple->TupleData[0]) {
1712 + case SSB_PCMCIA_CIS_ID:
1713 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
1714 + (tuple->TupleDataLen != 7),
1715 + "id tpl size");
1716 + bi->vendor = tuple->TupleData[1] |
1717 + ((u16)tuple->TupleData[2] << 8);
1718 + break;
1719 + case SSB_PCMCIA_CIS_BOARDREV:
1720 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1721 + "boardrev tpl size");
1722 + sprom->board_rev = tuple->TupleData[1];
1723 + break;
1724 + case SSB_PCMCIA_CIS_PA:
1725 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
1726 + (tuple->TupleDataLen != 10),
1727 + "pa tpl size");
1728 + sprom->pa0b0 = tuple->TupleData[1] |
1729 + ((u16)tuple->TupleData[2] << 8);
1730 + sprom->pa0b1 = tuple->TupleData[3] |
1731 + ((u16)tuple->TupleData[4] << 8);
1732 + sprom->pa0b2 = tuple->TupleData[5] |
1733 + ((u16)tuple->TupleData[6] << 8);
1734 + sprom->itssi_a = tuple->TupleData[7];
1735 + sprom->itssi_bg = tuple->TupleData[7];
1736 + sprom->maxpwr_a = tuple->TupleData[8];
1737 + sprom->maxpwr_bg = tuple->TupleData[8];
1738 + break;
1739 + case SSB_PCMCIA_CIS_OEMNAME:
1740 + /* We ignore this. */
1741 + break;
1742 + case SSB_PCMCIA_CIS_CCODE:
1743 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1744 + "ccode tpl size");
1745 + sprom->country_code = tuple->TupleData[1];
1746 + break;
1747 + case SSB_PCMCIA_CIS_ANTENNA:
1748 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1749 + "ant tpl size");
1750 + sprom->ant_available_a = tuple->TupleData[1];
1751 + sprom->ant_available_bg = tuple->TupleData[1];
1752 + break;
1753 + case SSB_PCMCIA_CIS_ANTGAIN:
1754 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1755 + "antg tpl size");
1756 + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
1757 + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
1758 + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
1759 + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
1760 + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
1761 + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
1762 + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
1763 + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
1764 + break;
1765 + case SSB_PCMCIA_CIS_BFLAGS:
1766 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
1767 + (tuple->TupleDataLen != 5),
1768 + "bfl tpl size");
1769 + sprom->boardflags_lo = tuple->TupleData[1] |
1770 + ((u16)tuple->TupleData[2] << 8);
1771 + break;
1772 + case SSB_PCMCIA_CIS_LEDS:
1773 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
1774 + "leds tpl size");
1775 + sprom->gpio0 = tuple->TupleData[1];
1776 + sprom->gpio1 = tuple->TupleData[2];
1777 + sprom->gpio2 = tuple->TupleData[3];
1778 + sprom->gpio3 = tuple->TupleData[4];
1779 + break;
1780 + }
1781 + return -ENOSPC; /* continue with next entry */
1782 +
1783 +error:
1784 + ssb_printk(KERN_ERR PFX
1785 + "PCMCIA: Failed to fetch device invariants: %s\n",
1786 + error_description);
1787 + return -ENODEV;
1788 +}
1789 +
1790 +
1791 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
1792 + struct ssb_init_invariants *iv)
1793 +{
1794 + struct ssb_sprom *sprom = &iv->sprom;
1795 + int res;
1796 +
1797 memset(sprom, 0xFF, sizeof(*sprom));
1798 sprom->revision = 1;
1799 sprom->boardflags_lo = 0;
1800 sprom->boardflags_hi = 0;
1801
1802 /* First fetch the MAC address. */
1803 - memset(&tuple, 0, sizeof(tuple));
1804 - tuple.DesiredTuple = CISTPL_FUNCE;
1805 - tuple.TupleData = buf;
1806 - tuple.TupleDataMax = sizeof(buf);
1807 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
1808 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
1809 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
1810 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
1811 - while (1) {
1812 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
1813 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
1814 - break;
1815 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
1816 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
1817 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
1818 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
1819 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
1820 + ssb_pcmcia_get_mac, sprom);
1821 + if (res != 0) {
1822 + ssb_printk(KERN_ERR PFX
1823 + "PCMCIA: Failed to fetch MAC address\n");
1824 + return -ENODEV;
1825 }
1826 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
1827 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
1828
1829 /* Fetch the vendor specific tuples. */
1830 - memset(&tuple, 0, sizeof(tuple));
1831 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
1832 - tuple.TupleData = buf;
1833 - tuple.TupleDataMax = sizeof(buf);
1834 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
1835 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
1836 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
1837 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
1838 - while (1) {
1839 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
1840 - switch (tuple.TupleData[0]) {
1841 - case SSB_PCMCIA_CIS_ID:
1842 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
1843 - (tuple.TupleDataLen != 7),
1844 - "id tpl size");
1845 - bi->vendor = tuple.TupleData[1] |
1846 - ((u16)tuple.TupleData[2] << 8);
1847 - break;
1848 - case SSB_PCMCIA_CIS_BOARDREV:
1849 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
1850 - "boardrev tpl size");
1851 - sprom->board_rev = tuple.TupleData[1];
1852 - break;
1853 - case SSB_PCMCIA_CIS_PA:
1854 - GOTO_ERROR_ON((tuple.TupleDataLen != 9) &&
1855 - (tuple.TupleDataLen != 10),
1856 - "pa tpl size");
1857 - sprom->pa0b0 = tuple.TupleData[1] |
1858 - ((u16)tuple.TupleData[2] << 8);
1859 - sprom->pa0b1 = tuple.TupleData[3] |
1860 - ((u16)tuple.TupleData[4] << 8);
1861 - sprom->pa0b2 = tuple.TupleData[5] |
1862 - ((u16)tuple.TupleData[6] << 8);
1863 - sprom->itssi_a = tuple.TupleData[7];
1864 - sprom->itssi_bg = tuple.TupleData[7];
1865 - sprom->maxpwr_a = tuple.TupleData[8];
1866 - sprom->maxpwr_bg = tuple.TupleData[8];
1867 - break;
1868 - case SSB_PCMCIA_CIS_OEMNAME:
1869 - /* We ignore this. */
1870 - break;
1871 - case SSB_PCMCIA_CIS_CCODE:
1872 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
1873 - "ccode tpl size");
1874 - sprom->country_code = tuple.TupleData[1];
1875 - break;
1876 - case SSB_PCMCIA_CIS_ANTENNA:
1877 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
1878 - "ant tpl size");
1879 - sprom->ant_available_a = tuple.TupleData[1];
1880 - sprom->ant_available_bg = tuple.TupleData[1];
1881 - break;
1882 - case SSB_PCMCIA_CIS_ANTGAIN:
1883 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
1884 - "antg tpl size");
1885 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
1886 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
1887 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
1888 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
1889 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
1890 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
1891 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
1892 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
1893 - break;
1894 - case SSB_PCMCIA_CIS_BFLAGS:
1895 - GOTO_ERROR_ON((tuple.TupleDataLen != 3) &&
1896 - (tuple.TupleDataLen != 5),
1897 - "bfl tpl size");
1898 - sprom->boardflags_lo = tuple.TupleData[1] |
1899 - ((u16)tuple.TupleData[2] << 8);
1900 - break;
1901 - case SSB_PCMCIA_CIS_LEDS:
1902 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
1903 - "leds tpl size");
1904 - sprom->gpio0 = tuple.TupleData[1];
1905 - sprom->gpio1 = tuple.TupleData[2];
1906 - sprom->gpio2 = tuple.TupleData[3];
1907 - sprom->gpio3 = tuple.TupleData[4];
1908 - break;
1909 - }
1910 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
1911 - if (res == -ENOSPC)
1912 - break;
1913 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
1914 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
1915 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
1916 - }
1917 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
1918 + ssb_pcmcia_do_get_invariants, iv);
1919 + if ((res == 0) || (res == -ENOSPC))
1920 + return 0;
1921
1922 - return 0;
1923 -error:
1924 ssb_printk(KERN_ERR PFX
1925 - "PCMCIA: Failed to fetch device invariants: %s\n",
1926 - error_description);
1927 + "PCMCIA: Failed to fetch device invariants\n");
1928 return -ENODEV;
1929 }
1930
1931 --- a/drivers/ssb/scan.c
1932 +++ b/drivers/ssb/scan.c
1933 @@ -2,7 +2,7 @@
1934 * Sonics Silicon Backplane
1935 * Bus scanning
1936 *
1937 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
1938 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
1939 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1940 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1941 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1942 @@ -260,7 +260,10 @@ static int we_support_multiple_80211_cor
1943 #ifdef CONFIG_SSB_PCIHOST
1944 if (bus->bustype == SSB_BUSTYPE_PCI) {
1945 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
1946 - bus->host_pci->device == 0x4324)
1947 + ((bus->host_pci->device == 0x4313) ||
1948 + (bus->host_pci->device == 0x431A) ||
1949 + (bus->host_pci->device == 0x4321) ||
1950 + (bus->host_pci->device == 0x4324)))
1951 return 1;
1952 }
1953 #endif /* CONFIG_SSB_PCIHOST */
1954 @@ -309,8 +312,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1955 } else {
1956 if (bus->bustype == SSB_BUSTYPE_PCI) {
1957 bus->chip_id = pcidev_to_chipid(bus->host_pci);
1958 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1959 - &bus->chip_rev);
1960 + bus->chip_rev = bus->host_pci->revision;
1961 bus->chip_package = 0;
1962 } else {
1963 bus->chip_id = 0x4710;
1964 @@ -354,7 +356,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1965 dev->bus = bus;
1966 dev->ops = bus->ops;
1967
1968 - ssb_dprintk(KERN_INFO PFX
1969 + printk(KERN_DEBUG PFX
1970 "Core %d found: %s "
1971 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
1972 i, ssb_core_name(dev->id.coreid),
1973 @@ -422,6 +424,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
1974 bus->pcicore.dev = dev;
1975 #endif /* CONFIG_SSB_DRIVER_PCICORE */
1976 break;
1977 + case SSB_DEV_ETHERNET:
1978 + if (bus->bustype == SSB_BUSTYPE_PCI) {
1979 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
1980 + (bus->host_pci->device & 0xFF00) == 0x4300) {
1981 + /* This is a dangling ethernet core on a
1982 + * wireless device. Ignore it. */
1983 + continue;
1984 + }
1985 + }
1986 + break;
1987 default:
1988 break;
1989 }
1990 --- a/drivers/ssb/sprom.c
1991 +++ b/drivers/ssb/sprom.c
1992 @@ -2,7 +2,7 @@
1993 * Sonics Silicon Backplane
1994 * Common SPROM support routines
1995 *
1996 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1997 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1998 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1999 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
2000 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
2001 @@ -14,9 +14,10 @@
2002 #include "ssb_private.h"
2003
2004 #include <linux/ctype.h>
2005 +#include <linux/slab.h>
2006
2007
2008 -static const struct ssb_sprom *fallback_sprom;
2009 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
2010
2011
2012 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
2013 @@ -102,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2014 u16 *sprom;
2015 int res = 0, err = -ENOMEM;
2016 size_t sprom_size_words = bus->sprom_size;
2017 + struct ssb_freeze_context freeze;
2018
2019 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
2020 if (!sprom)
2021 @@ -123,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2022 err = -ERESTARTSYS;
2023 if (mutex_lock_interruptible(&bus->sprom_mutex))
2024 goto out_kfree;
2025 - err = ssb_devices_freeze(bus);
2026 - if (err == -EOPNOTSUPP) {
2027 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
2028 - "No suspend support. Is CONFIG_PM enabled?\n");
2029 - goto out_unlock;
2030 - }
2031 + err = ssb_devices_freeze(bus, &freeze);
2032 if (err) {
2033 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
2034 goto out_unlock;
2035 }
2036 res = sprom_write(bus, sprom);
2037 - err = ssb_devices_thaw(bus);
2038 + err = ssb_devices_thaw(&freeze);
2039 if (err)
2040 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
2041 out_unlock:
2042 @@ -148,36 +145,43 @@ out:
2043 }
2044
2045 /**
2046 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
2047 - *
2048 - * @sprom: The SPROM data structure to register.
2049 + * ssb_arch_register_fallback_sprom - Registers a method providing a
2050 + * fallback SPROM if no SPROM is found.
2051 *
2052 - * With this function the architecture implementation may register a fallback
2053 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
2054 - * where no valid SPROM can be found in the shadow registers.
2055 + * @sprom_callback: The callback function.
2056 *
2057 - * This function is useful for weird architectures that have a half-assed SSB device
2058 - * hardwired to their PCI bus.
2059 + * With this function the architecture implementation may register a
2060 + * callback handler which fills the SPROM data structure. The fallback is
2061 + * only used for PCI based SSB devices, where no valid SPROM can be found
2062 + * in the shadow registers.
2063 + *
2064 + * This function is useful for weird architectures that have a half-assed
2065 + * SSB device hardwired to their PCI bus.
2066 + *
2067 + * Note that it does only work with PCI attached SSB devices. PCMCIA
2068 + * devices currently don't use this fallback.
2069 + * Architectures must provide the SPROM for native SSB devices anyway, so
2070 + * the fallback also isn't used for native devices.
2071 *
2072 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
2073 - * don't use this fallback.
2074 - * Architectures must provide the SPROM for native SSB devices anyway,
2075 - * so the fallback also isn't used for native devices.
2076 - *
2077 - * This function is available for architecture code, only. So it is not exported.
2078 + * This function is available for architecture code, only. So it is not
2079 + * exported.
2080 */
2081 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
2082 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
2083 + struct ssb_sprom *out))
2084 {
2085 - if (fallback_sprom)
2086 + if (get_fallback_sprom)
2087 return -EEXIST;
2088 - fallback_sprom = sprom;
2089 + get_fallback_sprom = sprom_callback;
2090
2091 return 0;
2092 }
2093
2094 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
2095 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
2096 {
2097 - return fallback_sprom;
2098 + if (!get_fallback_sprom)
2099 + return -ENOENT;
2100 +
2101 + return get_fallback_sprom(bus, out);
2102 }
2103
2104 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
2105 @@ -188,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
2106 /* this routine differs from specs as we do not access SPROM directly
2107 on PCMCIA */
2108 if (bus->bustype == SSB_BUSTYPE_PCI &&
2109 - bus->chipco.dev && /* can be unavailible! */
2110 + bus->chipco.dev && /* can be unavailable! */
2111 bus->chipco.dev->id.revision >= 31)
2112 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
2113
2114 --- a/drivers/ssb/ssb_private.h
2115 +++ b/drivers/ssb/ssb_private.h
2116 @@ -171,24 +171,33 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2117 const char *buf, size_t count,
2118 int (*sprom_check_crc)(const u16 *sprom, size_t size),
2119 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
2120 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
2121 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
2122 + struct ssb_sprom *out);
2123
2124
2125 /* core.c */
2126 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
2127 -extern int ssb_devices_freeze(struct ssb_bus *bus);
2128 -extern int ssb_devices_thaw(struct ssb_bus *bus);
2129 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
2130 int ssb_for_each_bus_call(unsigned long data,
2131 int (*func)(struct ssb_bus *bus, unsigned long data));
2132 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
2133
2134 +struct ssb_freeze_context {
2135 + /* Pointer to the bus */
2136 + struct ssb_bus *bus;
2137 + /* Boolean list to indicate whether a device is frozen on this bus. */
2138 + bool device_frozen[SSB_MAX_NR_CORES];
2139 +};
2140 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
2141 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
2142 +
2143 +
2144
2145 /* b43_pci_bridge.c */
2146 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
2147 extern int __init b43_pci_ssb_bridge_init(void);
2148 extern void __exit b43_pci_ssb_bridge_exit(void);
2149 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
2150 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
2151 static inline int b43_pci_ssb_bridge_init(void)
2152 {
2153 return 0;
2154 @@ -196,6 +205,6 @@ static inline int b43_pci_ssb_bridge_ini
2155 static inline void b43_pci_ssb_bridge_exit(void)
2156 {
2157 }
2158 -#endif /* CONFIG_SSB_PCIHOST */
2159 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
2160
2161 #endif /* LINUX_SSB_PRIVATE_H_ */
2162 --- a/include/linux/ssb/ssb.h
2163 +++ b/include/linux/ssb/ssb.h
2164 @@ -16,6 +16,12 @@ struct pcmcia_device;
2165 struct ssb_bus;
2166 struct ssb_driver;
2167
2168 +struct ssb_sprom_core_pwr_info {
2169 + u8 itssi_2g, itssi_5g;
2170 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
2171 + u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
2172 +};
2173 +
2174 struct ssb_sprom {
2175 u8 revision;
2176 u8 il0mac[6]; /* MAC address for 802.11b/g */
2177 @@ -25,8 +31,10 @@ struct ssb_sprom {
2178 u8 et1phyaddr; /* MII address for enet1 */
2179 u8 et0mdcport; /* MDIO for enet0 */
2180 u8 et1mdcport; /* MDIO for enet1 */
2181 - u8 board_rev; /* Board revision number from SPROM. */
2182 + u16 board_rev; /* Board revision number from SPROM. */
2183 u8 country_code; /* Country Code */
2184 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
2185 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
2186 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
2187 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
2188 u16 pa0b0;
2189 @@ -55,6 +63,10 @@ struct ssb_sprom {
2190 u8 tri5gl; /* 5.2GHz TX isolation */
2191 u8 tri5g; /* 5.3GHz TX isolation */
2192 u8 tri5gh; /* 5.8GHz TX isolation */
2193 + u8 txpid2g[4]; /* 2GHz TX power index */
2194 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
2195 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
2196 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
2197 u8 rxpo2g; /* 2GHz RX power offset */
2198 u8 rxpo5g; /* 5GHz RX power offset */
2199 u8 rssisav2g; /* 2GHz RSSI params */
2200 @@ -76,6 +88,8 @@ struct ssb_sprom {
2201 u16 boardflags2_hi; /* Board flags (bits 48-63) */
2202 /* TODO store board flags in a single u64 */
2203
2204 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
2205 +
2206 /* Antenna gain values for up to 4 antennas
2207 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
2208 * loss in the connectors is bigger than the gain. */
2209 @@ -88,6 +102,15 @@ struct ssb_sprom {
2210 } ghz5; /* 5GHz band */
2211 } antenna_gain;
2212
2213 + struct {
2214 + struct {
2215 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
2216 + } ghz2;
2217 + struct {
2218 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
2219 + } ghz5;
2220 + } fem;
2221 +
2222 /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
2223 };
2224
2225 @@ -95,7 +118,7 @@ struct ssb_sprom {
2226 struct ssb_boardinfo {
2227 u16 vendor;
2228 u16 type;
2229 - u16 rev;
2230 + u8 rev;
2231 };
2232
2233
2234 @@ -167,7 +190,7 @@ struct ssb_device {
2235 * is an optimization. */
2236 const struct ssb_bus_ops *ops;
2237
2238 - struct device *dev;
2239 + struct device *dev, *dma_dev;
2240
2241 struct ssb_bus *bus;
2242 struct ssb_device_id id;
2243 @@ -225,10 +248,9 @@ struct ssb_driver {
2244 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
2245
2246 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
2247 -static inline int ssb_driver_register(struct ssb_driver *drv)
2248 -{
2249 - return __ssb_driver_register(drv, THIS_MODULE);
2250 -}
2251 +#define ssb_driver_register(drv) \
2252 + __ssb_driver_register(drv, THIS_MODULE)
2253 +
2254 extern void ssb_driver_unregister(struct ssb_driver *drv);
2255
2256
2257 @@ -269,7 +291,8 @@ struct ssb_bus {
2258
2259 const struct ssb_bus_ops *ops;
2260
2261 - /* The core in the basic address register window. (PCI bus only) */
2262 + /* The core currently mapped into the MMIO window.
2263 + * Not valid on all host-buses. So don't use outside of SSB. */
2264 struct ssb_device *mapped_device;
2265 union {
2266 /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
2267 @@ -281,14 +304,17 @@ struct ssb_bus {
2268 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
2269 spinlock_t bar_lock;
2270
2271 - /* The bus this backplane is running on. */
2272 + /* The host-bus this backplane is running on. */
2273 enum ssb_bustype bustype;
2274 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
2275 - struct pci_dev *host_pci;
2276 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
2277 - struct pcmcia_device *host_pcmcia;
2278 - /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
2279 - struct sdio_func *host_sdio;
2280 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
2281 + union {
2282 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
2283 + struct pci_dev *host_pci;
2284 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
2285 + struct pcmcia_device *host_pcmcia;
2286 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
2287 + struct sdio_func *host_sdio;
2288 + };
2289
2290 /* See enum ssb_quirks */
2291 unsigned int quirks;
2292 @@ -300,7 +326,7 @@ struct ssb_bus {
2293
2294 /* ID information about the Chip. */
2295 u16 chip_id;
2296 - u16 chip_rev;
2297 + u8 chip_rev;
2298 u16 sprom_offset;
2299 u16 sprom_size; /* number of words in sprom */
2300 u8 chip_package;
2301 @@ -396,7 +422,9 @@ extern bool ssb_is_sprom_available(struc
2302
2303 /* Set a fallback SPROM.
2304 * See kdoc at the function definition for complete documentation. */
2305 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
2306 +extern int ssb_arch_register_fallback_sprom(
2307 + int (*sprom_callback)(struct ssb_bus *bus,
2308 + struct ssb_sprom *out));
2309
2310 /* Suspend a SSB bus.
2311 * Call this from the parent bus suspend routine. */
2312 @@ -667,6 +695,7 @@ extern int ssb_bus_may_powerdown(struct
2313 * Otherwise static always-on powercontrol will be used. */
2314 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
2315
2316 +extern void ssb_commit_settings(struct ssb_bus *bus);
2317
2318 /* Various helper functions */
2319 extern u32 ssb_admatch_base(u32 adm);
2320 --- a/include/linux/ssb/ssb_regs.h
2321 +++ b/include/linux/ssb/ssb_regs.h
2322 @@ -85,6 +85,8 @@
2323 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
2324 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
2325 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
2326 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
2327 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
2328 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
2329 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
2330 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
2331 @@ -95,7 +97,7 @@
2332 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
2333 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
2334 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
2335 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
2336 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
2337 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
2338 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
2339 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
2340 @@ -172,25 +174,25 @@
2341 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
2342 #define SSB_SPROM_BASE1 0x1000
2343 #define SSB_SPROM_BASE31 0x0800
2344 -#define SSB_SPROM_REVISION 0x107E
2345 +#define SSB_SPROM_REVISION 0x007E
2346 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
2347 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
2348 #define SSB_SPROM_REVISION_CRC_SHIFT 8
2349
2350 /* SPROM Revision 1 */
2351 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
2352 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
2353 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
2354 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
2355 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
2356 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
2357 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
2358 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
2359 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
2360 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
2361 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
2362 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
2363 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
2364 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
2365 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
2366 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
2367 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
2368 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
2369 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
2370 -#define SSB_SPROM1_BINF 0x105C /* Board info */
2371 +#define SSB_SPROM1_BINF 0x005C /* Board info */
2372 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
2373 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
2374 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
2375 @@ -198,63 +200,63 @@
2376 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
2377 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
2378 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
2379 -#define SSB_SPROM1_PA0B0 0x105E
2380 -#define SSB_SPROM1_PA0B1 0x1060
2381 -#define SSB_SPROM1_PA0B2 0x1062
2382 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
2383 +#define SSB_SPROM1_PA0B0 0x005E
2384 +#define SSB_SPROM1_PA0B1 0x0060
2385 +#define SSB_SPROM1_PA0B2 0x0062
2386 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
2387 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
2388 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
2389 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
2390 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
2391 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
2392 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
2393 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
2394 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
2395 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
2396 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
2397 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
2398 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
2399 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
2400 -#define SSB_SPROM1_PA1B0 0x106A
2401 -#define SSB_SPROM1_PA1B1 0x106C
2402 -#define SSB_SPROM1_PA1B2 0x106E
2403 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
2404 +#define SSB_SPROM1_PA1B0 0x006A
2405 +#define SSB_SPROM1_PA1B1 0x006C
2406 +#define SSB_SPROM1_PA1B2 0x006E
2407 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
2408 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
2409 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
2410 #define SSB_SPROM1_ITSSI_A_SHIFT 8
2411 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
2412 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
2413 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
2414 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
2415 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
2416 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
2417 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
2418 #define SSB_SPROM1_AGAIN_A_SHIFT 8
2419
2420 /* SPROM Revision 2 (inherits from rev 1) */
2421 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
2422 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
2423 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
2424 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
2425 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
2426 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
2427 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
2428 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
2429 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
2430 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
2431 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
2432 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
2433 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
2434 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
2435 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
2436 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
2437 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
2438 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
2439 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
2440 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
2441 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
2442 #define SSB_SPROM2_OPO_VALUE 0x00FF
2443 #define SSB_SPROM2_OPO_UNUSED 0xFF00
2444 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
2445 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
2446
2447 /* SPROM Revision 3 (inherits most data from rev 2) */
2448 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
2449 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
2450 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
2451 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
2452 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
2453 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
2454 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
2455 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
2456 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
2457 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
2458 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
2459 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
2460 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
2461 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
2462 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
2463 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
2464 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
2465 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
2466 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
2467 @@ -265,100 +267,144 @@
2468 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
2469
2470 /* SPROM Revision 4 */
2471 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
2472 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
2473 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
2474 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
2475 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
2476 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
2477 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
2478 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
2479 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
2480 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
2481 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
2482 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
2483 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
2484 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
2485 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
2486 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
2487 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
2488 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
2489 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
2490 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
2491 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
2492 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
2493 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
2494 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
2495 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
2496 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
2497 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
2498 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
2499 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
2500 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
2501 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
2502 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
2503 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
2504 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
2505 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
2506 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
2507 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
2508 #define SSB_SPROM4_AGAIN0_SHIFT 0
2509 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
2510 #define SSB_SPROM4_AGAIN1_SHIFT 8
2511 -#define SSB_SPROM4_AGAIN23 0x1060
2512 +#define SSB_SPROM4_AGAIN23 0x0060
2513 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
2514 #define SSB_SPROM4_AGAIN2_SHIFT 0
2515 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
2516 #define SSB_SPROM4_AGAIN3_SHIFT 8
2517 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
2518 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
2519 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
2520 +#define SSB_SPROM4_TXPID2G0 0x00FF
2521 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
2522 +#define SSB_SPROM4_TXPID2G1 0xFF00
2523 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
2524 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
2525 +#define SSB_SPROM4_TXPID2G2 0x00FF
2526 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
2527 +#define SSB_SPROM4_TXPID2G3 0xFF00
2528 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
2529 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
2530 +#define SSB_SPROM4_TXPID5G0 0x00FF
2531 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
2532 +#define SSB_SPROM4_TXPID5G1 0xFF00
2533 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
2534 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
2535 +#define SSB_SPROM4_TXPID5G2 0x00FF
2536 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
2537 +#define SSB_SPROM4_TXPID5G3 0xFF00
2538 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
2539 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
2540 +#define SSB_SPROM4_TXPID5GL0 0x00FF
2541 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
2542 +#define SSB_SPROM4_TXPID5GL1 0xFF00
2543 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
2544 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
2545 +#define SSB_SPROM4_TXPID5GL2 0x00FF
2546 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
2547 +#define SSB_SPROM4_TXPID5GL3 0xFF00
2548 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
2549 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
2550 +#define SSB_SPROM4_TXPID5GH0 0x00FF
2551 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
2552 +#define SSB_SPROM4_TXPID5GH1 0xFF00
2553 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
2554 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
2555 +#define SSB_SPROM4_TXPID5GH2 0x00FF
2556 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
2557 +#define SSB_SPROM4_TXPID5GH3 0xFF00
2558 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
2559 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
2560 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
2561 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
2562 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
2563 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
2564 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
2565 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
2566 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
2567 #define SSB_SPROM4_ITSSI_A_SHIFT 8
2568 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
2569 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
2570 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
2571 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
2572 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
2573 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
2574 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
2575 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
2576 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
2577 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
2578 -#define SSB_SPROM4_PA0B2 0x1086
2579 -#define SSB_SPROM4_PA1B0 0x108E
2580 -#define SSB_SPROM4_PA1B1 0x1090
2581 -#define SSB_SPROM4_PA1B2 0x1092
2582 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
2583 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
2584 +#define SSB_SPROM4_PA0B2 0x0086
2585 +#define SSB_SPROM4_PA1B0 0x008E
2586 +#define SSB_SPROM4_PA1B1 0x0090
2587 +#define SSB_SPROM4_PA1B2 0x0092
2588
2589 /* SPROM Revision 5 (inherits most data from rev 4) */
2590 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
2591 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
2592 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
2593 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
2594 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
2595 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
2596 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
2597 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
2598 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
2599 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
2600 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
2601 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
2602 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
2603 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
2604 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
2605 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
2606 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
2607 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
2608 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
2609 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
2610
2611 /* SPROM Revision 8 */
2612 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
2613 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
2614 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
2615 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
2616 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
2617 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
2618 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
2619 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
2620 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
2621 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
2622 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
2623 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
2624 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
2625 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
2626 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
2627 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
2628 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
2629 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
2630 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
2631 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
2632 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
2633 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
2634 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
2635 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
2636 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
2637 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
2638 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
2639 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
2640 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
2641 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
2642 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
2643 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
2644 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
2645 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
2646 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
2647 #define SSB_SPROM8_AGAIN0_SHIFT 0
2648 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
2649 #define SSB_SPROM8_AGAIN1_SHIFT 8
2650 -#define SSB_SPROM8_AGAIN23 0x10A0
2651 +#define SSB_SPROM8_AGAIN23 0x00A0
2652 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
2653 #define SSB_SPROM8_AGAIN2_SHIFT 0
2654 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
2655 #define SSB_SPROM8_AGAIN3_SHIFT 8
2656 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
2657 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
2658 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
2659 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
2660 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
2661 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
2662 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
2663 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
2664 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
2665 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
2666 #define SSB_SPROM8_RSSISMF2G 0x000F
2667 #define SSB_SPROM8_RSSISMC2G 0x00F0
2668 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
2669 @@ -366,7 +412,7 @@
2670 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
2671 #define SSB_SPROM8_BXA2G 0x1800
2672 #define SSB_SPROM8_BXA2G_SHIFT 11
2673 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
2674 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
2675 #define SSB_SPROM8_RSSISMF5G 0x000F
2676 #define SSB_SPROM8_RSSISMC5G 0x00F0
2677 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
2678 @@ -374,47 +420,138 @@
2679 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
2680 #define SSB_SPROM8_BXA5G 0x1800
2681 #define SSB_SPROM8_BXA5G_SHIFT 11
2682 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
2683 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
2684 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
2685 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
2686 #define SSB_SPROM8_TRI5G_SHIFT 8
2687 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
2688 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
2689 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
2690 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
2691 #define SSB_SPROM8_TRI5GH_SHIFT 8
2692 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
2693 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
2694 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
2695 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
2696 #define SSB_SPROM8_RXPO5G_SHIFT 8
2697 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
2698 +#define SSB_SPROM8_FEM2G 0x00AE
2699 +#define SSB_SPROM8_FEM5G 0x00B0
2700 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
2701 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
2702 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
2703 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
2704 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
2705 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
2706 +#define SSB_SROM8_FEM_TR_ISO 0x0700
2707 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
2708 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
2709 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
2710 +#define SSB_SPROM8_THERMAL 0x00B2
2711 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
2712 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
2713 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
2714 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
2715 +
2716 +/* There are 4 blocks with power info sharing the same layout */
2717 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
2718 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
2719 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
2720 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
2721 +
2722 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
2723 +#define SSB_SPROM8_2G_MAXP 0x00FF
2724 +#define SSB_SPROM8_2G_ITSSI 0xFF00
2725 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
2726 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
2727 +#define SSB_SROM8_2G_PA_1 0x04
2728 +#define SSB_SROM8_2G_PA_2 0x06
2729 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
2730 +#define SSB_SPROM8_5G_MAXP 0x00FF
2731 +#define SSB_SPROM8_5G_ITSSI 0xFF00
2732 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
2733 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
2734 +#define SSB_SPROM8_5GH_MAXP 0x00FF
2735 +#define SSB_SPROM8_5GL_MAXP 0xFF00
2736 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
2737 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
2738 +#define SSB_SROM8_5G_PA_1 0x0E
2739 +#define SSB_SROM8_5G_PA_2 0x10
2740 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
2741 +#define SSB_SROM8_5GL_PA_1 0x14
2742 +#define SSB_SROM8_5GL_PA_2 0x16
2743 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
2744 +#define SSB_SROM8_5GH_PA_1 0x1A
2745 +#define SSB_SROM8_5GH_PA_2 0x1C
2746 +
2747 +/* TODO: Make it deprecated */
2748 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
2749 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
2750 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
2751 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
2752 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
2753 -#define SSB_SPROM8_PA0B1 0x10C4
2754 -#define SSB_SPROM8_PA0B2 0x10C6
2755 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
2756 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
2757 +#define SSB_SPROM8_PA0B1 0x00C4
2758 +#define SSB_SPROM8_PA0B2 0x00C6
2759 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
2760 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
2761 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
2762 #define SSB_SPROM8_ITSSI_A_SHIFT 8
2763 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
2764 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
2765 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
2766 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
2767 #define SSB_SPROM8_MAXP_AL_SHIFT 8
2768 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
2769 -#define SSB_SPROM8_PA1B1 0x10CE
2770 -#define SSB_SPROM8_PA1B2 0x10D0
2771 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
2772 -#define SSB_SPROM8_PA1LOB1 0x10D4
2773 -#define SSB_SPROM8_PA1LOB2 0x10D6
2774 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
2775 -#define SSB_SPROM8_PA1HIB1 0x10DA
2776 -#define SSB_SPROM8_PA1HIB2 0x10DC
2777 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
2778 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
2779 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
2780 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
2781 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
2782 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
2783 +#define SSB_SPROM8_PA1B1 0x00CE
2784 +#define SSB_SPROM8_PA1B2 0x00D0
2785 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
2786 +#define SSB_SPROM8_PA1LOB1 0x00D4
2787 +#define SSB_SPROM8_PA1LOB2 0x00D6
2788 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
2789 +#define SSB_SPROM8_PA1HIB1 0x00DA
2790 +#define SSB_SPROM8_PA1HIB2 0x00DC
2791 +
2792 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
2793 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
2794 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
2795 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
2796 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
2797 +
2798 +/* Values for boardflags_lo read from SPROM */
2799 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
2800 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
2801 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
2802 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
2803 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
2804 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
2805 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
2806 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
2807 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
2808 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
2809 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
2810 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
2811 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
2812 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
2813 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
2814 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
2815 +
2816 +/* Values for boardflags_hi read from SPROM */
2817 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
2818 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
2819 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
2820 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
2821 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
2822 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
2823 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
2824 +
2825 +/* Values for boardflags2_lo read from SPROM */
2826 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
2827 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
2828 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
2829 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
2830 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
2831 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
2832 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
2833 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
2834 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
2835 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
2836 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
2837
2838 /* Values for SSB_SPROM1_BINF_CCODE */
2839 enum {
2840 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2841 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2842 @@ -8,7 +8,7 @@
2843 * gpio interface, extbus, and support for serial and parallel flashes.
2844 *
2845 * Copyright 2005, Broadcom Corporation
2846 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
2847 + * Copyright 2006, Michael Buesch <m@bues.ch>
2848 *
2849 * Licensed under the GPL version 2. See COPYING for details.
2850 */
2851 @@ -123,6 +123,8 @@
2852 #define SSB_CHIPCO_FLASHDATA 0x0048
2853 #define SSB_CHIPCO_BCAST_ADDR 0x0050
2854 #define SSB_CHIPCO_BCAST_DATA 0x0054
2855 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
2856 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
2857 #define SSB_CHIPCO_GPIOIN 0x0060
2858 #define SSB_CHIPCO_GPIOOUT 0x0064
2859 #define SSB_CHIPCO_GPIOOUTEN 0x0068
2860 @@ -131,6 +133,9 @@
2861 #define SSB_CHIPCO_GPIOIRQ 0x0074
2862 #define SSB_CHIPCO_WATCHDOG 0x0080
2863 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
2864 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
2865 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
2866 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
2867 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
2868 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
2869 #define SSB_CHIPCO_CLOCK_N 0x0090
2870 @@ -189,8 +194,10 @@
2871 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
2872 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
2873 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
2874 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
2875 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
2876 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
2877 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
2878 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
2879 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
2880 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
2881 #define SSB_CHIPCO_UART0_DATA 0x0300
2882 #define SSB_CHIPCO_UART0_IMR 0x0304
2883 --- a/drivers/ssb/b43_pci_bridge.c
2884 +++ b/drivers/ssb/b43_pci_bridge.c
2885 @@ -5,12 +5,13 @@
2886 * because of its small size we include it in the SSB core
2887 * instead of creating a standalone module.
2888 *
2889 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
2890 + * Copyright 2007 Michael Buesch <m@bues.ch>
2891 *
2892 * Licensed under the GNU/GPL. See COPYING for details.
2893 */
2894
2895 #include <linux/pci.h>
2896 +#include <linux/module.h>
2897 #include <linux/ssb/ssb.h>
2898
2899 #include "ssb_private.h"
2900 --- a/drivers/ssb/driver_extif.c
2901 +++ b/drivers/ssb/driver_extif.c
2902 @@ -3,7 +3,7 @@
2903 * Broadcom EXTIF core driver
2904 *
2905 * Copyright 2005, Broadcom Corporation
2906 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
2907 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
2908 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
2909 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
2910 *
2911 --- a/drivers/ssb/embedded.c
2912 +++ b/drivers/ssb/embedded.c
2913 @@ -3,7 +3,7 @@
2914 * Embedded systems support code
2915 *
2916 * Copyright 2005-2008, Broadcom Corporation
2917 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
2918 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
2919 *
2920 * Licensed under the GNU/GPL. See COPYING for details.
2921 */
2922 --- a/drivers/ssb/sdio.c
2923 +++ b/drivers/ssb/sdio.c
2924 @@ -6,7 +6,7 @@
2925 *
2926 * Based on drivers/ssb/pcmcia.c
2927 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2928 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2929 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2930 *
2931 * Licensed under the GNU/GPL. See COPYING for details.
2932 *
Personal OpenWRT clone
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