target/linux/ar71xx/patches-3.2/027-watchdog-ath79_wdt-flush-register-writes.patch

   1 From 156560a512a39284148d556ab96e2e833e816666 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Fri, 23 Dec 2011 19:25:42 +0100
   4 Subject: [PATCH 27/27] watchdog: ath79_wdt: flush register writes
   5
   6 The watchdog register writes required to have a flush
   7 in order to commit the values to the register. Without
   8 the flush, the driver not function correctly on AR934X
   9 SoCs.
  10
  11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  12 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
  13 Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
  14 ---
  15  drivers/watchdog/ath79_wdt.c |    6 ++++++
  16  1 files changed, 6 insertions(+), 0 deletions(-)
  17
  18 --- a/drivers/watchdog/ath79_wdt.c
  19 +++ b/drivers/watchdog/ath79_wdt.c
  20 @@ -68,17 +68,23 @@ static int max_timeout;
  21  static inline void ath79_wdt_keepalive(void)
  22  {
  23         ath79_reset_wr(AR71XX_RESET_REG_WDOG, wdt_freq * timeout);
  24 +       /* flush write */
  25 +       ath79_reset_rr(AR71XX_RESET_REG_WDOG);
  26  }
  27
  28  static inline void ath79_wdt_enable(void)
  29  {
  30         ath79_wdt_keepalive();
  31         ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
  32 +       /* flush write */
  33 +       ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
  34  }
  35
  36  static inline void ath79_wdt_disable(void)
  37  {
  38         ath79_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
  39 +       /* flush write */
  40 +       ath79_reset_rr(AR71XX_RESET_REG_WDOG_CTRL);
  41  }
  42
  43  static int ath79_wdt_set_timeout(int val)