target/linux/ar71xx/patches-3.2/134-MIPS-ath79-add-initial-support-for-the-Atheros-DB120.patch

   1 From a01e8727327cf0fb6382ca8700a3a3f73d93202a Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Fri, 9 Dec 2011 22:23:02 +0100
   4 Subject: [PATCH 34/35] MIPS: ath79: add initial support for the Atheros DB120 board
   5
   6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   7 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
   8 ---
   9  arch/mips/ath79/Kconfig      |   12 +++
  10  arch/mips/ath79/Makefile     |    1 +
  11  arch/mips/ath79/mach-db120.c |  155 ++++++++++++++++++++++++++++++++++++++++++
  12  arch/mips/ath79/machtypes.h  |    1 +
  13  4 files changed, 169 insertions(+), 0 deletions(-)
  14  create mode 100644 arch/mips/ath79/mach-db120.c
  15
  16 --- a/arch/mips/ath79/Kconfig
  17 +++ b/arch/mips/ath79/Kconfig
  18 @@ -26,6 +26,18 @@ config ATH79_MACH_AP81
  19           Say 'Y' here if you want your kernel to support the
  20           Atheros AP81 reference board.
  21
  22 +config ATH79_MACH_DB120
  23 +       bool "Atheros DB120 reference board"
  24 +       select SOC_AR934X
  25 +       select ATH79_DEV_GPIO_BUTTONS
  26 +       select ATH79_DEV_LEDS_GPIO
  27 +       select ATH79_DEV_SPI
  28 +       select ATH79_DEV_USB
  29 +       select ATH79_DEV_WMAC
  30 +       help
  31 +         Say 'Y' here if you want your kernel to support the
  32 +         Atheros DB120 reference board.
  33 +
  34  config ATH79_MACH_PB44
  35         bool "Atheros PB44 reference board"
  36         select SOC_AR71XX
  37 --- a/arch/mips/ath79/Makefile
  38 +++ b/arch/mips/ath79/Makefile
  39 @@ -28,5 +28,6 @@ obj-$(CONFIG_ATH79_DEV_WMAC)          += dev-wma
  40  #
  41  obj-$(CONFIG_ATH79_MACH_AP121)         += mach-ap121.o
  42  obj-$(CONFIG_ATH79_MACH_AP81)          += mach-ap81.o
  43 +obj-$(CONFIG_ATH79_MACH_DB120)         += mach-db120.o
  44  obj-$(CONFIG_ATH79_MACH_PB44)          += mach-pb44.o
  45  obj-$(CONFIG_ATH79_MACH_UBNT_XM)       += mach-ubnt-xm.o
  46 --- /dev/null
  47 +++ b/arch/mips/ath79/mach-db120.c
  48 @@ -0,0 +1,155 @@
  49 +/*
  50 + * Atheros DB120 reference board support
  51 + *
  52 + * Copyright (c) 2011 Qualcomm Atheros
  53 + * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
  54 + *
  55 + * All rights reserved.
  56 + *
  57 + * Redistribution and use in source and binary forms, with or without
  58 + * modification, are permitted (subject to the limitations in the
  59 + * disclaimer below) provided that the following conditions are met:
  60 + *
  61 + *  * Redistributions of source code must retain the above copyright
  62 + *    notice, this list of conditions and the following disclaimer.
  63 + *
  64 + *  * Redistributions in binary form must reproduce the above copyright
  65 + *    notice, this list of conditions and the following disclaimer in the
  66 + *    documentation and/or other materials provided with the
  67 + *    distribution.
  68 + *
  69 + *  * Neither the name of Qualcomm Atheros nor the names of its
  70 + *    contributors may be used to endorse or promote products derived
  71 + *    from this software without specific prior written permission.
  72 + *
  73 + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
  74 + * GRANTED BY THIS LICENSE.  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
  75 + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
  76 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  77 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  78 + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  79 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  80 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  81 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  82 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  83 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  84 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  85 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  86 + */
  87 +
  88 +#include <linux/pci.h>
  89 +#include <linux/ath9k_platform.h>
  90 +
  91 +#include "machtypes.h"
  92 +#include "dev-gpio-buttons.h"
  93 +#include "dev-leds-gpio.h"
  94 +#include "dev-spi.h"
  95 +#include "dev-usb.h"
  96 +#include "dev-wmac.h"
  97 +#include "pci.h"
  98 +
  99 +#define DB120_GPIO_LED_WLAN_5G         12
 100 +#define DB120_GPIO_LED_WLAN_2G         13
 101 +#define DB120_GPIO_LED_STATUS          14
 102 +#define DB120_GPIO_LED_WPS             15
 103 +
 104 +#define DB120_GPIO_BTN_WPS             16
 105 +
 106 +#define DB120_KEYS_POLL_INTERVAL       20      /* msecs */
 107 +#define DB120_KEYS_DEBOUNCE_INTERVAL   (3 * DB120_KEYS_POLL_INTERVAL)
 108 +
 109 +#define DB120_WMAC_CALDATA_OFFSET 0x1000
 110 +#define DB120_PCIE_CALDATA_OFFSET 0x5000
 111 +
 112 +static struct gpio_led db120_leds_gpio[] __initdata = {
 113 +       {
 114 +               .name           = "db120:green:status",
 115 +               .gpio           = DB120_GPIO_LED_STATUS,
 116 +               .active_low     = 1,
 117 +       },
 118 +       {
 119 +               .name           = "db120:green:wps",
 120 +               .gpio           = DB120_GPIO_LED_WPS,
 121 +               .active_low     = 1,
 122 +       },
 123 +       {
 124 +               .name           = "db120:green:wlan-5g",
 125 +               .gpio           = DB120_GPIO_LED_WLAN_5G,
 126 +               .active_low     = 1,
 127 +       },
 128 +       {
 129 +               .name           = "db120:green:wlan-2g",
 130 +               .gpio           = DB120_GPIO_LED_WLAN_2G,
 131 +               .active_low     = 1,
 132 +       },
 133 +};
 134 +
 135 +static struct gpio_keys_button db120_gpio_keys[] __initdata = {
 136 +       {
 137 +               .desc           = "WPS button",
 138 +               .type           = EV_KEY,
 139 +               .code           = KEY_WPS_BUTTON,
 140 +               .debounce_interval = DB120_KEYS_DEBOUNCE_INTERVAL,
 141 +               .gpio           = DB120_GPIO_BTN_WPS,
 142 +               .active_low     = 1,
 143 +       },
 144 +};
 145 +
 146 +static struct spi_board_info db120_spi_info[] = {
 147 +       {
 148 +               .bus_num        = 0,
 149 +               .chip_select    = 0,
 150 +               .max_speed_hz   = 25000000,
 151 +               .modalias       = "s25sl064a",
 152 +       }
 153 +};
 154 +
 155 +static struct ath79_spi_platform_data db120_spi_data = {
 156 +       .bus_num        = 0,
 157 +       .num_chipselect = 1,
 158 +};
 159 +
 160 +#ifdef CONFIG_PCI
 161 +static struct ath9k_platform_data db120_ath9k_data;
 162 +
 163 +static int db120_pci_plat_dev_init(struct pci_dev *dev)
 164 +{
 165 +       switch (PCI_SLOT(dev->devfn)) {
 166 +       case 0:
 167 +               dev->dev.platform_data = &db120_ath9k_data;
 168 +               break;
 169 +       }
 170 +
 171 +       return 0;
 172 +}
 173 +
 174 +static void __init db120_pci_init(u8 *eeprom)
 175 +{
 176 +       memcpy(db120_ath9k_data.eeprom_data, eeprom,
 177 +              sizeof(db120_ath9k_data.eeprom_data));
 178 +
 179 +       ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
 180 +       ath79_register_pci();
 181 +}
 182 +#else
 183 +static inline void db120_pci_init(void) {}
 184 +#endif /* CONFIG_PCI */
 185 +
 186 +static void __init db120_setup(void)
 187 +{
 188 +       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 189 +
 190 +       ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
 191 +                                db120_leds_gpio);
 192 +       ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
 193 +                                       ARRAY_SIZE(db120_gpio_keys),
 194 +                                       db120_gpio_keys);
 195 +       ath79_register_spi(&db120_spi_data, db120_spi_info,
 196 +                          ARRAY_SIZE(db120_spi_info));
 197 +       ath79_register_usb();
 198 +       ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET);
 199 +       db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
 200 +}
 201 +
 202 +MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
 203 +            db120_setup);
 204 --- a/arch/mips/ath79/machtypes.h
 205 +++ b/arch/mips/ath79/machtypes.h
 206 @@ -18,6 +18,7 @@ enum ath79_mach_type {
 207         ATH79_MACH_GENERIC = 0,
 208         ATH79_MACH_AP121,               /* Atheros AP121 reference board */
 209         ATH79_MACH_AP81,                /* Atheros AP81 reference board */
 210 +       ATH79_MACH_DB120,               /* Atheros DB120 reference board */
 211         ATH79_MACH_PB44,                /* Atheros PB44 reference board */
 212         ATH79_MACH_UBNT_XM,             /* Ubiquiti Networks XM board rev 1.0 */
 213  };