target/linux/ramips/files/arch/mips/ralink/rt3883/rt3883.c

   1 /*
   2  * Ralink RT3662/RT3883 SoC specific setup
   3  *
   4  * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * Parts of this file are based on Ralink's 2.6.21 BSP
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published
  10  * by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16
  17 #include <asm/mach-ralink/common.h>
  18 #include <asm/mach-ralink/ramips_gpio.h>
  19 #include <asm/mach-ralink/rt3883.h>
  20 #include <asm/mach-ralink/rt3883_regs.h>
  21
  22 void __iomem * rt3883_sysc_base;
  23 void __iomem * rt3883_memc_base;
  24
  25 void __init ramips_soc_prom_init(void)
  26 {
  27         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
  28         u32 n0;
  29         u32 n1;
  30         u32 id;
  31
  32         n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
  33         n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
  34         id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
  35
  36         snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
  37                 "Ralink %c%c%c%c%c%c%c%c ver:%u eco:%u",
  38                 (char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
  39                 (char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
  40                 (char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
  41                 (char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
  42                 (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
  43                 (id & RT3883_REVID_ECO_ID_MASK));
  44
  45         ramips_mem_base = RT3883_SDRAM_BASE;
  46         ramips_mem_size_min = RT3883_MEM_SIZE_MIN;
  47         ramips_mem_size_max = RT3883_MEM_SIZE_MAX;
  48 }
  49
  50 static struct ramips_gpio_chip rt3883_gpio_chips[] = {
  51         {
  52                 .chip = {
  53                         .label                  = "RT3883-GPIO0",
  54                         .base                   = 0,
  55                         .ngpio                  = 24,
  56                 },
  57                 .regs = {
  58                         [RAMIPS_GPIO_REG_INT]   = 0x00,
  59                         [RAMIPS_GPIO_REG_EDGE]  = 0x04,
  60                         [RAMIPS_GPIO_REG_RENA]  = 0x08,
  61                         [RAMIPS_GPIO_REG_FENA]  = 0x0c,
  62                         [RAMIPS_GPIO_REG_DATA]  = 0x20,
  63                         [RAMIPS_GPIO_REG_DIR]   = 0x24,
  64                         [RAMIPS_GPIO_REG_POL]   = 0x28,
  65                         [RAMIPS_GPIO_REG_SET]   = 0x2c,
  66                         [RAMIPS_GPIO_REG_RESET] = 0x30,
  67                         [RAMIPS_GPIO_REG_TOGGLE] = 0x34,
  68                 },
  69                 .map_base       = RT3883_PIO_BASE,
  70                 .map_size       = RT3883_PIO_SIZE,
  71         },
  72         {
  73                 .chip = {
  74                         .label                  = "RT3883-GPIO1",
  75                         .base                   = 24,
  76                         .ngpio                  = 16,
  77                 },
  78                 .regs = {
  79                         [RAMIPS_GPIO_REG_INT]   = 0x38,
  80                         [RAMIPS_GPIO_REG_EDGE]  = 0x3c,
  81                         [RAMIPS_GPIO_REG_RENA]  = 0x40,
  82                         [RAMIPS_GPIO_REG_FENA]  = 0x44,
  83                         [RAMIPS_GPIO_REG_DATA]  = 0x48,
  84                         [RAMIPS_GPIO_REG_DIR]   = 0x4c,
  85                         [RAMIPS_GPIO_REG_POL]   = 0x50,
  86                         [RAMIPS_GPIO_REG_SET]   = 0x54,
  87                         [RAMIPS_GPIO_REG_RESET] = 0x58,
  88                         [RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
  89                 },
  90                 .map_base       = RT3883_PIO_BASE,
  91                 .map_size       = RT3883_PIO_SIZE,
  92         },
  93         {
  94                 .chip = {
  95                         .label                  = "RT3883-GPIO2",
  96                         .base                   = 40,
  97                         .ngpio                  = 32,
  98                 },
  99                 .regs = {
 100                         [RAMIPS_GPIO_REG_INT]   = 0x60,
 101                         [RAMIPS_GPIO_REG_EDGE]  = 0x64,
 102                         [RAMIPS_GPIO_REG_RENA]  = 0x68,
 103                         [RAMIPS_GPIO_REG_FENA]  = 0x6c,
 104                         [RAMIPS_GPIO_REG_DATA]  = 0x70,
 105                         [RAMIPS_GPIO_REG_DIR]   = 0x74,
 106                         [RAMIPS_GPIO_REG_POL]   = 0x78,
 107                         [RAMIPS_GPIO_REG_SET]   = 0x7c,
 108                         [RAMIPS_GPIO_REG_RESET] = 0x80,
 109                         [RAMIPS_GPIO_REG_TOGGLE] = 0x84,
 110                 },
 111                 .map_base       = RT3883_PIO_BASE,
 112                 .map_size       = RT3883_PIO_SIZE,
 113         },
 114         {
 115                 .chip = {
 116                         .label                  = "RT3883-GPIO3",
 117                         .base                   = 72,
 118                         .ngpio                  = 24,
 119                 },
 120                 .regs = {
 121                         [RAMIPS_GPIO_REG_INT]   = 0x88,
 122                         [RAMIPS_GPIO_REG_EDGE]  = 0x8c,
 123                         [RAMIPS_GPIO_REG_RENA]  = 0x90,
 124                         [RAMIPS_GPIO_REG_FENA]  = 0x94,
 125                         [RAMIPS_GPIO_REG_DATA]  = 0x98,
 126                         [RAMIPS_GPIO_REG_DIR]   = 0x9c,
 127                         [RAMIPS_GPIO_REG_POL]   = 0xa0,
 128                         [RAMIPS_GPIO_REG_SET]   = 0xa4,
 129                         [RAMIPS_GPIO_REG_RESET] = 0xa8,
 130                         [RAMIPS_GPIO_REG_TOGGLE] = 0xac,
 131                 },
 132                 .map_base       = RT3883_PIO_BASE,
 133                 .map_size       = RT3883_PIO_SIZE,
 134         },
 135 };
 136
 137 static struct ramips_gpio_data rt3883_gpio_data = {
 138         .chips = rt3883_gpio_chips,
 139         .num_chips = ARRAY_SIZE(rt3883_gpio_chips),
 140 };
 141
 142 static void rt3883_gpio_reserve(int first, int last)
 143 {
 144         for (; first <= last; first++)
 145                 gpio_request(first, "reserved");
 146 }
 147
 148 void __init rt3883_gpio_init(u32 mode)
 149 {
 150         u32 t;
 151
 152         rt3883_sysc_wr(mode, RT3883_SYSC_REG_GPIO_MODE);
 153
 154         ramips_gpio_init(&rt3883_gpio_data);
 155         if ((mode & RT3883_GPIO_MODE_I2C) == 0)
 156                 rt3883_gpio_reserve(RT3883_GPIO_I2C_SD, RT3883_GPIO_I2C_SCLK);
 157
 158         if ((mode & RT3883_GPIO_MODE_SPI) == 0)
 159                 rt3883_gpio_reserve(RT3883_GPIO_SPI_CS0, RT3883_GPIO_SPI_CLK);
 160
 161         t = mode >> RT3883_GPIO_MODE_UART0_SHIFT;
 162         t &= RT3883_GPIO_MODE_UART0_MASK;
 163         switch (t) {
 164         case RT3883_GPIO_MODE_UARTF:
 165         case RT3883_GPIO_MODE_PCM_UARTF:
 166         case RT3883_GPIO_MODE_PCM_I2S:
 167         case RT3883_GPIO_MODE_I2S_UARTF:
 168                 rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_14);
 169                 break;
 170         case RT3883_GPIO_MODE_PCM_GPIO:
 171                 rt3883_gpio_reserve(RT3883_GPIO_11, RT3883_GPIO_14);
 172                 break;
 173         case RT3883_GPIO_MODE_GPIO_UARTF:
 174         case RT3883_GPIO_MODE_GPIO_I2S:
 175                 rt3883_gpio_reserve(RT3883_GPIO_7, RT3883_GPIO_10);
 176                 break;
 177         }
 178
 179         if ((mode & RT3883_GPIO_MODE_UART1) == 0)
 180                 rt3883_gpio_reserve(RT3883_GPIO_UART1_TXD,
 181                                     RT3883_GPIO_UART1_RXD);
 182
 183         if ((mode & RT3883_GPIO_MODE_JTAG) == 0)
 184                 rt3883_gpio_reserve(RT3883_GPIO_JTAG_TDO,
 185                                     RT3883_GPIO_JTAG_TCLK);
 186
 187         if ((mode & RT3883_GPIO_MODE_MDIO) == 0)
 188                 rt3883_gpio_reserve(RT3883_GPIO_MDIO_MDC,
 189                                     RT3883_GPIO_MDIO_MDIO);
 190
 191         if ((mode & RT3883_GPIO_MODE_GE1) == 0)
 192                 rt3883_gpio_reserve(RT3883_GPIO_GE1_TXD0,
 193                                     RT3883_GPIO_GE1_RXCLK);
 194
 195         if ((mode & RT3883_GPIO_MODE_GE2) == 0)
 196                 rt3883_gpio_reserve(RT3883_GPIO_GE2_TXD0,
 197                                     RT3883_GPIO_GE2_RXCLK);
 198
 199         t = mode >> RT3883_GPIO_MODE_PCI_SHIFT;
 200         t &= RT3883_GPIO_MODE_PCI_MASK;
 201         if (t != RT3883_GPIO_MODE_PCI_GPIO)
 202                 rt3883_gpio_reserve(RT3883_GPIO_PCI_AD0,
 203                                     RT3883_GPIO_PCI_AD31);
 204
 205         t = mode >> RT3883_GPIO_MODE_LNA_A_SHIFT;
 206         t &= RT3883_GPIO_MODE_LNA_A_MASK;
 207         if (t != RT3883_GPIO_MODE_LNA_A_GPIO)
 208                 rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_A0,
 209                                     RT3883_GPIO_LNA_PE_A2);
 210
 211         t = mode >> RT3883_GPIO_MODE_LNA_G_SHIFT;
 212         t &= RT3883_GPIO_MODE_LNA_G_MASK;
 213         if (t != RT3883_GPIO_MODE_LNA_G_GPIO)
 214                 rt3883_gpio_reserve(RT3883_GPIO_LNA_PE_G0,
 215                                     RT3883_GPIO_LNA_PE_G2);
 216 }