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broadcom-diag: add support for some new devices
[openwrt.git] / target / linux / generic / patches-2.6.39 / 020-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -3,7 +3,7 @@
4 * Broadcom ChipCommon core driver
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
13 if (!ccdev)
14 return;
15 bus = ccdev->bus;
16 +
17 + /* We support SLOW only on 6..9 */
18 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
19 + mode = SSB_CLKMODE_DYNAMIC;
20 +
21 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
22 + return; /* PMU controls clockmode, separated function needed */
23 + SSB_WARN_ON(ccdev->id.revision >= 20);
24 +
25 /* chipcommon cores prior to rev6 don't support dynamic clock control */
26 if (ccdev->id.revision < 6)
27 return;
28 - /* chipcommon cores rev10 are a whole new ball game */
29 +
30 + /* ChipCommon cores rev10+ need testing */
31 if (ccdev->id.revision >= 10)
32 return;
33 +
34 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
35 return;
36
37 switch (mode) {
38 - case SSB_CLKMODE_SLOW:
39 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
40 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
41 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
42 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
43 break;
44 case SSB_CLKMODE_FAST:
45 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
46 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
47 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
48 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
49 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
50 + if (ccdev->id.revision < 10) {
51 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
52 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
53 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
54 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
55 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
56 + } else {
57 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
58 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
59 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
60 + /* udelay(150); TODO: not available in early init */
61 + }
62 break;
63 case SSB_CLKMODE_DYNAMIC:
64 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
65 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
66 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
67 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
68 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
69 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
70 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
71 -
72 - /* for dynamic control, we have to release our xtal_pu "force on" */
73 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
74 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
75 + if (ccdev->id.revision < 10) {
76 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
77 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
78 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
79 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
80 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
81 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
82 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
83 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
84 +
85 + /* For dynamic control, we have to release our xtal_pu
86 + * "force on" */
87 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
88 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
89 + } else {
90 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
91 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
92 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
93 + }
94 break;
95 default:
96 SSB_WARN_ON(1);
97 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
98 if (cc->dev->id.revision >= 11)
99 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
100 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
101 +
102 + if (cc->dev->id.revision >= 20) {
103 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
104 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
105 + }
106 +
107 ssb_pmu_init(cc);
108 chipco_powercontrol_init(cc);
109 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
110 --- a/drivers/ssb/driver_chipcommon_pmu.c
111 +++ b/drivers/ssb/driver_chipcommon_pmu.c
112 @@ -2,7 +2,7 @@
113 * Sonics Silicon Backplane
114 * Broadcom ChipCommon Power Management Unit driver
115 *
116 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
117 + * Copyright 2009, Michael Buesch <m@bues.ch>
118 * Copyright 2007, Broadcom Corporation
119 *
120 * Licensed under the GNU/GPL. See COPYING for details.
121 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
122 u32 min_msk = 0, max_msk = 0;
123 unsigned int i;
124 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
125 - unsigned int updown_tab_size;
126 + unsigned int updown_tab_size = 0;
127 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
128 - unsigned int depend_tab_size;
129 + unsigned int depend_tab_size = 0;
130
131 switch (bus->chip_id) {
132 case 0x4312:
133 + min_msk = 0xCBB;
134 + break;
135 case 0x4322:
136 /* We keep the default settings:
137 * min_msk = 0xCBB
138 --- a/drivers/ssb/driver_gige.c
139 +++ b/drivers/ssb/driver_gige.c
140 @@ -3,7 +3,7 @@
141 * Broadcom Gigabit Ethernet core driver
142 *
143 * Copyright 2008, Broadcom Corporation
144 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
145 + * Copyright 2008, Michael Buesch <m@bues.ch>
146 *
147 * Licensed under the GNU/GPL. See COPYING for details.
148 */
149 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
150 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
151 }
152
153 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
154 - int reg, int size, u32 *val)
155 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
156 + unsigned int devfn, int reg,
157 + int size, u32 *val)
158 {
159 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
160 unsigned long flags;
161 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
162 return PCIBIOS_SUCCESSFUL;
163 }
164
165 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
166 - int reg, int size, u32 val)
167 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
168 + unsigned int devfn, int reg,
169 + int size, u32 val)
170 {
171 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
172 unsigned long flags;
173 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
174 return PCIBIOS_SUCCESSFUL;
175 }
176
177 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
178 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
179 + const struct ssb_device_id *id)
180 {
181 struct ssb_gige *dev;
182 u32 base, tmslow, tmshigh;
183 --- a/drivers/ssb/driver_pcicore.c
184 +++ b/drivers/ssb/driver_pcicore.c
185 @@ -3,7 +3,7 @@
186 * Broadcom PCI-core driver
187 *
188 * Copyright 2005, Broadcom Corporation
189 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
190 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
191 *
192 * Licensed under the GNU/GPL. See COPYING for details.
193 */
194 @@ -15,6 +15,11 @@
195
196 #include "ssb_private.h"
197
198 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
199 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
200 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
201 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
202 + u8 address, u16 data);
203
204 static inline
205 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
206 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
207 return ssb_mips_irq(extpci_core->dev) + 2;
208 }
209
210 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
211 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
212 {
213 u32 val;
214
215 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
216 register_pci_controller(&ssb_pcicore_controller);
217 }
218
219 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
220 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
221 {
222 struct ssb_bus *bus = pc->dev->bus;
223 u16 chipid_top;
224 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
225 }
226 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
227
228 +/**************************************************
229 + * Workarounds.
230 + **************************************************/
231 +
232 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
233 +{
234 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
235 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
236 + tmp &= ~0xF000;
237 + tmp |= (pc->dev->core_index << 12);
238 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
239 + }
240 +}
241 +
242 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
243 +{
244 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
245 +}
246 +
247 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
248 +{
249 + const u8 serdes_pll_device = 0x1D;
250 + const u8 serdes_rx_device = 0x1F;
251 + u16 tmp;
252 +
253 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
254 + ssb_pcicore_polarity_workaround(pc));
255 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
256 + if (tmp & 0x4000)
257 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
258 +}
259 +
260 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
261 +{
262 + struct ssb_device *pdev = pc->dev;
263 + struct ssb_bus *bus = pdev->bus;
264 + u32 tmp;
265 +
266 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
267 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
268 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
269 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
270 +
271 + if (pdev->id.revision < 5) {
272 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
273 + tmp &= ~SSB_IMCFGLO_SERTO;
274 + tmp |= 2;
275 + tmp &= ~SSB_IMCFGLO_REQTO;
276 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
277 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
278 + ssb_commit_settings(bus);
279 + } else if (pdev->id.revision >= 11) {
280 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
281 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
282 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
283 + }
284 +}
285 +
286 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
287 +{
288 + u32 tmp;
289 + u8 rev = pc->dev->id.revision;
290 +
291 + if (rev == 0 || rev == 1) {
292 + /* TLP Workaround register. */
293 + tmp = ssb_pcie_read(pc, 0x4);
294 + tmp |= 0x8;
295 + ssb_pcie_write(pc, 0x4, tmp);
296 + }
297 + if (rev == 1) {
298 + /* DLLP Link Control register. */
299 + tmp = ssb_pcie_read(pc, 0x100);
300 + tmp |= 0x40;
301 + ssb_pcie_write(pc, 0x100, tmp);
302 + }
303 +
304 + if (rev == 0) {
305 + const u8 serdes_rx_device = 0x1F;
306 +
307 + ssb_pcie_mdio_write(pc, serdes_rx_device,
308 + 2 /* Timer */, 0x8128);
309 + ssb_pcie_mdio_write(pc, serdes_rx_device,
310 + 6 /* CDR */, 0x0100);
311 + ssb_pcie_mdio_write(pc, serdes_rx_device,
312 + 7 /* CDR BW */, 0x1466);
313 + } else if (rev == 3 || rev == 4 || rev == 5) {
314 + /* TODO: DLLP Power Management Threshold */
315 + ssb_pcicore_serdes_workaround(pc);
316 + /* TODO: ASPM */
317 + } else if (rev == 7) {
318 + /* TODO: No PLL down */
319 + }
320 +
321 + if (rev >= 6) {
322 + /* Miscellaneous Configuration Fixup */
323 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
324 + if (!(tmp & 0x8000))
325 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
326 + tmp | 0x8000);
327 + }
328 +}
329
330 /**************************************************
331 * Generic and Clientmode operation code.
332 **************************************************/
333
334 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
335 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
336 {
337 + struct ssb_device *pdev = pc->dev;
338 + struct ssb_bus *bus = pdev->bus;
339 +
340 + if (bus->bustype == SSB_BUSTYPE_PCI)
341 + ssb_pcicore_fix_sprom_core_index(pc);
342 +
343 /* Disable PCI interrupts. */
344 - ssb_write32(pc->dev, SSB_INTVEC, 0);
345 + ssb_write32(pdev, SSB_INTVEC, 0);
346 +
347 + /* Additional PCIe always once-executed workarounds */
348 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
349 + ssb_pcicore_serdes_workaround(pc);
350 + /* TODO: ASPM */
351 + /* TODO: Clock Request Update */
352 + }
353 }
354
355 -void ssb_pcicore_init(struct ssb_pcicore *pc)
356 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
357 {
358 struct ssb_device *dev = pc->dev;
359 - struct ssb_bus *bus;
360
361 if (!dev)
362 return;
363 - bus = dev->bus;
364 if (!ssb_device_is_enabled(dev))
365 ssb_device_enable(dev, 0);
366
367 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
368 pcicore_write32(pc, 0x134, data);
369 }
370
371 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
372 - u8 address, u16 data)
373 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
374 +{
375 + const u16 mdio_control = 0x128;
376 + const u16 mdio_data = 0x12C;
377 + u32 v;
378 + int i;
379 +
380 + v = (1 << 30); /* Start of Transaction */
381 + v |= (1 << 28); /* Write Transaction */
382 + v |= (1 << 17); /* Turnaround */
383 + v |= (0x1F << 18);
384 + v |= (phy << 4);
385 + pcicore_write32(pc, mdio_data, v);
386 +
387 + udelay(10);
388 + for (i = 0; i < 200; i++) {
389 + v = pcicore_read32(pc, mdio_control);
390 + if (v & 0x100 /* Trans complete */)
391 + break;
392 + msleep(1);
393 + }
394 +}
395 +
396 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
397 {
398 const u16 mdio_control = 0x128;
399 const u16 mdio_data = 0x12C;
400 + int max_retries = 10;
401 + u16 ret = 0;
402 u32 v;
403 int i;
404
405 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
406 v |= 0x2; /* MDIO Clock Divisor */
407 pcicore_write32(pc, mdio_control, v);
408
409 + if (pc->dev->id.revision >= 10) {
410 + max_retries = 200;
411 + ssb_pcie_mdio_set_phy(pc, device);
412 + }
413 +
414 v = (1 << 30); /* Start of Transaction */
415 - v |= (1 << 28); /* Write Transaction */
416 + v |= (1 << 29); /* Read Transaction */
417 v |= (1 << 17); /* Turnaround */
418 - v |= (u32)device << 22;
419 + if (pc->dev->id.revision < 10)
420 + v |= (u32)device << 22;
421 v |= (u32)address << 18;
422 - v |= data;
423 pcicore_write32(pc, mdio_data, v);
424 /* Wait for the device to complete the transaction */
425 udelay(10);
426 - for (i = 0; i < 10; i++) {
427 + for (i = 0; i < max_retries; i++) {
428 v = pcicore_read32(pc, mdio_control);
429 - if (v & 0x100 /* Trans complete */)
430 + if (v & 0x100 /* Trans complete */) {
431 + udelay(10);
432 + ret = pcicore_read32(pc, mdio_data);
433 break;
434 + }
435 msleep(1);
436 }
437 pcicore_write32(pc, mdio_control, 0);
438 + return ret;
439 }
440
441 -static void ssb_broadcast_value(struct ssb_device *dev,
442 - u32 address, u32 data)
443 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
444 + u8 address, u16 data)
445 {
446 - /* This is used for both, PCI and ChipCommon core, so be careful. */
447 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
448 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
449 + const u16 mdio_control = 0x128;
450 + const u16 mdio_data = 0x12C;
451 + int max_retries = 10;
452 + u32 v;
453 + int i;
454
455 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
456 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
457 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
458 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
459 -}
460 + v = 0x80; /* Enable Preamble Sequence */
461 + v |= 0x2; /* MDIO Clock Divisor */
462 + pcicore_write32(pc, mdio_control, v);
463
464 -static void ssb_commit_settings(struct ssb_bus *bus)
465 -{
466 - struct ssb_device *dev;
467 + if (pc->dev->id.revision >= 10) {
468 + max_retries = 200;
469 + ssb_pcie_mdio_set_phy(pc, device);
470 + }
471
472 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
473 - if (WARN_ON(!dev))
474 - return;
475 - /* This forces an update of the cached registers. */
476 - ssb_broadcast_value(dev, 0xFD8, 0);
477 + v = (1 << 30); /* Start of Transaction */
478 + v |= (1 << 28); /* Write Transaction */
479 + v |= (1 << 17); /* Turnaround */
480 + if (pc->dev->id.revision < 10)
481 + v |= (u32)device << 22;
482 + v |= (u32)address << 18;
483 + v |= data;
484 + pcicore_write32(pc, mdio_data, v);
485 + /* Wait for the device to complete the transaction */
486 + udelay(10);
487 + for (i = 0; i < max_retries; i++) {
488 + v = pcicore_read32(pc, mdio_control);
489 + if (v & 0x100 /* Trans complete */)
490 + break;
491 + msleep(1);
492 + }
493 + pcicore_write32(pc, mdio_control, 0);
494 }
495
496 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
497 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
498 if (pc->setup_done)
499 goto out;
500 if (pdev->id.coreid == SSB_DEV_PCI) {
501 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
502 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
503 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
504 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
505 -
506 - if (pdev->id.revision < 5) {
507 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
508 - tmp &= ~SSB_IMCFGLO_SERTO;
509 - tmp |= 2;
510 - tmp &= ~SSB_IMCFGLO_REQTO;
511 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
512 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
513 - ssb_commit_settings(bus);
514 - } else if (pdev->id.revision >= 11) {
515 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
516 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
517 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
518 - }
519 + ssb_pcicore_pci_setup_workarounds(pc);
520 } else {
521 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
522 - //TODO: Better make defines for all these magic PCIE values.
523 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
524 - /* TLP Workaround register. */
525 - tmp = ssb_pcie_read(pc, 0x4);
526 - tmp |= 0x8;
527 - ssb_pcie_write(pc, 0x4, tmp);
528 - }
529 - if (pdev->id.revision == 0) {
530 - const u8 serdes_rx_device = 0x1F;
531 -
532 - ssb_pcie_mdio_write(pc, serdes_rx_device,
533 - 2 /* Timer */, 0x8128);
534 - ssb_pcie_mdio_write(pc, serdes_rx_device,
535 - 6 /* CDR */, 0x0100);
536 - ssb_pcie_mdio_write(pc, serdes_rx_device,
537 - 7 /* CDR BW */, 0x1466);
538 - } else if (pdev->id.revision == 1) {
539 - /* DLLP Link Control register. */
540 - tmp = ssb_pcie_read(pc, 0x100);
541 - tmp |= 0x40;
542 - ssb_pcie_write(pc, 0x100, tmp);
543 - }
544 + ssb_pcicore_pcie_setup_workarounds(pc);
545 }
546 pc->setup_done = 1;
547 out:
548 --- a/drivers/ssb/main.c
549 +++ b/drivers/ssb/main.c
550 @@ -3,7 +3,7 @@
551 * Subsystem core
552 *
553 * Copyright 2005, Broadcom Corporation
554 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
555 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
556 *
557 * Licensed under the GNU/GPL. See COPYING for details.
558 */
559 @@ -12,6 +12,7 @@
560
561 #include <linux/delay.h>
562 #include <linux/io.h>
563 +#include <linux/module.h>
564 #include <linux/ssb/ssb.h>
565 #include <linux/ssb/ssb_regs.h>
566 #include <linux/ssb/ssb_driver_gige.h>
567 @@ -557,7 +558,7 @@ error:
568 }
569
570 /* Needs ssb_buses_lock() */
571 -static int ssb_attach_queued_buses(void)
572 +static int __devinit ssb_attach_queued_buses(void)
573 {
574 struct ssb_bus *bus, *n;
575 int err = 0;
576 @@ -768,9 +769,9 @@ out:
577 return err;
578 }
579
580 -static int ssb_bus_register(struct ssb_bus *bus,
581 - ssb_invariants_func_t get_invariants,
582 - unsigned long baseaddr)
583 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
584 + ssb_invariants_func_t get_invariants,
585 + unsigned long baseaddr)
586 {
587 int err;
588
589 @@ -851,8 +852,8 @@ err_disable_xtal:
590 }
591
592 #ifdef CONFIG_SSB_PCIHOST
593 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
594 - struct pci_dev *host_pci)
595 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
596 + struct pci_dev *host_pci)
597 {
598 int err;
599
600 @@ -875,9 +876,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
601 #endif /* CONFIG_SSB_PCIHOST */
602
603 #ifdef CONFIG_SSB_PCMCIAHOST
604 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
605 - struct pcmcia_device *pcmcia_dev,
606 - unsigned long baseaddr)
607 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
608 + struct pcmcia_device *pcmcia_dev,
609 + unsigned long baseaddr)
610 {
611 int err;
612
613 @@ -897,8 +898,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
614 #endif /* CONFIG_SSB_PCMCIAHOST */
615
616 #ifdef CONFIG_SSB_SDIOHOST
617 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
618 - unsigned int quirks)
619 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
620 + struct sdio_func *func,
621 + unsigned int quirks)
622 {
623 int err;
624
625 @@ -918,9 +920,9 @@ int ssb_bus_sdiobus_register(struct ssb_
626 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
627 #endif /* CONFIG_SSB_PCMCIAHOST */
628
629 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
630 - unsigned long baseaddr,
631 - ssb_invariants_func_t get_invariants)
632 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
633 + unsigned long baseaddr,
634 + ssb_invariants_func_t get_invariants)
635 {
636 int err;
637
638 @@ -1001,8 +1003,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
639 switch (plltype) {
640 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
641 if (m & SSB_CHIPCO_CLK_T6_MMASK)
642 - return SSB_CHIPCO_CLK_T6_M0;
643 - return SSB_CHIPCO_CLK_T6_M1;
644 + return SSB_CHIPCO_CLK_T6_M1;
645 + return SSB_CHIPCO_CLK_T6_M0;
646 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
647 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
648 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
649 @@ -1117,23 +1119,22 @@ static u32 ssb_tmslow_reject_bitmask(str
650 {
651 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
652
653 - /* The REJECT bit changed position in TMSLOW between
654 - * Backplane revisions. */
655 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
656 switch (rev) {
657 case SSB_IDLOW_SSBREV_22:
658 - return SSB_TMSLOW_REJECT_22;
659 + case SSB_IDLOW_SSBREV_24:
660 + case SSB_IDLOW_SSBREV_26:
661 + return SSB_TMSLOW_REJECT;
662 case SSB_IDLOW_SSBREV_23:
663 return SSB_TMSLOW_REJECT_23;
664 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
665 - case SSB_IDLOW_SSBREV_25: /* same here */
666 - case SSB_IDLOW_SSBREV_26: /* same here */
667 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
668 case SSB_IDLOW_SSBREV_27: /* same here */
669 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
670 + return SSB_TMSLOW_REJECT; /* this is a guess */
671 default:
672 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
673 WARN_ON(1);
674 }
675 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
676 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
677 }
678
679 int ssb_device_is_enabled(struct ssb_device *dev)
680 @@ -1260,13 +1261,34 @@ void ssb_device_disable(struct ssb_devic
681 }
682 EXPORT_SYMBOL(ssb_device_disable);
683
684 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
685 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
686 +{
687 + u16 chip_id = dev->bus->chip_id;
688 +
689 + if (dev->id.coreid == SSB_DEV_80211) {
690 + return (chip_id == 0x4322 || chip_id == 43221 ||
691 + chip_id == 43231 || chip_id == 43222);
692 + }
693 +
694 + return 0;
695 +}
696 +
697 u32 ssb_dma_translation(struct ssb_device *dev)
698 {
699 switch (dev->bus->bustype) {
700 case SSB_BUSTYPE_SSB:
701 return 0;
702 case SSB_BUSTYPE_PCI:
703 - return SSB_PCI_DMA;
704 + if (pci_is_pcie(dev->bus->host_pci) &&
705 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
706 + return SSB_PCIE_DMA_H32;
707 + } else {
708 + if (ssb_dma_translation_special_bit(dev))
709 + return SSB_PCIE_DMA_H32;
710 + else
711 + return SSB_PCI_DMA;
712 + }
713 default:
714 __ssb_dma_not_implemented(dev);
715 }
716 @@ -1309,20 +1331,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
717
718 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
719 {
720 - struct ssb_chipcommon *cc;
721 int err;
722 enum ssb_clkmode mode;
723
724 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
725 if (err)
726 goto error;
727 - cc = &bus->chipco;
728 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
729 - ssb_chipco_set_clockmode(cc, mode);
730
731 #ifdef CONFIG_SSB_DEBUG
732 bus->powered_up = 1;
733 #endif
734 +
735 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
736 + ssb_chipco_set_clockmode(&bus->chipco, mode);
737 +
738 return 0;
739 error:
740 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
741 @@ -1330,6 +1352,37 @@ error:
742 }
743 EXPORT_SYMBOL(ssb_bus_powerup);
744
745 +static void ssb_broadcast_value(struct ssb_device *dev,
746 + u32 address, u32 data)
747 +{
748 +#ifdef CONFIG_SSB_DRIVER_PCICORE
749 + /* This is used for both, PCI and ChipCommon core, so be careful. */
750 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
751 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
752 +#endif
753 +
754 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
755 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
756 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
757 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
758 +}
759 +
760 +void ssb_commit_settings(struct ssb_bus *bus)
761 +{
762 + struct ssb_device *dev;
763 +
764 +#ifdef CONFIG_SSB_DRIVER_PCICORE
765 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
766 +#else
767 + dev = bus->chipco.dev;
768 +#endif
769 + if (WARN_ON(!dev))
770 + return;
771 + /* This forces an update of the cached registers. */
772 + ssb_broadcast_value(dev, 0xFD8, 0);
773 +}
774 +EXPORT_SYMBOL(ssb_commit_settings);
775 +
776 u32 ssb_admatch_base(u32 adm)
777 {
778 u32 base = 0;
779 --- a/drivers/ssb/pci.c
780 +++ b/drivers/ssb/pci.c
781 @@ -1,7 +1,7 @@
782 /*
783 * Sonics Silicon Backplane PCI-Hostbus related functions.
784 *
785 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
786 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
787 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
788 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
789 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
790 @@ -607,6 +607,29 @@ static void sprom_extract_r8(struct ssb_
791 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
792 sizeof(out->antenna_gain.ghz5));
793
794 + /* Extract FEM info */
795 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
796 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
797 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
798 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
799 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
800 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
801 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
802 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
803 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
804 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
805 +
806 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
807 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
808 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
809 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
810 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
811 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
812 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
813 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
814 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
815 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
816 +
817 sprom_extract_r458(out, in);
818
819 /* TODO - get remaining rev 8 stuff needed */
820 @@ -662,7 +685,6 @@ static int sprom_extract(struct ssb_bus
821 static int ssb_pci_sprom_get(struct ssb_bus *bus,
822 struct ssb_sprom *sprom)
823 {
824 - const struct ssb_sprom *fallback;
825 int err;
826 u16 *buf;
827
828 @@ -707,10 +729,17 @@ static int ssb_pci_sprom_get(struct ssb_
829 if (err) {
830 /* All CRC attempts failed.
831 * Maybe there is no SPROM on the device?
832 - * If we have a fallback, use that. */
833 - fallback = ssb_get_fallback_sprom();
834 - if (fallback) {
835 - memcpy(sprom, fallback, sizeof(*sprom));
836 + * Now we ask the arch code if there is some sprom
837 + * available for this device in some other storage */
838 + err = ssb_fill_sprom_with_fallback(bus, sprom);
839 + if (err) {
840 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
841 + " fallback SPROM failed (err %d)\n",
842 + err);
843 + } else {
844 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
845 + " revision %d provided by"
846 + " platform.\n", sprom->revision);
847 err = 0;
848 goto out_free;
849 }
850 @@ -728,12 +757,9 @@ out_free:
851 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
852 struct ssb_boardinfo *bi)
853 {
854 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
855 - &bi->vendor);
856 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
857 - &bi->type);
858 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
859 - &bi->rev);
860 + bi->vendor = bus->host_pci->subsystem_vendor;
861 + bi->type = bus->host_pci->subsystem_device;
862 + bi->rev = bus->host_pci->revision;
863 }
864
865 int ssb_pci_get_invariants(struct ssb_bus *bus,
866 --- a/drivers/ssb/pcihost_wrapper.c
867 +++ b/drivers/ssb/pcihost_wrapper.c
868 @@ -6,7 +6,7 @@
869 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
870 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
871 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
872 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
873 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
874 *
875 * Licensed under the GNU/GPL. See COPYING for details.
876 */
877 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
878 # define ssb_pcihost_resume NULL
879 #endif /* CONFIG_PM */
880
881 -static int ssb_pcihost_probe(struct pci_dev *dev,
882 - const struct pci_device_id *id)
883 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
884 + const struct pci_device_id *id)
885 {
886 struct ssb_bus *ssb;
887 int err = -ENOMEM;
888 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
889 pci_set_drvdata(dev, NULL);
890 }
891
892 -int ssb_pcihost_register(struct pci_driver *driver)
893 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
894 {
895 driver->probe = ssb_pcihost_probe;
896 driver->remove = ssb_pcihost_remove;
897 --- a/drivers/ssb/scan.c
898 +++ b/drivers/ssb/scan.c
899 @@ -2,7 +2,7 @@
900 * Sonics Silicon Backplane
901 * Bus scanning
902 *
903 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
904 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
905 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
906 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
907 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
908 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
909 #ifdef CONFIG_SSB_PCIHOST
910 if (bus->bustype == SSB_BUSTYPE_PCI) {
911 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
912 - bus->host_pci->device == 0x4324)
913 + ((bus->host_pci->device == 0x4313) ||
914 + (bus->host_pci->device == 0x431A) ||
915 + (bus->host_pci->device == 0x4321) ||
916 + (bus->host_pci->device == 0x4324)))
917 return 1;
918 }
919 #endif /* CONFIG_SSB_PCIHOST */
920 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
921 } else {
922 if (bus->bustype == SSB_BUSTYPE_PCI) {
923 bus->chip_id = pcidev_to_chipid(bus->host_pci);
924 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
925 - &bus->chip_rev);
926 + bus->chip_rev = bus->host_pci->revision;
927 bus->chip_package = 0;
928 } else {
929 bus->chip_id = 0x4710;
930 --- a/drivers/ssb/sprom.c
931 +++ b/drivers/ssb/sprom.c
932 @@ -2,7 +2,7 @@
933 * Sonics Silicon Backplane
934 * Common SPROM support routines
935 *
936 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
937 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
938 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
939 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
940 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
941 @@ -17,7 +17,7 @@
942 #include <linux/slab.h>
943
944
945 -static const struct ssb_sprom *fallback_sprom;
946 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
947
948
949 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
950 @@ -145,36 +145,43 @@ out:
951 }
952
953 /**
954 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
955 + * ssb_arch_register_fallback_sprom - Registers a method providing a
956 + * fallback SPROM if no SPROM is found.
957 *
958 - * @sprom: The SPROM data structure to register.
959 + * @sprom_callback: The callback function.
960 *
961 - * With this function the architecture implementation may register a fallback
962 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
963 - * where no valid SPROM can be found in the shadow registers.
964 + * With this function the architecture implementation may register a
965 + * callback handler which fills the SPROM data structure. The fallback is
966 + * only used for PCI based SSB devices, where no valid SPROM can be found
967 + * in the shadow registers.
968 + *
969 + * This function is useful for weird architectures that have a half-assed
970 + * SSB device hardwired to their PCI bus.
971 + *
972 + * Note that it does only work with PCI attached SSB devices. PCMCIA
973 + * devices currently don't use this fallback.
974 + * Architectures must provide the SPROM for native SSB devices anyway, so
975 + * the fallback also isn't used for native devices.
976 *
977 - * This function is useful for weird architectures that have a half-assed SSB device
978 - * hardwired to their PCI bus.
979 - *
980 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
981 - * don't use this fallback.
982 - * Architectures must provide the SPROM for native SSB devices anyway,
983 - * so the fallback also isn't used for native devices.
984 - *
985 - * This function is available for architecture code, only. So it is not exported.
986 + * This function is available for architecture code, only. So it is not
987 + * exported.
988 */
989 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
990 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
991 + struct ssb_sprom *out))
992 {
993 - if (fallback_sprom)
994 + if (get_fallback_sprom)
995 return -EEXIST;
996 - fallback_sprom = sprom;
997 + get_fallback_sprom = sprom_callback;
998
999 return 0;
1000 }
1001
1002 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1003 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1004 {
1005 - return fallback_sprom;
1006 + if (!get_fallback_sprom)
1007 + return -ENOENT;
1008 +
1009 + return get_fallback_sprom(bus, out);
1010 }
1011
1012 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1013 --- a/drivers/ssb/ssb_private.h
1014 +++ b/drivers/ssb/ssb_private.h
1015 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1016 const char *buf, size_t count,
1017 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1018 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1019 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1020 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1021 + struct ssb_sprom *out);
1022
1023
1024 /* core.c */
1025 --- a/include/linux/ssb/ssb.h
1026 +++ b/include/linux/ssb/ssb.h
1027 @@ -25,8 +25,10 @@ struct ssb_sprom {
1028 u8 et1phyaddr; /* MII address for enet1 */
1029 u8 et0mdcport; /* MDIO for enet0 */
1030 u8 et1mdcport; /* MDIO for enet1 */
1031 - u8 board_rev; /* Board revision number from SPROM. */
1032 + u16 board_rev; /* Board revision number from SPROM. */
1033 u8 country_code; /* Country Code */
1034 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
1035 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
1036 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
1037 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
1038 u16 pa0b0;
1039 @@ -92,6 +94,15 @@ struct ssb_sprom {
1040 } ghz5; /* 5GHz band */
1041 } antenna_gain;
1042
1043 + struct {
1044 + struct {
1045 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1046 + } ghz2;
1047 + struct {
1048 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1049 + } ghz5;
1050 + } fem;
1051 +
1052 /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
1053 };
1054
1055 @@ -99,7 +110,7 @@ struct ssb_sprom {
1056 struct ssb_boardinfo {
1057 u16 vendor;
1058 u16 type;
1059 - u16 rev;
1060 + u8 rev;
1061 };
1062
1063
1064 @@ -229,10 +240,9 @@ struct ssb_driver {
1065 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
1066
1067 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
1068 -static inline int ssb_driver_register(struct ssb_driver *drv)
1069 -{
1070 - return __ssb_driver_register(drv, THIS_MODULE);
1071 -}
1072 +#define ssb_driver_register(drv) \
1073 + __ssb_driver_register(drv, THIS_MODULE)
1074 +
1075 extern void ssb_driver_unregister(struct ssb_driver *drv);
1076
1077
1078 @@ -308,7 +318,7 @@ struct ssb_bus {
1079
1080 /* ID information about the Chip. */
1081 u16 chip_id;
1082 - u16 chip_rev;
1083 + u8 chip_rev;
1084 u16 sprom_offset;
1085 u16 sprom_size; /* number of words in sprom */
1086 u8 chip_package;
1087 @@ -404,7 +414,9 @@ extern bool ssb_is_sprom_available(struc
1088
1089 /* Set a fallback SPROM.
1090 * See kdoc at the function definition for complete documentation. */
1091 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
1092 +extern int ssb_arch_register_fallback_sprom(
1093 + int (*sprom_callback)(struct ssb_bus *bus,
1094 + struct ssb_sprom *out));
1095
1096 /* Suspend a SSB bus.
1097 * Call this from the parent bus suspend routine. */
1098 @@ -518,6 +530,7 @@ extern int ssb_bus_may_powerdown(struct
1099 * Otherwise static always-on powercontrol will be used. */
1100 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
1101
1102 +extern void ssb_commit_settings(struct ssb_bus *bus);
1103
1104 /* Various helper functions */
1105 extern u32 ssb_admatch_base(u32 adm);
1106 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1107 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1108 @@ -8,7 +8,7 @@
1109 * gpio interface, extbus, and support for serial and parallel flashes.
1110 *
1111 * Copyright 2005, Broadcom Corporation
1112 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
1113 + * Copyright 2006, Michael Buesch <m@bues.ch>
1114 *
1115 * Licensed under the GPL version 2. See COPYING for details.
1116 */
1117 @@ -123,6 +123,8 @@
1118 #define SSB_CHIPCO_FLASHDATA 0x0048
1119 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1120 #define SSB_CHIPCO_BCAST_DATA 0x0054
1121 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1122 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1123 #define SSB_CHIPCO_GPIOIN 0x0060
1124 #define SSB_CHIPCO_GPIOOUT 0x0064
1125 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1126 @@ -131,6 +133,9 @@
1127 #define SSB_CHIPCO_GPIOIRQ 0x0074
1128 #define SSB_CHIPCO_WATCHDOG 0x0080
1129 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1130 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1131 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1132 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1133 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1134 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1135 #define SSB_CHIPCO_CLOCK_N 0x0090
1136 @@ -189,8 +194,10 @@
1137 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1138 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1139 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1140 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1141 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1142 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1143 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1144 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1145 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1146 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1147 #define SSB_CHIPCO_UART0_DATA 0x0300
1148 #define SSB_CHIPCO_UART0_IMR 0x0304
1149 --- a/include/linux/ssb/ssb_regs.h
1150 +++ b/include/linux/ssb/ssb_regs.h
1151 @@ -97,7 +97,7 @@
1152 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
1153 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
1154 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
1155 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
1156 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
1157 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
1158 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
1159 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
1160 @@ -432,6 +432,23 @@
1161 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1162 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1163 #define SSB_SPROM8_RXPO5G_SHIFT 8
1164 +#define SSB_SPROM8_FEM2G 0x00AE
1165 +#define SSB_SPROM8_FEM5G 0x00B0
1166 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
1167 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
1168 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
1169 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
1170 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
1171 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
1172 +#define SSB_SROM8_FEM_TR_ISO 0x0700
1173 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
1174 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
1175 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
1176 +#define SSB_SPROM8_THERMAL 0x00B2
1177 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
1178 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
1179 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
1180 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
1181 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1182 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1183 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1184 @@ -462,6 +479,46 @@
1185 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1186 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1187
1188 +/* Values for boardflags_lo read from SPROM */
1189 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
1190 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
1191 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
1192 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
1193 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
1194 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
1195 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
1196 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
1197 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
1198 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
1199 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
1200 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
1201 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
1202 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
1203 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
1204 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
1205 +
1206 +/* Values for boardflags_hi read from SPROM */
1207 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
1208 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
1209 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
1210 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
1211 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
1212 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
1213 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
1214 +
1215 +/* Values for boardflags2_lo read from SPROM */
1216 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
1217 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
1218 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
1219 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
1220 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
1221 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
1222 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
1223 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
1224 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
1225 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
1226 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
1227 +
1228 /* Values for SSB_SPROM1_BINF_CCODE */
1229 enum {
1230 SSB_SPROM1CCODE_WORLD = 0,
1231 --- a/drivers/ssb/b43_pci_bridge.c
1232 +++ b/drivers/ssb/b43_pci_bridge.c
1233 @@ -5,12 +5,13 @@
1234 * because of its small size we include it in the SSB core
1235 * instead of creating a standalone module.
1236 *
1237 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
1238 + * Copyright 2007 Michael Buesch <m@bues.ch>
1239 *
1240 * Licensed under the GNU/GPL. See COPYING for details.
1241 */
1242
1243 #include <linux/pci.h>
1244 +#include <linux/module.h>
1245 #include <linux/ssb/ssb.h>
1246
1247 #include "ssb_private.h"
1248 --- a/drivers/ssb/driver_extif.c
1249 +++ b/drivers/ssb/driver_extif.c
1250 @@ -3,7 +3,7 @@
1251 * Broadcom EXTIF core driver
1252 *
1253 * Copyright 2005, Broadcom Corporation
1254 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1255 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1256 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
1257 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
1258 *
1259 --- a/drivers/ssb/driver_mipscore.c
1260 +++ b/drivers/ssb/driver_mipscore.c
1261 @@ -3,7 +3,7 @@
1262 * Broadcom MIPS core driver
1263 *
1264 * Copyright 2005, Broadcom Corporation
1265 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1266 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1267 *
1268 * Licensed under the GNU/GPL. See COPYING for details.
1269 */
1270 --- a/drivers/ssb/embedded.c
1271 +++ b/drivers/ssb/embedded.c
1272 @@ -3,7 +3,7 @@
1273 * Embedded systems support code
1274 *
1275 * Copyright 2005-2008, Broadcom Corporation
1276 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
1277 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1278 *
1279 * Licensed under the GNU/GPL. See COPYING for details.
1280 */
1281 --- a/drivers/ssb/pcmcia.c
1282 +++ b/drivers/ssb/pcmcia.c
1283 @@ -3,7 +3,7 @@
1284 * PCMCIA-Hostbus related functions
1285 *
1286 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1287 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1288 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1289 *
1290 * Licensed under the GNU/GPL. See COPYING for details.
1291 */
1292 --- a/drivers/ssb/sdio.c
1293 +++ b/drivers/ssb/sdio.c
1294 @@ -6,7 +6,7 @@
1295 *
1296 * Based on drivers/ssb/pcmcia.c
1297 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1298 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1299 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1300 *
1301 * Licensed under the GNU/GPL. See COPYING for details.
1302 *
Personal OpenWRT clone
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