target/linux/generic/patches-3.1/020-ssb_update.patch

   1 --- a/drivers/ssb/b43_pci_bridge.c
   2 +++ b/drivers/ssb/b43_pci_bridge.c
   3 @@ -11,6 +11,7 @@
   4   */
   5
   6  #include <linux/pci.h>
   7 +#include <linux/module.h>
   8  #include <linux/ssb/ssb.h>
   9
  10  #include "ssb_private.h"
  11 --- a/drivers/ssb/main.c
  12 +++ b/drivers/ssb/main.c
  13 @@ -12,6 +12,7 @@
  14
  15  #include <linux/delay.h>
  16  #include <linux/io.h>
  17 +#include <linux/module.h>
  18  #include <linux/ssb/ssb.h>
  19  #include <linux/ssb/ssb_regs.h>
  20  #include <linux/ssb/ssb_driver_gige.h>
  21 @@ -1260,16 +1261,34 @@ void ssb_device_disable(struct ssb_devic
  22  }
  23  EXPORT_SYMBOL(ssb_device_disable);
  24
  25 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
  26 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
  27 +{
  28 +       u16 chip_id = dev->bus->chip_id;
  29 +
  30 +       if (dev->id.coreid == SSB_DEV_80211) {
  31 +               return (chip_id == 0x4322 || chip_id == 43221 ||
  32 +                       chip_id == 43231 || chip_id == 43222);
  33 +       }
  34 +
  35 +       return 0;
  36 +}
  37 +
  38  u32 ssb_dma_translation(struct ssb_device *dev)
  39  {
  40         switch (dev->bus->bustype) {
  41         case SSB_BUSTYPE_SSB:
  42                 return 0;
  43         case SSB_BUSTYPE_PCI:
  44 -               if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
  45 +               if (pci_is_pcie(dev->bus->host_pci) &&
  46 +                   ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
  47                         return SSB_PCIE_DMA_H32;
  48 -               else
  49 -                       return SSB_PCI_DMA;
  50 +               } else {
  51 +                       if (ssb_dma_translation_special_bit(dev))
  52 +                               return SSB_PCIE_DMA_H32;
  53 +                       else
  54 +                               return SSB_PCI_DMA;
  55 +               }
  56         default:
  57                 __ssb_dma_not_implemented(dev);
  58         }
  59 --- a/drivers/ssb/pci.c
  60 +++ b/drivers/ssb/pci.c
  61 @@ -607,6 +607,29 @@ static void sprom_extract_r8(struct ssb_
  62         memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
  63                sizeof(out->antenna_gain.ghz5));
  64
  65 +       /* Extract FEM info */
  66 +       SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
  67 +               SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
  68 +       SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
  69 +               SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
  70 +       SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
  71 +               SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
  72 +       SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
  73 +               SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
  74 +       SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
  75 +               SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
  76 +
  77 +       SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
  78 +               SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
  79 +       SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
  80 +               SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
  81 +       SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
  82 +               SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
  83 +       SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
  84 +               SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
  85 +       SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
  86 +               SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
  87 +
  88         sprom_extract_r458(out, in);
  89
  90         /* TODO - get remaining rev 8 stuff needed */
  91 --- a/include/linux/ssb/ssb.h
  92 +++ b/include/linux/ssb/ssb.h
  93 @@ -25,7 +25,7 @@ struct ssb_sprom {
  94         u8 et1phyaddr;          /* MII address for enet1 */
  95         u8 et0mdcport;          /* MDIO for enet0 */
  96         u8 et1mdcport;          /* MDIO for enet1 */
  97 -       u8 board_rev;           /* Board revision number from SPROM. */
  98 +       u16 board_rev;          /* Board revision number from SPROM. */
  99         u8 country_code;        /* Country Code */
 100         u16 leddc_on_time;      /* LED Powersave Duty Cycle On Count */
 101         u16 leddc_off_time;     /* LED Powersave Duty Cycle Off Count */
 102 @@ -94,6 +94,15 @@ struct ssb_sprom {
 103                 } ghz5;         /* 5GHz band */
 104         } antenna_gain;
 105
 106 +       struct {
 107 +               struct {
 108 +                       u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
 109 +               } ghz2;
 110 +               struct {
 111 +                       u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
 112 +               } ghz5;
 113 +       } fem;
 114 +
 115         /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
 116  };
 117
 118 @@ -231,10 +240,9 @@ struct ssb_driver {
 119  #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
 120
 121  extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
 122 -static inline int ssb_driver_register(struct ssb_driver *drv)
 123 -{
 124 -       return __ssb_driver_register(drv, THIS_MODULE);
 125 -}
 126 +#define ssb_driver_register(drv) \
 127 +       __ssb_driver_register(drv, THIS_MODULE)
 128 +
 129  extern void ssb_driver_unregister(struct ssb_driver *drv);
 130
 131
 132 --- a/include/linux/ssb/ssb_regs.h
 133 +++ b/include/linux/ssb/ssb_regs.h
 134 @@ -432,6 +432,23 @@
 135  #define  SSB_SPROM8_RXPO2G             0x00FF  /* 2GHz RX power offset */
 136  #define  SSB_SPROM8_RXPO5G             0xFF00  /* 5GHz RX power offset */
 137  #define  SSB_SPROM8_RXPO5G_SHIFT       8
 138 +#define SSB_SPROM8_FEM2G               0x00AE
 139 +#define SSB_SPROM8_FEM5G               0x00B0
 140 +#define  SSB_SROM8_FEM_TSSIPOS         0x0001
 141 +#define  SSB_SROM8_FEM_TSSIPOS_SHIFT   0
 142 +#define  SSB_SROM8_FEM_EXTPA_GAIN      0x0006
 143 +#define  SSB_SROM8_FEM_EXTPA_GAIN_SHIFT        1
 144 +#define  SSB_SROM8_FEM_PDET_RANGE      0x00F8
 145 +#define  SSB_SROM8_FEM_PDET_RANGE_SHIFT        3
 146 +#define  SSB_SROM8_FEM_TR_ISO          0x0700
 147 +#define  SSB_SROM8_FEM_TR_ISO_SHIFT    8
 148 +#define  SSB_SROM8_FEM_ANTSWLUT                0xF800
 149 +#define  SSB_SROM8_FEM_ANTSWLUT_SHIFT  11
 150 +#define SSB_SPROM8_THERMAL             0x00B2
 151 +#define SSB_SPROM8_MPWR_RAWTS          0x00B4
 152 +#define SSB_SPROM8_TS_SLP_OPT_CORRX    0x00B6
 153 +#define SSB_SPROM8_FOC_HWIQ_IQSWP      0x00B8
 154 +#define SSB_SPROM8_PHYCAL_TEMPDELTA    0x00BA
 155  #define SSB_SPROM8_MAXP_BG             0x00C0  /* Max Power 2GHz in path 1 */
 156  #define  SSB_SPROM8_MAXP_BG_MASK       0x00FF  /* Mask for Max Power 2GHz */
 157  #define  SSB_SPROM8_ITSSI_BG           0xFF00  /* Mask for path 1 itssi_bg */
 158 @@ -462,6 +479,46 @@
 159  #define SSB_SPROM8_OFDM5GLPO           0x014A  /* 5.2GHz OFDM power offset */
 160  #define SSB_SPROM8_OFDM5GHPO           0x014E  /* 5.8GHz OFDM power offset */
 161
 162 +/* Values for boardflags_lo read from SPROM */
 163 +#define SSB_BFL_BTCOEXIST              0x0001  /* implements Bluetooth coexistance */
 164 +#define SSB_BFL_PACTRL                 0x0002  /* GPIO 9 controlling the PA */
 165 +#define SSB_BFL_AIRLINEMODE            0x0004  /* implements GPIO 13 radio disable indication */
 166 +#define SSB_BFL_RSSI                   0x0008  /* software calculates nrssi slope. */
 167 +#define SSB_BFL_ENETSPI                        0x0010  /* has ephy roboswitch spi */
 168 +#define SSB_BFL_XTAL_NOSLOW            0x0020  /* no slow clock available */
 169 +#define SSB_BFL_CCKHIPWR               0x0040  /* can do high power CCK transmission */
 170 +#define SSB_BFL_ENETADM                        0x0080  /* has ADMtek switch */
 171 +#define SSB_BFL_ENETVLAN               0x0100  /* can do vlan */
 172 +#define SSB_BFL_AFTERBURNER            0x0200  /* supports Afterburner mode */
 173 +#define SSB_BFL_NOPCI                  0x0400  /* board leaves PCI floating */
 174 +#define SSB_BFL_FEM                    0x0800  /* supports the Front End Module */
 175 +#define SSB_BFL_EXTLNA                 0x1000  /* has an external LNA */
 176 +#define SSB_BFL_HGPA                   0x2000  /* had high gain PA */
 177 +#define SSB_BFL_BTCMOD                 0x4000  /* BFL_BTCOEXIST is given in alternate GPIOs */
 178 +#define SSB_BFL_ALTIQ                  0x8000  /* alternate I/Q settings */
 179 +
 180 +/* Values for boardflags_hi read from SPROM */
 181 +#define SSB_BFH_NOPA                   0x0001  /* has no PA */
 182 +#define SSB_BFH_RSSIINV                        0x0002  /* RSSI uses positive slope (not TSSI) */
 183 +#define SSB_BFH_PAREF                  0x0004  /* uses the PARef LDO */
 184 +#define SSB_BFH_3TSWITCH               0x0008  /* uses a triple throw switch shared with bluetooth */
 185 +#define SSB_BFH_PHASESHIFT             0x0010  /* can support phase shifter */
 186 +#define SSB_BFH_BUCKBOOST              0x0020  /* has buck/booster */
 187 +#define SSB_BFH_FEM_BT                 0x0040  /* has FEM and switch to share antenna with bluetooth */
 188 +
 189 +/* Values for boardflags2_lo read from SPROM */
 190 +#define SSB_BFL2_RXBB_INT_REG_DIS      0x0001  /* external RX BB regulator present */
 191 +#define SSB_BFL2_APLL_WAR              0x0002  /* alternative A-band PLL settings implemented */
 192 +#define SSB_BFL2_TXPWRCTRL_EN          0x0004  /* permits enabling TX Power Control */
 193 +#define SSB_BFL2_2X4_DIV               0x0008  /* 2x4 diversity switch */
 194 +#define SSB_BFL2_5G_PWRGAIN            0x0010  /* supports 5G band power gain */
 195 +#define SSB_BFL2_PCIEWAR_OVR           0x0020  /* overrides ASPM and Clkreq settings */
 196 +#define SSB_BFL2_CAESERS_BRD           0x0040  /* is Caesers board (unused) */
 197 +#define SSB_BFL2_BTC3WIRE              0x0080  /* used 3-wire bluetooth coexist */
 198 +#define SSB_BFL2_SKWRKFEM_BRD          0x0100  /* 4321mcm93 uses Skyworks FEM */
 199 +#define SSB_BFL2_SPUR_WAR              0x0200  /* has a workaround for clock-harmonic spurs */
 200 +#define SSB_BFL2_GPLL_WAR              0x0400  /* altenative G-band PLL settings implemented */
 201 +
 202  /* Values for SSB_SPROM1_BINF_CCODE */
 203  enum {
 204         SSB_SPROM1CCODE_WORLD = 0,