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base reset polarity off initial readings
[openwrt.git] / package / linux / kernel-source / include / sbconfig.h
1 /*
2 * Broadcom SiliconBackplane hardware register definitions.
3 *
4 * Copyright 2004, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11 * $Id$
12 */
13
14 #ifndef _SBCONFIG_H
15 #define _SBCONFIG_H
16
17 /* cpp contortions to concatenate w/arg prescan */
18 #ifndef PAD
19 #define _PADLINE(line) pad ## line
20 #define _XSTR(line) _PADLINE(line)
21 #define PAD _XSTR(__LINE__)
22 #endif
23
24 /*
25 * SiliconBackplane Address Map.
26 * All regions may not exist on all chips.
27 */
28 #define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
29 #define SB_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
30 #define SB_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
31 #define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
32 #define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
33 #define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
34 #define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
35 #define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
36 #define SB_EUART (SB_EXTIF_BASE + 0x00800000)
37 #define SB_LED (SB_EXTIF_BASE + 0x00900000)
38
39 /* enumeration space related defs */
40 #define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
41 #define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
42 #define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
43 #define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
44
45 /* mips address */
46 #define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
47
48 /*
49 * Sonics Configuration Space Registers.
50 */
51 #define SBIPSFLAG 0x08
52 #define SBTPSFLAG 0x18
53 #define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
54 #define SBTMERRLOG 0x50 /* sonics >= 2.3 */
55 #define SBADMATCH3 0x60
56 #define SBADMATCH2 0x68
57 #define SBADMATCH1 0x70
58 #define SBIMSTATE 0x90
59 #define SBINTVEC 0x94
60 #define SBTMSTATELOW 0x98
61 #define SBTMSTATEHIGH 0x9c
62 #define SBBWA0 0xa0
63 #define SBIMCONFIGLOW 0xa8
64 #define SBIMCONFIGHIGH 0xac
65 #define SBADMATCH0 0xb0
66 #define SBTMCONFIGLOW 0xb8
67 #define SBTMCONFIGHIGH 0xbc
68 #define SBBCONFIG 0xc0
69 #define SBBSTATE 0xc8
70 #define SBACTCNFG 0xd8
71 #define SBFLAGST 0xe8
72 #define SBIDLOW 0xf8
73 #define SBIDHIGH 0xfc
74
75 #ifndef _LANGUAGE_ASSEMBLY
76
77 typedef volatile struct _sbconfig {
78 uint32 PAD[2];
79 uint32 sbipsflag; /* initiator port ocp slave flag */
80 uint32 PAD[3];
81 uint32 sbtpsflag; /* target port ocp slave flag */
82 uint32 PAD[11];
83 uint32 sbtmerrloga; /* (sonics >= 2.3) */
84 uint32 PAD;
85 uint32 sbtmerrlog; /* (sonics >= 2.3) */
86 uint32 PAD[3];
87 uint32 sbadmatch3; /* address match3 */
88 uint32 PAD;
89 uint32 sbadmatch2; /* address match2 */
90 uint32 PAD;
91 uint32 sbadmatch1; /* address match1 */
92 uint32 PAD[7];
93 uint32 sbimstate; /* initiator agent state */
94 uint32 sbintvec; /* interrupt mask */
95 uint32 sbtmstatelow; /* target state */
96 uint32 sbtmstatehigh; /* target state */
97 uint32 sbbwa0; /* bandwidth allocation table0 */
98 uint32 PAD;
99 uint32 sbimconfiglow; /* initiator configuration */
100 uint32 sbimconfighigh; /* initiator configuration */
101 uint32 sbadmatch0; /* address match0 */
102 uint32 PAD;
103 uint32 sbtmconfiglow; /* target configuration */
104 uint32 sbtmconfighigh; /* target configuration */
105 uint32 sbbconfig; /* broadcast configuration */
106 uint32 PAD;
107 uint32 sbbstate; /* broadcast state */
108 uint32 PAD[3];
109 uint32 sbactcnfg; /* activate configuration */
110 uint32 PAD[3];
111 uint32 sbflagst; /* current sbflags */
112 uint32 PAD[3];
113 uint32 sbidlow; /* identification */
114 uint32 sbidhigh; /* identification */
115 } sbconfig_t;
116
117 #endif /* _LANGUAGE_ASSEMBLY */
118
119 /* sbipsflag */
120 #define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
121 #define SBIPS_INT1_SHIFT 0
122 #define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
123 #define SBIPS_INT2_SHIFT 8
124 #define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
125 #define SBIPS_INT3_SHIFT 16
126 #define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
127 #define SBIPS_INT4_SHIFT 24
128
129 /* sbtpsflag */
130 #define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
131 #define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
132
133 /* sbtmerrlog */
134 #define SBTMEL_CM 0x00000007 /* command */
135 #define SBTMEL_CI 0x0000ff00 /* connection id */
136 #define SBTMEL_EC 0x0f000000 /* error code */
137 #define SBTMEL_ME 0x80000000 /* multiple error */
138
139 /* sbimstate */
140 #define SBIM_PC 0xf /* pipecount */
141 #define SBIM_AP_MASK 0x30 /* arbitration policy */
142 #define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
143 #define SBIM_AP_TS 0x10 /* use timesliaces only */
144 #define SBIM_AP_TK 0x20 /* use token only */
145 #define SBIM_AP_RSV 0x30 /* reserved */
146 #define SBIM_IBE 0x20000 /* inbanderror */
147 #define SBIM_TO 0x40000 /* timeout */
148 #define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
149 #define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
150
151 /* sbtmstatelow */
152 #define SBTML_RESET 0x1 /* reset */
153 #define SBTML_REJ 0x2 /* reject */
154 #define SBTML_CLK 0x10000 /* clock enable */
155 #define SBTML_FGC 0x20000 /* force gated clocks on */
156 #define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
157 #define SBTML_PE 0x40000000 /* pme enable */
158 #define SBTML_BE 0x80000000 /* bist enable */
159
160 /* sbtmstatehigh */
161 #define SBTMH_SERR 0x1 /* serror */
162 #define SBTMH_INT 0x2 /* interrupt */
163 #define SBTMH_BUSY 0x4 /* busy */
164 #define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
165 #define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
166 #define SBTMH_GCR 0x20000000 /* gated clock request */
167 #define SBTMH_BISTF 0x40000000 /* bist failed */
168 #define SBTMH_BISTD 0x80000000 /* bist done */
169
170 /* sbbwa0 */
171 #define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
172 #define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
173 #define SBBWA_TAB1_SHIFT 16
174
175 /* sbimconfiglow */
176 #define SBIMCL_STO_MASK 0x7 /* service timeout */
177 #define SBIMCL_RTO_MASK 0x70 /* request timeout */
178 #define SBIMCL_RTO_SHIFT 4
179 #define SBIMCL_CID_MASK 0xff0000 /* connection id */
180 #define SBIMCL_CID_SHIFT 16
181
182 /* sbimconfighigh */
183 #define SBIMCH_IEM_MASK 0xc /* inband error mode */
184 #define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
185 #define SBIMCH_TEM_SHIFT 4
186 #define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
187 #define SBIMCH_BEM_SHIFT 6
188
189 /* sbadmatch0 */
190 #define SBAM_TYPE_MASK 0x3 /* address type */
191 #define SBAM_AD64 0x4 /* reserved */
192 #define SBAM_ADINT0_MASK 0xf8 /* type0 size */
193 #define SBAM_ADINT0_SHIFT 3
194 #define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
195 #define SBAM_ADINT1_SHIFT 3
196 #define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
197 #define SBAM_ADINT2_SHIFT 3
198 #define SBAM_ADEN 0x400 /* enable */
199 #define SBAM_ADNEG 0x800 /* negative decode */
200 #define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
201 #define SBAM_BASE0_SHIFT 8
202 #define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
203 #define SBAM_BASE1_SHIFT 12
204 #define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
205 #define SBAM_BASE2_SHIFT 16
206
207 /* sbtmconfiglow */
208 #define SBTMCL_CD_MASK 0xff /* clock divide */
209 #define SBTMCL_CO_MASK 0xf800 /* clock offset */
210 #define SBTMCL_CO_SHIFT 11
211 #define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
212 #define SBTMCL_IF_SHIFT 18
213 #define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
214 #define SBTMCL_IM_SHIFT 24
215
216 /* sbtmconfighigh */
217 #define SBTMCH_BM_MASK 0x3 /* busy mode */
218 #define SBTMCH_RM_MASK 0x3 /* retry mode */
219 #define SBTMCH_RM_SHIFT 2
220 #define SBTMCH_SM_MASK 0x30 /* stop mode */
221 #define SBTMCH_SM_SHIFT 4
222 #define SBTMCH_EM_MASK 0x300 /* sb error mode */
223 #define SBTMCH_EM_SHIFT 8
224 #define SBTMCH_IM_MASK 0xc00 /* int mode */
225 #define SBTMCH_IM_SHIFT 10
226
227 /* sbbconfig */
228 #define SBBC_LAT_MASK 0x3 /* sb latency */
229 #define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
230 #define SBBC_MAX0_SHIFT 16
231 #define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
232 #define SBBC_MAX1_SHIFT 20
233
234 /* sbbstate */
235 #define SBBS_SRD 0x1 /* st reg disable */
236 #define SBBS_HRD 0x2 /* hold reg disable */
237
238 /* sbidlow */
239 #define SBIDL_CS_MASK 0x3 /* config space */
240 #define SBIDL_AR_MASK 0x38 /* # address ranges supported */
241 #define SBIDL_AR_SHIFT 3
242 #define SBIDL_SYNCH 0x40 /* sync */
243 #define SBIDL_INIT 0x80 /* initiator */
244 #define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
245 #define SBIDL_MINLAT_SHIFT 8
246 #define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
247 #define SBIDL_MAXLAT_SHIFT 12
248 #define SBIDL_FIRST 0x10000 /* this initiator is first */
249 #define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
250 #define SBIDL_CW_SHIFT 18
251 #define SBIDL_TP_MASK 0xf00000 /* target ports */
252 #define SBIDL_TP_SHIFT 20
253 #define SBIDL_IP_MASK 0xf000000 /* initiator ports */
254 #define SBIDL_IP_SHIFT 24
255 #define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
256 #define SBIDL_RV_SHIFT 28
257
258 /* sbidhigh */
259 #define SBIDH_RC_MASK 0xf /* revision code*/
260 #define SBIDH_CC_MASK 0xfff0 /* core code */
261 #define SBIDH_CC_SHIFT 4
262 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
263 #define SBIDH_VC_SHIFT 16
264
265 #define SB_COMMIT 0xfd8 /* update buffered registers value */
266
267 /* vendor codes */
268 #define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
269
270 /* core codes */
271 #define SB_CC 0x800 /* chipcommon core */
272 #define SB_ILINE20 0x801 /* iline20 core */
273 #define SB_SDRAM 0x803 /* sdram core */
274 #define SB_PCI 0x804 /* pci core */
275 #define SB_MIPS 0x805 /* mips core */
276 #define SB_ENET 0x806 /* enet mac core */
277 #define SB_CODEC 0x807 /* v90 codec core */
278 #define SB_USB 0x808 /* usb 1.1 host/device core */
279 #define SB_ILINE100 0x80a /* iline100 core */
280 #define SB_IPSEC 0x80b /* ipsec core */
281 #define SB_PCMCIA 0x80d /* pcmcia core */
282 #define SB_MEMC 0x80f /* memc sdram core */
283 #define SB_EXTIF 0x811 /* external interface core */
284 #define SB_D11 0x812 /* 802.11 MAC core */
285 #define SB_MIPS33 0x816 /* mips3302 core */
286 #define SB_USB11H 0x817 /* usb 1.1 host core */
287 #define SB_USB11D 0x818 /* usb 1.1 device core */
288 #define SB_USB20H 0x819 /* usb 2.0 host core */
289 #define SB_USB20D 0x81A /* usb 2.0 device core */
290 #define SB_SDIOH 0x81B /* sdio host core */
291
292 #endif /* _SBCONFIG_H */
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