projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: update bcma and ssb to version master-2011-07-22 from wireless-testing
[openwrt.git] / target / linux / generic / patches-2.6.36 / 941-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -384,6 +384,35 @@ static int ssb_device_uevent(struct devi
4 ssb_dev->id.revision);
5 }
6
7 +#define ssb_config_attr(attrib, field, format_string) \
8 +static ssize_t \
9 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
10 +{ \
11 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
12 +}
13 +
14 +ssb_config_attr(core_num, core_index, "%u\n")
15 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
16 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
17 +ssb_config_attr(revision, id.revision, "%u\n")
18 +ssb_config_attr(irq, irq, "%u\n")
19 +static ssize_t
20 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
21 +{
22 + return sprintf(buf, "%s\n",
23 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
24 +}
25 +
26 +static struct device_attribute ssb_device_attrs[] = {
27 + __ATTR_RO(name),
28 + __ATTR_RO(core_num),
29 + __ATTR_RO(coreid),
30 + __ATTR_RO(vendor),
31 + __ATTR_RO(revision),
32 + __ATTR_RO(irq),
33 + __ATTR_NULL,
34 +};
35 +
36 static struct bus_type ssb_bustype = {
37 .name = "ssb",
38 .match = ssb_bus_match,
39 @@ -393,6 +422,7 @@ static struct bus_type ssb_bustype = {
40 .suspend = ssb_device_suspend,
41 .resume = ssb_device_resume,
42 .uevent = ssb_device_uevent,
43 + .dev_attrs = ssb_device_attrs,
44 };
45
46 static void ssb_buses_lock(void)
47 @@ -528,7 +558,7 @@ error:
48 }
49
50 /* Needs ssb_buses_lock() */
51 -static int ssb_attach_queued_buses(void)
52 +static int __devinit ssb_attach_queued_buses(void)
53 {
54 struct ssb_bus *bus, *n;
55 int err = 0;
56 @@ -739,9 +769,9 @@ out:
57 return err;
58 }
59
60 -static int ssb_bus_register(struct ssb_bus *bus,
61 - ssb_invariants_func_t get_invariants,
62 - unsigned long baseaddr)
63 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
64 + ssb_invariants_func_t get_invariants,
65 + unsigned long baseaddr)
66 {
67 int err;
68
69 @@ -822,8 +852,8 @@ err_disable_xtal:
70 }
71
72 #ifdef CONFIG_SSB_PCIHOST
73 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
74 - struct pci_dev *host_pci)
75 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
76 + struct pci_dev *host_pci)
77 {
78 int err;
79
80 @@ -846,9 +876,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
81 #endif /* CONFIG_SSB_PCIHOST */
82
83 #ifdef CONFIG_SSB_PCMCIAHOST
84 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
85 - struct pcmcia_device *pcmcia_dev,
86 - unsigned long baseaddr)
87 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
88 + struct pcmcia_device *pcmcia_dev,
89 + unsigned long baseaddr)
90 {
91 int err;
92
93 @@ -868,8 +898,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
94 #endif /* CONFIG_SSB_PCMCIAHOST */
95
96 #ifdef CONFIG_SSB_SDIOHOST
97 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
98 - unsigned int quirks)
99 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
100 + struct sdio_func *func,
101 + unsigned int quirks)
102 {
103 int err;
104
105 @@ -889,9 +920,9 @@ int ssb_bus_sdiobus_register(struct ssb_
106 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
107 #endif /* CONFIG_SSB_PCMCIAHOST */
108
109 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
110 - unsigned long baseaddr,
111 - ssb_invariants_func_t get_invariants)
112 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
113 + unsigned long baseaddr,
114 + ssb_invariants_func_t get_invariants)
115 {
116 int err;
117
118 @@ -972,8 +1003,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
119 switch (plltype) {
120 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
121 if (m & SSB_CHIPCO_CLK_T6_MMASK)
122 - return SSB_CHIPCO_CLK_T6_M0;
123 - return SSB_CHIPCO_CLK_T6_M1;
124 + return SSB_CHIPCO_CLK_T6_M1;
125 + return SSB_CHIPCO_CLK_T6_M0;
126 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
127 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
128 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
129 @@ -1088,23 +1119,22 @@ static u32 ssb_tmslow_reject_bitmask(str
130 {
131 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
132
133 - /* The REJECT bit changed position in TMSLOW between
134 - * Backplane revisions. */
135 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
136 switch (rev) {
137 case SSB_IDLOW_SSBREV_22:
138 - return SSB_TMSLOW_REJECT_22;
139 + case SSB_IDLOW_SSBREV_24:
140 + case SSB_IDLOW_SSBREV_26:
141 + return SSB_TMSLOW_REJECT;
142 case SSB_IDLOW_SSBREV_23:
143 return SSB_TMSLOW_REJECT_23;
144 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
145 - case SSB_IDLOW_SSBREV_25: /* same here */
146 - case SSB_IDLOW_SSBREV_26: /* same here */
147 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
148 case SSB_IDLOW_SSBREV_27: /* same here */
149 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
150 + return SSB_TMSLOW_REJECT; /* this is a guess */
151 default:
152 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
153 WARN_ON(1);
154 }
155 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
156 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
157 }
158
159 int ssb_device_is_enabled(struct ssb_device *dev)
160 @@ -1163,10 +1193,10 @@ void ssb_device_enable(struct ssb_device
161 }
162 EXPORT_SYMBOL(ssb_device_enable);
163
164 -/* Wait for a bit in a register to get set or unset.
165 +/* Wait for bitmask in a register to get set or cleared.
166 * timeout is in units of ten-microseconds */
167 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
168 - int timeout, int set)
169 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
170 + int timeout, int set)
171 {
172 int i;
173 u32 val;
174 @@ -1174,7 +1204,7 @@ static int ssb_wait_bit(struct ssb_devic
175 for (i = 0; i < timeout; i++) {
176 val = ssb_read32(dev, reg);
177 if (set) {
178 - if (val & bitmask)
179 + if ((val & bitmask) == bitmask)
180 return 0;
181 } else {
182 if (!(val & bitmask))
183 @@ -1191,20 +1221,38 @@ static int ssb_wait_bit(struct ssb_devic
184
185 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
186 {
187 - u32 reject;
188 + u32 reject, val;
189
190 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
191 return;
192
193 reject = ssb_tmslow_reject_bitmask(dev);
194 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
195 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
196 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
197 - ssb_write32(dev, SSB_TMSLOW,
198 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
199 - reject | SSB_TMSLOW_RESET |
200 - core_specific_flags);
201 - ssb_flush_tmslow(dev);
202 +
203 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
204 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
205 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
206 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
207 +
208 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
209 + val = ssb_read32(dev, SSB_IMSTATE);
210 + val |= SSB_IMSTATE_REJECT;
211 + ssb_write32(dev, SSB_IMSTATE, val);
212 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
213 + 0);
214 + }
215 +
216 + ssb_write32(dev, SSB_TMSLOW,
217 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
218 + reject | SSB_TMSLOW_RESET |
219 + core_specific_flags);
220 + ssb_flush_tmslow(dev);
221 +
222 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
223 + val = ssb_read32(dev, SSB_IMSTATE);
224 + val &= ~SSB_IMSTATE_REJECT;
225 + ssb_write32(dev, SSB_IMSTATE, val);
226 + }
227 + }
228
229 ssb_write32(dev, SSB_TMSLOW,
230 reject | SSB_TMSLOW_RESET |
231 @@ -1219,7 +1267,10 @@ u32 ssb_dma_translation(struct ssb_devic
232 case SSB_BUSTYPE_SSB:
233 return 0;
234 case SSB_BUSTYPE_PCI:
235 - return SSB_PCI_DMA;
236 + if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
237 + return SSB_PCIE_DMA_H32;
238 + else
239 + return SSB_PCI_DMA;
240 default:
241 __ssb_dma_not_implemented(dev);
242 }
243 @@ -1262,20 +1313,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
244
245 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
246 {
247 - struct ssb_chipcommon *cc;
248 int err;
249 enum ssb_clkmode mode;
250
251 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
252 if (err)
253 goto error;
254 - cc = &bus->chipco;
255 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
256 - ssb_chipco_set_clockmode(cc, mode);
257
258 #ifdef CONFIG_SSB_DEBUG
259 bus->powered_up = 1;
260 #endif
261 +
262 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
263 + ssb_chipco_set_clockmode(&bus->chipco, mode);
264 +
265 return 0;
266 error:
267 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
268 @@ -1283,6 +1334,37 @@ error:
269 }
270 EXPORT_SYMBOL(ssb_bus_powerup);
271
272 +static void ssb_broadcast_value(struct ssb_device *dev,
273 + u32 address, u32 data)
274 +{
275 +#ifdef CONFIG_SSB_DRIVER_PCICORE
276 + /* This is used for both, PCI and ChipCommon core, so be careful. */
277 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
278 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
279 +#endif
280 +
281 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
282 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
283 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
284 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
285 +}
286 +
287 +void ssb_commit_settings(struct ssb_bus *bus)
288 +{
289 + struct ssb_device *dev;
290 +
291 +#ifdef CONFIG_SSB_DRIVER_PCICORE
292 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
293 +#else
294 + dev = bus->chipco.dev;
295 +#endif
296 + if (WARN_ON(!dev))
297 + return;
298 + /* This forces an update of the cached registers. */
299 + ssb_broadcast_value(dev, 0xFD8, 0);
300 +}
301 +EXPORT_SYMBOL(ssb_commit_settings);
302 +
303 u32 ssb_admatch_base(u32 adm)
304 {
305 u32 base = 0;
306 --- a/drivers/ssb/pci.c
307 +++ b/drivers/ssb/pci.c
308 @@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss
309 out->antenna_gain.ghz5.a3 = gain;
310 }
311
312 +/* Revs 4 5 and 8 have partially shared layout */
313 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
314 +{
315 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
316 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
317 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
318 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
319 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
320 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
321 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
322 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
323 +
324 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
325 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
326 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
327 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
328 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
329 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
330 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
331 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
332 +
333 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
334 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
335 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
336 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
337 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
338 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
339 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
340 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
341 +
342 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
343 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
344 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
345 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
346 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
347 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
348 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
349 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
350 +}
351 +
352 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
353 {
354 int i;
355 @@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb
356 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
357 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
358 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
359 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
360 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
361 } else {
362 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
363 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
364 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
365 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
366 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
367 }
368 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
369 SSB_SPROM4_ANTAVAIL_A_SHIFT);
370 @@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb
371 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
372 sizeof(out->antenna_gain.ghz5));
373
374 + sprom_extract_r458(out, in);
375 +
376 /* TODO - get remaining rev 4 stuff needed */
377 }
378
379 @@ -561,6 +607,8 @@ static void sprom_extract_r8(struct ssb_
380 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
381 sizeof(out->antenna_gain.ghz5));
382
383 + sprom_extract_r458(out, in);
384 +
385 /* TODO - get remaining rev 8 stuff needed */
386 }
387
388 @@ -573,37 +621,34 @@ static int sprom_extract(struct ssb_bus
389 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
390 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
391 memset(out->et1mac, 0xFF, 6);
392 +
393 if ((bus->chip_id & 0xFF00) == 0x4400) {
394 /* Workaround: The BCM44XX chip has a stupid revision
395 * number stored in the SPROM.
396 * Always extract r1. */
397 out->revision = 1;
398 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
399 + }
400 +
401 + switch (out->revision) {
402 + case 1:
403 + case 2:
404 + case 3:
405 sprom_extract_r123(out, in);
406 - } else if (bus->chip_id == 0x4321) {
407 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
408 - out->revision = 4;
409 + break;
410 + case 4:
411 + case 5:
412 sprom_extract_r45(out, in);
413 - } else {
414 - switch (out->revision) {
415 - case 1:
416 - case 2:
417 - case 3:
418 - sprom_extract_r123(out, in);
419 - break;
420 - case 4:
421 - case 5:
422 - sprom_extract_r45(out, in);
423 - break;
424 - case 8:
425 - sprom_extract_r8(out, in);
426 - break;
427 - default:
428 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
429 - " revision %d detected. Will extract"
430 - " v1\n", out->revision);
431 - out->revision = 1;
432 - sprom_extract_r123(out, in);
433 - }
434 + break;
435 + case 8:
436 + sprom_extract_r8(out, in);
437 + break;
438 + default:
439 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
440 + " revision %d detected. Will extract"
441 + " v1\n", out->revision);
442 + out->revision = 1;
443 + sprom_extract_r123(out, in);
444 }
445
446 if (out->boardflags_lo == 0xFFFF)
447 @@ -617,15 +662,14 @@ static int sprom_extract(struct ssb_bus
448 static int ssb_pci_sprom_get(struct ssb_bus *bus,
449 struct ssb_sprom *sprom)
450 {
451 - const struct ssb_sprom *fallback;
452 - int err = -ENOMEM;
453 + int err;
454 u16 *buf;
455
456 if (!ssb_is_sprom_available(bus)) {
457 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
458 return -ENODEV;
459 }
460 - if (bus->chipco.dev) { /* can be unavailible! */
461 + if (bus->chipco.dev) { /* can be unavailable! */
462 /*
463 * get SPROM offset: SSB_SPROM_BASE1 except for
464 * chipcommon rev >= 31 or chip ID is 0x4312 and
465 @@ -645,7 +689,7 @@ static int ssb_pci_sprom_get(struct ssb_
466
467 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
468 if (!buf)
469 - goto out;
470 + return -ENOMEM;
471 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
472 sprom_do_read(bus, buf);
473 err = sprom_check_crc(buf, bus->sprom_size);
474 @@ -655,17 +699,24 @@ static int ssb_pci_sprom_get(struct ssb_
475 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
476 GFP_KERNEL);
477 if (!buf)
478 - goto out;
479 + return -ENOMEM;
480 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
481 sprom_do_read(bus, buf);
482 err = sprom_check_crc(buf, bus->sprom_size);
483 if (err) {
484 /* All CRC attempts failed.
485 * Maybe there is no SPROM on the device?
486 - * If we have a fallback, use that. */
487 - fallback = ssb_get_fallback_sprom();
488 - if (fallback) {
489 - memcpy(sprom, fallback, sizeof(*sprom));
490 + * Now we ask the arch code if there is some sprom
491 + * available for this device in some other storage */
492 + err = ssb_fill_sprom_with_fallback(bus, sprom);
493 + if (err) {
494 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
495 + " fallback SPROM failed (err %d)\n",
496 + err);
497 + } else {
498 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
499 + " revision %d provided by"
500 + " platform.\n", sprom->revision);
501 err = 0;
502 goto out_free;
503 }
504 @@ -677,19 +728,15 @@ static int ssb_pci_sprom_get(struct ssb_
505
506 out_free:
507 kfree(buf);
508 -out:
509 return err;
510 }
511
512 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
513 struct ssb_boardinfo *bi)
514 {
515 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
516 - &bi->vendor);
517 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
518 - &bi->type);
519 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
520 - &bi->rev);
521 + bi->vendor = bus->host_pci->subsystem_vendor;
522 + bi->type = bus->host_pci->subsystem_device;
523 + bi->rev = bus->host_pci->revision;
524 }
525
526 int ssb_pci_get_invariants(struct ssb_bus *bus,
527 --- a/drivers/ssb/pcihost_wrapper.c
528 +++ b/drivers/ssb/pcihost_wrapper.c
529 @@ -53,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
530 # define ssb_pcihost_resume NULL
531 #endif /* CONFIG_PM */
532
533 -static int ssb_pcihost_probe(struct pci_dev *dev,
534 - const struct pci_device_id *id)
535 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
536 + const struct pci_device_id *id)
537 {
538 struct ssb_bus *ssb;
539 int err = -ENOMEM;
540 const char *name;
541 + u32 val;
542
543 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
544 if (!ssb)
545 @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
546 goto err_pci_disable;
547 pci_set_master(dev);
548
549 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
550 + * PCI Tx retries from interfering with C3 CPU state */
551 + pci_read_config_dword(dev, 0x40, &val);
552 + if ((val & 0x0000ff00) != 0)
553 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
554 +
555 err = ssb_bus_pcibus_register(ssb, dev);
556 if (err)
557 goto err_pci_release_regions;
558 @@ -103,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
559 pci_set_drvdata(dev, NULL);
560 }
561
562 -int ssb_pcihost_register(struct pci_driver *driver)
563 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
564 {
565 driver->probe = ssb_pcihost_probe;
566 driver->remove = ssb_pcihost_remove;
567 --- a/drivers/ssb/scan.c
568 +++ b/drivers/ssb/scan.c
569 @@ -259,7 +259,10 @@ static int we_support_multiple_80211_cor
570 #ifdef CONFIG_SSB_PCIHOST
571 if (bus->bustype == SSB_BUSTYPE_PCI) {
572 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
573 - bus->host_pci->device == 0x4324)
574 + ((bus->host_pci->device == 0x4313) ||
575 + (bus->host_pci->device == 0x431A) ||
576 + (bus->host_pci->device == 0x4321) ||
577 + (bus->host_pci->device == 0x4324)))
578 return 1;
579 }
580 #endif /* CONFIG_SSB_PCIHOST */
581 @@ -308,8 +311,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
582 } else {
583 if (bus->bustype == SSB_BUSTYPE_PCI) {
584 bus->chip_id = pcidev_to_chipid(bus->host_pci);
585 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
586 - &bus->chip_rev);
587 + bus->chip_rev = bus->host_pci->revision;
588 bus->chip_package = 0;
589 } else {
590 bus->chip_id = 0x4710;
591 @@ -406,10 +408,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
592 /* Ignore PCI cores on PCI-E cards.
593 * Ignore PCI-E cores on PCI cards. */
594 if (dev->id.coreid == SSB_DEV_PCI) {
595 - if (bus->host_pci->is_pcie)
596 + if (pci_is_pcie(bus->host_pci))
597 continue;
598 } else {
599 - if (!bus->host_pci->is_pcie)
600 + if (!pci_is_pcie(bus->host_pci))
601 continue;
602 }
603 }
604 @@ -421,6 +423,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
605 bus->pcicore.dev = dev;
606 #endif /* CONFIG_SSB_DRIVER_PCICORE */
607 break;
608 + case SSB_DEV_ETHERNET:
609 + if (bus->bustype == SSB_BUSTYPE_PCI) {
610 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
611 + (bus->host_pci->device & 0xFF00) == 0x4300) {
612 + /* This is a dangling ethernet core on a
613 + * wireless device. Ignore it. */
614 + continue;
615 + }
616 + }
617 + break;
618 default:
619 break;
620 }
621 --- a/include/linux/ssb/ssb.h
622 +++ b/include/linux/ssb/ssb.h
623 @@ -27,6 +27,8 @@ struct ssb_sprom {
624 u8 et1mdcport; /* MDIO for enet1 */
625 u8 board_rev; /* Board revision number from SPROM. */
626 u8 country_code; /* Country Code */
627 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
628 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
629 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
630 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
631 u16 pa0b0;
632 @@ -55,6 +57,10 @@ struct ssb_sprom {
633 u8 tri5gl; /* 5.2GHz TX isolation */
634 u8 tri5g; /* 5.3GHz TX isolation */
635 u8 tri5gh; /* 5.8GHz TX isolation */
636 + u8 txpid2g[4]; /* 2GHz TX power index */
637 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
638 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
639 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
640 u8 rxpo2g; /* 2GHz RX power offset */
641 u8 rxpo5g; /* 5GHz RX power offset */
642 u8 rssisav2g; /* 2GHz RSSI params */
643 @@ -95,7 +101,7 @@ struct ssb_sprom {
644 struct ssb_boardinfo {
645 u16 vendor;
646 u16 type;
647 - u16 rev;
648 + u8 rev;
649 };
650
651
652 @@ -304,7 +310,7 @@ struct ssb_bus {
653
654 /* ID information about the Chip. */
655 u16 chip_id;
656 - u16 chip_rev;
657 + u8 chip_rev;
658 u16 sprom_offset;
659 u16 sprom_size; /* number of words in sprom */
660 u8 chip_package;
661 @@ -400,7 +406,9 @@ extern bool ssb_is_sprom_available(struc
662
663 /* Set a fallback SPROM.
664 * See kdoc at the function definition for complete documentation. */
665 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
666 +extern int ssb_arch_register_fallback_sprom(
667 + int (*sprom_callback)(struct ssb_bus *bus,
668 + struct ssb_sprom *out));
669
670 /* Suspend a SSB bus.
671 * Call this from the parent bus suspend routine. */
672 @@ -514,6 +522,7 @@ extern int ssb_bus_may_powerdown(struct
673 * Otherwise static always-on powercontrol will be used. */
674 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
675
676 +extern void ssb_commit_settings(struct ssb_bus *bus);
677
678 /* Various helper functions */
679 extern u32 ssb_admatch_base(u32 adm);
680 --- a/include/linux/ssb/ssb_driver_gige.h
681 +++ b/include/linux/ssb/ssb_driver_gige.h
682 @@ -96,16 +96,21 @@ static inline bool ssb_gige_must_flush_p
683 return 0;
684 }
685
686 -extern char * nvram_get(const char *name);
687 +#ifdef CONFIG_BCM47XX
688 +#include <asm/mach-bcm47xx/nvram.h>
689 /* Get the device MAC address */
690 static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
691 {
692 -#ifdef CONFIG_BCM47XX
693 - char *res = nvram_get("et0macaddr");
694 - if (res)
695 - memcpy(macaddr, res, 6);
696 -#endif
697 + char buf[20];
698 + if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
699 + return;
700 + nvram_parse_macaddr(buf, macaddr);
701 }
702 +#else
703 +static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
704 +{
705 +}
706 +#endif
707
708 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
709 struct pci_dev *pdev);
710 --- a/include/linux/ssb/ssb_regs.h
711 +++ b/include/linux/ssb/ssb_regs.h
712 @@ -85,6 +85,8 @@
713 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
714 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
715 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
716 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
717 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
718 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
719 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
720 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
721 @@ -95,7 +97,7 @@
722 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
723 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
724 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
725 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
726 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
727 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
728 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
729 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
730 @@ -267,6 +269,8 @@
731 /* SPROM Revision 4 */
732 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
733 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
734 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
735 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
736 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
737 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
738 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
739 @@ -298,6 +302,46 @@
740 #define SSB_SPROM4_AGAIN2_SHIFT 0
741 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
742 #define SSB_SPROM4_AGAIN3_SHIFT 8
743 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
744 +#define SSB_SPROM4_TXPID2G0 0x00FF
745 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
746 +#define SSB_SPROM4_TXPID2G1 0xFF00
747 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
748 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
749 +#define SSB_SPROM4_TXPID2G2 0x00FF
750 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
751 +#define SSB_SPROM4_TXPID2G3 0xFF00
752 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
753 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
754 +#define SSB_SPROM4_TXPID5G0 0x00FF
755 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
756 +#define SSB_SPROM4_TXPID5G1 0xFF00
757 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
758 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
759 +#define SSB_SPROM4_TXPID5G2 0x00FF
760 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
761 +#define SSB_SPROM4_TXPID5G3 0xFF00
762 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
763 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
764 +#define SSB_SPROM4_TXPID5GL0 0x00FF
765 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
766 +#define SSB_SPROM4_TXPID5GL1 0xFF00
767 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
768 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
769 +#define SSB_SPROM4_TXPID5GL2 0x00FF
770 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
771 +#define SSB_SPROM4_TXPID5GL3 0xFF00
772 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
773 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
774 +#define SSB_SPROM4_TXPID5GH0 0x00FF
775 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
776 +#define SSB_SPROM4_TXPID5GH1 0xFF00
777 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
778 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
779 +#define SSB_SPROM4_TXPID5GH2 0x00FF
780 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
781 +#define SSB_SPROM4_TXPID5GH3 0xFF00
782 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
783 #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
784 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
785 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
786 @@ -317,6 +361,8 @@
787 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
788 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
789 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
790 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
791 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
792 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
793 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
794 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
795 --- a/drivers/ssb/driver_chipcommon.c
796 +++ b/drivers/ssb/driver_chipcommon.c
797 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
798 if (!ccdev)
799 return;
800 bus = ccdev->bus;
801 +
802 + /* We support SLOW only on 6..9 */
803 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
804 + mode = SSB_CLKMODE_DYNAMIC;
805 +
806 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
807 + return; /* PMU controls clockmode, separated function needed */
808 + SSB_WARN_ON(ccdev->id.revision >= 20);
809 +
810 /* chipcommon cores prior to rev6 don't support dynamic clock control */
811 if (ccdev->id.revision < 6)
812 return;
813 - /* chipcommon cores rev10 are a whole new ball game */
814 +
815 + /* ChipCommon cores rev10+ need testing */
816 if (ccdev->id.revision >= 10)
817 return;
818 +
819 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
820 return;
821
822 switch (mode) {
823 - case SSB_CLKMODE_SLOW:
824 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
825 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
826 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
827 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
828 break;
829 case SSB_CLKMODE_FAST:
830 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
831 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
832 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
833 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
834 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
835 + if (ccdev->id.revision < 10) {
836 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
837 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
838 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
839 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
840 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
841 + } else {
842 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
843 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
844 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
845 + /* udelay(150); TODO: not available in early init */
846 + }
847 break;
848 case SSB_CLKMODE_DYNAMIC:
849 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
850 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
851 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
852 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
853 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
854 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
855 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
856 -
857 - /* for dynamic control, we have to release our xtal_pu "force on" */
858 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
859 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
860 + if (ccdev->id.revision < 10) {
861 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
862 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
863 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
864 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
865 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
866 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
867 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
868 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
869 +
870 + /* For dynamic control, we have to release our xtal_pu
871 + * "force on" */
872 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
873 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
874 + } else {
875 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
876 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
877 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
878 + }
879 break;
880 default:
881 SSB_WARN_ON(1);
882 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
883 if (cc->dev->id.revision >= 11)
884 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
885 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
886 +
887 + if (cc->dev->id.revision >= 20) {
888 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
889 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
890 + }
891 +
892 ssb_pmu_init(cc);
893 chipco_powercontrol_init(cc);
894 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
895 --- a/drivers/ssb/driver_chipcommon_pmu.c
896 +++ b/drivers/ssb/driver_chipcommon_pmu.c
897 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
898 u32 min_msk = 0, max_msk = 0;
899 unsigned int i;
900 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
901 - unsigned int updown_tab_size;
902 + unsigned int updown_tab_size = 0;
903 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
904 - unsigned int depend_tab_size;
905 + unsigned int depend_tab_size = 0;
906
907 switch (bus->chip_id) {
908 case 0x4312:
909 + min_msk = 0xCBB;
910 + break;
911 case 0x4322:
912 /* We keep the default settings:
913 * min_msk = 0xCBB
914 --- a/drivers/ssb/driver_gige.c
915 +++ b/drivers/ssb/driver_gige.c
916 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
917 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
918 }
919
920 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
921 - int reg, int size, u32 *val)
922 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
923 + unsigned int devfn, int reg,
924 + int size, u32 *val)
925 {
926 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
927 unsigned long flags;
928 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
929 return PCIBIOS_SUCCESSFUL;
930 }
931
932 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
933 - int reg, int size, u32 val)
934 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
935 + unsigned int devfn, int reg,
936 + int size, u32 val)
937 {
938 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
939 unsigned long flags;
940 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
941 return PCIBIOS_SUCCESSFUL;
942 }
943
944 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
945 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
946 + const struct ssb_device_id *id)
947 {
948 struct ssb_gige *dev;
949 u32 base, tmslow, tmshigh;
950 --- a/drivers/ssb/driver_pcicore.c
951 +++ b/drivers/ssb/driver_pcicore.c
952 @@ -15,6 +15,11 @@
953
954 #include "ssb_private.h"
955
956 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
957 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
958 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
959 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
960 + u8 address, u16 data);
961
962 static inline
963 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
964 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
965 return ssb_mips_irq(extpci_core->dev) + 2;
966 }
967
968 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
969 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
970 {
971 u32 val;
972
973 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
974 register_pci_controller(&ssb_pcicore_controller);
975 }
976
977 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
978 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
979 {
980 struct ssb_bus *bus = pc->dev->bus;
981 u16 chipid_top;
982 @@ -403,25 +408,133 @@ static int pcicore_is_in_hostmode(struct
983 }
984 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
985
986 +/**************************************************
987 + * Workarounds.
988 + **************************************************/
989 +
990 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
991 +{
992 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
993 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
994 + tmp &= ~0xF000;
995 + tmp |= (pc->dev->core_index << 12);
996 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
997 + }
998 +}
999 +
1000 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
1001 +{
1002 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1003 +}
1004 +
1005 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
1006 +{
1007 + const u8 serdes_pll_device = 0x1D;
1008 + const u8 serdes_rx_device = 0x1F;
1009 + u16 tmp;
1010 +
1011 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1012 + ssb_pcicore_polarity_workaround(pc));
1013 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1014 + if (tmp & 0x4000)
1015 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1016 +}
1017 +
1018 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
1019 +{
1020 + struct ssb_device *pdev = pc->dev;
1021 + struct ssb_bus *bus = pdev->bus;
1022 + u32 tmp;
1023 +
1024 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1025 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
1026 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
1027 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1028 +
1029 + if (pdev->id.revision < 5) {
1030 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
1031 + tmp &= ~SSB_IMCFGLO_SERTO;
1032 + tmp |= 2;
1033 + tmp &= ~SSB_IMCFGLO_REQTO;
1034 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1035 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
1036 + ssb_commit_settings(bus);
1037 + } else if (pdev->id.revision >= 11) {
1038 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1039 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
1040 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1041 + }
1042 +}
1043 +
1044 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
1045 +{
1046 + u32 tmp;
1047 + u8 rev = pc->dev->id.revision;
1048 +
1049 + if (rev == 0 || rev == 1) {
1050 + /* TLP Workaround register. */
1051 + tmp = ssb_pcie_read(pc, 0x4);
1052 + tmp |= 0x8;
1053 + ssb_pcie_write(pc, 0x4, tmp);
1054 + }
1055 + if (rev == 1) {
1056 + /* DLLP Link Control register. */
1057 + tmp = ssb_pcie_read(pc, 0x100);
1058 + tmp |= 0x40;
1059 + ssb_pcie_write(pc, 0x100, tmp);
1060 + }
1061 +
1062 + if (rev == 0) {
1063 + const u8 serdes_rx_device = 0x1F;
1064 +
1065 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1066 + 2 /* Timer */, 0x8128);
1067 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1068 + 6 /* CDR */, 0x0100);
1069 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1070 + 7 /* CDR BW */, 0x1466);
1071 + } else if (rev == 3 || rev == 4 || rev == 5) {
1072 + /* TODO: DLLP Power Management Threshold */
1073 + ssb_pcicore_serdes_workaround(pc);
1074 + /* TODO: ASPM */
1075 + } else if (rev == 7) {
1076 + /* TODO: No PLL down */
1077 + }
1078 +
1079 + if (rev >= 6) {
1080 + /* Miscellaneous Configuration Fixup */
1081 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
1082 + if (!(tmp & 0x8000))
1083 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
1084 + tmp | 0x8000);
1085 + }
1086 +}
1087
1088 /**************************************************
1089 * Generic and Clientmode operation code.
1090 **************************************************/
1091
1092 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1093 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1094 {
1095 + ssb_pcicore_fix_sprom_core_index(pc);
1096 +
1097 /* Disable PCI interrupts. */
1098 ssb_write32(pc->dev, SSB_INTVEC, 0);
1099 +
1100 + /* Additional PCIe always once-executed workarounds */
1101 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
1102 + ssb_pcicore_serdes_workaround(pc);
1103 + /* TODO: ASPM */
1104 + /* TODO: Clock Request Update */
1105 + }
1106 }
1107
1108 -void ssb_pcicore_init(struct ssb_pcicore *pc)
1109 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
1110 {
1111 struct ssb_device *dev = pc->dev;
1112 - struct ssb_bus *bus;
1113
1114 if (!dev)
1115 return;
1116 - bus = dev->bus;
1117 if (!ssb_device_is_enabled(dev))
1118 ssb_device_enable(dev, 0);
1119
1120 @@ -446,11 +559,35 @@ static void ssb_pcie_write(struct ssb_pc
1121 pcicore_write32(pc, 0x134, data);
1122 }
1123
1124 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1125 - u8 address, u16 data)
1126 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
1127 +{
1128 + const u16 mdio_control = 0x128;
1129 + const u16 mdio_data = 0x12C;
1130 + u32 v;
1131 + int i;
1132 +
1133 + v = (1 << 30); /* Start of Transaction */
1134 + v |= (1 << 28); /* Write Transaction */
1135 + v |= (1 << 17); /* Turnaround */
1136 + v |= (0x1F << 18);
1137 + v |= (phy << 4);
1138 + pcicore_write32(pc, mdio_data, v);
1139 +
1140 + udelay(10);
1141 + for (i = 0; i < 200; i++) {
1142 + v = pcicore_read32(pc, mdio_control);
1143 + if (v & 0x100 /* Trans complete */)
1144 + break;
1145 + msleep(1);
1146 + }
1147 +}
1148 +
1149 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
1150 {
1151 const u16 mdio_control = 0x128;
1152 const u16 mdio_data = 0x12C;
1153 + int max_retries = 10;
1154 + u16 ret = 0;
1155 u32 v;
1156 int i;
1157
1158 @@ -458,46 +595,68 @@ static void ssb_pcie_mdio_write(struct s
1159 v |= 0x2; /* MDIO Clock Divisor */
1160 pcicore_write32(pc, mdio_control, v);
1161
1162 + if (pc->dev->id.revision >= 10) {
1163 + max_retries = 200;
1164 + ssb_pcie_mdio_set_phy(pc, device);
1165 + }
1166 +
1167 v = (1 << 30); /* Start of Transaction */
1168 - v |= (1 << 28); /* Write Transaction */
1169 + v |= (1 << 29); /* Read Transaction */
1170 v |= (1 << 17); /* Turnaround */
1171 - v |= (u32)device << 22;
1172 + if (pc->dev->id.revision < 10)
1173 + v |= (u32)device << 22;
1174 v |= (u32)address << 18;
1175 - v |= data;
1176 pcicore_write32(pc, mdio_data, v);
1177 /* Wait for the device to complete the transaction */
1178 udelay(10);
1179 - for (i = 0; i < 10; i++) {
1180 + for (i = 0; i < max_retries; i++) {
1181 v = pcicore_read32(pc, mdio_control);
1182 - if (v & 0x100 /* Trans complete */)
1183 + if (v & 0x100 /* Trans complete */) {
1184 + udelay(10);
1185 + ret = pcicore_read32(pc, mdio_data);
1186 break;
1187 + }
1188 msleep(1);
1189 }
1190 pcicore_write32(pc, mdio_control, 0);
1191 + return ret;
1192 }
1193
1194 -static void ssb_broadcast_value(struct ssb_device *dev,
1195 - u32 address, u32 data)
1196 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1197 + u8 address, u16 data)
1198 {
1199 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1200 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1201 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1202 + const u16 mdio_control = 0x128;
1203 + const u16 mdio_data = 0x12C;
1204 + int max_retries = 10;
1205 + u32 v;
1206 + int i;
1207
1208 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1209 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1210 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1211 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1212 -}
1213 + v = 0x80; /* Enable Preamble Sequence */
1214 + v |= 0x2; /* MDIO Clock Divisor */
1215 + pcicore_write32(pc, mdio_control, v);
1216
1217 -static void ssb_commit_settings(struct ssb_bus *bus)
1218 -{
1219 - struct ssb_device *dev;
1220 + if (pc->dev->id.revision >= 10) {
1221 + max_retries = 200;
1222 + ssb_pcie_mdio_set_phy(pc, device);
1223 + }
1224
1225 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1226 - if (WARN_ON(!dev))
1227 - return;
1228 - /* This forces an update of the cached registers. */
1229 - ssb_broadcast_value(dev, 0xFD8, 0);
1230 + v = (1 << 30); /* Start of Transaction */
1231 + v |= (1 << 28); /* Write Transaction */
1232 + v |= (1 << 17); /* Turnaround */
1233 + if (pc->dev->id.revision < 10)
1234 + v |= (u32)device << 22;
1235 + v |= (u32)address << 18;
1236 + v |= data;
1237 + pcicore_write32(pc, mdio_data, v);
1238 + /* Wait for the device to complete the transaction */
1239 + udelay(10);
1240 + for (i = 0; i < max_retries; i++) {
1241 + v = pcicore_read32(pc, mdio_control);
1242 + if (v & 0x100 /* Trans complete */)
1243 + break;
1244 + msleep(1);
1245 + }
1246 + pcicore_write32(pc, mdio_control, 0);
1247 }
1248
1249 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1250 @@ -550,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1251 if (pc->setup_done)
1252 goto out;
1253 if (pdev->id.coreid == SSB_DEV_PCI) {
1254 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1255 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1256 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1257 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1258 -
1259 - if (pdev->id.revision < 5) {
1260 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1261 - tmp &= ~SSB_IMCFGLO_SERTO;
1262 - tmp |= 2;
1263 - tmp &= ~SSB_IMCFGLO_REQTO;
1264 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1265 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1266 - ssb_commit_settings(bus);
1267 - } else if (pdev->id.revision >= 11) {
1268 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1269 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1270 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1271 - }
1272 + ssb_pcicore_pci_setup_workarounds(pc);
1273 } else {
1274 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1275 - //TODO: Better make defines for all these magic PCIE values.
1276 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1277 - /* TLP Workaround register. */
1278 - tmp = ssb_pcie_read(pc, 0x4);
1279 - tmp |= 0x8;
1280 - ssb_pcie_write(pc, 0x4, tmp);
1281 - }
1282 - if (pdev->id.revision == 0) {
1283 - const u8 serdes_rx_device = 0x1F;
1284 -
1285 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1286 - 2 /* Timer */, 0x8128);
1287 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1288 - 6 /* CDR */, 0x0100);
1289 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1290 - 7 /* CDR BW */, 0x1466);
1291 - } else if (pdev->id.revision == 1) {
1292 - /* DLLP Link Control register. */
1293 - tmp = ssb_pcie_read(pc, 0x100);
1294 - tmp |= 0x40;
1295 - ssb_pcie_write(pc, 0x100, tmp);
1296 - }
1297 + ssb_pcicore_pcie_setup_workarounds(pc);
1298 }
1299 pc->setup_done = 1;
1300 out:
1301 --- a/drivers/ssb/sprom.c
1302 +++ b/drivers/ssb/sprom.c
1303 @@ -17,7 +17,7 @@
1304 #include <linux/slab.h>
1305
1306
1307 -static const struct ssb_sprom *fallback_sprom;
1308 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1309
1310
1311 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1312 @@ -145,36 +145,43 @@ out:
1313 }
1314
1315 /**
1316 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1317 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1318 + * fallback SPROM if no SPROM is found.
1319 *
1320 - * @sprom: The SPROM data structure to register.
1321 + * @sprom_callback: The callback function.
1322 *
1323 - * With this function the architecture implementation may register a fallback
1324 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1325 - * where no valid SPROM can be found in the shadow registers.
1326 + * With this function the architecture implementation may register a
1327 + * callback handler which fills the SPROM data structure. The fallback is
1328 + * only used for PCI based SSB devices, where no valid SPROM can be found
1329 + * in the shadow registers.
1330 *
1331 - * This function is useful for weird architectures that have a half-assed SSB device
1332 - * hardwired to their PCI bus.
1333 + * This function is useful for weird architectures that have a half-assed
1334 + * SSB device hardwired to their PCI bus.
1335 *
1336 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1337 - * don't use this fallback.
1338 - * Architectures must provide the SPROM for native SSB devices anyway,
1339 - * so the fallback also isn't used for native devices.
1340 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1341 + * devices currently don't use this fallback.
1342 + * Architectures must provide the SPROM for native SSB devices anyway, so
1343 + * the fallback also isn't used for native devices.
1344 *
1345 - * This function is available for architecture code, only. So it is not exported.
1346 + * This function is available for architecture code, only. So it is not
1347 + * exported.
1348 */
1349 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1350 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1351 + struct ssb_sprom *out))
1352 {
1353 - if (fallback_sprom)
1354 + if (get_fallback_sprom)
1355 return -EEXIST;
1356 - fallback_sprom = sprom;
1357 + get_fallback_sprom = sprom_callback;
1358
1359 return 0;
1360 }
1361
1362 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1363 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1364 {
1365 - return fallback_sprom;
1366 + if (!get_fallback_sprom)
1367 + return -ENOENT;
1368 +
1369 + return get_fallback_sprom(bus, out);
1370 }
1371
1372 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1373 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
1374 /* this routine differs from specs as we do not access SPROM directly
1375 on PCMCIA */
1376 if (bus->bustype == SSB_BUSTYPE_PCI &&
1377 - bus->chipco.dev && /* can be unavailible! */
1378 + bus->chipco.dev && /* can be unavailable! */
1379 bus->chipco.dev->id.revision >= 31)
1380 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1381
1382 --- a/drivers/ssb/ssb_private.h
1383 +++ b/drivers/ssb/ssb_private.h
1384 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1385 const char *buf, size_t count,
1386 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1387 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1388 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1389 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1390 + struct ssb_sprom *out);
1391
1392
1393 /* core.c */
1394 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1395 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1396 @@ -123,6 +123,8 @@
1397 #define SSB_CHIPCO_FLASHDATA 0x0048
1398 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1399 #define SSB_CHIPCO_BCAST_DATA 0x0054
1400 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1401 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1402 #define SSB_CHIPCO_GPIOIN 0x0060
1403 #define SSB_CHIPCO_GPIOOUT 0x0064
1404 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1405 @@ -131,6 +133,9 @@
1406 #define SSB_CHIPCO_GPIOIRQ 0x0074
1407 #define SSB_CHIPCO_WATCHDOG 0x0080
1408 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1409 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1410 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1411 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1412 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1413 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1414 #define SSB_CHIPCO_CLOCK_N 0x0090
1415 @@ -189,8 +194,10 @@
1416 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1417 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1418 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1419 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1420 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1421 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1422 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1423 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1424 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1425 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1426 #define SSB_CHIPCO_UART0_DATA 0x0300
1427 #define SSB_CHIPCO_UART0_IMR 0x0304
Personal OpenWRT clone
This page took 0.101616 seconds and 5 git commands to generate.