[ar71xx] use SoC specific irq dispatch code
[openwrt.git] / target / linux / brcm47xx / patches-2.6.23 / 621-ssb-common-gpio-api.patch
1 --- a/drivers/ssb/driver_chipcommon.c
2 +++ b/drivers/ssb/driver_chipcommon.c
3 @@ -361,37 +361,31 @@
4 {
5 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
6 }
7 -EXPORT_SYMBOL(ssb_chipco_gpio_in);
8
9 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
10 {
11 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
12 }
13 -EXPORT_SYMBOL(ssb_chipco_gpio_out);
14
15 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
16 {
17 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
18 }
19 -EXPORT_SYMBOL(ssb_chipco_gpio_outen);
20
21 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
22 {
23 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
24 }
25 -EXPORT_SYMBOL(ssb_chipco_gpio_control);
26
27 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
28 {
29 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
30 }
31 -EXPORT_SYMBOL(ssb_chipco_gpio_intmask);
32
33 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
34 {
35 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
36 }
37 -EXPORT_SYMBOL(ssb_chipco_gpio_polarity);
38
39 #ifdef CONFIG_SSB_SERIAL
40 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
41 --- a/drivers/ssb/driver_extif.c
42 +++ b/drivers/ssb/driver_extif.c
43 @@ -122,30 +122,25 @@
44 {
45 return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask;
46 }
47 -EXPORT_SYMBOL(ssb_extif_gpio_in);
48
49 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
50 {
51 return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
52 mask, value);
53 }
54 -EXPORT_SYMBOL(ssb_extif_gpio_out);
55
56 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
57 {
58 return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
59 mask, value);
60 }
61 -EXPORT_SYMBOL(ssb_extif_gpio_outen);
62
63 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
64 {
65 return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
66 }
67 -EXPORT_SYMBOL(ssb_extif_gpio_polarity);
68
69 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
70 {
71 return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
72 }
73 -EXPORT_SYMBOL(ssb_extif_gpio_intmask);
74 --- a/drivers/ssb/embedded.c
75 +++ b/drivers/ssb/embedded.c
76 @@ -11,6 +11,8 @@
77 #include <linux/ssb/ssb.h>
78 #include <linux/ssb/ssb_embedded.h>
79
80 +#include "ssb_private.h"
81 +
82
83 int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks)
84 {
85 @@ -24,3 +26,107 @@
86 }
87 return -ENODEV;
88 }
89 +
90 +u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
91 +{
92 + unsigned long flags;
93 + u32 res = 0;
94 +
95 + spin_lock_irqsave(&bus->gpio_lock, flags);
96 + if (ssb_chipco_available(&bus->chipco))
97 + res = ssb_chipco_gpio_in(&bus->chipco, mask);
98 + else if (ssb_extif_available(&bus->extif))
99 + res = ssb_extif_gpio_in(&bus->extif, mask);
100 + else
101 + SSB_WARN_ON(1);
102 + spin_unlock_irqrestore(&bus->gpio_lock, flags);
103 +
104 + return res;
105 +}
106 +EXPORT_SYMBOL(ssb_gpio_in);
107 +
108 +u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value)
109 +{
110 + unsigned long flags;
111 + u32 res = 0;
112 +
113 + spin_lock_irqsave(&bus->gpio_lock, flags);
114 + if (ssb_chipco_available(&bus->chipco))
115 + res = ssb_chipco_gpio_out(&bus->chipco, mask, value);
116 + else if (ssb_extif_available(&bus->extif))
117 + res = ssb_extif_gpio_out(&bus->extif, mask, value);
118 + else
119 + SSB_WARN_ON(1);
120 + spin_unlock_irqrestore(&bus->gpio_lock, flags);
121 +
122 + return res;
123 +}
124 +EXPORT_SYMBOL(ssb_gpio_out);
125 +
126 +u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value)
127 +{
128 + unsigned long flags;
129 + u32 res = 0;
130 +
131 + spin_lock_irqsave(&bus->gpio_lock, flags);
132 + if (ssb_chipco_available(&bus->chipco))
133 + res = ssb_chipco_gpio_outen(&bus->chipco, mask, value);
134 + else if (ssb_extif_available(&bus->extif))
135 + res = ssb_extif_gpio_outen(&bus->extif, mask, value);
136 + else
137 + SSB_WARN_ON(1);
138 + spin_unlock_irqrestore(&bus->gpio_lock, flags);
139 +
140 + return res;
141 +}
142 +EXPORT_SYMBOL(ssb_gpio_outen);
143 +
144 +u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value)
145 +{
146 + unsigned long flags;
147 + u32 res = 0;
148 +
149 + spin_lock_irqsave(&bus->gpio_lock, flags);
150 + if (ssb_chipco_available(&bus->chipco))
151 + res = ssb_chipco_gpio_control(&bus->chipco, mask, value);
152 + spin_unlock_irqrestore(&bus->gpio_lock, flags);
153 +
154 + return res;
155 +}
156 +EXPORT_SYMBOL(ssb_gpio_control);
157 +
158 +u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value)
159 +{
160 + unsigned long flags;
161 + u32 res = 0;
162 +
163 + spin_lock_irqsave(&bus->gpio_lock, flags);
164 + if (ssb_chipco_available(&bus->chipco))
165 + res = ssb_chipco_gpio_intmask(&bus->chipco, mask, value);
166 + else if (ssb_extif_available(&bus->extif))
167 + res = ssb_extif_gpio_intmask(&bus->extif, mask, value);
168 + else
169 + SSB_WARN_ON(1);
170 + spin_unlock_irqrestore(&bus->gpio_lock, flags);
171 +
172 + return res;
173 +}
174 +EXPORT_SYMBOL(ssb_gpio_intmask);
175 +
176 +u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value)
177 +{
178 + unsigned long flags;
179 + u32 res = 0;
180 +
181 + spin_lock_irqsave(&bus->gpio_lock, flags);
182 + if (ssb_chipco_available(&bus->chipco))
183 + res = ssb_chipco_gpio_polarity(&bus->chipco, mask, value);
184 + else if (ssb_extif_available(&bus->extif))
185 + res = ssb_extif_gpio_polarity(&bus->extif, mask, value);
186 + else
187 + SSB_WARN_ON(1);
188 + spin_unlock_irqrestore(&bus->gpio_lock, flags);
189 +
190 + return res;
191 +}
192 +EXPORT_SYMBOL(ssb_gpio_polarity);
193 --- a/include/linux/ssb/ssb.h
194 +++ b/include/linux/ssb/ssb.h
195 @@ -283,6 +283,11 @@
196 /* Contents of the SPROM. */
197 struct ssb_sprom sprom;
198
199 +#ifdef CONFIG_SSB_EMBEDDED
200 + /* Lock for GPIO register access. */
201 + spinlock_t gpio_lock;
202 +#endif /* EMBEDDED */
203 +
204 /* Internal-only stuff follows. Do not touch. */
205 struct list_head list;
206 #ifdef CONFIG_SSB_DEBUG
207 --- a/include/linux/ssb/ssb_embedded.h
208 +++ b/include/linux/ssb/ssb_embedded.h
209 @@ -7,4 +7,12 @@
210
211 extern int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks);
212
213 +/* Generic GPIO API */
214 +u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask);
215 +u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value);
216 +u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value);
217 +u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value);
218 +u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value);
219 +u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value);
220 +
221 #endif /* LINUX_SSB_EMBEDDED_H_ */
222 --- a/drivers/ssb/main.c
223 +++ b/drivers/ssb/main.c
224 @@ -571,6 +571,9 @@
225
226 spin_lock_init(&bus->bar_lock);
227 INIT_LIST_HEAD(&bus->list);
228 +#ifdef CONFIG_SSB_EMBEDDED
229 + spin_lock_init(&bus->gpio_lock);
230 +#endif
231
232 /* Powerup the bus */
233 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
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