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[kernel] make 64-bits MIPS kernel compile again on arch/mips/kernel/module.c
[openwrt.git] / target / linux / ifxmips / files / drivers / char / ifxmips_ssc.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 *
16 * Copyright(C) 2006 infineon
17 * Copyright(C) 2007 John Crispin <blogic@openwrt.org>
18 *
19 */
20
21 /*
22 ### TO DO: general issues:
23 - power management
24 - interrupt handling (direct/indirect)
25 - pin/mux-handling (just overall concept due to project dependency)
26 - multiple instances capability
27 - slave functionality
28 */
29
30 #include <linux/module.h>
31 #include <linux/errno.h>
32 #include <linux/signal.h>
33 #include <linux/sched.h>
34 #include <linux/timer.h>
35 #include <linux/interrupt.h>
36 #include <linux/major.h>
37 #include <linux/string.h>
38 #include <linux/fs.h>
39 #include <linux/fcntl.h>
40 #include <linux/ptrace.h>
41 #include <linux/mm.h>
42 #include <linux/ioport.h>
43 #include <linux/init.h>
44 #include <linux/delay.h>
45 #include <linux/spinlock.h>
46 #include <linux/slab.h>
47 #include <linux/io.h>
48 #include <linux/irq.h>
49 #include <linux/uaccess.h>
50 #include <linux/bitops.h>
51
52 #include <linux/types.h>
53 #include <linux/kernel.h>
54 #include <linux/version.h>
55
56 #include <asm/system.h>
57 #include <asm/ifxmips/ifxmips.h>
58 #include <asm/ifxmips/ifxmips_irq.h>
59 #include <asm/ifxmips/ifx_ssc_defines.h>
60 #include <asm/ifxmips/ifx_ssc.h>
61
62 /* allow the user to set the major device number */
63 static int maj;
64
65 /*
66 * This is the per-channel data structure containing pointers, flags
67 * and variables for the port. This driver supports a maximum of PORT_CNT.
68 * isp is allocated in ifx_ssc_init() based on the chip version.
69 */
70 static struct ifx_ssc_port *isp;
71
72 /* other forward declarations */
73 static unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info);
74 static void tx_int(struct ifx_ssc_port *);
75
76 extern unsigned int ifxmips_get_fpi_hz(void);
77 extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr);
78
79 static inline unsigned int ifx_ssc_get_kernel_clk(struct ifx_ssc_port *info)
80 {
81 unsigned int rmc;
82
83 rmc = (ifxmips_r32(IFXMIPS_SSC_CLC) & IFX_CLC_RUN_DIVIDER_MASK) >> IFX_CLC_RUN_DIVIDER_OFFSET;
84 if (rmc == 0) {
85 printk("ifx_ssc_get_kernel_clk rmc==0 \n");
86 return 0;
87 }
88 return ifxmips_get_fpi_hz() / rmc;
89 }
90
91 static inline void rx_int(struct ifx_ssc_port *info)
92 {
93 int fifo_fill_lev, bytes_in_buf, i;
94 unsigned long tmp_val;
95 unsigned long *tmp_ptr;
96 unsigned int rx_valid_cnt;
97 /* number of words waiting in the RX FIFO */
98 fifo_fill_lev = (ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_RECEIVED_WORDS_MASK) >> IFX_SSC_FSTAT_RECEIVED_WORDS_OFFSET;
99 bytes_in_buf = info->rxbuf_end - info->rxbuf_ptr;
100 /* transfer with 32 bits per entry */
101 while ((bytes_in_buf >= 4) && (fifo_fill_lev > 0)) {
102 tmp_ptr = (unsigned long *)info->rxbuf_ptr;
103 *tmp_ptr = ifxmips_r32(IFXMIPS_SSC_RB);
104 info->rxbuf_ptr += 4;
105 info->stats.rxBytes += 4;
106 fifo_fill_lev--;
107 bytes_in_buf -= 4;
108 }
109
110 /* now do the rest as mentioned in STATE.RXBV */
111 while ((bytes_in_buf > 0) && (fifo_fill_lev > 0)) {
112 rx_valid_cnt = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_RX_BYTE_VALID_MASK) >> IFX_SSC_STATE_RX_BYTE_VALID_OFFSET;
113 if (rx_valid_cnt == 0)
114 break;
115
116 if (rx_valid_cnt > bytes_in_buf)
117 rx_valid_cnt = bytes_in_buf;
118
119 tmp_val = ifxmips_r32(IFXMIPS_SSC_RB);
120
121 for (i = 0; i < rx_valid_cnt; i++) {
122 *info->rxbuf_ptr = (tmp_val >> (8 * (rx_valid_cnt - i - 1))) & 0xff;
123 bytes_in_buf--;
124 info->rxbuf_ptr++;
125 }
126 info->stats.rxBytes += rx_valid_cnt;
127 }
128
129 /* check if transfer is complete */
130 if (info->rxbuf_ptr >= info->rxbuf_end) {
131 disable_irq(IFXMIPS_SSC_RIR);
132 wake_up_interruptible(&info->rwait);
133 } else if ((info->opts.modeRxTx == IFX_SSC_MODE_RX) && (ifxmips_r32(IFXMIPS_SSC_RXCNT) == 0)) {
134 if (info->rxbuf_end - info->rxbuf_ptr < IFX_SSC_RXREQ_BLOCK_SIZE)
135 ifxmips_w32((info->rxbuf_end - info->rxbuf_ptr) << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
136 else
137 ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
138 }
139 }
140
141 static inline void tx_int(struct ifx_ssc_port *info)
142 {
143
144 int fifo_space, fill, i;
145 fifo_space = ((ifxmips_r32(IFXMIPS_SSC_ID) & IFX_SSC_PERID_TXFS_MASK) >> IFX_SSC_PERID_TXFS_OFFSET)
146 -((ifxmips_r32(IFXMIPS_SSC_FSTAT) & IFX_SSC_FSTAT_TRANSMIT_WORDS_MASK) >> IFX_SSC_FSTAT_TRANSMIT_WORDS_OFFSET);
147
148 if (fifo_space == 0)
149 return;
150
151 fill = info->txbuf_end - info->txbuf_ptr;
152
153 if (fill > fifo_space * 4)
154 fill = fifo_space * 4;
155
156 for (i = 0; i < fill / 4; i++) {
157 /* at first 32 bit access */
158 ifxmips_w32(*(UINT32 *)info->txbuf_ptr, IFXMIPS_SSC_TB);
159 info->txbuf_ptr += 4;
160 }
161
162 fifo_space -= fill / 4;
163 info->stats.txBytes += fill & ~0x3;
164 fill &= 0x3;
165 if ((fifo_space > 0) & (fill > 1)) {
166 /* trailing 16 bit access */
167 WRITE_PERIPHERAL_REGISTER_16(*(UINT16 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
168 info->txbuf_ptr += 2;
169 info->stats.txBytes += 2;
170 fifo_space--;
171 fill -= 2;
172 }
173
174 if ((fifo_space > 0) & (fill > 0)) {
175 /* trailing 8 bit access */
176 WRITE_PERIPHERAL_REGISTER_8(*(UINT8 *)info->txbuf_ptr, info->mapbase + IFX_SSC_TB);
177 info->txbuf_ptr++;
178 info->stats.txBytes++;
179 }
180
181 /* check if transmission complete */
182 if (info->txbuf_ptr >= info->txbuf_end) {
183 disable_irq(IFXMIPS_SSC_TIR);
184 kfree(info->txbuf);
185 info->txbuf = NULL;
186 }
187
188 }
189
190 irqreturn_t ifx_ssc_rx_int(int irq, void *dev_id)
191 {
192 struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
193 rx_int(info);
194
195 return IRQ_HANDLED;
196 }
197
198 irqreturn_t ifx_ssc_tx_int(int irq, void *dev_id)
199 {
200 struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
201 tx_int(info);
202
203 return IRQ_HANDLED;
204 }
205
206 irqreturn_t ifx_ssc_err_int(int irq, void *dev_id)
207 {
208 struct ifx_ssc_port *info = (struct ifx_ssc_port *)dev_id;
209 unsigned int state;
210 unsigned int write_back = 0;
211 unsigned long flags;
212
213 local_irq_save(flags);
214 state = ifxmips_r32(IFXMIPS_SSC_STATE);
215
216 if ((state & IFX_SSC_STATE_RX_UFL) != 0) {
217 info->stats.rxUnErr++;
218 write_back |= IFX_SSC_WHBSTATE_CLR_RX_UFL_ERROR;
219 }
220
221 if ((state & IFX_SSC_STATE_RX_OFL) != 0) {
222 info->stats.rxOvErr++;
223 write_back |= IFX_SSC_WHBSTATE_CLR_RX_OFL_ERROR;
224 }
225
226 if ((state & IFX_SSC_STATE_TX_OFL) != 0) {
227 info->stats.txOvErr++;
228 write_back |= IFX_SSC_WHBSTATE_CLR_TX_OFL_ERROR;
229 }
230
231 if ((state & IFX_SSC_STATE_TX_UFL) != 0) {
232 info->stats.txUnErr++;
233 write_back |= IFX_SSC_WHBSTATE_CLR_TX_UFL_ERROR;
234 }
235
236 if ((state & IFX_SSC_STATE_MODE_ERR) != 0) {
237 info->stats.modeErr++;
238 write_back |= IFX_SSC_WHBSTATE_CLR_MODE_ERROR;
239 }
240
241 if (write_back)
242 ifxmips_w32(write_back, IFXMIPS_SSC_WHBSTATE);
243
244 local_irq_restore(flags);
245
246 return IRQ_HANDLED;
247 }
248
249 static void ifx_ssc_abort(struct ifx_ssc_port *info)
250 {
251 unsigned long flags;
252 bool enabled;
253
254 local_irq_save(flags);
255
256 disable_irq(IFXMIPS_SSC_RIR);
257 disable_irq(IFXMIPS_SSC_TIR);
258 disable_irq(IFXMIPS_SSC_EIR);
259
260 local_irq_restore(flags);
261
262 /* disable SSC(also aborts a receive request!) */
263 /* ### TO DO: Perhaps it's better to abort after the receiption of a
264 complete word. The disable cuts the transmission immediatly and
265 releases the chip selects. This could result in unpredictable
266 behavior of connected external devices!
267 */
268 enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED) != 0;
269 ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
270
271 /* flush fifos */
272 ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_TXFCON);
273 ifxmips_w32(IFX_SSC_XFCON_FIFO_FLUSH, IFXMIPS_SSC_RXFCON);
274
275 /* free txbuf */
276 if (info->txbuf != NULL) {
277 kfree(info->txbuf);
278 info->txbuf = NULL;
279 }
280
281 /* wakeup read process */
282 if (info->rxbuf != NULL)
283 wake_up_interruptible(&info->rwait);
284
285 /* clear pending int's */
286 ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR);
287 ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR);
288 ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR);
289
290 /* clear error flags */
291 ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
292
293 if (enabled)
294 ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
295
296 }
297
298 /*
299 * This routine is called whenever a port is opened. It enforces
300 * exclusive opening of a port and enables interrupts, etc.
301 */
302 int ifx_ssc_open(struct inode *inode, struct file *filp)
303 {
304 struct ifx_ssc_port *info;
305 int line;
306 int from_kernel = 0;
307
308 if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) {
309 from_kernel = 1;
310 line = (int) inode;
311 } else
312 line = MINOR(filp->f_dentry->d_inode->i_rdev);
313
314 /* don't open more minor devices than we can support */
315 if (line < 0 || line >= PORT_CNT)
316 return -ENXIO;
317
318 info = &isp[line];
319
320 /* exclusive open */
321 if (info->port_is_open != 0)
322 return -EBUSY;
323 info->port_is_open++;
324
325 disable_irq(IFXMIPS_SSC_RIR);
326 disable_irq(IFXMIPS_SSC_TIR);
327 disable_irq(IFXMIPS_SSC_EIR);
328
329 /* Flush and enable TX/RX FIFO */
330 ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
331 ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_FLUSH | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
332
333 /* logically flush the software FIFOs */
334 info->rxbuf_ptr = 0;
335 info->txbuf_ptr = 0;
336
337 /* clear all error bits */
338 ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ALL_ERROR, IFXMIPS_SSC_WHBSTATE);
339
340 /* clear pending interrupts */
341 ifxmips_mask_and_ack_irq(IFXMIPS_SSC_RIR);
342 ifxmips_mask_and_ack_irq(IFXMIPS_SSC_TIR);
343 ifxmips_mask_and_ack_irq(IFXMIPS_SSC_EIR);
344
345 ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
346
347 return 0;
348 }
349 EXPORT_SYMBOL(ifx_ssc_open);
350
351 int ifx_ssc_close(struct inode *inode, struct file *filp)
352 {
353 struct ifx_ssc_port *info;
354 int idx;
355
356 if ((inode == (struct inode *)0) || (inode == (struct inode *)1))
357 idx = (int) inode;
358 else
359 idx = MINOR(filp->f_dentry->d_inode->i_rdev);
360
361 if (idx < 0 || idx >= PORT_CNT)
362 return -ENXIO;
363
364 info = &isp[idx];
365 if (!info)
366 return -ENXIO;
367
368 ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
369
370 ifx_ssc_abort(info);
371
372 info->port_is_open--;
373
374 return 0;
375 }
376 EXPORT_SYMBOL(ifx_ssc_close);
377
378 static ssize_t ifx_ssc_read_helper_poll(struct ifx_ssc_port *info, char *buf,
379 size_t len, int from_kernel)
380 {
381 ssize_t ret_val;
382 unsigned long flags;
383
384 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
385 return -EFAULT;
386 local_irq_save(flags);
387 info->rxbuf_ptr = info->rxbuf;
388 info->rxbuf_end = info->rxbuf + len;
389 local_irq_restore(flags);
390 /* Vinetic driver always works in IFX_SSC_MODE_RXTX */
391 /* TXRX in poll mode */
392 while (info->rxbuf_ptr < info->rxbuf_end) {
393 if (info->txbuf_ptr < info->txbuf_end)
394 tx_int(info);
395
396 rx_int(info);
397 };
398
399 ret_val = info->rxbuf_ptr - info->rxbuf;
400
401 return ret_val;
402 }
403
404 static ssize_t ifx_ssc_read_helper(struct ifx_ssc_port *info, char *buf,
405 size_t len, int from_kernel)
406 {
407 ssize_t ret_val;
408 unsigned long flags;
409 DECLARE_WAITQUEUE(wait, current);
410
411 if (info->opts.modeRxTx == IFX_SSC_MODE_TX)
412 return -EFAULT;
413
414 local_irq_save(flags);
415 info->rxbuf_ptr = info->rxbuf;
416 info->rxbuf_end = info->rxbuf + len;
417
418 if (info->opts.modeRxTx == IFX_SSC_MODE_RXTX) {
419 if ((info->txbuf == NULL) || (info->txbuf != info->txbuf_ptr) || (info->txbuf_end != len + info->txbuf)) {
420 local_irq_restore(flags);
421 printk("IFX SSC - %s: write must be called before calling " "read in combined RX/TX!\n", __func__);
422 return -EFAULT;
423 }
424
425 local_irq_restore(flags);
426 tx_int(info);
427
428 if (info->txbuf_ptr < info->txbuf_end)
429 enable_irq(IFXMIPS_SSC_TIR);
430
431 enable_irq(IFXMIPS_SSC_RIR);
432 } else {
433 local_irq_restore(flags);
434 if (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK)
435 return -EBUSY;
436 enable_irq(IFXMIPS_SSC_RIR);
437 if (len < IFX_SSC_RXREQ_BLOCK_SIZE)
438 ifxmips_w32(len << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
439 else
440 ifxmips_w32(IFX_SSC_RXREQ_BLOCK_SIZE << IFX_SSC_RXREQ_RXCOUNT_OFFSET, IFXMIPS_SSC_RXREQ);
441 }
442
443 __add_wait_queue(&info->rwait, &wait);
444 set_current_state(TASK_INTERRUPTIBLE);
445
446 do {
447 local_irq_save(flags);
448 if (info->rxbuf_ptr >= info->rxbuf_end)
449 break;
450
451 local_irq_restore(flags);
452
453 if (signal_pending(current)) {
454 ret_val = -ERESTARTSYS;
455 goto out;
456 }
457 schedule();
458 } while (1);
459
460 ret_val = info->rxbuf_ptr - info->rxbuf;
461 local_irq_restore(flags);
462
463 out:
464 current->state = TASK_RUNNING;
465 __remove_wait_queue(&info->rwait, &wait);
466
467 return ret_val;
468 }
469
470 static ssize_t ifx_ssc_write_helper(struct ifx_ssc_port *info, const char *buf,
471 size_t len, int from_kernel)
472 {
473 if (info->opts.modeRxTx == IFX_SSC_MODE_RX)
474 return -EFAULT;
475
476 info->txbuf_ptr = info->txbuf;
477 info->txbuf_end = len + info->txbuf;
478 if (info->opts.modeRxTx == IFX_SSC_MODE_TX) {
479 tx_int(info);
480 if (info->txbuf_ptr < info->txbuf_end)
481 enable_irq(IFXMIPS_SSC_TIR);
482 }
483
484 return len;
485 }
486
487 ssize_t ifx_ssc_kread(int port, char *kbuf, size_t len)
488 {
489 struct ifx_ssc_port *info;
490 ssize_t ret_val;
491
492 if (port < 0 || port >= PORT_CNT)
493 return -ENXIO;
494
495 if (len == 0)
496 return 0;
497
498 info = &isp[port];
499
500 if (info->rxbuf != NULL) {
501 printk("SSC device busy\n");
502 return -EBUSY;
503 }
504
505 info->rxbuf = kbuf;
506 if (info->rxbuf == NULL) {
507 printk("SSC device error\n");
508 return -EINVAL;
509 }
510
511 ret_val = ifx_ssc_read_helper_poll(info, kbuf, len, 1);
512 info->rxbuf = NULL;
513
514 disable_irq(IFXMIPS_SSC_RIR);
515
516 return ret_val;
517 }
518 EXPORT_SYMBOL(ifx_ssc_kread);
519
520 ssize_t ifx_ssc_kwrite(int port, const char *kbuf, size_t len)
521 {
522 struct ifx_ssc_port *info;
523 ssize_t ret_val;
524
525 if (port < 0 || port >= PORT_CNT)
526 return -ENXIO;
527
528 if (len == 0)
529 return 0;
530
531 info = &isp[port];
532
533 /* check if transmission in progress */
534 if (info->txbuf != NULL)
535 return -EBUSY;
536
537 info->txbuf = (char *)kbuf;
538
539 ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 1);
540
541 if (ret_val < 0)
542 info->txbuf = NULL;
543
544 return ret_val;
545 }
546 EXPORT_SYMBOL(ifx_ssc_kwrite);
547
548 static ssize_t ifx_ssc_read(struct file *filp, char *ubuf, size_t len, loff_t *off)
549 {
550 ssize_t ret_val;
551 int idx;
552 struct ifx_ssc_port *info;
553
554 idx = MINOR(filp->f_dentry->d_inode->i_rdev);
555 info = &isp[idx];
556
557 if (info->rxbuf != NULL)
558 return -EBUSY;
559
560 info->rxbuf = kmalloc(len + 3, GFP_KERNEL);
561 if (info->rxbuf == NULL)
562 return -ENOMEM;
563
564 ret_val = ifx_ssc_read_helper(info, info->rxbuf, len, 0);
565 if (copy_to_user((void *)ubuf, info->rxbuf, ret_val) != 0)
566 ret_val = -EFAULT;
567
568 disable_irq(IFXMIPS_SSC_RIR);
569
570 kfree(info->rxbuf);
571 info->rxbuf = NULL;
572
573 return ret_val;
574 }
575
576 static ssize_t ifx_ssc_write(struct file *filp, const char *ubuf, size_t len, loff_t *off)
577 {
578 int idx;
579 struct ifx_ssc_port *info;
580 int ret_val;
581
582 if (len == 0)
583 return 0;
584
585 idx = MINOR(filp->f_dentry->d_inode->i_rdev);
586 info = &isp[idx];
587
588 if (info->txbuf != NULL)
589 return -EBUSY;
590
591 info->txbuf = kmalloc(len + 3, GFP_KERNEL);
592 if (info->txbuf == NULL)
593 return -ENOMEM;
594
595 ret_val = copy_from_user(info->txbuf, ubuf, len);
596 if (ret_val == 0)
597 ret_val = ifx_ssc_write_helper(info, info->txbuf, len, 0);
598 else
599 ret_val = -EFAULT;
600
601 if (ret_val < 0) {
602 kfree(info->txbuf);
603 info->txbuf = NULL;
604 }
605
606 return ret_val;
607 }
608
609 static struct ifx_ssc_frm_status *ifx_ssc_frm_status_get(struct ifx_ssc_port *info)
610 {
611 unsigned long tmp;
612
613 tmp = ifxmips_r32(IFXMIPS_SSC_SFSTAT);
614 info->frm_status.DataBusy = (tmp & IFX_SSC_SFSTAT_IN_DATA) > 0;
615 info->frm_status.PauseBusy = (tmp & IFX_SSC_SFSTAT_IN_PAUSE) > 0;
616 info->frm_status.DataCount = (tmp & IFX_SSC_SFSTAT_DATA_COUNT_MASK) >> IFX_SSC_SFSTAT_DATA_COUNT_OFFSET;
617 info->frm_status.PauseCount = (tmp & IFX_SSC_SFSTAT_PAUSE_COUNT_MASK) >> IFX_SSC_SFSTAT_PAUSE_COUNT_OFFSET;
618 tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
619 info->frm_status.EnIntAfterData = (tmp & IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE) > 0;
620 info->frm_status.EnIntAfterPause = (tmp & IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE) > 0;
621
622 return &info->frm_status;
623 }
624
625 static struct ifx_ssc_frm_opts *ifx_ssc_frm_control_get(struct ifx_ssc_port *info)
626 {
627 unsigned long tmp;
628
629 tmp = ifxmips_r32(IFXMIPS_SSC_SFCON);
630 info->frm_opts.FrameEnable = (tmp & IFX_SSC_SFCON_SF_ENABLE) > 0;
631 info->frm_opts.DataLength = (tmp & IFX_SSC_SFCON_DATA_LENGTH_MASK) >> IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
632 info->frm_opts.PauseLength = (tmp & IFX_SSC_SFCON_PAUSE_LENGTH_MASK) >> IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
633 info->frm_opts.IdleData = (tmp & IFX_SSC_SFCON_PAUSE_DATA_MASK) >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
634 info->frm_opts.IdleClock = (tmp & IFX_SSC_SFCON_PAUSE_CLOCK_MASK) >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
635 info->frm_opts.StopAfterPause = (tmp & IFX_SSC_SFCON_STOP_AFTER_PAUSE) > 0;
636
637 return &info->frm_opts;
638 }
639
640 static int ifx_ssc_frm_control_set(struct ifx_ssc_port *info)
641 {
642 unsigned long tmp;
643
644 if ((info->frm_opts.DataLength > IFX_SSC_SFCON_DATA_LENGTH_MAX)
645 || (info->frm_opts.DataLength < 1)
646 || (info->frm_opts.PauseLength > IFX_SSC_SFCON_PAUSE_LENGTH_MAX)
647 || (info->frm_opts.PauseLength < 1)
648 || (info->frm_opts.IdleData & ~(IFX_SSC_SFCON_PAUSE_DATA_MASK >> IFX_SSC_SFCON_PAUSE_DATA_OFFSET))
649 || (info->frm_opts.IdleClock & ~(IFX_SSC_SFCON_PAUSE_CLOCK_MASK >> IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET)))
650 return -EINVAL;
651
652 /* read interrupt bits(they're not changed here) */
653 tmp = ifxmips_r32(IFXMIPS_SSC_SFCON) &
654 (IFX_SSC_SFCON_FIR_ENABLE_BEFORE_PAUSE | IFX_SSC_SFCON_FIR_ENABLE_AFTER_PAUSE);
655
656 /* set all values with respect to it's bit position(for data and pause
657 length set N-1) */
658 tmp = (info->frm_opts.DataLength - 1) << IFX_SSC_SFCON_DATA_LENGTH_OFFSET;
659 tmp |= (info->frm_opts.PauseLength - 1) << IFX_SSC_SFCON_PAUSE_LENGTH_OFFSET;
660 tmp |= info->frm_opts.IdleData << IFX_SSC_SFCON_PAUSE_DATA_OFFSET;
661 tmp |= info->frm_opts.IdleClock << IFX_SSC_SFCON_PAUSE_CLOCK_OFFSET;
662 tmp |= info->frm_opts.FrameEnable * IFX_SSC_SFCON_SF_ENABLE;
663 tmp |= info->frm_opts.StopAfterPause * IFX_SSC_SFCON_STOP_AFTER_PAUSE;
664
665 ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
666
667 return 0;
668 }
669
670 static int ifx_ssc_rxtx_mode_set(struct ifx_ssc_port *info, unsigned int val)
671 {
672 unsigned long tmp;
673
674 if (!(info) || (val & ~(IFX_SSC_MODE_MASK)))
675 return -EINVAL;
676
677 if ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)
678 || (ifxmips_r32(IFXMIPS_SSC_RXCNT) & IFX_SSC_RXCNT_TODO_MASK))
679 return -EBUSY;
680
681 tmp = (ifxmips_r32(IFXMIPS_SSC_CON) & ~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF)) | (val);
682 ifxmips_w32(tmp, IFXMIPS_SSC_SFCON);
683 info->opts.modeRxTx = val;
684
685 return 0;
686 }
687
688 static int ifx_ssc_sethwopts(struct ifx_ssc_port *info)
689 {
690 unsigned long flags, bits;
691 struct ifx_ssc_hwopts *opts = &info->opts;
692
693 if ((opts->dataWidth < IFX_SSC_MIN_DATA_WIDTH)
694 || (opts->dataWidth > IFX_SSC_MAX_DATA_WIDTH))
695 return -EINVAL;
696
697 bits = (opts->dataWidth - 1) << IFX_SSC_CON_DATA_WIDTH_OFFSET;
698 bits |= IFX_SSC_CON_ENABLE_BYTE_VALID;
699
700 if (opts->rxOvErrDetect)
701 bits |= IFX_SSC_CON_RX_OFL_CHECK;
702 if (opts->rxUndErrDetect)
703 bits |= IFX_SSC_CON_RX_UFL_CHECK;
704 if (opts->txOvErrDetect)
705 bits |= IFX_SSC_CON_TX_OFL_CHECK;
706 if (opts->txUndErrDetect)
707 bits |= IFX_SSC_CON_TX_UFL_CHECK;
708 if (opts->loopBack)
709 bits |= IFX_SSC_CON_LOOPBACK_MODE;
710 if (opts->echoMode)
711 bits |= IFX_SSC_CON_ECHO_MODE_ON;
712 if (opts->headingControl)
713 bits |= IFX_SSC_CON_MSB_FIRST;
714 if (opts->clockPhase)
715 bits |= IFX_SSC_CON_LATCH_THEN_SHIFT;
716 if (opts->clockPolarity)
717 bits |= IFX_SSC_CON_CLOCK_FALL;
718
719 switch (opts->modeRxTx) {
720 case IFX_SSC_MODE_TX:
721 bits |= IFX_SSC_CON_RX_OFF;
722 break;
723 case IFX_SSC_MODE_RX:
724 bits |= IFX_SSC_CON_TX_OFF;
725 break;
726 }
727
728 local_irq_save(flags);
729
730 ifxmips_w32(bits, IFXMIPS_SSC_CON);
731 ifxmips_w32((info->opts.gpoCs << IFX_SSC_GPOCON_ISCSB0_POS) |
732 (info->opts.gpoInv << IFX_SSC_GPOCON_INVOUT0_POS), IFXMIPS_SSC_GPOCON);
733
734 ifxmips_w32(info->opts.gpoCs << IFX_SSC_WHBGPOSTAT_SETOUT0_POS, IFXMIPS_SSC_WHBGPOSTAT);
735
736 /* master mode */
737 if (opts->masterSelect)
738 ifxmips_w32(IFX_SSC_WHBSTATE_SET_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
739 else
740 ifxmips_w32(IFX_SSC_WHBSTATE_CLR_MASTER_SELECT, IFXMIPS_SSC_WHBSTATE);
741
742 /* init serial framing */
743 ifxmips_w32(0, IFXMIPS_SSC_SFCON);
744 /* set up the port pins */
745 /* check for general requirements to switch(external) pad/pin characteristics */
746 /* TODO: P0.9 SPI_CS4, P0.10 SPI_CS5, P 0.11 SPI_CS6, because of ASC0 */
747 /* p0.15 SPI_CS1(EEPROM), P0.13 SPI_CS3, */
748 /* Set p0.15 to alternative 01, others to 00(In/OUT) */
749 *(IFXMIPS_GPIO_P0_DIR) = (*IFXMIPS_GPIO_P0_DIR) | (0xA000);
750 *(IFXMIPS_GPIO_P0_ALTSEL0) = (((*IFXMIPS_GPIO_P0_ALTSEL0) | (0x8000)) & (~(0x2000)));
751 *(IFXMIPS_GPIO_P0_ALTSEL1) = (((*IFXMIPS_GPIO_P0_ALTSEL1) & (~0x8000)) & (~(0x2000)));
752 *(IFXMIPS_GPIO_P0_OD) = (*IFXMIPS_GPIO_P0_OD) | 0xA000;
753
754 /* p1.6 SPI_CS2(SFLASH), p1.0 SPI_DIN, p1.1 SPI_DOUT, p1.2 SPI_CLK */
755 *(IFXMIPS_GPIO_P1_DIR) = ((*IFXMIPS_GPIO_P1_DIR) | (0x46)) & (~1);
756 *(IFXMIPS_GPIO_P1_ALTSEL0) = ((*IFXMIPS_GPIO_P1_ALTSEL0) | (0x47));
757 *(IFXMIPS_GPIO_P1_ALTSEL1) = (*IFXMIPS_GPIO_P1_ALTSEL1) & (~0x47);
758 *(IFXMIPS_GPIO_P1_OD) = (*IFXMIPS_GPIO_P1_OD) | 0x0046;
759
760 /*CS3 */
761 /*TODO: CS4 CS5 CS6 */
762 *IFXMIPS_GPIO_P0_OUT = ((*IFXMIPS_GPIO_P0_OUT) | 0x2000);
763
764 local_irq_restore(flags);
765
766 return 0;
767 }
768
769 static int ifx_ssc_set_baud(struct ifx_ssc_port *info, unsigned int baud)
770 {
771 unsigned int ifx_ssc_clock;
772 unsigned int br;
773 unsigned long flags;
774 bool enabled;
775 int retval = 0;
776
777 ifx_ssc_clock = ifx_ssc_get_kernel_clk(info);
778 if (ifx_ssc_clock == 0) {
779 retval = -EINVAL;
780 goto out;
781 }
782
783 local_irq_save(flags);
784
785 enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
786 ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
787
788 br = (((ifx_ssc_clock >> 1) + baud / 2) / baud) - 1;
789 wmb();
790
791 if (br > 0xffff || ((br == 0) &&
792 ((ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_MASTER) == 0))) {
793 local_irq_restore(flags);
794 printk("%s: invalid baudrate %u\n", __func__, baud);
795 return -EINVAL;
796 }
797
798 ifxmips_w32(br, IFXMIPS_SSC_BR);
799
800 if (enabled)
801 ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
802
803 local_irq_restore(flags);
804
805 out:
806 return retval;
807 }
808
809 static int ifx_ssc_hwinit(struct ifx_ssc_port *info)
810 {
811 unsigned long flags;
812 bool enabled;
813
814 enabled = (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_IS_ENABLED);
815 ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
816
817 if (ifx_ssc_sethwopts(info) < 0) {
818 printk("%s: setting the hardware options failed\n", __func__);
819 return -EINVAL;
820 }
821
822 if (ifx_ssc_set_baud(info, info->baud) < 0) {
823 printk("%s: setting the baud rate failed\n", __func__);
824 return -EINVAL;
825 }
826
827 local_irq_save(flags);
828
829 /* TX FIFO */
830 ifxmips_w32((IFX_SSC_DEF_TXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_TXFCON);
831 /* RX FIFO */
832 ifxmips_w32((IFX_SSC_DEF_RXFIFO_FL << IFX_SSC_XFCON_ITL_OFFSET) | IFX_SSC_XFCON_FIFO_ENABLE, IFXMIPS_SSC_RXFCON);
833
834 local_irq_restore(flags);
835
836 if (enabled)
837 ifxmips_w32(IFX_SSC_WHBSTATE_SET_ENABLE, IFXMIPS_SSC_WHBSTATE);
838
839 return 0;
840 }
841
842 int ifx_ssc_ioctl(struct inode *inode, struct file *filp,
843 unsigned int cmd, unsigned long data)
844 {
845 struct ifx_ssc_port *info;
846 int line, ret_val = 0;
847 unsigned long flags;
848 unsigned long tmp;
849 int from_kernel = 0;
850
851 if ((inode == (struct inode *)0) || (inode == (struct inode *)1)) {
852 from_kernel = 1;
853 line = (int) inode;
854 } else
855 line = MINOR(filp->f_dentry->d_inode->i_rdev);
856
857 if (line < 0 || line >= PORT_CNT)
858 return -ENXIO;
859
860 info = &isp[line];
861
862 switch (cmd) {
863 case IFX_SSC_STATS_READ:
864 /* data must be a pointer to a struct ifx_ssc_statistics */
865 if (from_kernel)
866 memcpy((void *)data, (void *)&info->stats,
867 sizeof(struct ifx_ssc_statistics));
868 else if (copy_to_user((void *)data,
869 (void *)&info->stats,
870 sizeof(struct ifx_ssc_statistics)))
871 ret_val = -EFAULT;
872 break;
873 case IFX_SSC_STATS_RESET:
874 /* just resets the statistics counters */
875 memset((void *)&info->stats, 0,
876 sizeof(struct ifx_ssc_statistics));
877 break;
878 case IFX_SSC_BAUD_SET:
879 /* if the buffers are not empty then the port is */
880 /* busy and we shouldn't change things on-the-fly! */
881 if (!info->txbuf || !info->rxbuf ||
882 (ifxmips_r32(IFXMIPS_SSC_STATE) & IFX_SSC_STATE_BUSY)) {
883 ret_val = -EBUSY;
884 break;
885 }
886 /* misuse flags */
887 if (from_kernel)
888 flags = *((unsigned long *)data);
889 else if (copy_from_user((void *)&flags,
890 (void *)data, sizeof(flags))) {
891 ret_val = -EFAULT;
892 break;
893 }
894 if (flags == 0) {
895 ret_val = -EINVAL;
896 break;
897 }
898 if (ifx_ssc_set_baud(info, flags) < 0) {
899 ret_val = -EINVAL;
900 break;
901 }
902 info->baud = flags;
903 break;
904 case IFX_SSC_BAUD_GET:
905 if (from_kernel)
906 *((unsigned int *)data) = info->baud;
907 else if (copy_to_user((void *)data,
908 (void *)&info->baud,
909 sizeof(unsigned long)))
910 ret_val = -EFAULT;
911 break;
912 case IFX_SSC_RXTX_MODE_SET:
913 if (from_kernel)
914 tmp = *((unsigned long *)data);
915 else if (copy_from_user((void *)&tmp,
916 (void *)data, sizeof(tmp))) {
917 ret_val = -EFAULT;
918 break;
919 }
920 ret_val = ifx_ssc_rxtx_mode_set(info, tmp);
921 break;
922 case IFX_SSC_RXTX_MODE_GET:
923 tmp = ifxmips_r32(IFXMIPS_SSC_CON) &
924 (~(IFX_SSC_CON_RX_OFF | IFX_SSC_CON_TX_OFF));
925 if (from_kernel)
926 *((unsigned int *)data) = tmp;
927 else if (copy_to_user((void *)data,
928 (void *)&tmp, sizeof(tmp)))
929 ret_val = -EFAULT;
930 break;
931
932 case IFX_SSC_ABORT:
933 ifx_ssc_abort(info);
934 break;
935
936 case IFX_SSC_GPO_OUT_SET:
937 if (from_kernel)
938 tmp = *((unsigned long *)data);
939 else if (copy_from_user((void *)&tmp,
940 (void *)data, sizeof(tmp))) {
941 ret_val = -EFAULT;
942 break;
943 }
944 if (tmp > IFX_SSC_MAX_GPO_OUT)
945 ret_val = -EINVAL;
946 else
947 ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_SETOUT0_POS),
948 IFXMIPS_SSC_WHBGPOSTAT);
949 break;
950 case IFX_SSC_GPO_OUT_CLR:
951 if (from_kernel)
952 tmp = *((unsigned long *)data);
953 else if (copy_from_user((void *)&tmp, (void *)data, sizeof(tmp))) {
954 ret_val = -EFAULT;
955 break;
956 }
957 if (tmp > IFX_SSC_MAX_GPO_OUT)
958 ret_val = -EINVAL;
959 else
960 ifxmips_w32(1 << (tmp + IFX_SSC_WHBGPOSTAT_CLROUT0_POS),
961 IFXMIPS_SSC_WHBGPOSTAT);
962 break;
963 case IFX_SSC_GPO_OUT_GET:
964 tmp = ifxmips_r32(IFXMIPS_SSC_GPOSTAT);
965 if (from_kernel)
966 *((unsigned int *)data) = tmp;
967 else if (copy_to_user((void *)data,
968 (void *)&tmp, sizeof(tmp)))
969 ret_val = -EFAULT;
970 break;
971 case IFX_SSC_FRM_STATUS_GET:
972 ifx_ssc_frm_status_get(info);
973 if (from_kernel)
974 memcpy((void *)data, (void *)&info->frm_status,
975 sizeof(struct ifx_ssc_frm_status));
976 else if (copy_to_user((void *)data,
977 (void *)&info->frm_status,
978 sizeof(struct ifx_ssc_frm_status)))
979 ret_val = -EFAULT;
980 break;
981 case IFX_SSC_FRM_CONTROL_GET:
982 ifx_ssc_frm_control_get(info);
983 if (from_kernel)
984 memcpy((void *)data, (void *)&info->frm_opts,
985 sizeof(struct ifx_ssc_frm_opts));
986 else if (copy_to_user((void *)data,
987 (void *)&info->frm_opts,
988 sizeof(struct ifx_ssc_frm_opts)))
989 ret_val = -EFAULT;
990 break;
991 case IFX_SSC_FRM_CONTROL_SET:
992 if (from_kernel)
993 memcpy((void *)&info->frm_opts, (void *)data,
994 sizeof(struct ifx_ssc_frm_opts));
995 else if (copy_to_user((void *)&info->frm_opts,
996 (void *)data,
997 sizeof(struct ifx_ssc_frm_opts))) {
998 ret_val = -EFAULT;
999 break;
1000 }
1001 ret_val = ifx_ssc_frm_control_set(info);
1002 break;
1003 case IFX_SSC_HWOPTS_SET:
1004 /* data must be a pointer to a struct ifx_ssc_hwopts */
1005 /* if the buffers are not empty then the port is */
1006 /* busy and we shouldn't change things on-the-fly! */
1007 if (!info->txbuf || !info->rxbuf ||
1008 (ifxmips_r32(IFXMIPS_SSC_STATE)
1009 & IFX_SSC_STATE_BUSY)) {
1010 ret_val = -EBUSY;
1011 break;
1012 }
1013 if (from_kernel)
1014 memcpy((void *)&info->opts, (void *)data,
1015 sizeof(struct ifx_ssc_hwopts));
1016 else if (copy_from_user((void *)&info->opts,
1017 (void *)data, sizeof(struct ifx_ssc_hwopts))) {
1018 ret_val = -EFAULT;
1019 break;
1020 }
1021 if (ifx_ssc_hwinit(info) < 0)
1022 ret_val = -EIO;
1023 break;
1024 case IFX_SSC_HWOPTS_GET:
1025 /* data must be a pointer to a struct ifx_ssc_hwopts */
1026 if (from_kernel)
1027 memcpy((void *)data, (void *)&info->opts,
1028 sizeof(struct ifx_ssc_hwopts));
1029 else if (copy_to_user((void *)data,
1030 (void *)&info->opts,
1031 sizeof(struct ifx_ssc_hwopts)))
1032 ret_val = -EFAULT;
1033 break;
1034 default:
1035 ret_val = -ENOIOCTLCMD;
1036 }
1037
1038 return ret_val;
1039 }
1040 EXPORT_SYMBOL(ifx_ssc_ioctl);
1041
1042 static struct file_operations ifx_ssc_fops = {
1043 .owner = THIS_MODULE,
1044 .read = ifx_ssc_read,
1045 .write = ifx_ssc_write,
1046 .ioctl = ifx_ssc_ioctl,
1047 .open = ifx_ssc_open,
1048 .release = ifx_ssc_close,
1049 };
1050
1051 int __init ifx_ssc_init(void)
1052 {
1053 struct ifx_ssc_port *info;
1054 int i, nbytes;
1055 unsigned long flags;
1056 int ret_val;
1057
1058 ret_val = -ENOMEM;
1059 nbytes = PORT_CNT * sizeof(struct ifx_ssc_port);
1060 isp = kmalloc(nbytes, GFP_KERNEL);
1061
1062 if (isp == NULL) {
1063 printk("%s: no memory for isp\n", __func__);
1064 return ret_val;
1065 }
1066 memset(isp, 0, nbytes);
1067
1068 ret_val = -ENXIO;
1069 i = register_chrdev(maj, "ssc", &ifx_ssc_fops);
1070 if (i < 0) {
1071 printk("Unable to register major %d for the Infineon SSC\n", maj);
1072 if (maj == 0) {
1073 goto errout;
1074 } else {
1075 maj = 0;
1076 i = register_chrdev(maj, "ssc", &ifx_ssc_fops);
1077 if (i < 0) {
1078 printk("Unable to register major %d for the Infineon SSC\n", maj);
1079 goto errout;
1080 }
1081 }
1082 }
1083
1084 if (maj == 0)
1085 maj = i;
1086
1087 /* set default values in ifx_ssc_port */
1088 for (i = 0; i < PORT_CNT; i++) {
1089 info = &isp[i];
1090 info->port_nr = i;
1091 /* default values for the HwOpts */
1092 info->opts.AbortErrDetect = IFX_SSC_DEF_ABRT_ERR_DETECT;
1093 info->opts.rxOvErrDetect = IFX_SSC_DEF_RO_ERR_DETECT;
1094 info->opts.rxUndErrDetect = IFX_SSC_DEF_RU_ERR_DETECT;
1095 info->opts.txOvErrDetect = IFX_SSC_DEF_TO_ERR_DETECT;
1096 info->opts.txUndErrDetect = IFX_SSC_DEF_TU_ERR_DETECT;
1097 info->opts.loopBack = IFX_SSC_DEF_LOOP_BACK;
1098 info->opts.echoMode = IFX_SSC_DEF_ECHO_MODE;
1099 info->opts.idleValue = IFX_SSC_DEF_IDLE_DATA;
1100 info->opts.clockPolarity = IFX_SSC_DEF_CLOCK_POLARITY;
1101 info->opts.clockPhase = IFX_SSC_DEF_CLOCK_PHASE;
1102 info->opts.headingControl = IFX_SSC_DEF_HEADING_CONTROL;
1103 info->opts.dataWidth = IFX_SSC_DEF_DATA_WIDTH;
1104 info->opts.modeRxTx = IFX_SSC_DEF_MODE_RXTX;
1105 info->opts.gpoCs = IFX_SSC_DEF_GPO_CS;
1106 info->opts.gpoInv = IFX_SSC_DEF_GPO_INV;
1107 info->opts.masterSelect = IFX_SSC_DEF_MASTERSLAVE;
1108 info->baud = IFX_SSC_DEF_BAUDRATE;
1109 info->rxbuf = NULL;
1110 info->txbuf = NULL;
1111 /* values specific to SSC1 */
1112 if (i == 0)
1113 info->mapbase = IFXMIPS_SSC_BASE_ADDR;
1114
1115 ifxmips_w32(IFX_SSC_DEF_RMC << IFX_CLC_RUN_DIVIDER_OFFSET, IFXMIPS_SSC_CLC);
1116
1117 init_waitqueue_head(&info->rwait);
1118
1119 local_irq_save(flags);
1120
1121 /* init serial framing register */
1122 ifxmips_w32(IFX_SSC_DEF_SFCON, IFXMIPS_SSC_SFCON);
1123
1124 ret_val = request_irq(IFXMIPS_SSC_TIR, ifx_ssc_tx_int, IRQF_DISABLED, "ifx_ssc_tx", info);
1125 if (ret_val) {
1126 printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_TIR);
1127 local_irq_restore(flags);
1128 goto errout;
1129 }
1130
1131 ret_val = request_irq(IFXMIPS_SSC_RIR, ifx_ssc_rx_int, IRQF_DISABLED, "ifx_ssc_rx", info);
1132 if (ret_val) {
1133 printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_RIR);
1134 local_irq_restore(flags);
1135 goto irqerr;
1136 }
1137
1138 ret_val = request_irq(IFXMIPS_SSC_EIR, ifx_ssc_err_int, IRQF_DISABLED, "ifx_ssc_err", info);
1139 if (ret_val) {
1140 printk("%s: unable to get irq %d\n", __func__, IFXMIPS_SSC_EIR);
1141 local_irq_restore(flags);
1142 goto irqerr;
1143 }
1144 ifxmips_w32(IFX_SSC_DEF_IRNEN, IFXMIPS_SSC_IRN);
1145
1146 #if 0
1147 enable_irq(IFXMIPS_SSC_TIR);
1148 enable_irq(IFXMIPS_SSC_RIR);
1149 enable_irq(IFXMIPS_SSC_EIR);
1150 #endif
1151
1152 local_irq_restore(flags);
1153 }
1154
1155 for (i = 0; i < PORT_CNT; i++) {
1156 info = &isp[i];
1157 if (ifx_ssc_hwinit(info) < 0) {
1158 printk("%s: hardware init failed for port %d\n", __func__, i);
1159 goto irqerr;
1160 }
1161 }
1162
1163
1164 return 0;
1165
1166 irqerr:
1167 free_irq(IFXMIPS_SSC_TIR, &isp[0]);
1168 free_irq(IFXMIPS_SSC_RIR, &isp[0]);
1169 free_irq(IFXMIPS_SSC_EIR, &isp[0]);
1170 errout:
1171 kfree(isp);
1172 return ret_val;
1173 }
1174
1175 void __exit ifx_ssc_cleanup_module(void)
1176 {
1177 int i;
1178
1179 for (i = 0; i < PORT_CNT; i++) {
1180 ifxmips_w32(IFX_SSC_WHBSTATE_CLR_ENABLE, IFXMIPS_SSC_WHBSTATE);
1181 free_irq(IFXMIPS_SSC_TIR, &isp[i]);
1182 free_irq(IFXMIPS_SSC_RIR, &isp[i]);
1183 free_irq(IFXMIPS_SSC_EIR, &isp[i]);
1184 }
1185 kfree(isp);
1186 }
1187
1188 module_init(ifx_ssc_init);
1189 module_exit(ifx_ssc_cleanup_module);
1190
1191 inline int ifx_ssc_cs_low(u32 pin)
1192 {
1193 int ret = 0;
1194 ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_GPO_OUT_CLR, (unsigned long) &pin);
1195 if (ret)
1196 printk("clear CS %d fails\n", pin);
1197 wmb();
1198
1199 return ret;
1200 }
1201 EXPORT_SYMBOL(ifx_ssc_cs_low);
1202
1203 inline int ifx_ssc_cs_high(u32 pin)
1204 {
1205 int ret = 0;
1206 ret = ifx_ssc_ioctl((struct inode *)0, NULL, IFX_SSC_GPO_OUT_SET, (unsigned long) &pin);
1207 if (ret)
1208 printk("set CS %d fails\n", pin);
1209 wmb();
1210
1211 return ret;
1212 }
1213 EXPORT_SYMBOL(ifx_ssc_cs_high);
1214
1215 static int ssc_session(char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1216 {
1217 int ret = 0;
1218
1219 char *ssc_tx_buf = NULL;
1220 char *ssc_rx_buf = NULL;
1221 int eff_size = 0;
1222 u8 mode = 0;
1223
1224 if (tx_buf == NULL && tx_len == 0 && rx_buf == NULL && rx_len == 0) {
1225 printk("invalid parameters\n");
1226 ret = -EINVAL;
1227 goto ssc_session_exit;
1228 } else if (tx_buf == NULL || tx_len == 0) {
1229 if (rx_buf != NULL && rx_len != 0) {
1230 mode = IFX_SSC_MODE_RX;
1231 } else {
1232 printk("invalid parameters\n");
1233 ret = -EINVAL;
1234 goto ssc_session_exit;
1235 }
1236 } else if (rx_buf == NULL || rx_len == 0) {
1237 if (tx_buf != NULL && tx_len != 0)
1238 mode = IFX_SSC_MODE_TX;
1239 else {
1240 printk("invalid parameters\n");
1241 ret = -EINVAL;
1242 goto ssc_session_exit;
1243 }
1244 } else
1245 mode = IFX_SSC_MODE_RXTX;
1246
1247 if (mode == IFX_SSC_MODE_RXTX)
1248 eff_size = tx_len + rx_len;
1249 else if (mode == IFX_SSC_MODE_RX)
1250 eff_size = rx_len;
1251 else
1252 eff_size = tx_len;
1253
1254 /* 4 bytes alignment, required by driver */
1255 ssc_tx_buf = kmalloc(sizeof(char) *
1256 ((eff_size + 3) & (~3)),
1257 GFP_ATOMIC);
1258 ssc_rx_buf = kmalloc(sizeof(char) *
1259 ((eff_size + 3) & (~3)),
1260 GFP_ATOMIC);
1261 if (ssc_tx_buf == NULL || ssc_rx_buf == NULL) {
1262 printk("no memory for size of %d\n", eff_size);
1263 ret = -ENOMEM;
1264 goto ssc_session_exit;
1265 }
1266 memset((void *)ssc_tx_buf, 0, eff_size);
1267 memset((void *)ssc_rx_buf, 0, eff_size);
1268
1269 if (tx_len > 0)
1270 memcpy(ssc_tx_buf, tx_buf, tx_len);
1271
1272 ret = ifx_ssc_kwrite(0, ssc_tx_buf, eff_size);
1273
1274 if (ret > 0)
1275 ssc_tx_buf = NULL; /* should be freed by ifx_ssc_kwrite */
1276
1277 if (ret != eff_size) {
1278 printk("ifx_ssc_write return %d\n", ret);
1279 goto ssc_session_exit;
1280 }
1281 ret = ifx_ssc_kread(0, ssc_rx_buf, eff_size);
1282 if (ret != eff_size) {
1283 printk("ifx_ssc_read return %d\n", ret);
1284 goto ssc_session_exit;
1285 }
1286
1287 memcpy(rx_buf, ssc_rx_buf + tx_len, rx_len);
1288
1289 if (mode == IFX_SSC_MODE_TX)
1290 ret = tx_len;
1291 else
1292 ret = rx_len;
1293
1294 ssc_session_exit:
1295 if (ssc_tx_buf != NULL)
1296 kfree(ssc_tx_buf);
1297 if (ssc_rx_buf != NULL)
1298 kfree(ssc_rx_buf);
1299
1300 if (ret < 0)
1301 printk("ssc session fails\n");
1302
1303 return ret;
1304 }
1305
1306 int ifx_ssc_txrx(char *tx_buf, u32 tx_len, char *rx_buf, u32 rx_len)
1307 {
1308 return ssc_session(tx_buf, tx_len, rx_buf, rx_len);
1309 }
1310 EXPORT_SYMBOL(ifx_ssc_txrx);
1311
1312 int ifx_ssc_tx(char *tx_buf, u32 tx_len)
1313 {
1314 return ssc_session(tx_buf, tx_len, NULL, 0);
1315 }
1316 EXPORT_SYMBOL(ifx_ssc_tx);
1317
1318 int ifx_ssc_rx(char *rx_buf, u32 rx_len)
1319 {
1320 return ssc_session(NULL, 0, rx_buf, rx_len);
1321 }
1322 EXPORT_SYMBOL(ifx_ssc_rx);
1323
1324 MODULE_LICENSE("GPL");
1325 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1326 MODULE_DESCRIPTION("ifxmips ssc driver");
1327
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