target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c

   1 #include <linux/types.h>
   2 #include <linux/pci.h>
   3 #include <linux/kernel.h>
   4 #include <linux/init.h>
   5 #include <linux/delay.h>
   6 #include <linux/mm.h>
   7 #include <asm/ifxmips/ifxmips.h>
   8 #include <asm/ifxmips/ifxmips_irq.h>
   9 #include <asm/addrspace.h>
  10 #include <linux/vmalloc.h>
  11
  12 #define IFXMIPS_PCI_MEM_BASE    0x18000000
  13 #define IFXMIPS_PCI_MEM_SIZE    0x02000000
  14 #define IFXMIPS_PCI_IO_BASE     0x1AE00000
  15 #define IFXMIPS_PCI_IO_SIZE     0x00200000
  16
  17 extern int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  18 extern int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  19
  20 struct pci_ops ifxmips_pci_ops = {
  21         .read = ifxmips_pci_read_config_dword,
  22         .write = ifxmips_pci_write_config_dword
  23 };
  24
  25 static struct resource pci_io_resource = {
  26         .name = "io pci IO space",
  27         .start = IFXMIPS_PCI_IO_BASE,
  28         .end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
  29         .flags = IORESOURCE_IO
  30 };
  31
  32 static struct resource pci_mem_resource = {
  33         .name = "ext pci memory space",
  34         .start = IFXMIPS_PCI_MEM_BASE,
  35         .end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
  36         .flags = IORESOURCE_MEM
  37 };
  38
  39 static struct pci_controller ifxmips_pci_controller = {
  40         .pci_ops = &ifxmips_pci_ops,
  41         .mem_resource = &pci_mem_resource,
  42         .mem_offset     = 0x00000000UL,
  43         .io_resource = &pci_io_resource,
  44         .io_offset      = 0x00000000UL,
  45 };
  46
  47 u32 ifxmips_pci_mapped_cfg;
  48
  49 int pcibios_plat_dev_init(struct pci_dev *dev){
  50         u8 pin;
  51
  52         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
  53         switch(pin) {
  54                 case 0:
  55                         break;
  56                 case 1:
  57                         //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
  58                         ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
  59                         ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
  60                         break;
  61                 case 2:
  62                 case 3:
  63                 case 4:
  64                         printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
  65                 default:
  66                         printk ("WARNING: invalid interrupt pin %d\n", pin);
  67                         return 1;
  68         }
  69         return 0;
  70 }
  71
  72 static void __init ifxmips_pci_startup (void){
  73         u32 temp_buffer;
  74         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, IFXMIPS_CGU_IFCCR);
  75         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, IFXMIPS_CGU_IFCCR);
  76         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), IFXMIPS_CGU_IFCCR);
  77         ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
  78         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
  79         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
  80         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
  81         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
  82         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
  83         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
  84         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
  85         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
  86         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
  87         /* enable auto-switching between PCI and EBU */
  88         ifxmips_w32(0xa, PCI_CR_CLK_CTRL);
  89         /* busy, i.e. configuration is not done, PCI access has to be retried */
  90         ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
  91         wmb ();
  92         /* BUS Master/IO/MEM access */
  93         ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
  94
  95         /* enable external 2 PCI masters */
  96         temp_buffer = ifxmips_r32(PCI_CR_PC_ARB);
  97         temp_buffer &= (~(0xf << 16));
  98         /* enable internal arbiter */
  99         temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
 100         /* enable internal PCI master reqest */
 101         temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
 102
 103         /* enable EBU reqest */
 104         temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
 105
 106         /* enable all external masters request */
 107         temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
 108         ifxmips_w32(temp_buffer, PCI_CR_PC_ARB);
 109         wmb ();
 110
 111         ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
 112         ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
 113         ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
 114         ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
 115         ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
 116         ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
 117         ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
 118         ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 119         ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
 120         ifxmips_w32(0x0e000008, PCI_CR_BAR11MASK);
 121         ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11);
 122         ifxmips_w32(0, PCI_CS_BASE_ADDR1);
 123 #ifdef CONFIG_SWAP_IO_SPACE
 124         /* both TX and RX endian swap are enabled */
 125         ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
 126         wmb ();
 127 #endif
 128         /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
 129         ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
 130         ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
 131         /*use 8 dw burst length */
 132         ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 133         ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
 134         wmb();
 135         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
 136         wmb();
 137         mdelay(1);
 138         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
 139 }
 140
 141 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
 142         switch (slot) {
 143                 case 13:
 144                         /* IDSEL = AD29 --> USB Host Controller */
 145                         return (INT_NUM_IM1_IRL0 + 17);
 146                 case 14:
 147                         /* IDSEL = AD30 --> mini PCI connector */
 148                         return (INT_NUM_IM0_IRL0 + 22);
 149                 default:
 150                         printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
 151                         return 0;
 152         }
 153 }
 154
 155 int pcibios_init(void){
 156         extern int pci_probe_only;
 157
 158         pci_probe_only = 0;
 159         printk ("PCI: Probing PCI hardware on host bus 0.\n");
 160         ifxmips_pci_startup ();
 161         //      IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
 162         ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16);
 163         printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg);
 164         ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
 165         printk("IFXMips PCI I/O mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_controller.io_map_base);
 166         register_pci_controller(&ifxmips_pci_controller);
 167         return 0;
 168 }
 169
 170 arch_initcall(pcibios_init);