2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_RESERVED BIT(19)
70 #define AR7240_AT_CTRL_ARP_EN BIT(20)
72 #define AR7240_REG_TAG_PRIORITY 0x70
74 #define AR7240_REG_SERVICE_TAG 0x74
75 #define AR7240_SERVICE_TAG_M BITM(16)
77 #define AR7240_REG_CPU_PORT 0x78
78 #define AR7240_MIRROR_PORT_S 4
79 #define AR7240_CPU_PORT_EN BIT(8)
81 #define AR7240_REG_MIB_FUNCTION0 0x80
82 #define AR7240_MIB_TIMER_M BITM(16)
83 #define AR7240_MIB_AT_HALF_EN BIT(16)
84 #define AR7240_MIB_BUSY BIT(17)
85 #define AR7240_MIB_FUNC_S 24
86 #define AR7240_MIB_FUNC_NO_OP 0x0
87 #define AR7240_MIB_FUNC_FLUSH 0x1
88 #define AR7240_MIB_FUNC_CAPTURE 0x3
90 #define AR7240_REG_MDIO_CTRL 0x98
91 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
92 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
93 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
94 #define AR7240_MDIO_CTRL_CMD_WRITE 0
95 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
96 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
97 #define AR7240_MDIO_CTRL_BUSY BIT(31)
99 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
101 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
102 #define AR7240_PORT_STATUS_SPEED_S 0
103 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
104 #define AR7240_PORT_STATUS_SPEED_10 0
105 #define AR7240_PORT_STATUS_SPEED_100 1
106 #define AR7240_PORT_STATUS_SPEED_1000 2
107 #define AR7240_PORT_STATUS_TXMAC BIT(2)
108 #define AR7240_PORT_STATUS_RXMAC BIT(3)
109 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
110 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
111 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
112 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
113 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
114 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
116 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
117 #define AR7240_PORT_CTRL_STATE_M BITM(3)
118 #define AR7240_PORT_CTRL_STATE_DISABLED 0
119 #define AR7240_PORT_CTRL_STATE_BLOCK 1
120 #define AR7240_PORT_CTRL_STATE_LISTEN 2
121 #define AR7240_PORT_CTRL_STATE_LEARN 3
122 #define AR7240_PORT_CTRL_STATE_FORWARD 4
123 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
124 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
125 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
126 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
127 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
128 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
129 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
130 #define AR7240_PORT_CTRL_HEADER BIT(11)
131 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
132 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
133 #define AR7240_PORT_CTRL_LEARN BIT(14)
134 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
135 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
136 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
138 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
140 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
141 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
142 #define AR7240_PORT_VLAN_MODE_S 30
143 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
144 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
145 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
146 #define AR7240_PORT_VLAN_MODE_SECURE 3
149 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
151 #define AR7240_STATS_RXBROAD 0x00
152 #define AR7240_STATS_RXPAUSE 0x04
153 #define AR7240_STATS_RXMULTI 0x08
154 #define AR7240_STATS_RXFCSERR 0x0c
155 #define AR7240_STATS_RXALIGNERR 0x10
156 #define AR7240_STATS_RXRUNT 0x14
157 #define AR7240_STATS_RXFRAGMENT 0x18
158 #define AR7240_STATS_RX64BYTE 0x1c
159 #define AR7240_STATS_RX128BYTE 0x20
160 #define AR7240_STATS_RX256BYTE 0x24
161 #define AR7240_STATS_RX512BYTE 0x28
162 #define AR7240_STATS_RX1024BYTE 0x2c
163 #define AR7240_STATS_RX1518BYTE 0x30
164 #define AR7240_STATS_RXMAXBYTE 0x34
165 #define AR7240_STATS_RXTOOLONG 0x38
166 #define AR7240_STATS_RXGOODBYTE 0x3c
167 #define AR7240_STATS_RXBADBYTE 0x44
168 #define AR7240_STATS_RXOVERFLOW 0x4c
169 #define AR7240_STATS_FILTERED 0x50
170 #define AR7240_STATS_TXBROAD 0x54
171 #define AR7240_STATS_TXPAUSE 0x58
172 #define AR7240_STATS_TXMULTI 0x5c
173 #define AR7240_STATS_TXUNDERRUN 0x60
174 #define AR7240_STATS_TX64BYTE 0x64
175 #define AR7240_STATS_TX128BYTE 0x68
176 #define AR7240_STATS_TX256BYTE 0x6c
177 #define AR7240_STATS_TX512BYTE 0x70
178 #define AR7240_STATS_TX1024BYTE 0x74
179 #define AR7240_STATS_TX1518BYTE 0x78
180 #define AR7240_STATS_TXMAXBYTE 0x7c
181 #define AR7240_STATS_TXOVERSIZE 0x80
182 #define AR7240_STATS_TXBYTE 0x84
183 #define AR7240_STATS_TXCOLLISION 0x8c
184 #define AR7240_STATS_TXABORTCOL 0x90
185 #define AR7240_STATS_TXMULTICOL 0x94
186 #define AR7240_STATS_TXSINGLECOL 0x98
187 #define AR7240_STATS_TXEXCDEFER 0x9c
188 #define AR7240_STATS_TXDEFER 0xa0
189 #define AR7240_STATS_TXLATECOL 0xa4
191 #define AR7240_PORT_CPU 0
192 #define AR7240_NUM_PORTS 6
193 #define AR7240_NUM_PHYS 5
195 #define AR7240_PHY_ID1 0x004d
196 #define AR7240_PHY_ID2 0xd041
198 #define AR934X_PHY_ID1 0x004d
199 #define AR934X_PHY_ID2 0xd042
201 #define AR7240_MAX_VLANS 16
203 #define AR934X_REG_OPER_MODE0 0x04
204 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
205 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
207 #define AR934X_REG_OPER_MODE1 0x08
208 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
210 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
212 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
213 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
214 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
215 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
216 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
217 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
218 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
219 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
220 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
222 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
223 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
224 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
225 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
226 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
227 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
228 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
230 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
233 struct mii_bus
*mii_bus
;
234 struct ag71xx_switch_platform_data
*swdata
;
235 struct switch_dev swdev
;
239 u16 vlan_id
[AR7240_MAX_VLANS
];
240 u8 vlan_table
[AR7240_MAX_VLANS
];
242 u16 pvid
[AR7240_NUM_PORTS
];
246 struct ar7240sw_hw_stat
{
247 char string
[ETH_GSTRING_LEN
];
252 static DEFINE_MUTEX(reg_mutex
);
254 static inline int sw_is_ar7240(struct ar7240sw
*as
)
256 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR7240
;
259 static inline int sw_is_ar934x(struct ar7240sw
*as
)
261 return as
->ver
== AR7240_MASK_CTRL_VERSION_AR934X
;
264 static inline u32
ar7240sw_port_mask(struct ar7240sw
*as
, int port
)
269 static inline u32
ar7240sw_port_mask_all(struct ar7240sw
*as
)
271 return BIT(as
->swdev
.ports
) - 1;
274 static inline u32
ar7240sw_port_mask_but(struct ar7240sw
*as
, int port
)
276 return ar7240sw_port_mask_all(as
) & ~BIT(port
);
279 static inline u16
mk_phy_addr(u32 reg
)
281 return 0x17 & ((reg
>> 4) | 0x10);
284 static inline u16
mk_phy_reg(u32 reg
)
286 return (reg
<< 1) & 0x1e;
289 static inline u16
mk_high_addr(u32 reg
)
291 return (reg
>> 7) & 0x1ff;
294 static u32
__ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg
)
301 reg
= (reg
& 0xfffffffc) >> 2;
302 phy_addr
= mk_phy_addr(reg
);
303 phy_reg
= mk_phy_reg(reg
);
305 local_irq_save(flags
);
306 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
307 lo
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
);
308 hi
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
+ 1);
309 local_irq_restore(flags
);
311 return (hi
<< 16) | lo
;
314 static void __ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg
, u32 val
)
320 reg
= (reg
& 0xfffffffc) >> 2;
321 phy_addr
= mk_phy_addr(reg
);
322 phy_reg
= mk_phy_reg(reg
);
324 local_irq_save(flags
);
325 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
326 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
+ 1, (val
>> 16));
327 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
, (val
& 0xffff));
328 local_irq_restore(flags
);
331 static u32
ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg_addr
)
335 mutex_lock(®_mutex
);
336 ret
= __ar7240sw_reg_read(mii
, reg_addr
);
337 mutex_unlock(®_mutex
);
342 static void ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg_addr
, u32 reg_val
)
344 mutex_lock(®_mutex
);
345 __ar7240sw_reg_write(mii
, reg_addr
, reg_val
);
346 mutex_unlock(®_mutex
);
349 static u32
ar7240sw_reg_rmw(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
)
353 mutex_lock(®_mutex
);
354 t
= __ar7240sw_reg_read(mii
, reg
);
357 __ar7240sw_reg_write(mii
, reg
, t
);
358 mutex_unlock(®_mutex
);
363 static void ar7240sw_reg_set(struct mii_bus
*mii
, u32 reg
, u32 val
)
367 mutex_lock(®_mutex
);
368 t
= __ar7240sw_reg_read(mii
, reg
);
370 __ar7240sw_reg_write(mii
, reg
, t
);
371 mutex_unlock(®_mutex
);
374 static int __ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
379 for (i
= 0; i
< timeout
; i
++) {
382 t
= __ar7240sw_reg_read(mii
, reg
);
383 if ((t
& mask
) == val
)
392 static int ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
397 mutex_lock(®_mutex
);
398 ret
= __ar7240sw_reg_wait(mii
, reg
, mask
, val
, timeout
);
399 mutex_unlock(®_mutex
);
403 u16
ar7240sw_phy_read(struct mii_bus
*mii
, unsigned phy_addr
,
409 if (phy_addr
>= AR7240_NUM_PHYS
)
412 mutex_lock(®_mutex
);
413 t
= (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
414 (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
415 AR7240_MDIO_CTRL_MASTER_EN
|
416 AR7240_MDIO_CTRL_BUSY
|
417 AR7240_MDIO_CTRL_CMD_READ
;
419 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
420 err
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
421 AR7240_MDIO_CTRL_BUSY
, 0, 5);
423 val
= __ar7240sw_reg_read(mii
, AR7240_REG_MDIO_CTRL
);
424 mutex_unlock(®_mutex
);
426 return val
& AR7240_MDIO_CTRL_DATA_M
;
429 int ar7240sw_phy_write(struct mii_bus
*mii
, unsigned phy_addr
,
430 unsigned reg_addr
, u16 reg_val
)
435 if (phy_addr
>= AR7240_NUM_PHYS
)
438 mutex_lock(®_mutex
);
439 t
= (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
440 (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
441 AR7240_MDIO_CTRL_MASTER_EN
|
442 AR7240_MDIO_CTRL_BUSY
|
443 AR7240_MDIO_CTRL_CMD_WRITE
|
446 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
447 ret
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
448 AR7240_MDIO_CTRL_BUSY
, 0, 5);
449 mutex_unlock(®_mutex
);
454 static void ar7240sw_disable_port(struct ar7240sw
*as
, unsigned port
)
456 ar7240sw_reg_write(as
->mii_bus
, AR7240_REG_PORT_CTRL(port
),
457 AR7240_PORT_CTRL_STATE_DISABLED
);
460 static void ar7240sw_setup(struct ar7240sw
*as
)
462 struct mii_bus
*mii
= as
->mii_bus
;
464 /* Enable CPU port, and disable mirror port */
465 ar7240sw_reg_write(mii
, AR7240_REG_CPU_PORT
,
467 (15 << AR7240_MIRROR_PORT_S
));
469 /* Setup TAG priority mapping */
470 ar7240sw_reg_write(mii
, AR7240_REG_TAG_PRIORITY
, 0xfa50);
472 /* Enable ARP frame acknowledge, aging, MAC replacing */
473 ar7240sw_reg_write(mii
, AR7240_REG_AT_CTRL
,
474 AR7240_AT_CTRL_RESERVED
|
475 0x2b /* 5 min age time */ |
476 AR7240_AT_CTRL_AGE_EN
|
477 AR7240_AT_CTRL_ARP_EN
|
478 AR7240_AT_CTRL_LEARN_CHANGE
);
480 /* Enable Broadcast frames transmitted to the CPU */
481 ar7240sw_reg_set(mii
, AR7240_REG_FLOOD_MASK
,
482 AR7240_FLOOD_MASK_BROAD_TO_CPU
);
485 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
, AR7240_GLOBAL_CTRL_MTU_M
,
488 /* setup Service TAG */
489 ar7240sw_reg_rmw(mii
, AR7240_REG_SERVICE_TAG
, AR7240_SERVICE_TAG_M
, 0);
492 static int ar7240sw_reset(struct ar7240sw
*as
)
494 struct mii_bus
*mii
= as
->mii_bus
;
498 /* Set all ports to disabled state. */
499 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++)
500 ar7240sw_disable_port(as
, i
);
502 /* Wait for transmit queues to drain. */
505 /* Reset the switch. */
506 ar7240sw_reg_write(mii
, AR7240_REG_MASK_CTRL
,
507 AR7240_MASK_CTRL_SOFT_RESET
);
509 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MASK_CTRL
,
510 AR7240_MASK_CTRL_SOFT_RESET
, 0, 1000);
516 static void ar7240sw_setup_port(struct ar7240sw
*as
, unsigned port
, u8 portmask
)
518 struct mii_bus
*mii
= as
->mii_bus
;
522 ctrl
= AR7240_PORT_CTRL_STATE_FORWARD
| AR7240_PORT_CTRL_LEARN
|
523 AR7240_PORT_CTRL_SINGLE_VLAN
;
525 if (port
== AR7240_PORT_CPU
) {
526 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
527 AR7240_PORT_STATUS_SPEED_1000
|
528 AR7240_PORT_STATUS_TXFLOW
|
529 AR7240_PORT_STATUS_RXFLOW
|
530 AR7240_PORT_STATUS_TXMAC
|
531 AR7240_PORT_STATUS_RXMAC
|
532 AR7240_PORT_STATUS_DUPLEX
);
534 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
535 AR7240_PORT_STATUS_LINK_AUTO
);
538 /* Set the default VID for this port */
540 vid
= as
->vlan_id
[as
->pvid
[port
]];
541 mode
= AR7240_PORT_VLAN_MODE_SECURE
;
544 mode
= AR7240_PORT_VLAN_MODE_PORT_ONLY
;
547 if (as
->vlan
&& (as
->vlan_tagged
& BIT(port
))) {
548 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_ADD
<<
549 AR7240_PORT_CTRL_VLAN_MODE_S
;
551 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_STRIP
<<
552 AR7240_PORT_CTRL_VLAN_MODE_S
;
556 if (port
== AR7240_PORT_CPU
)
557 portmask
= ar7240sw_port_mask_but(as
, AR7240_PORT_CPU
);
559 portmask
= ar7240sw_port_mask(as
, AR7240_PORT_CPU
);
562 /* allow the port to talk to all other ports, but exclude its
563 * own ID to prevent frames from being reflected back to the
564 * port that they came from */
565 portmask
&= ar7240sw_port_mask_but(as
, port
);
567 ar7240sw_reg_write(mii
, AR7240_REG_PORT_CTRL(port
), ctrl
);
568 if (sw_is_ar934x(as
)) {
571 vlan1
= (vid
<< AR934X_PORT_VLAN1_DEFAULT_CVID_S
);
572 vlan2
= (portmask
<< AR934X_PORT_VLAN2_PORT_VID_MEM_S
) |
573 (mode
<< AR934X_PORT_VLAN2_8021Q_MODE_S
);
574 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN1(port
), vlan1
);
575 ar7240sw_reg_write(mii
, AR934X_REG_PORT_VLAN2(port
), vlan2
);
579 vlan
= vid
| (mode
<< AR7240_PORT_VLAN_MODE_S
) |
580 (portmask
<< AR7240_PORT_VLAN_DEST_PORTS_S
);
582 ar7240sw_reg_write(mii
, AR7240_REG_PORT_VLAN(port
), vlan
);
586 static int ar7240_set_addr(struct ar7240sw
*as
, u8
*addr
)
588 struct mii_bus
*mii
= as
->mii_bus
;
591 t
= (addr
[4] << 8) | addr
[5];
592 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR0
, t
);
594 t
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
595 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR1
, t
);
601 ar7240_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
602 struct switch_val
*val
)
604 struct ar7240sw
*as
= sw_to_ar7240(dev
);
605 as
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
610 ar7240_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
611 struct switch_val
*val
)
613 struct ar7240sw
*as
= sw_to_ar7240(dev
);
614 val
->value
.i
= as
->vlan_id
[val
->port_vlan
];
619 ar7240_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
621 struct ar7240sw
*as
= sw_to_ar7240(dev
);
623 /* make sure no invalid PVIDs get set */
625 if (vlan
>= dev
->vlans
)
628 as
->pvid
[port
] = vlan
;
633 ar7240_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
635 struct ar7240sw
*as
= sw_to_ar7240(dev
);
636 *vlan
= as
->pvid
[port
];
641 ar7240_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
643 struct ar7240sw
*as
= sw_to_ar7240(dev
);
644 u8 ports
= as
->vlan_table
[val
->port_vlan
];
648 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
649 struct switch_port
*p
;
651 if (!(ports
& (1 << i
)))
654 p
= &val
->value
.ports
[val
->len
++];
656 if (as
->vlan_tagged
& (1 << i
))
657 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
665 ar7240_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
667 struct ar7240sw
*as
= sw_to_ar7240(dev
);
668 u8
*vt
= &as
->vlan_table
[val
->port_vlan
];
672 for (i
= 0; i
< val
->len
; i
++) {
673 struct switch_port
*p
= &val
->value
.ports
[i
];
675 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
))
676 as
->vlan_tagged
|= (1 << p
->id
);
678 as
->vlan_tagged
&= ~(1 << p
->id
);
679 as
->pvid
[p
->id
] = val
->port_vlan
;
681 /* make sure that an untagged port does not
682 * appear in other vlans */
683 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
684 if (j
== val
->port_vlan
)
686 as
->vlan_table
[j
] &= ~(1 << p
->id
);
696 ar7240_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
697 struct switch_val
*val
)
699 struct ar7240sw
*as
= sw_to_ar7240(dev
);
700 as
->vlan
= !!val
->value
.i
;
705 ar7240_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
706 struct switch_val
*val
)
708 struct ar7240sw
*as
= sw_to_ar7240(dev
);
709 val
->value
.i
= as
->vlan
;
714 ar7240_speed_str(u32 status
)
718 speed
= (status
>> AR7240_PORT_STATUS_SPEED_S
) &
719 AR7240_PORT_STATUS_SPEED_M
;
721 case AR7240_PORT_STATUS_SPEED_10
:
723 case AR7240_PORT_STATUS_SPEED_100
:
725 case AR7240_PORT_STATUS_SPEED_1000
:
733 ar7240_port_get_link(struct switch_dev
*dev
, const struct switch_attr
*attr
,
734 struct switch_val
*val
)
736 struct ar7240sw
*as
= sw_to_ar7240(dev
);
737 struct mii_bus
*mii
= as
->mii_bus
;
742 port
= val
->port_vlan
;
744 memset(as
->buf
, '\0', sizeof(as
->buf
));
745 status
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_STATUS(port
));
747 if (status
& AR7240_PORT_STATUS_LINK_UP
) {
748 len
= snprintf(as
->buf
, sizeof(as
->buf
),
749 "port:%d link:up speed:%s %s-duplex %s%s%s",
751 ar7240_speed_str(status
),
752 (status
& AR7240_PORT_STATUS_DUPLEX
) ?
754 (status
& AR7240_PORT_STATUS_TXFLOW
) ?
756 (status
& AR7240_PORT_STATUS_RXFLOW
) ?
758 (status
& AR7240_PORT_STATUS_LINK_AUTO
) ?
761 len
= snprintf(as
->buf
, sizeof(as
->buf
),
762 "port:%d link:down", port
);
765 val
->value
.s
= as
->buf
;
772 ar7240_vtu_op(struct ar7240sw
*as
, u32 op
, u32 val
)
774 struct mii_bus
*mii
= as
->mii_bus
;
776 if (ar7240sw_reg_wait(mii
, AR7240_REG_VTU
, AR7240_VTU_ACTIVE
, 0, 5))
779 if ((op
& AR7240_VTU_OP
) == AR7240_VTU_OP_LOAD
) {
780 val
&= AR7240_VTUDATA_MEMBER
;
781 val
|= AR7240_VTUDATA_VALID
;
782 ar7240sw_reg_write(mii
, AR7240_REG_VTU_DATA
, val
);
784 op
|= AR7240_VTU_ACTIVE
;
785 ar7240sw_reg_write(mii
, AR7240_REG_VTU
, op
);
789 ar7240_hw_apply(struct switch_dev
*dev
)
791 struct ar7240sw
*as
= sw_to_ar7240(dev
);
792 u8 portmask
[AR7240_NUM_PORTS
];
795 /* flush all vlan translation unit entries */
796 ar7240_vtu_op(as
, AR7240_VTU_OP_FLUSH
, 0);
798 memset(portmask
, 0, sizeof(portmask
));
800 /* calculate the port destination masks and load vlans
801 * into the vlan translation unit */
802 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
803 u8 vp
= as
->vlan_table
[j
];
808 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
811 portmask
[i
] |= vp
& ~mask
;
816 (as
->vlan_id
[j
] << AR7240_VTU_VID_S
),
821 * isolate all ports, but connect them to the cpu port */
822 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
823 if (i
== AR7240_PORT_CPU
)
826 portmask
[i
] = 1 << AR7240_PORT_CPU
;
827 portmask
[AR7240_PORT_CPU
] |= (1 << i
);
831 /* update the port destination mask registers and tag settings */
832 for (i
= 0; i
< as
->swdev
.ports
; i
++)
833 ar7240sw_setup_port(as
, i
, portmask
[i
]);
839 ar7240_reset_switch(struct switch_dev
*dev
)
841 struct ar7240sw
*as
= sw_to_ar7240(dev
);
846 static struct switch_attr ar7240_globals
[] = {
848 .type
= SWITCH_TYPE_INT
,
849 .name
= "enable_vlan",
850 .description
= "Enable VLAN mode",
851 .set
= ar7240_set_vlan
,
852 .get
= ar7240_get_vlan
,
857 static struct switch_attr ar7240_port
[] = {
859 .type
= SWITCH_TYPE_STRING
,
861 .description
= "Get port link information",
864 .get
= ar7240_port_get_link
,
868 static struct switch_attr ar7240_vlan
[] = {
870 .type
= SWITCH_TYPE_INT
,
872 .description
= "VLAN ID",
873 .set
= ar7240_set_vid
,
874 .get
= ar7240_get_vid
,
879 static const struct switch_dev_ops ar7240_ops
= {
881 .attr
= ar7240_globals
,
882 .n_attr
= ARRAY_SIZE(ar7240_globals
),
886 .n_attr
= ARRAY_SIZE(ar7240_port
),
890 .n_attr
= ARRAY_SIZE(ar7240_vlan
),
892 .get_port_pvid
= ar7240_get_pvid
,
893 .set_port_pvid
= ar7240_set_pvid
,
894 .get_vlan_ports
= ar7240_get_ports
,
895 .set_vlan_ports
= ar7240_set_ports
,
896 .apply_config
= ar7240_hw_apply
,
897 .reset_switch
= ar7240_reset_switch
,
900 static struct ar7240sw
*ar7240_probe(struct ag71xx
*ag
)
902 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
903 struct mii_bus
*mii
= ag
->mii_bus
;
905 struct switch_dev
*swdev
;
911 phy_id1
= ar7240sw_phy_read(mii
, 0, MII_PHYSID1
);
912 phy_id2
= ar7240sw_phy_read(mii
, 0, MII_PHYSID2
);
913 if ((phy_id1
!= AR7240_PHY_ID1
|| phy_id2
!= AR7240_PHY_ID2
) &&
914 (phy_id1
!= AR934X_PHY_ID1
|| phy_id2
!= AR934X_PHY_ID2
)) {
915 pr_err("%s: unknown phy id '%04x:%04x'\n",
916 ag
->dev
->name
, phy_id1
, phy_id2
);
920 as
= kzalloc(sizeof(*as
), GFP_KERNEL
);
925 as
->swdata
= pdata
->switch_data
;
929 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_MASK_CTRL
);
930 as
->ver
= (ctrl
>> AR7240_MASK_CTRL_VERSION_S
) &
931 AR7240_MASK_CTRL_VERSION_M
;
933 if (sw_is_ar7240(as
)) {
934 swdev
->name
= "AR7240/AR9330 built-in switch";
935 } else if (sw_is_ar934x(as
)) {
936 swdev
->name
= "AR934X built-in switch";
938 if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
939 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
940 AR934X_OPER_MODE0_MAC_GMII_EN
);
941 } else if (pdata
->phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
942 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE0
,
943 AR934X_OPER_MODE0_PHY_MII_EN
);
945 pr_err("%s: invalid PHY interface mode\n",
950 if (as
->swdata
->phy4_mii_en
)
951 ar7240sw_reg_set(mii
, AR934X_REG_OPER_MODE1
,
952 AR934X_REG_OPER_MODE1_PHY4_MII_EN
);
954 pr_err("%s: unsupported chip, ctrl=%08x\n",
955 ag
->dev
->name
, ctrl
);
959 swdev
->ports
= AR7240_NUM_PORTS
- 1;
960 swdev
->cpu_port
= AR7240_PORT_CPU
;
961 swdev
->vlans
= AR7240_MAX_VLANS
;
962 swdev
->ops
= &ar7240_ops
;
964 if (register_switch(&as
->swdev
, ag
->dev
) < 0)
967 pr_info("%s: Found an %s\n", ag
->dev
->name
, swdev
->name
);
969 /* initialize defaults */
970 for (i
= 0; i
< AR7240_MAX_VLANS
; i
++)
973 as
->vlan_table
[0] = ar7240sw_port_mask_all(as
);
982 static void link_function(struct work_struct
*work
) {
983 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, link_work
.work
);
988 for (i
= 0; i
< 4; i
++) {
989 int link
= ar7240sw_phy_read(ag
->mii_bus
, i
, MII_BMSR
);
990 if(link
& BMSR_LSTATUS
) {
996 spin_lock_irqsave(&ag
->lock
, flags
);
997 if(status
!= ag
->link
) {
999 ag71xx_link_adjust(ag
);
1001 spin_unlock_irqrestore(&ag
->lock
, flags
);
1003 schedule_delayed_work(&ag
->link_work
, HZ
/ 2);
1006 void ag71xx_ar7240_start(struct ag71xx
*ag
)
1008 struct ar7240sw
*as
= ag
->phy_priv
;
1012 ag
->speed
= SPEED_1000
;
1015 ar7240_set_addr(as
, ag
->dev
->dev_addr
);
1016 ar7240_hw_apply(&as
->swdev
);
1018 schedule_delayed_work(&ag
->link_work
, HZ
/ 10);
1021 void ag71xx_ar7240_stop(struct ag71xx
*ag
)
1023 cancel_delayed_work_sync(&ag
->link_work
);
1026 int __devinit
ag71xx_ar7240_init(struct ag71xx
*ag
)
1028 struct ar7240sw
*as
;
1030 as
= ar7240_probe(ag
);
1037 INIT_DELAYED_WORK(&ag
->link_work
, link_function
);
1042 void ag71xx_ar7240_cleanup(struct ag71xx
*ag
)
1044 struct ar7240sw
*as
= ag
->phy_priv
;
1049 unregister_switch(&as
->swdev
);
1051 ag
->phy_priv
= NULL
;