[package] add Marvell orion watchdog timer module
[openwrt.git] / target / linux / ar71xx / files / drivers / mtd / nand / rb750_nand.c
1 /*
2 * NAND flash driver for the MikroTik RouterBOARD 750
3 *
4 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/mtd/nand.h>
13 #include <linux/mtd/mtd.h>
14 #include <linux/mtd/partitions.h>
15 #include <linux/platform_device.h>
16 #include <linux/io.h>
17 #include <linux/slab.h>
18
19 #include <asm/mach-ar71xx/ar71xx.h>
20 #include <asm/mach-ar71xx/mach-rb750.h>
21
22 #define DRV_NAME "rb750-nand"
23 #define DRV_VERSION "0.1.0"
24 #define DRV_DESC "NAND flash driver for the RouterBOARD 750"
25
26 #define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0)
27 #define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE)
28 #define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE)
29 #define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE)
30 #define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE)
31 #define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY)
32 #define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE)
33
34 #define RB750_NAND_DATA_SHIFT 1
35 #define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT)
36 #define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY)
37 #define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \
38 RB750_NAND_NRE | RB750_NAND_NWE | \
39 RB750_NAND_NCE)
40
41 struct rb750_nand_info {
42 struct nand_chip chip;
43 struct mtd_info mtd;
44 };
45
46 /*
47 * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
48 * will not be able to find the kernel that we load.
49 */
50 static struct nand_ecclayout rb750_nand_ecclayout = {
51 .eccbytes = 6,
52 .eccpos = { 8, 9, 10, 13, 14, 15 },
53 .oobavail = 9,
54 .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
55 };
56
57 static struct mtd_partition rb750_nand_partitions[] = {
58 {
59 .name = "booter",
60 .offset = 0,
61 .size = (256 * 1024),
62 .mask_flags = MTD_WRITEABLE,
63 }, {
64 .name = "kernel",
65 .offset = (256 * 1024),
66 .size = (4 * 1024 * 1024) - (256 * 1024),
67 }, {
68 .name = "rootfs",
69 .offset = MTDPART_OFS_NXTBLK,
70 .size = MTDPART_SIZ_FULL,
71 },
72 };
73
74 static void rb750_nand_write(const u8 *buf, unsigned len)
75 {
76 void __iomem *base = ar71xx_gpio_base;
77 u32 out;
78 unsigned i;
79
80 /* set data lines to output mode */
81 __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_DATA_BITS,
82 base + GPIO_REG_OE);
83
84 out = __raw_readl(base + GPIO_REG_OUT);
85 out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE);
86 for (i = 0; i != len; i++) {
87 u32 data;
88
89 data = buf[i];
90 data <<= RB750_NAND_DATA_SHIFT;
91 data |= out;
92 __raw_writel(data, base + GPIO_REG_OUT);
93
94 __raw_writel(data | RB750_NAND_NWE, base + GPIO_REG_OUT);
95 /* flush write */
96 __raw_readl(base + GPIO_REG_OUT);
97 }
98
99 /* set data lines to input mode */
100 __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~RB750_NAND_DATA_BITS,
101 base + GPIO_REG_OE);
102 /* flush write */
103 __raw_readl(base + GPIO_REG_OE);
104 }
105
106 static int rb750_nand_read_verify(u8 *read_buf, unsigned len,
107 const u8 *verify_buf)
108 {
109 void __iomem *base = ar71xx_gpio_base;
110 unsigned i;
111
112 for (i = 0; i < len; i++) {
113 u8 data;
114
115 /* activate RE line */
116 __raw_writel(RB750_NAND_NRE, base + GPIO_REG_CLEAR);
117 /* flush write */
118 __raw_readl(base + GPIO_REG_CLEAR);
119
120 /* read input lines */
121 data = __raw_readl(base + GPIO_REG_IN) >> RB750_NAND_DATA_SHIFT;
122
123 /* deactivate RE line */
124 __raw_writel(RB750_NAND_NRE, base + GPIO_REG_SET);
125
126 if (read_buf)
127 read_buf[i] = data;
128 else if (verify_buf && verify_buf[i] != data)
129 return -EFAULT;
130 }
131
132 return 0;
133 }
134
135 static void rb750_nand_select_chip(struct mtd_info *mtd, int chip)
136 {
137 void __iomem *base = ar71xx_gpio_base;
138 u32 func;
139
140 func = __raw_readl(base + GPIO_REG_FUNC);
141 if (chip >= 0) {
142 /* disable latch */
143 rb750_latch_change(RB750_LVC573_LE, 0);
144
145 /* disable alternate functions */
146 ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE,
147 AR724X_GPIO_FUNC_SPI_EN);
148
149 /* set input mode for data lines */
150 __raw_writel(__raw_readl(base + GPIO_REG_OE) &
151 ~RB750_NAND_INPUT_BITS,
152 base + GPIO_REG_OE);
153
154 /* deactivate RE and WE lines */
155 __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE,
156 base + GPIO_REG_SET);
157 /* flush write */
158 (void) __raw_readl(base + GPIO_REG_SET);
159
160 /* activate CE line */
161 __raw_writel(RB750_NAND_NCE, base + GPIO_REG_CLEAR);
162 } else {
163 /* deactivate CE line */
164 __raw_writel(RB750_NAND_NCE, base + GPIO_REG_SET);
165 /* flush write */
166 (void) __raw_readl(base + GPIO_REG_SET);
167
168 __raw_writel(__raw_readl(base + GPIO_REG_OE) |
169 RB750_NAND_IO0 | RB750_NAND_RDY,
170 base + GPIO_REG_OE);
171
172 /* restore alternate functions */
173 ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN,
174 AR724X_GPIO_FUNC_JTAG_DISABLE);
175
176 /* enable latch */
177 rb750_latch_change(0, RB750_LVC573_LE);
178 }
179 }
180
181 static int rb750_nand_dev_ready(struct mtd_info *mtd)
182 {
183 void __iomem *base = ar71xx_gpio_base;
184
185 return !!(__raw_readl(base + GPIO_REG_IN) & RB750_NAND_RDY);
186 }
187
188 static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
189 unsigned int ctrl)
190 {
191 if (ctrl & NAND_CTRL_CHANGE) {
192 void __iomem *base = ar71xx_gpio_base;
193 u32 t;
194
195 t = __raw_readl(base + GPIO_REG_OUT);
196
197 t &= ~(RB750_NAND_CLE | RB750_NAND_ALE);
198 t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0;
199 t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0;
200
201 __raw_writel(t, base + GPIO_REG_OUT);
202 /* flush write */
203 __raw_readl(base + GPIO_REG_OUT);
204 }
205
206 if (cmd != NAND_CMD_NONE) {
207 u8 t = cmd;
208 rb750_nand_write(&t, 1);
209 }
210 }
211
212 static u8 rb750_nand_read_byte(struct mtd_info *mtd)
213 {
214 u8 data = 0;
215 rb750_nand_read_verify(&data, 1, NULL);
216 return data;
217 }
218
219 static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
220 {
221 rb750_nand_read_verify(buf, len, NULL);
222 }
223
224 static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
225 {
226 rb750_nand_write(buf, len);
227 }
228
229 static int rb750_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, int len)
230 {
231 return rb750_nand_read_verify(NULL, len, buf);
232 }
233
234 static void __init rb750_nand_gpio_init(void)
235 {
236 void __iomem *base = ar71xx_gpio_base;
237 u32 out;
238
239 out = __raw_readl(base + GPIO_REG_OUT);
240
241 /* setup output levels */
242 __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE,
243 base + GPIO_REG_SET);
244
245 __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE,
246 base + GPIO_REG_CLEAR);
247
248 /* setup input lines */
249 __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(RB750_NAND_INPUT_BITS),
250 base + GPIO_REG_OE);
251
252 /* setup output lines */
253 __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_OUTPUT_BITS,
254 base + GPIO_REG_OE);
255
256 rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0);
257 }
258
259 static int __init rb750_nand_probe(struct platform_device *pdev)
260 {
261 struct rb750_nand_info *info;
262 int ret;
263
264 printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
265
266 rb750_nand_gpio_init();
267
268 info = kzalloc(sizeof(*info), GFP_KERNEL);
269 if (!info)
270 return -ENOMEM;
271
272 info->chip.priv = &info;
273 info->mtd.priv = &info->chip;
274 info->mtd.owner = THIS_MODULE;
275
276 info->chip.select_chip = rb750_nand_select_chip;
277 info->chip.cmd_ctrl = rb750_nand_cmd_ctrl;
278 info->chip.dev_ready = rb750_nand_dev_ready;
279 info->chip.read_byte = rb750_nand_read_byte;
280 info->chip.write_buf = rb750_nand_write_buf;
281 info->chip.read_buf = rb750_nand_read_buf;
282 info->chip.verify_buf = rb750_nand_verify_buf;
283
284 info->chip.chip_delay = 25;
285 info->chip.ecc.mode = NAND_ECC_SOFT;
286 info->chip.options |= NAND_NO_AUTOINCR;
287
288 platform_set_drvdata(pdev, info);
289
290 ret = nand_scan_ident(&info->mtd, 1);
291 if (ret) {
292 ret = -ENXIO;
293 goto err_free_info;
294 }
295
296 if (info->mtd.writesize == 512)
297 info->chip.ecc.layout = &rb750_nand_ecclayout;
298
299 ret = nand_scan_tail(&info->mtd);
300 if (ret) {
301 return -ENXIO;
302 goto err_set_drvdata;
303 }
304
305 #ifdef CONFIG_MTD_PARTITIONS
306 ret = add_mtd_partitions(&info->mtd, rb750_nand_partitions,
307 ARRAY_SIZE(rb750_nand_partitions));
308 #else
309 ret = add_mtd_device(&info->mtd);
310 #endif
311 if (ret)
312 goto err_release_nand;
313
314 return 0;
315
316 err_release_nand:
317 nand_release(&info->mtd);
318 err_set_drvdata:
319 platform_set_drvdata(pdev, NULL);
320 err_free_info:
321 kfree(info);
322 return ret;
323 }
324
325 static int __devexit rb750_nand_remove(struct platform_device *pdev)
326 {
327 struct rb750_nand_info *info = platform_get_drvdata(pdev);
328
329 nand_release(&info->mtd);
330 platform_set_drvdata(pdev, NULL);
331 kfree(info);
332
333 return 0;
334 }
335
336 static struct platform_driver rb750_nand_driver = {
337 .probe = rb750_nand_probe,
338 .remove = __devexit_p(rb750_nand_remove),
339 .driver = {
340 .name = DRV_NAME,
341 .owner = THIS_MODULE,
342 },
343 };
344
345 static int __init rb750_nand_init(void)
346 {
347 return platform_driver_register(&rb750_nand_driver);
348 }
349
350 static void __exit rb750_nand_exit(void)
351 {
352 platform_driver_unregister(&rb750_nand_driver);
353 }
354
355 module_init(rb750_nand_init);
356 module_exit(rb750_nand_exit);
357
358 MODULE_DESCRIPTION(DRV_DESC);
359 MODULE_VERSION(DRV_VERSION);
360 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
361 MODULE_LICENSE("GPL v2");
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