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ath9k: make the regulatory override less intrusive - allow it to parse CTLs
[openwrt.git] / target / linux / generic / patches-2.6.34 / 975-ssb_update.patch
1 --- a/drivers/net/b44.c
2 +++ b/drivers/net/b44.c
3 @@ -135,7 +135,6 @@ static void b44_init_rings(struct b44 *)
4
5 static void b44_init_hw(struct b44 *, int);
6
7 -static int dma_desc_align_mask;
8 static int dma_desc_sync_size;
9 static int instance;
10
11 @@ -150,9 +149,8 @@ static inline void b44_sync_dma_desc_for
12 unsigned long offset,
13 enum dma_data_direction dir)
14 {
15 - ssb_dma_sync_single_range_for_device(sdev, dma_base,
16 - offset & dma_desc_align_mask,
17 - dma_desc_sync_size, dir);
18 + dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
19 + dma_desc_sync_size, dir);
20 }
21
22 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
23 @@ -160,9 +158,8 @@ static inline void b44_sync_dma_desc_for
24 unsigned long offset,
25 enum dma_data_direction dir)
26 {
27 - ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
28 - offset & dma_desc_align_mask,
29 - dma_desc_sync_size, dir);
30 + dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
31 + dma_desc_sync_size, dir);
32 }
33
34 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
35 @@ -608,10 +605,10 @@ static void b44_tx(struct b44 *bp)
36
37 BUG_ON(skb == NULL);
38
39 - ssb_dma_unmap_single(bp->sdev,
40 - rp->mapping,
41 - skb->len,
42 - DMA_TO_DEVICE);
43 + dma_unmap_single(bp->sdev->dma_dev,
44 + rp->mapping,
45 + skb->len,
46 + DMA_TO_DEVICE);
47 rp->skb = NULL;
48 dev_kfree_skb_irq(skb);
49 }
50 @@ -648,29 +645,29 @@ static int b44_alloc_rx_skb(struct b44 *
51 if (skb == NULL)
52 return -ENOMEM;
53
54 - mapping = ssb_dma_map_single(bp->sdev, skb->data,
55 - RX_PKT_BUF_SZ,
56 - DMA_FROM_DEVICE);
57 + mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
58 + RX_PKT_BUF_SZ,
59 + DMA_FROM_DEVICE);
60
61 /* Hardware bug work-around, the chip is unable to do PCI DMA
62 to/from anything above 1GB :-( */
63 - if (ssb_dma_mapping_error(bp->sdev, mapping) ||
64 + if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
65 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
66 /* Sigh... */
67 - if (!ssb_dma_mapping_error(bp->sdev, mapping))
68 - ssb_dma_unmap_single(bp->sdev, mapping,
69 + if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
70 + dma_unmap_single(bp->sdev->dma_dev, mapping,
71 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
72 dev_kfree_skb_any(skb);
73 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
74 if (skb == NULL)
75 return -ENOMEM;
76 - mapping = ssb_dma_map_single(bp->sdev, skb->data,
77 - RX_PKT_BUF_SZ,
78 - DMA_FROM_DEVICE);
79 - if (ssb_dma_mapping_error(bp->sdev, mapping) ||
80 - mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
81 - if (!ssb_dma_mapping_error(bp->sdev, mapping))
82 - ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
83 + mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
84 + RX_PKT_BUF_SZ,
85 + DMA_FROM_DEVICE);
86 + if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
87 + mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
88 + if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
89 + dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
90 dev_kfree_skb_any(skb);
91 return -ENOMEM;
92 }
93 @@ -745,9 +742,9 @@ static void b44_recycle_rx(struct b44 *b
94 dest_idx * sizeof(*dest_desc),
95 DMA_BIDIRECTIONAL);
96
97 - ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
98 - RX_PKT_BUF_SZ,
99 - DMA_FROM_DEVICE);
100 + dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
101 + RX_PKT_BUF_SZ,
102 + DMA_FROM_DEVICE);
103 }
104
105 static int b44_rx(struct b44 *bp, int budget)
106 @@ -767,9 +764,9 @@ static int b44_rx(struct b44 *bp, int bu
107 struct rx_header *rh;
108 u16 len;
109
110 - ssb_dma_sync_single_for_cpu(bp->sdev, map,
111 - RX_PKT_BUF_SZ,
112 - DMA_FROM_DEVICE);
113 + dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
114 + RX_PKT_BUF_SZ,
115 + DMA_FROM_DEVICE);
116 rh = (struct rx_header *) skb->data;
117 len = le16_to_cpu(rh->len);
118 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
119 @@ -801,8 +798,8 @@ static int b44_rx(struct b44 *bp, int bu
120 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
121 if (skb_size < 0)
122 goto drop_it;
123 - ssb_dma_unmap_single(bp->sdev, map,
124 - skb_size, DMA_FROM_DEVICE);
125 + dma_unmap_single(bp->sdev->dma_dev, map,
126 + skb_size, DMA_FROM_DEVICE);
127 /* Leave out rx_header */
128 skb_put(skb, len + RX_PKT_OFFSET);
129 skb_pull(skb, RX_PKT_OFFSET);
130 @@ -954,24 +951,24 @@ static netdev_tx_t b44_start_xmit(struct
131 goto err_out;
132 }
133
134 - mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
135 - if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
136 + mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
137 + if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
138 struct sk_buff *bounce_skb;
139
140 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
141 - if (!ssb_dma_mapping_error(bp->sdev, mapping))
142 - ssb_dma_unmap_single(bp->sdev, mapping, len,
143 + if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
144 + dma_unmap_single(bp->sdev->dma_dev, mapping, len,
145 DMA_TO_DEVICE);
146
147 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
148 if (!bounce_skb)
149 goto err_out;
150
151 - mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
152 - len, DMA_TO_DEVICE);
153 - if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
154 - if (!ssb_dma_mapping_error(bp->sdev, mapping))
155 - ssb_dma_unmap_single(bp->sdev, mapping,
156 + mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
157 + len, DMA_TO_DEVICE);
158 + if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
159 + if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
160 + dma_unmap_single(bp->sdev->dma_dev, mapping,
161 len, DMA_TO_DEVICE);
162 dev_kfree_skb_any(bounce_skb);
163 goto err_out;
164 @@ -1014,8 +1011,6 @@ static netdev_tx_t b44_start_xmit(struct
165 if (TX_BUFFS_AVAIL(bp) < 1)
166 netif_stop_queue(dev);
167
168 - dev->trans_start = jiffies;
169 -
170 out_unlock:
171 spin_unlock_irqrestore(&bp->lock, flags);
172
173 @@ -1070,8 +1065,8 @@ static void b44_free_rings(struct b44 *b
174
175 if (rp->skb == NULL)
176 continue;
177 - ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
178 - DMA_FROM_DEVICE);
179 + dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
180 + DMA_FROM_DEVICE);
181 dev_kfree_skb_any(rp->skb);
182 rp->skb = NULL;
183 }
184 @@ -1082,8 +1077,8 @@ static void b44_free_rings(struct b44 *b
185
186 if (rp->skb == NULL)
187 continue;
188 - ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
189 - DMA_TO_DEVICE);
190 + dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
191 + DMA_TO_DEVICE);
192 dev_kfree_skb_any(rp->skb);
193 rp->skb = NULL;
194 }
195 @@ -1105,14 +1100,12 @@ static void b44_init_rings(struct b44 *b
196 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
197
198 if (bp->flags & B44_FLAG_RX_RING_HACK)
199 - ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
200 - DMA_TABLE_BYTES,
201 - DMA_BIDIRECTIONAL);
202 + dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
203 + DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
204
205 if (bp->flags & B44_FLAG_TX_RING_HACK)
206 - ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
207 - DMA_TABLE_BYTES,
208 - DMA_TO_DEVICE);
209 + dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
210 + DMA_TABLE_BYTES, DMA_TO_DEVICE);
211
212 for (i = 0; i < bp->rx_pending; i++) {
213 if (b44_alloc_rx_skb(bp, -1, i) < 0)
214 @@ -1132,27 +1125,23 @@ static void b44_free_consistent(struct b
215 bp->tx_buffers = NULL;
216 if (bp->rx_ring) {
217 if (bp->flags & B44_FLAG_RX_RING_HACK) {
218 - ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
219 - DMA_TABLE_BYTES,
220 - DMA_BIDIRECTIONAL);
221 + dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
222 + DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
223 kfree(bp->rx_ring);
224 } else
225 - ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
226 - bp->rx_ring, bp->rx_ring_dma,
227 - GFP_KERNEL);
228 + dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
229 + bp->rx_ring, bp->rx_ring_dma);
230 bp->rx_ring = NULL;
231 bp->flags &= ~B44_FLAG_RX_RING_HACK;
232 }
233 if (bp->tx_ring) {
234 if (bp->flags & B44_FLAG_TX_RING_HACK) {
235 - ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
236 - DMA_TABLE_BYTES,
237 - DMA_TO_DEVICE);
238 + dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
239 + DMA_TABLE_BYTES, DMA_TO_DEVICE);
240 kfree(bp->tx_ring);
241 } else
242 - ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
243 - bp->tx_ring, bp->tx_ring_dma,
244 - GFP_KERNEL);
245 + dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
246 + bp->tx_ring, bp->tx_ring_dma);
247 bp->tx_ring = NULL;
248 bp->flags &= ~B44_FLAG_TX_RING_HACK;
249 }
250 @@ -1177,7 +1166,8 @@ static int b44_alloc_consistent(struct b
251 goto out_err;
252
253 size = DMA_TABLE_BYTES;
254 - bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
255 + bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
256 + &bp->rx_ring_dma, gfp);
257 if (!bp->rx_ring) {
258 /* Allocation may have failed due to pci_alloc_consistent
259 insisting on use of GFP_DMA, which is more restrictive
260 @@ -1189,11 +1179,11 @@ static int b44_alloc_consistent(struct b
261 if (!rx_ring)
262 goto out_err;
263
264 - rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
265 - DMA_TABLE_BYTES,
266 - DMA_BIDIRECTIONAL);
267 + rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
268 + DMA_TABLE_BYTES,
269 + DMA_BIDIRECTIONAL);
270
271 - if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
272 + if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
273 rx_ring_dma + size > DMA_BIT_MASK(30)) {
274 kfree(rx_ring);
275 goto out_err;
276 @@ -1204,7 +1194,8 @@ static int b44_alloc_consistent(struct b
277 bp->flags |= B44_FLAG_RX_RING_HACK;
278 }
279
280 - bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
281 + bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
282 + &bp->tx_ring_dma, gfp);
283 if (!bp->tx_ring) {
284 /* Allocation may have failed due to ssb_dma_alloc_consistent
285 insisting on use of GFP_DMA, which is more restrictive
286 @@ -1216,11 +1207,11 @@ static int b44_alloc_consistent(struct b
287 if (!tx_ring)
288 goto out_err;
289
290 - tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
291 - DMA_TABLE_BYTES,
292 - DMA_TO_DEVICE);
293 + tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
294 + DMA_TABLE_BYTES,
295 + DMA_TO_DEVICE);
296
297 - if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
298 + if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
299 tx_ring_dma + size > DMA_BIT_MASK(30)) {
300 kfree(tx_ring);
301 goto out_err;
302 @@ -2178,12 +2169,14 @@ static int __devinit b44_init_one(struct
303 "Failed to powerup the bus\n");
304 goto err_out_free_dev;
305 }
306 - err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
307 - if (err) {
308 +
309 + if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
310 + dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
311 dev_err(sdev->dev,
312 "Required 30BIT DMA mask unsupported by the system\n");
313 goto err_out_powerdown;
314 }
315 +
316 err = b44_get_invariants(bp);
317 if (err) {
318 dev_err(sdev->dev,
319 @@ -2346,7 +2339,6 @@ static int __init b44_init(void)
320 int err;
321
322 /* Setup paramaters for syncing RX/TX DMA descriptors */
323 - dma_desc_align_mask = ~(dma_desc_align_size - 1);
324 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
325
326 err = b44_pci_init();
327 --- a/drivers/ssb/driver_chipcommon.c
328 +++ b/drivers/ssb/driver_chipcommon.c
329 @@ -209,6 +209,24 @@ static void chipco_powercontrol_init(str
330 }
331 }
332
333 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
334 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
335 +{
336 + struct ssb_bus *bus = cc->dev->bus;
337 +
338 + switch (bus->chip_id) {
339 + case 0x4312:
340 + case 0x4322:
341 + case 0x4328:
342 + return 7000;
343 + case 0x4325:
344 + /* TODO: */
345 + default:
346 + return 15000;
347 + }
348 +}
349 +
350 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
351 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
352 {
353 struct ssb_bus *bus = cc->dev->bus;
354 @@ -218,6 +236,12 @@ static void calc_fast_powerup_delay(stru
355
356 if (bus->bustype != SSB_BUSTYPE_PCI)
357 return;
358 +
359 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
360 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
361 + return;
362 + }
363 +
364 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
365 return;
366
367 @@ -373,6 +397,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
368 {
369 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
370 }
371 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
372
373 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
374 {
375 --- a/drivers/ssb/driver_chipcommon_pmu.c
376 +++ b/drivers/ssb/driver_chipcommon_pmu.c
377 @@ -502,9 +502,9 @@ static void ssb_pmu_resources_init(struc
378 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
379 }
380
381 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
382 void ssb_pmu_init(struct ssb_chipcommon *cc)
383 {
384 - struct ssb_bus *bus = cc->dev->bus;
385 u32 pmucap;
386
387 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
388 @@ -516,15 +516,12 @@ void ssb_pmu_init(struct ssb_chipcommon
389 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
390 cc->pmu.rev, pmucap);
391
392 - if (cc->pmu.rev >= 1) {
393 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
394 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
395 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
396 - } else {
397 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
398 - SSB_CHIPCO_PMU_CTL_NOILPONW);
399 - }
400 - }
401 + if (cc->pmu.rev == 1)
402 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
403 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
404 + else
405 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
406 + SSB_CHIPCO_PMU_CTL_NOILPONW);
407 ssb_pmu_pll_init(cc);
408 ssb_pmu_resources_init(cc);
409 }
410 --- a/drivers/ssb/main.c
411 +++ b/drivers/ssb/main.c
412 @@ -486,6 +486,7 @@ static int ssb_devices_register(struct s
413 #ifdef CONFIG_SSB_PCIHOST
414 sdev->irq = bus->host_pci->irq;
415 dev->parent = &bus->host_pci->dev;
416 + sdev->dma_dev = dev->parent;
417 #endif
418 break;
419 case SSB_BUSTYPE_PCMCIA:
420 @@ -501,6 +502,7 @@ static int ssb_devices_register(struct s
421 break;
422 case SSB_BUSTYPE_SSB:
423 dev->dma_mask = &dev->coherent_dma_mask;
424 + sdev->dma_dev = dev;
425 break;
426 }
427
428 @@ -834,6 +836,9 @@ int ssb_bus_pcibus_register(struct ssb_b
429 if (!err) {
430 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
431 "PCI device %s\n", dev_name(&host_pci->dev));
432 + } else {
433 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
434 + " of SSB with error %d\n", err);
435 }
436
437 return err;
438 @@ -1223,80 +1228,6 @@ u32 ssb_dma_translation(struct ssb_devic
439 }
440 EXPORT_SYMBOL(ssb_dma_translation);
441
442 -int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
443 -{
444 -#ifdef CONFIG_SSB_PCIHOST
445 - int err;
446 -#endif
447 -
448 - switch (dev->bus->bustype) {
449 - case SSB_BUSTYPE_PCI:
450 -#ifdef CONFIG_SSB_PCIHOST
451 - err = pci_set_dma_mask(dev->bus->host_pci, mask);
452 - if (err)
453 - return err;
454 - err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
455 - return err;
456 -#endif
457 - case SSB_BUSTYPE_SSB:
458 - return dma_set_mask(dev->dev, mask);
459 - default:
460 - __ssb_dma_not_implemented(dev);
461 - }
462 - return -ENOSYS;
463 -}
464 -EXPORT_SYMBOL(ssb_dma_set_mask);
465 -
466 -void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
467 - dma_addr_t *dma_handle, gfp_t gfp_flags)
468 -{
469 - switch (dev->bus->bustype) {
470 - case SSB_BUSTYPE_PCI:
471 -#ifdef CONFIG_SSB_PCIHOST
472 - if (gfp_flags & GFP_DMA) {
473 - /* Workaround: The PCI API does not support passing
474 - * a GFP flag. */
475 - return dma_alloc_coherent(&dev->bus->host_pci->dev,
476 - size, dma_handle, gfp_flags);
477 - }
478 - return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
479 -#endif
480 - case SSB_BUSTYPE_SSB:
481 - return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
482 - default:
483 - __ssb_dma_not_implemented(dev);
484 - }
485 - return NULL;
486 -}
487 -EXPORT_SYMBOL(ssb_dma_alloc_consistent);
488 -
489 -void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
490 - void *vaddr, dma_addr_t dma_handle,
491 - gfp_t gfp_flags)
492 -{
493 - switch (dev->bus->bustype) {
494 - case SSB_BUSTYPE_PCI:
495 -#ifdef CONFIG_SSB_PCIHOST
496 - if (gfp_flags & GFP_DMA) {
497 - /* Workaround: The PCI API does not support passing
498 - * a GFP flag. */
499 - dma_free_coherent(&dev->bus->host_pci->dev,
500 - size, vaddr, dma_handle);
501 - return;
502 - }
503 - pci_free_consistent(dev->bus->host_pci, size,
504 - vaddr, dma_handle);
505 - return;
506 -#endif
507 - case SSB_BUSTYPE_SSB:
508 - dma_free_coherent(dev->dev, size, vaddr, dma_handle);
509 - return;
510 - default:
511 - __ssb_dma_not_implemented(dev);
512 - }
513 -}
514 -EXPORT_SYMBOL(ssb_dma_free_consistent);
515 -
516 int ssb_bus_may_powerdown(struct ssb_bus *bus)
517 {
518 struct ssb_chipcommon *cc;
519 --- a/drivers/ssb/pci.c
520 +++ b/drivers/ssb/pci.c
521 @@ -168,7 +168,7 @@ err_pci:
522 }
523
524 /* Get the word-offset for a SSB_SPROM_XXX define. */
525 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE1) / sizeof(u16))
526 +#define SPOFF(offset) ((offset) / sizeof(u16))
527 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
528 #define SPEX16(_outvar, _offset, _mask, _shift) \
529 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
530 --- a/include/linux/ssb/ssb.h
531 +++ b/include/linux/ssb/ssb.h
532 @@ -167,7 +167,7 @@ struct ssb_device {
533 * is an optimization. */
534 const struct ssb_bus_ops *ops;
535
536 - struct device *dev;
537 + struct device *dev, *dma_dev;
538
539 struct ssb_bus *bus;
540 struct ssb_device_id id;
541 @@ -470,14 +470,6 @@ extern u32 ssb_dma_translation(struct ss
542 #define SSB_DMA_TRANSLATION_MASK 0xC0000000
543 #define SSB_DMA_TRANSLATION_SHIFT 30
544
545 -extern int ssb_dma_set_mask(struct ssb_device *dev, u64 mask);
546 -
547 -extern void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
548 - dma_addr_t *dma_handle, gfp_t gfp_flags);
549 -extern void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
550 - void *vaddr, dma_addr_t dma_handle,
551 - gfp_t gfp_flags);
552 -
553 static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
554 {
555 #ifdef CONFIG_SSB_DEBUG
556 @@ -486,155 +478,6 @@ static inline void __cold __ssb_dma_not_
557 #endif /* DEBUG */
558 }
559
560 -static inline int ssb_dma_mapping_error(struct ssb_device *dev, dma_addr_t addr)
561 -{
562 - switch (dev->bus->bustype) {
563 - case SSB_BUSTYPE_PCI:
564 -#ifdef CONFIG_SSB_PCIHOST
565 - return pci_dma_mapping_error(dev->bus->host_pci, addr);
566 -#endif
567 - break;
568 - case SSB_BUSTYPE_SSB:
569 - return dma_mapping_error(dev->dev, addr);
570 - default:
571 - break;
572 - }
573 - __ssb_dma_not_implemented(dev);
574 - return -ENOSYS;
575 -}
576 -
577 -static inline dma_addr_t ssb_dma_map_single(struct ssb_device *dev, void *p,
578 - size_t size, enum dma_data_direction dir)
579 -{
580 - switch (dev->bus->bustype) {
581 - case SSB_BUSTYPE_PCI:
582 -#ifdef CONFIG_SSB_PCIHOST
583 - return pci_map_single(dev->bus->host_pci, p, size, dir);
584 -#endif
585 - break;
586 - case SSB_BUSTYPE_SSB:
587 - return dma_map_single(dev->dev, p, size, dir);
588 - default:
589 - break;
590 - }
591 - __ssb_dma_not_implemented(dev);
592 - return 0;
593 -}
594 -
595 -static inline void ssb_dma_unmap_single(struct ssb_device *dev, dma_addr_t dma_addr,
596 - size_t size, enum dma_data_direction dir)
597 -{
598 - switch (dev->bus->bustype) {
599 - case SSB_BUSTYPE_PCI:
600 -#ifdef CONFIG_SSB_PCIHOST
601 - pci_unmap_single(dev->bus->host_pci, dma_addr, size, dir);
602 - return;
603 -#endif
604 - break;
605 - case SSB_BUSTYPE_SSB:
606 - dma_unmap_single(dev->dev, dma_addr, size, dir);
607 - return;
608 - default:
609 - break;
610 - }
611 - __ssb_dma_not_implemented(dev);
612 -}
613 -
614 -static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev,
615 - dma_addr_t dma_addr,
616 - size_t size,
617 - enum dma_data_direction dir)
618 -{
619 - switch (dev->bus->bustype) {
620 - case SSB_BUSTYPE_PCI:
621 -#ifdef CONFIG_SSB_PCIHOST
622 - pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
623 - size, dir);
624 - return;
625 -#endif
626 - break;
627 - case SSB_BUSTYPE_SSB:
628 - dma_sync_single_for_cpu(dev->dev, dma_addr, size, dir);
629 - return;
630 - default:
631 - break;
632 - }
633 - __ssb_dma_not_implemented(dev);
634 -}
635 -
636 -static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev,
637 - dma_addr_t dma_addr,
638 - size_t size,
639 - enum dma_data_direction dir)
640 -{
641 - switch (dev->bus->bustype) {
642 - case SSB_BUSTYPE_PCI:
643 -#ifdef CONFIG_SSB_PCIHOST
644 - pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
645 - size, dir);
646 - return;
647 -#endif
648 - break;
649 - case SSB_BUSTYPE_SSB:
650 - dma_sync_single_for_device(dev->dev, dma_addr, size, dir);
651 - return;
652 - default:
653 - break;
654 - }
655 - __ssb_dma_not_implemented(dev);
656 -}
657 -
658 -static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev,
659 - dma_addr_t dma_addr,
660 - unsigned long offset,
661 - size_t size,
662 - enum dma_data_direction dir)
663 -{
664 - switch (dev->bus->bustype) {
665 - case SSB_BUSTYPE_PCI:
666 -#ifdef CONFIG_SSB_PCIHOST
667 - /* Just sync everything. That's all the PCI API can do. */
668 - pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
669 - offset + size, dir);
670 - return;
671 -#endif
672 - break;
673 - case SSB_BUSTYPE_SSB:
674 - dma_sync_single_range_for_cpu(dev->dev, dma_addr, offset,
675 - size, dir);
676 - return;
677 - default:
678 - break;
679 - }
680 - __ssb_dma_not_implemented(dev);
681 -}
682 -
683 -static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev,
684 - dma_addr_t dma_addr,
685 - unsigned long offset,
686 - size_t size,
687 - enum dma_data_direction dir)
688 -{
689 - switch (dev->bus->bustype) {
690 - case SSB_BUSTYPE_PCI:
691 -#ifdef CONFIG_SSB_PCIHOST
692 - /* Just sync everything. That's all the PCI API can do. */
693 - pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
694 - offset + size, dir);
695 - return;
696 -#endif
697 - break;
698 - case SSB_BUSTYPE_SSB:
699 - dma_sync_single_range_for_device(dev->dev, dma_addr, offset,
700 - size, dir);
701 - return;
702 - default:
703 - break;
704 - }
705 - __ssb_dma_not_implemented(dev);
706 -}
707 -
708 -
709 #ifdef CONFIG_SSB_PCIHOST
710 /* PCI-host wrapper driver */
711 extern int ssb_pcihost_register(struct pci_driver *driver);
712 --- a/include/linux/ssb/ssb_regs.h
713 +++ b/include/linux/ssb/ssb_regs.h
714 @@ -172,25 +172,25 @@
715 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
716 #define SSB_SPROM_BASE1 0x1000
717 #define SSB_SPROM_BASE31 0x0800
718 -#define SSB_SPROM_REVISION 0x107E
719 +#define SSB_SPROM_REVISION 0x007E
720 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
721 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
722 #define SSB_SPROM_REVISION_CRC_SHIFT 8
723
724 /* SPROM Revision 1 */
725 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
726 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
727 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
728 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
729 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
730 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
731 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
732 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
733 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
734 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
735 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
736 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
737 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
738 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
739 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
740 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
741 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
742 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
743 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
744 -#define SSB_SPROM1_BINF 0x105C /* Board info */
745 +#define SSB_SPROM1_BINF 0x005C /* Board info */
746 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
747 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
748 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
749 @@ -198,63 +198,63 @@
750 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
751 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
752 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
753 -#define SSB_SPROM1_PA0B0 0x105E
754 -#define SSB_SPROM1_PA0B1 0x1060
755 -#define SSB_SPROM1_PA0B2 0x1062
756 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
757 +#define SSB_SPROM1_PA0B0 0x005E
758 +#define SSB_SPROM1_PA0B1 0x0060
759 +#define SSB_SPROM1_PA0B2 0x0062
760 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
761 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
762 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
763 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
764 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
765 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
766 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
767 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
768 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
769 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
770 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
771 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
772 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
773 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
774 -#define SSB_SPROM1_PA1B0 0x106A
775 -#define SSB_SPROM1_PA1B1 0x106C
776 -#define SSB_SPROM1_PA1B2 0x106E
777 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
778 +#define SSB_SPROM1_PA1B0 0x006A
779 +#define SSB_SPROM1_PA1B1 0x006C
780 +#define SSB_SPROM1_PA1B2 0x006E
781 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
782 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
783 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
784 #define SSB_SPROM1_ITSSI_A_SHIFT 8
785 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
786 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
787 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
788 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
789 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
790 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
791 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
792 #define SSB_SPROM1_AGAIN_A_SHIFT 8
793
794 /* SPROM Revision 2 (inherits from rev 1) */
795 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
796 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
797 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
798 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
799 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
800 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
801 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
802 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
803 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
804 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
805 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
806 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
807 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
808 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
809 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
810 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
811 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
812 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
813 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
814 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
815 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
816 #define SSB_SPROM2_OPO_VALUE 0x00FF
817 #define SSB_SPROM2_OPO_UNUSED 0xFF00
818 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
819 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
820
821 /* SPROM Revision 3 (inherits most data from rev 2) */
822 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
823 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
824 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
825 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
826 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
827 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
828 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
829 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
830 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
831 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
832 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
833 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
834 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
835 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
836 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
837 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
838 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
839 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
840 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
841 @@ -265,100 +265,100 @@
842 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
843
844 /* SPROM Revision 4 */
845 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
846 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
847 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
848 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
849 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
850 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
851 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
852 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
853 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
854 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
855 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
856 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
857 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
858 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
859 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
860 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
861 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
862 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
863 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
864 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
865 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
866 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
867 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
868 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
869 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
870 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
871 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
872 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
873 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
874 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
875 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
876 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
877 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
878 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
879 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
880 #define SSB_SPROM4_AGAIN0_SHIFT 0
881 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
882 #define SSB_SPROM4_AGAIN1_SHIFT 8
883 -#define SSB_SPROM4_AGAIN23 0x1060
884 +#define SSB_SPROM4_AGAIN23 0x0060
885 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
886 #define SSB_SPROM4_AGAIN2_SHIFT 0
887 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
888 #define SSB_SPROM4_AGAIN3_SHIFT 8
889 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
890 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
891 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
892 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
893 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
894 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
895 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
896 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
897 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
898 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
899 #define SSB_SPROM4_ITSSI_A_SHIFT 8
900 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
901 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
902 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
903 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
904 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
905 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
906 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
907 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
908 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
909 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
910 -#define SSB_SPROM4_PA0B2 0x1086
911 -#define SSB_SPROM4_PA1B0 0x108E
912 -#define SSB_SPROM4_PA1B1 0x1090
913 -#define SSB_SPROM4_PA1B2 0x1092
914 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
915 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
916 +#define SSB_SPROM4_PA0B2 0x0086
917 +#define SSB_SPROM4_PA1B0 0x008E
918 +#define SSB_SPROM4_PA1B1 0x0090
919 +#define SSB_SPROM4_PA1B2 0x0092
920
921 /* SPROM Revision 5 (inherits most data from rev 4) */
922 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
923 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
924 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
925 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
926 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
927 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
928 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
929 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
930 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
931 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
932 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
933 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
934 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
935 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
936 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
937 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
938 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
939 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
940
941 /* SPROM Revision 8 */
942 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
943 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
944 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
945 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
946 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
947 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
948 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
949 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
950 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
951 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
952 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
953 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
954 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
955 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
956 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
957 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
958 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
959 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
960 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
961 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
962 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
963 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
964 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
965 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
966 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
967 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
968 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
969 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
970 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
971 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
972 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
973 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
974 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
975 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
976 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
977 #define SSB_SPROM8_AGAIN0_SHIFT 0
978 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
979 #define SSB_SPROM8_AGAIN1_SHIFT 8
980 -#define SSB_SPROM8_AGAIN23 0x10A0
981 +#define SSB_SPROM8_AGAIN23 0x00A0
982 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
983 #define SSB_SPROM8_AGAIN2_SHIFT 0
984 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
985 #define SSB_SPROM8_AGAIN3_SHIFT 8
986 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
987 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
988 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
989 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
990 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
991 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
992 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
993 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
994 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
995 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
996 #define SSB_SPROM8_RSSISMF2G 0x000F
997 #define SSB_SPROM8_RSSISMC2G 0x00F0
998 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
999 @@ -366,7 +366,7 @@
1000 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
1001 #define SSB_SPROM8_BXA2G 0x1800
1002 #define SSB_SPROM8_BXA2G_SHIFT 11
1003 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1004 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
1005 #define SSB_SPROM8_RSSISMF5G 0x000F
1006 #define SSB_SPROM8_RSSISMC5G 0x00F0
1007 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
1008 @@ -374,47 +374,47 @@
1009 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
1010 #define SSB_SPROM8_BXA5G 0x1800
1011 #define SSB_SPROM8_BXA5G_SHIFT 11
1012 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1013 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
1014 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1015 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1016 #define SSB_SPROM8_TRI5G_SHIFT 8
1017 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1018 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
1019 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1020 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1021 #define SSB_SPROM8_TRI5GH_SHIFT 8
1022 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1023 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
1024 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1025 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1026 #define SSB_SPROM8_RXPO5G_SHIFT 8
1027 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1028 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1029 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1030 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1031 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
1032 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1033 -#define SSB_SPROM8_PA0B1 0x10C4
1034 -#define SSB_SPROM8_PA0B2 0x10C6
1035 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1036 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1037 +#define SSB_SPROM8_PA0B1 0x00C4
1038 +#define SSB_SPROM8_PA0B2 0x00C6
1039 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
1040 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1041 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1042 #define SSB_SPROM8_ITSSI_A_SHIFT 8
1043 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1044 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
1045 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1046 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1047 #define SSB_SPROM8_MAXP_AL_SHIFT 8
1048 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1049 -#define SSB_SPROM8_PA1B1 0x10CE
1050 -#define SSB_SPROM8_PA1B2 0x10D0
1051 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1052 -#define SSB_SPROM8_PA1LOB1 0x10D4
1053 -#define SSB_SPROM8_PA1LOB2 0x10D6
1054 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1055 -#define SSB_SPROM8_PA1HIB1 0x10DA
1056 -#define SSB_SPROM8_PA1HIB2 0x10DC
1057 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1058 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1059 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1060 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1061 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1062 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1063 +#define SSB_SPROM8_PA1B1 0x00CE
1064 +#define SSB_SPROM8_PA1B2 0x00D0
1065 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1066 +#define SSB_SPROM8_PA1LOB1 0x00D4
1067 +#define SSB_SPROM8_PA1LOB2 0x00D6
1068 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1069 +#define SSB_SPROM8_PA1HIB1 0x00DA
1070 +#define SSB_SPROM8_PA1HIB2 0x00DC
1071 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1072 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1073 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1074 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1075 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1076
1077 /* Values for SSB_SPROM1_BINF_CCODE */
1078 enum {
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