target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/bootmem.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/traps.h>
  24 #include <asm/time.h>           /* for mips_hpt_frequency */
  25 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  26 #include <asm/mips_machine.h>
  27
  28 #include <asm/mach-ar71xx/ar71xx.h>
  29 #include <asm/mach-ar71xx/pci.h>
  30
  31 #include "devices.h"
  32
  33 #define AR71XX_SYS_TYPE_LEN     64
  34 #define AR71XX_BASE_FREQ        40000000
  35 #define AR91XX_BASE_FREQ        5000000
  36
  37 unsigned long ar71xx_mach_type;
  38
  39 u32 ar71xx_cpu_freq;
  40 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  41
  42 u32 ar71xx_ahb_freq;
  43 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  44
  45 u32 ar71xx_ddr_freq;
  46 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  47
  48 enum ar71xx_soc_type ar71xx_soc;
  49 EXPORT_SYMBOL_GPL(ar71xx_soc);
  50
  51 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
  52                              struct ar71xx_pci_irq *map) __initdata;
  53
  54 int (*ar71xx_pci_be_handler)(int is_fixup);
  55
  56 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  57
  58 static void ar71xx_restart(char *command)
  59 {
  60         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  61         for (;;)
  62                 if (cpu_wait)
  63                         cpu_wait();
  64 }
  65
  66 static void ar71xx_halt(void)
  67 {
  68         while (1)
  69                 cpu_wait();
  70 }
  71
  72 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
  73 {
  74         int err = 0;
  75
  76         if (ar71xx_pci_be_handler)
  77                 err = ar71xx_pci_be_handler(is_fixup);
  78
  79         return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  80 }
  81
  82 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
  83 {
  84         if (!ar71xx_pci_bios_init)
  85                 return 0;
  86
  87         return ar71xx_pci_bios_init(nr_irqs, map);
  88 }
  89
  90 static void __init ar71xx_detect_mem_size(void)
  91 {
  92         unsigned long size;
  93
  94         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  95              size <<= 1 ) {
  96                 if (!memcmp(ar71xx_detect_mem_size,
  97                             ar71xx_detect_mem_size + size, 1024))
  98                         break;
  99         }
 100
 101         add_memory_region(0, size, BOOT_MEM_RAM);
 102 }
 103
 104 static void __init ar71xx_detect_sys_type(void)
 105 {
 106         char *chip;
 107         u32 id;
 108         u32 rev;
 109
 110         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) & REV_ID_MASK;
 111         rev = (id >> REV_ID_REVISION_SHIFT) & REV_ID_REVISION_MASK;
 112
 113         switch (id & REV_ID_CHIP_MASK) {
 114         case REV_ID_CHIP_AR7130:
 115                 ar71xx_soc = AR71XX_SOC_AR7130;
 116                 chip = "7130";
 117                 break;
 118
 119         case REV_ID_CHIP_AR7141:
 120                 ar71xx_soc = AR71XX_SOC_AR7141;
 121                 chip = "7141";
 122                 break;
 123
 124         case REV_ID_CHIP_AR7161:
 125                 ar71xx_soc = AR71XX_SOC_AR7161;
 126                 chip = "7161";
 127                 break;
 128
 129         case REV_ID_CHIP_AR9130:
 130                 ar71xx_soc = AR71XX_SOC_AR9130;
 131                 chip = "9130";
 132                 break;
 133
 134         case REV_ID_CHIP_AR9132:
 135                 ar71xx_soc = AR71XX_SOC_AR9132;
 136                 chip = "9132";
 137                 break;
 138
 139         default:
 140                 panic("ar71xx: unknown chip id:0x%02x\n", id);
 141         }
 142
 143         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u (id:0x%02x)",
 144                 chip, rev, id);
 145 }
 146
 147 static void __init ar91xx_detect_sys_frequency(void)
 148 {
 149         u32 pll;
 150         u32 freq;
 151         u32 div;
 152
 153         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 154
 155         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 156         freq = div * AR91XX_BASE_FREQ;
 157
 158         ar71xx_cpu_freq = freq;
 159
 160         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 161         ar71xx_ddr_freq = freq / div;
 162
 163         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 164         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 165 }
 166
 167 static void __init ar71xx_detect_sys_frequency(void)
 168 {
 169         u32 pll;
 170         u32 freq;
 171         u32 div;
 172
 173         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 174
 175         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 176         freq = div * AR71XX_BASE_FREQ;
 177
 178         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 179         ar71xx_cpu_freq = freq / div;
 180
 181         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 182         ar71xx_ddr_freq = freq / div;
 183
 184         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 185         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 186 }
 187
 188 static void __init detect_sys_frequency(void)
 189 {
 190         switch (ar71xx_soc) {
 191         case AR71XX_SOC_AR7130:
 192         case AR71XX_SOC_AR7141:
 193         case AR71XX_SOC_AR7161:
 194                 ar71xx_detect_sys_frequency();
 195                 break;
 196
 197         case AR71XX_SOC_AR9130:
 198         case AR71XX_SOC_AR9132:
 199                 ar91xx_detect_sys_frequency();
 200                 break;
 201
 202         default:
 203                 BUG();
 204         }
 205 }
 206
 207 #ifdef CONFIG_AR71XX_EARLY_SERIAL
 208 static void __init ar71xx_early_serial_setup(void)
 209 {
 210         struct uart_port p;
 211
 212         memset(&p, 0, sizeof(p));
 213
 214         p.flags         = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
 215         p.iotype        = UPIO_MEM32;
 216         p.uartclk       = ar71xx_ahb_freq;
 217         p.irq           = AR71XX_MISC_IRQ_UART;
 218         p.regshift      = 2;
 219         p.mapbase       = AR71XX_UART_BASE;
 220
 221         early_serial_setup(&p);
 222 }
 223 #else
 224 static inline void ar71xx_early_serial_setup(void) {};
 225 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
 226
 227 const char *get_system_type(void)
 228 {
 229         return ar71xx_sys_type;
 230 }
 231
 232 unsigned int __cpuinit get_c0_compare_irq(void)
 233 {
 234         return CP0_LEGACY_COMPARE_IRQ;
 235 }
 236
 237 void __init plat_mem_setup(void)
 238 {
 239         set_io_port_base(KSEG1);
 240
 241         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 242                                                 AR71XX_DDR_CTRL_SIZE);
 243
 244         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 245                                                 AR71XX_PLL_SIZE);
 246
 247         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 248                                                 AR71XX_RESET_SIZE);
 249
 250         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 251
 252         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 253                                                 AR71XX_USB_CTRL_SIZE);
 254
 255         ar71xx_detect_mem_size();
 256         ar71xx_detect_sys_type();
 257         detect_sys_frequency();
 258
 259         printk(KERN_INFO
 260                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 261                 ar71xx_sys_type,
 262                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 263                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 264                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 265
 266         _machine_restart = ar71xx_restart;
 267         _machine_halt = ar71xx_halt;
 268         pm_power_off = ar71xx_halt;
 269
 270         board_be_handler = ar71xx_be_handler;
 271
 272         ar71xx_early_serial_setup();
 273 }
 274
 275 void __init plat_time_init(void)
 276 {
 277         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 278 }
 279
 280 static int __init ar71xx_machine_setup(void)
 281 {
 282         ar71xx_gpio_init();
 283
 284         ar71xx_add_device_uart();
 285         ar71xx_add_device_wdt();
 286
 287         mips_machine_setup(ar71xx_mach_type);
 288         return 0;
 289 }
 290
 291 arch_initcall(ar71xx_machine_setup);