package/uboot-xburst/files/include/configs/n516.h

   1 /*
   2  * (C) Copyright 2006
   3  * Ingenic Semiconductor, <jlwei@ingenic.cn>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /*
  22  * This file contains the configuration parameters for the pavo board.
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 //#define DEBUG
  29 //#define DEBUG_SHELL
  30
  31 #define CONFIG_MIPS32           1  /* MIPS32 CPU core */
  32 #define CONFIG_JzRISC           1  /* JzRISC core */
  33 #define CONFIG_JZSOC            1  /* Jz SoC */
  34 #define CONFIG_JZ4740           1  /* Jz4740 SoC */
  35 #define CONFIG_PAVO             1  /* PAVO validation board */
  36
  37 #define CONFIG_BOARD_NAME       "n516"
  38 #define CONFIG_BOARD_HWREV      "1.0"
  39 #define CONFIG_FIRMWARE_EPOCH   "0"
  40 #define CONFIG_UPDATE_TMPBUF    0x80600000
  41 #define CONFIG_UPDATE_CHUNKSIZE 0x800000
  42 #define CONFIG_UPDATE_FILENAME  "update.oifw"
  43 #define CONFIG_UPDATE_FILEEXT   ".oifw"
  44 #define CONFIG_UBI_PARTITION    "UBI"
  45
  46 #define CONFIG_SKIP_LOWLEVEL_INIT       1
  47 #undef  CONFIG_SKIP_RELOCATE_UBOOT
  48
  49 #if 0
  50 #define CONFIG_LCD                 /* LCD support */
  51 #define CONFIG_JZLCD_METRONOME_800x600
  52 #define LCD_BPP                 LCD_COLOR8
  53
  54 #define WFM_DATA_SIZE  ( 1 << 14 )
  55 #define CONFIG_METRONOME_WF_LEN (64 * (1 << 10))
  56 #define CONFIG_METRONOME_WF_NAND_OFFSET (0x100000)
  57 #define BMP_LOGO_HEIGHT 0
  58 #define CONFIG_UBI_WF_VOLUME "waveforms"
  59 #define CONFIG_UBI_BOOTSPLASH_VOLUME "bootsplash"
  60 #define CONFIG_METRONOME_BOOTSPLASH_LEN 480000
  61 #endif
  62
  63 #if 0
  64 #define CONFIG_JZSOC_I2C
  65 #define CONFIG_HARD_I2C
  66 #define CONFIG_SYS_I2C_SPEED    100000
  67 #define CONFIG_SYS_I2C_SLAVE    0
  68 #define CONFIG_LPC_I2C_ADDR     0x54
  69 #endif
  70
  71 #define JZ4740_NORBOOT_CFG      JZ4740_NORBOOT_16BIT    /* NOR Boot config code */
  72 #define JZ4740_NANDBOOT_CFG     JZ4740_NANDBOOT_B8R3    /* NAND Boot config code */
  73
  74 #define CONFIG_SYS_CPU_SPEED            336000000       /* CPU clock: 336 MHz */
  75 #define CONFIG_SYS_EXTAL                12000000        /* EXTAL freq: 12 MHz */
  76 #define CONFIG_SYS_HZ                   (CONFIG_SYS_EXTAL/256) /* incrementer freq */
  77
  78 #define CONFIG_SYS_UART_BASE            UART0_BASE      /* Base of the UART channel */
  79
  80 #define CONFIG_BAUDRATE         57600
  81 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  82
  83
  84 #define CONFIG_MMC              1
  85 #define CONFIG_GENERIC_MMC      1
  86 #define CONFIG_JZ_MMC           1
  87 #define CONFIG_FAT              1
  88
  89 #define CONFIG_SYS_HUSH_PARSER
  90 #define CONFIG_SYS_PROMPT_HUSH_PS2 ">"
  91 #define CONFIG_CMDLINE_EDITING
  92
  93 /* allow to overwrite serial and ethaddr */
  94 #define CONFIG_ENV_OVERWRITE
  95
  96 #include <config_cmd_default.h>
  97
  98 #undef CONFIG_CMD_BDI           /* bdinfo                       */
  99 #undef CONFIG_CMD_FPGA
 100 #undef CONFIG_CMD_ECHO          /* echo arguments               */
 101 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect       */
 102 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 103 #undef CONFIG_CMD_IMI           /* iminfo                       */
 104 #undef CONFIG_CMD_ITEST /* Integer (and string) test    */
 105 #undef CONFIG_CMD_LOADB /* loadb                        */
 106 #undef CONFIG_CMD_LOADS /* loads                        */
 107 #undef CONFIG_CMD_NFS           /* NFS support                  */
 108 #undef CONFIG_CMD_SETGETDCR     /* DCR support on 4xx           */
 109 #undef CONFIG_CMD_SOURCE        /* "source" command support     */
 110 #undef CONFIG_CMD_XIMG          /* Load part of Multi Image     */
 111 #undef CONFIG_CMD_NET
 112
 113 //#define CONFIG_CMD_ASKENV
 114 //#define CONFIG_CMD_DHCP
 115 //#define CONFIG_CMD_PING
 116 #define CONFIG_CMD_NAND
 117 #define CONFIG_CMD_MMC
 118 #define CONFIG_CMD_FAT
 119 /*#define CONFIG_CMD_UBI*/
 120 /*#define CONFIG_CMD_MTDPARTS*/
 121 //#define CONFIG_CMD_JFFS2
 122 //#define CONFIG_JFFS2_NAND
 123 //#define CONFIG_JFFS2_CMDLINE
 124 #define CONFIG_CMD_UPDATE
 125
 126 #define CONFIG_DOS_PARTITION
 127
 128 /*#define CONFIG_MTD_PARTITIONS*/
 129 #define CONFIG_RBTREE
 130
 131 #define CONFIG_BOOTP_MASK       ( CONFIG_BOOTP_DEFAUL )
 132
 133 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 134 #if 0
 135 #define CONFIG_ZERO_BOOTDELAY_CHECK
 136 #define CONFIG_BOOTDELAY        0
 137 #define CONFIG_BOOTFILE         uImage  /* file to load */
 138 #define CONFIG_BOOTARGS         "mem=64M console=ttyS0,57600n8 ip=off rootfstype=ubifs root=ubi:rootfs ubi.mtd=UBI rw panic=5 " MTDPARTS_DEFAULT
 139 #define CONFIG_BOOTCOMMAND      "check_and_update; setenv bootargs $bootargs $batt_level_param; ubi read 0x80600000 bootsplash && show_image 0x80600000; ubi read 0x80600000 kernel; bootm 0x80600000; ubi read 0x80600000 errorsplash && show_image 0x80600000; while test 0 = 0; do check_and_update; done"
 140 #define CONFIG_SYS_AUTOLOAD     "n"             /* No autoload */
 141 #define CONFIG_IPADDR           192.168.111.1
 142 #define CONFIG_SERVERIP         192.168.111.2
 143 #define MTDIDS_DEFAULT          "nand0=jz4740-nand"
 144 #define MTDPARTS_DEFAULT        "mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)"
 145 #define CONFIG_EXTRA_ENV_SETTINGS "mtdids=nand0=jz4740-nand\0mtdparts=mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)\0" \
 146                                 "stdout=serial\0stderr=lcd\0"
 147 #endif
 148
 149 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAUL)
 150 #define CONFIG_BOOTDELAY        0
 151 #define CONFIG_BOOTFILE         "uImage"        /* file to load */
 152 #define CONFIG_BOOTARGS         "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
 153 #define CONFIG_BOOTCOMMAND      "nand read 0x80600000 0x400000 0x200000;bootm"
 154
 155
 156
 157 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 158
 159 /*
 160  * Serial download configuration
 161  *
 162  */
 163 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 164 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 165
 166 /*
 167  * Miscellaneous configurable options
 168  */
 169 #define CONFIG_SYS_LONGHELP                             /* undef to save memory      */
 170 #define CONFIG_SYS_PROMPT               "n516 # "       /* Monitor Command Prompt    */
 171 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size   */
 172 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)  /* Print Buffer Size */
 173 #define CONFIG_SYS_MAXARGS              16              /* max number of command args*/
 174
 175 #define CONFIG_SYS_MALLOC_LEN           1024*1024*2
 176 #define CONFIG_SYS_BOOTPARAMS_LEN       128*1024
 177
 178 #define CONFIG_SYS_SDRAM_BASE           0x80000000     /* Cached addr */
 179
 180 #define CONFIG_SYS_INIT_SP_OFFSET       0x400000
 181
 182 #define CONFIG_SYS_LOAD_ADDR            0x80600000     /* default load address  */
 183
 184 #define CONFIG_SYS_MEMTEST_START        0x80100000
 185 #define CONFIG_SYS_MEMTEST_END          0x80800000
 186
 187 /*-----------------------------------------------------------------------
 188  * Environment
 189  *----------------------------------------------------------------------*/
 190 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 191 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 192 #else
 193 #define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
 194 #endif
 195
 196 /*-----------------------------------------------------------------------
 197  * NAND FLASH configuration
 198  */
 199 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 200 #define NAND_MAX_CHIPS          1
 201 #define CONFIG_SYS_NAND_BASE           0xB8000000
 202 #define CONFIG_SYS_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 203
 204 /*
 205  * IPL (Initial Program Loader, integrated inside CPU)
 206  * Will load first 8k from NAND (SPL) into cache and execute it from there.
 207  *
 208  * SPL (Secondary Program Loader)
 209  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 210  * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
 211  * controller and the NAND controller so that the special U-Boot image can be
 212  * loaded from NAND to SDRAM.
 213  *
 214  * NUB (NAND U-Boot)
 215  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 216  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 217  *
 218  */
 219 #define CONFIG_SYS_NAND_U_BOOT_DST      0x80100000      /* Load NUB to this addr        */
 220 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
 221
 222 /*
 223  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 224  */
 225 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)     /* Offset to RAM U-Boot image   */
 226 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 << 10)     /* Size of RAM U-Boot image     */
 227
 228 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
 229 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 << 10)     /* NAND chip block size         */
 230 #define CONFIG_SYS_NAND_BADBLOCK_PAGE   63              /* NAND bad block was marked at this page in a block, starting from 0 */
 231 #define CONFIG_SYS_NAND_ECC_POS         6
 232
 233 #ifdef CONFIG_ENV_IS_IN_NAND
 234 //#define CONFIG_ENV_SIZE                       CONFIG_SYS_NAND_BLOCK_SIZE
 235 #define CONFIG_ENV_SIZE                 (128 * 1024)
 236 //#define CONFIG_ENV_OFFSET             (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE) /* environment starts here  */
 237 #define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
 238 //#define CONFIG_ENV_OFFSET_REDUND      (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 239 #endif
 240
 241
 242 /*-----------------------------------------------------------------------
 243  * NOR FLASH and environment organization
 244  */
 245 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks */
 246 #define CONFIG_SYS_MAX_FLASH_SECT       (128)   /* max number of sectors on one chip */
 247
 248 #define PHYS_FLASH_1            0xa8000000 /* Flash Bank #1 */
 249
 250 /* The following #defines are needed to get flash environment right */
 251 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE   /* in pavo/config.mk TEXT_BASE=0x88000000*/
 252 #define CONFIG_SYS_SYS_MONITOR_BASE     TEXT_BASE   /* in pavo/config.mk TEXT_BASE=0x88000000*/
 253 #define CONFIG_SYS_MONITOR_LEN          (256*1024)  /* Reserve 256 kB for Monitor */
 254
 255 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 256
 257 /* timeout values are in ticks */
 258 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 259 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
 260
 261 #ifdef CONFIG_ENV_IS_IN_FLASH
 262 #define CONFIG_ENV_IS_NOWHERE   1
 263 #define CONFIG_ENV_ADDR         0xa8040000
 264 #define CONFIG_ENV_SIZE         0x20000
 265 #endif
 266
 267 /*-----------------------------------------------------------------------
 268  * SDRAM Info.
 269  */
 270 #define CONFIG_NR_DRAM_BANKS    1
 271
 272 // SDRAM paramters
 273 #define SDRAM_BW16              0       /* Data bus width: 0-32bit, 1-16bit */
 274 #define SDRAM_BANK4             1       /* Banks each chip: 0-2bank, 1-4bank */
 275 #define SDRAM_ROW               13      /* Row address: 11 to 13 */
 276 #define SDRAM_COL               9       /* Column address: 8 to 12 */
 277 #define SDRAM_CASL              2       /* CAS latency: 2 or 3 */
 278
 279 // SDRAM Timings, unit: ns
 280 #define SDRAM_TRAS              45      /* RAS# Active Time */
 281 #define SDRAM_RCD               20      /* RAS# to CAS# Delay */
 282 #define SDRAM_TPC               20      /* RAS# Precharge Time */
 283 #define SDRAM_TRWL              7       /* Write Latency Time */
 284 #define SDRAM_TREF              15625   /* Refresh period: 4096 refresh cycles/64ms */
 285
 286 /*-----------------------------------------------------------------------
 287  * Cache Configuration
 288  */
 289 #define CONFIG_SYS_DCACHE_SIZE          16384
 290 #define CONFIG_SYS_ICACHE_SIZE          16384
 291 #define CONFIG_SYS_CACHELINE_SIZE       32
 292
 293 /*-----------------------------------------------------------------------
 294  * GPIO definition
 295  */
 296 #define GPIO_SD_VCC_EN_N        113 /* GPD17 */
 297 #define GPIO_SD_CD_N           103 /* GPD7 */
 298 #define GPIO_SD_WP             111 /* GPD15 */
 299 #define GPIO_USB_DETE          115 /* GPD6 */
 300 //#define GPIO_DC_DETE_N               103 /* GPD7 */
 301 #define GPIO_CHARG_STAT_N      112 /* GPD15 */
 302 #define GPIO_DISP_OFF_N                97 /* GPD1 */
 303 #define GPIO_UDC_HOTPLUG       100 /* GPD4 */
 304 #define GPIO_LED_EN            124 /* GPD28 */
 305
 306 #define GPIO_RST_L          50   /* GPB18 LCD_SPL */
 307 #define GPIO_LCDRDY         49   /* GPB17 LCD_CLS */
 308 #define GPIO_STBY           86   /* GPC22 LCD_PS */
 309 #define GPIO_ERR            87   /* GPC23 LCD_REV */
 310
 311 #endif  /* __CONFIG_H */