package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_dma.h

   1 #ifndef BCM43xx_DMA_H_
   2 #define BCM43xx_DMA_H_
   3
   4 #include <linux/list.h>
   5 #include <linux/spinlock.h>
   6 #include <linux/workqueue.h>
   7 #include <linux/linkage.h>
   8 #include <asm/atomic.h>
   9
  10 #include "bcm43xx.h"
  11
  12
  13 /* DMA-Interrupt reasons. */
  14 #define BCM43xx_DMAIRQ_FATALMASK        ((1 << 10) | (1 << 11) | (1 << 12) \
  15                                          | (1 << 14) | (1 << 15))
  16 #define BCM43xx_DMAIRQ_NONFATALMASK     (1 << 13)
  17 #define BCM43xx_DMAIRQ_RX_DONE          (1 << 16)
  18
  19
  20 /*** 32-bit DMA Engine. ***/
  21
  22 /* 32-bit DMA controller registers. */
  23 #define BCM43xx_DMA32_TXCTL                             0x00
  24 #define         BCM43xx_DMA32_TXENABLE                  0x00000001
  25 #define         BCM43xx_DMA32_TXSUSPEND                 0x00000002
  26 #define         BCM43xx_DMA32_TXLOOPBACK                0x00000004
  27 #define         BCM43xx_DMA32_TXFLUSH                   0x00000010
  28 #define         BCM43xx_DMA32_TXADDREXT_MASK            0x00030000
  29 #define         BCM43xx_DMA32_TXADDREXT_SHIFT           16
  30 #define BCM43xx_DMA32_TXRING                            0x04
  31 #define BCM43xx_DMA32_TXINDEX                           0x08
  32 #define BCM43xx_DMA32_TXSTATUS                          0x0C
  33 #define         BCM43xx_DMA32_TXDPTR                    0x00000FFF
  34 #define         BCM43xx_DMA32_TXSTATE                   0x0000F000
  35 #define                 BCM43xx_DMA32_TXSTAT_DISABLED   0x00000000
  36 #define                 BCM43xx_DMA32_TXSTAT_ACTIVE     0x00001000
  37 #define                 BCM43xx_DMA32_TXSTAT_IDLEWAIT   0x00002000
  38 #define                 BCM43xx_DMA32_TXSTAT_STOPPED    0x00003000
  39 #define                 BCM43xx_DMA32_TXSTAT_SUSP       0x00004000
  40 #define         BCM43xx_DMA32_TXERROR                   0x000F0000
  41 #define                 BCM43xx_DMA32_TXERR_NOERR       0x00000000
  42 #define                 BCM43xx_DMA32_TXERR_PROT        0x00010000
  43 #define                 BCM43xx_DMA32_TXERR_UNDERRUN    0x00020000
  44 #define                 BCM43xx_DMA32_TXERR_BUFREAD     0x00030000
  45 #define                 BCM43xx_DMA32_TXERR_DESCREAD    0x00040000
  46 #define         BCM43xx_DMA32_TXACTIVE                  0xFFF00000
  47 #define BCM43xx_DMA32_RXCTL                             0x10
  48 #define         BCM43xx_DMA32_RXENABLE                  0x00000001
  49 #define         BCM43xx_DMA32_RXFROFF_MASK              0x000000FE
  50 #define         BCM43xx_DMA32_RXFROFF_SHIFT             1
  51 #define         BCM43xx_DMA32_RXDIRECTFIFO              0x00000100
  52 #define         BCM43xx_DMA32_RXADDREXT_MASK            0x00030000
  53 #define         BCM43xx_DMA32_RXADDREXT_SHIFT           16
  54 #define BCM43xx_DMA32_RXRING                            0x14
  55 #define BCM43xx_DMA32_RXINDEX                           0x18
  56 #define BCM43xx_DMA32_RXSTATUS                          0x1C
  57 #define         BCM43xx_DMA32_RXDPTR                    0x00000FFF
  58 #define         BCM43xx_DMA32_RXSTATE                   0x0000F000
  59 #define                 BCM43xx_DMA32_RXSTAT_DISABLED   0x00000000
  60 #define                 BCM43xx_DMA32_RXSTAT_ACTIVE     0x00001000
  61 #define                 BCM43xx_DMA32_RXSTAT_IDLEWAIT   0x00002000
  62 #define                 BCM43xx_DMA32_RXSTAT_STOPPED    0x00003000
  63 #define         BCM43xx_DMA32_RXERROR                   0x000F0000
  64 #define                 BCM43xx_DMA32_RXERR_NOERR       0x00000000
  65 #define                 BCM43xx_DMA32_RXERR_PROT        0x00010000
  66 #define                 BCM43xx_DMA32_RXERR_OVERFLOW    0x00020000
  67 #define                 BCM43xx_DMA32_RXERR_BUFWRITE    0x00030000
  68 #define                 BCM43xx_DMA32_RXERR_DESCREAD    0x00040000
  69 #define         BCM43xx_DMA32_RXACTIVE                  0xFFF00000
  70
  71 /* 32-bit DMA descriptor. */
  72 struct bcm43xx_dmadesc32 {
  73         __le32 control;
  74         __le32 address;
  75 } __attribute__((__packed__));
  76 #define BCM43xx_DMA32_DCTL_BYTECNT              0x00001FFF
  77 #define BCM43xx_DMA32_DCTL_ADDREXT_MASK         0x00030000
  78 #define BCM43xx_DMA32_DCTL_ADDREXT_SHIFT        16
  79 #define BCM43xx_DMA32_DCTL_DTABLEEND            0x10000000
  80 #define BCM43xx_DMA32_DCTL_IRQ                  0x20000000
  81 #define BCM43xx_DMA32_DCTL_FRAMEEND             0x40000000
  82 #define BCM43xx_DMA32_DCTL_FRAMESTART           0x80000000
  83
  84
  85
  86 /*** 64-bit DMA Engine. ***/
  87
  88 /* 64-bit DMA controller registers. */
  89 #define BCM43xx_DMA64_TXCTL                             0x00
  90 #define         BCM43xx_DMA64_TXENABLE                  0x00000001
  91 #define         BCM43xx_DMA64_TXSUSPEND                 0x00000002
  92 #define         BCM43xx_DMA64_TXLOOPBACK                0x00000004
  93 #define         BCM43xx_DMA64_TXFLUSH                   0x00000010
  94 #define         BCM43xx_DMA64_TXADDREXT_MASK            0x00030000
  95 #define         BCM43xx_DMA64_TXADDREXT_SHIFT           16
  96 #define BCM43xx_DMA64_TXINDEX                           0x04
  97 #define BCM43xx_DMA64_TXRINGLO                          0x08
  98 #define BCM43xx_DMA64_TXRINGHI                          0x0C
  99 #define BCM43xx_DMA64_TXSTATUS                          0x10
 100 #define         BCM43xx_DMA64_TXSTATDPTR                0x00001FFF
 101 #define         BCM43xx_DMA64_TXSTAT                    0xF0000000
 102 #define                 BCM43xx_DMA64_TXSTAT_DISABLED   0x00000000
 103 #define                 BCM43xx_DMA64_TXSTAT_ACTIVE     0x10000000
 104 #define                 BCM43xx_DMA64_TXSTAT_IDLEWAIT   0x20000000
 105 #define                 BCM43xx_DMA64_TXSTAT_STOPPED    0x30000000
 106 #define                 BCM43xx_DMA64_TXSTAT_SUSP       0x40000000
 107 #define BCM43xx_DMA64_TXERROR                           0x14
 108 #define         BCM43xx_DMA64_TXERRDPTR                 0x0001FFFF
 109 #define         BCM43xx_DMA64_TXERR                     0xF0000000
 110 #define                 BCM43xx_DMA64_TXERR_NOERR       0x00000000
 111 #define                 BCM43xx_DMA64_TXERR_PROT        0x10000000
 112 #define                 BCM43xx_DMA64_TXERR_UNDERRUN    0x20000000
 113 #define                 BCM43xx_DMA64_TXERR_TRANSFER    0x30000000
 114 #define                 BCM43xx_DMA64_TXERR_DESCREAD    0x40000000
 115 #define                 BCM43xx_DMA64_TXERR_CORE        0x50000000
 116 #define BCM43xx_DMA64_RXCTL                             0x20
 117 #define         BCM43xx_DMA64_RXENABLE                  0x00000001
 118 #define         BCM43xx_DMA64_RXFROFF_MASK              0x000000FE
 119 #define         BCM43xx_DMA64_RXFROFF_SHIFT             1
 120 #define         BCM43xx_DMA64_RXDIRECTFIFO              0x00000100
 121 #define         BCM43xx_DMA64_RXADDREXT_MASK            0x00030000
 122 #define         BCM43xx_DMA64_RXADDREXT_SHIFT           16
 123 #define BCM43xx_DMA64_RXINDEX                           0x24
 124 #define BCM43xx_DMA64_RXRINGLO                          0x28
 125 #define BCM43xx_DMA64_RXRINGHI                          0x2C
 126 #define BCM43xx_DMA64_RXSTATUS                          0x30
 127 #define         BCM43xx_DMA64_RXSTATDPTR                0x00001FFF
 128 #define         BCM43xx_DMA64_RXSTAT                    0xF0000000
 129 #define                 BCM43xx_DMA64_RXSTAT_DISABLED   0x00000000
 130 #define                 BCM43xx_DMA64_RXSTAT_ACTIVE     0x10000000
 131 #define                 BCM43xx_DMA64_RXSTAT_IDLEWAIT   0x20000000
 132 #define                 BCM43xx_DMA64_RXSTAT_STOPPED    0x30000000
 133 #define                 BCM43xx_DMA64_RXSTAT_SUSP       0x40000000
 134 #define BCM43xx_DMA64_RXERROR                           0x34
 135 #define         BCM43xx_DMA64_RXERRDPTR                 0x0001FFFF
 136 #define         BCM43xx_DMA64_RXERR                     0xF0000000
 137 #define                 BCM43xx_DMA64_RXERR_NOERR       0x00000000
 138 #define                 BCM43xx_DMA64_RXERR_PROT        0x10000000
 139 #define                 BCM43xx_DMA64_RXERR_UNDERRUN    0x20000000
 140 #define                 BCM43xx_DMA64_RXERR_TRANSFER    0x30000000
 141 #define                 BCM43xx_DMA64_RXERR_DESCREAD    0x40000000
 142 #define                 BCM43xx_DMA64_RXERR_CORE        0x50000000
 143
 144 /* 64-bit DMA descriptor. */
 145 struct bcm43xx_dmadesc64 {
 146         __le32 control0;
 147         __le32 control1;
 148         __le32 address_low;
 149         __le32 address_high;
 150 } __attribute__((__packed__));
 151 #define BCM43xx_DMA64_DCTL0_DTABLEEND           0x10000000
 152 #define BCM43xx_DMA64_DCTL0_IRQ                 0x20000000
 153 #define BCM43xx_DMA64_DCTL0_FRAMEEND            0x40000000
 154 #define BCM43xx_DMA64_DCTL0_FRAMESTART          0x80000000
 155 #define BCM43xx_DMA64_DCTL1_BYTECNT             0x00001FFF
 156 #define BCM43xx_DMA64_DCTL1_ADDREXT_MASK        0x00030000
 157 #define BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT       16
 158
 159
 160
 161 struct bcm43xx_dmadesc_generic {
 162         union {
 163                 struct bcm43xx_dmadesc32 dma32;
 164                 struct bcm43xx_dmadesc64 dma64;
 165         } __attribute__((__packed__));
 166 } __attribute__((__packed__));
 167
 168
 169 /* Misc DMA constants */
 170 #define BCM43xx_DMA_RINGMEMSIZE         PAGE_SIZE
 171 #define BCM43xx_DMA0_RX_FRAMEOFFSET     30
 172 #define BCM43xx_DMA3_RX_FRAMEOFFSET     0
 173
 174
 175 /* DMA engine tuning knobs */
 176 #define BCM43xx_TXRING_SLOTS            128
 177 #define BCM43xx_RXRING_SLOTS            64
 178 #define BCM43xx_DMA0_RX_BUFFERSIZE      (2304 + 100)
 179 #define BCM43xx_DMA3_RX_BUFFERSIZE      16
 180
 181
 182
 183 #ifdef CONFIG_BCM43XX_MAC80211_DMA
 184
 185
 186 struct sk_buff;
 187 struct bcm43xx_private;
 188 struct bcm43xx_txstatus;
 189
 190
 191 struct bcm43xx_dmadesc_meta {
 192         /* The kernel DMA-able buffer. */
 193         struct sk_buff *skb;
 194         /* DMA base bus-address of the descriptor buffer. */
 195         dma_addr_t dmaaddr;
 196         /* ieee80211 TX status. Only used once per 802.11 frag. */
 197         u8 is_last_fragment;
 198         struct ieee80211_tx_status txstat;
 199 };
 200
 201 struct bcm43xx_dmaring;
 202
 203 /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
 204 struct bcm43xx_dma_ops {
 205         struct bcm43xx_dmadesc_generic * (*idx2desc)(struct bcm43xx_dmaring *ring,
 206                                                      int slot,
 207                                                      struct bcm43xx_dmadesc_meta **meta);
 208         void (*fill_descriptor)(struct bcm43xx_dmaring *ring,
 209                                 struct bcm43xx_dmadesc_generic *desc,
 210                                 dma_addr_t dmaaddr, u16 bufsize,
 211                                 int start, int end, int irq);
 212         void (*poke_tx)(struct bcm43xx_dmaring *ring, int slot);
 213         void (*tx_suspend)(struct bcm43xx_dmaring *ring);
 214         void (*tx_resume)(struct bcm43xx_dmaring *ring);
 215         int (*get_current_rxslot)(struct bcm43xx_dmaring *ring);
 216         void (*set_current_rxslot)(struct bcm43xx_dmaring *ring, int slot);
 217 };
 218
 219 struct bcm43xx_dmaring {
 220         /* Lowlevel DMA ops. */
 221         const struct bcm43xx_dma_ops *ops;
 222         /* Kernel virtual base address of the ring memory. */
 223         void *descbase;
 224         /* Meta data about all descriptors. */
 225         struct bcm43xx_dmadesc_meta *meta;
 226         /* Cache of TX headers for each slot.
 227          * This is to avoid an allocation on each TX.
 228          * This is NULL for an RX ring.
 229          */
 230         u8 *txhdr_cache;
 231         /* (Unadjusted) DMA base bus-address of the ring memory. */
 232         dma_addr_t dmabase;
 233         /* Number of descriptor slots in the ring. */
 234         int nr_slots;
 235         /* Number of used descriptor slots. */
 236         int used_slots;
 237         /* Currently used slot in the ring. */
 238         int current_slot;
 239         /* Total number of packets sent. Statistics only. */
 240         unsigned int nr_tx_packets;
 241         /* Frameoffset in octets. */
 242         u32 frameoffset;
 243         /* Descriptor buffer size. */
 244         u16 rx_buffersize;
 245         /* The MMIO base register of the DMA controller. */
 246         u16 mmio_base;
 247         /* DMA controller index number (0-5). */
 248         int index;
 249         /* Boolean. Is this a TX ring? */
 250         u8 tx;
 251         /* Boolean. 64bit DMA if true, 32bit DMA otherwise. */
 252         u8 dma64;
 253         /* Boolean. Is this ring stopped at ieee80211 level? */
 254         u8 stopped;
 255         /* Lock, only used for TX. */
 256         spinlock_t lock;
 257         struct bcm43xx_wldev *dev;
 258 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
 259         /* Maximum number of used slots. */
 260         int max_used_slots;
 261         /* Last time we injected a ring overflow. */
 262         unsigned long last_injected_overflow;
 263 #endif /* CONFIG_BCM43XX_MAC80211_DEBUG*/
 264 };
 265
 266
 267 static inline
 268 u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,
 269                      u16 offset)
 270 {
 271         return bcm43xx_read32(ring->dev, ring->mmio_base + offset);
 272 }
 273
 274 static inline
 275 void bcm43xx_dma_write(struct bcm43xx_dmaring *ring,
 276                        u16 offset, u32 value)
 277 {
 278         bcm43xx_write32(ring->dev, ring->mmio_base + offset, value);
 279 }
 280
 281
 282 int bcm43xx_dma_init(struct bcm43xx_wldev *dev);
 283 void bcm43xx_dma_free(struct bcm43xx_wldev *dev);
 284
 285 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
 286                                    u16 dmacontroller_mmio_base,
 287                                    int dma64);
 288 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
 289                                    u16 dmacontroller_mmio_base,
 290                                    int dma64);
 291
 292 u16 bcm43xx_dmacontroller_base(int dma64bit, int dmacontroller_idx);
 293
 294 void bcm43xx_dma_tx_suspend(struct bcm43xx_wldev *dev);
 295 void bcm43xx_dma_tx_resume(struct bcm43xx_wldev *dev);
 296
 297 void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
 298                               struct ieee80211_tx_queue_stats *stats);
 299
 300 int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
 301                    struct sk_buff *skb,
 302                    struct ieee80211_tx_control *ctl);
 303 void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
 304                                  const struct bcm43xx_txstatus *status);
 305
 306 void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);
 307
 308 #else /* CONFIG_BCM43XX_MAC80211_DMA */
 309
 310
 311 static inline
 312 int bcm43xx_dma_init(struct bcm43xx_wldev *dev)
 313 {
 314         return 0;
 315 }
 316 static inline
 317 void bcm43xx_dma_free(struct bcm43xx_wldev *dev)
 318 {
 319 }
 320 static inline
 321 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_wldev *dev,
 322                                    u16 dmacontroller_mmio_base,
 323                                    int dma64)
 324 {
 325         return 0;
 326 }
 327 static inline
 328 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_wldev *dev,
 329                                    u16 dmacontroller_mmio_base,
 330                                    int dma64)
 331 {
 332         return 0;
 333 }
 334 static inline
 335 void bcm43xx_dma_get_tx_stats(struct bcm43xx_wldev *dev,
 336                               struct ieee80211_tx_queue_stats *stats)
 337 {
 338 }
 339 static inline
 340 int bcm43xx_dma_tx(struct bcm43xx_wldev *dev,
 341                    struct sk_buff *skb,
 342                    struct ieee80211_tx_control *ctl)
 343 {
 344         return 0;
 345 }
 346 static inline
 347 void bcm43xx_dma_handle_txstatus(struct bcm43xx_wldev *dev,
 348                                  const struct bcm43xx_txstatus *status)
 349 {
 350 }
 351 static inline
 352 void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
 353 {
 354 }
 355 static inline
 356 void bcm43xx_dma_tx_suspend(struct bcm43xx_wldev *dev)
 357 {
 358 }
 359 static inline
 360 void bcm43xx_dma_tx_resume(struct bcm43xx_wldev *dev)
 361 {
 362 }
 363
 364 #endif /* CONFIG_BCM43XX_MAC80211_DMA */
 365 #endif /* BCM43xx_DMA_H_ */