projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
[ar71xx] preliminary support for the Ubiquiti RouterStation Pro
[openwrt.git] / target / linux / s3c24xx / patches-2.6.24 / 1169-uplevel-samsung-camera-unit.patch.patch
1 From 1ccc3052a80284d3d7fbdfc0badadf6ae4236f79 Mon Sep 17 00:00:00 2001
2 From: Andy Green <andy@opennoko.com>
3 Date: Wed, 2 Jul 2008 22:37:38 +0100
4 Subject: [PATCH] uplevel-samsung-camera-unit.patch
5
6 Update this old code to clk API, I2C changes, official GPIO API
7 various struct changes, explicit readl() writel(), DMA API changes.
8 Still not ready for actual use (eg, I2C) but a LOT closer.
9
10 Compiles on 2.6.24 without errors or warnings now.
11
12 Use CONFIG_S3C2440_CAMERA=y in .config
13
14 Signed-off-by: Andy Green <andy@openmoko.com>
15 ---
16 arch/arm/mach-s3c2440/Kconfig | 5 +-
17 arch/arm/mach-s3c2440/Makefile | 26 +-
18 arch/arm/mach-s3c2440/camera/Makefile | 1 -
19 arch/arm/mach-s3c2440/camera/cam_reg.h | 92 +++--
20 arch/arm/mach-s3c2440/camera/camif.c | 633 +++++++++++++++------------
21 arch/arm/mach-s3c2440/camera/camif_fsm.c | 5 +
22 arch/arm/mach-s3c2440/camera/imgsensor.c | 43 +-
23 arch/arm/mach-s3c2440/camera/qt-driver.c | 5 +-
24 arch/arm/mach-s3c2440/camera/video-driver.c | 87 +++--
25 arch/arm/mach-s3c2440/camera/videodev.c | 24 +-
26 arch/arm/mach-s3c2440/camera/videodev.h | 16 +-
27 11 files changed, 533 insertions(+), 404 deletions(-)
28
29 diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
30 index c350511..4a211d8 100644
31 --- a/arch/arm/mach-s3c2440/Kconfig
32 +++ b/arch/arm/mach-s3c2440/Kconfig
33 @@ -30,9 +30,6 @@ config S3C2440_C_FIQ
34 Support for S3C2440 FIQ support in C -- see
35 ./arch/arm/macs3c2440/fiq_c_isr.c
36
37 -source "arch/arm/mach-s3c2440/camera/Kconfig"
38 -
39 -
40 menu "S3C2440 Machines"
41
42 config MACH_ANUBIS
43 @@ -102,3 +99,5 @@ config NEO1973_GTA02_2440
44 of the FIC/Openmoko Neo1973 GTA02 GSM Phone.
45
46 endmenu
47 +
48 +#source "arch/arm/mach-s3c2440/camera/Kconfig"
49 diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
50 index 7112231..e3ca9e3 100644
51 --- a/arch/arm/mach-s3c2440/Makefile
52 +++ b/arch/arm/mach-s3c2440/Makefile
53 @@ -1,2 +1,26 @@
54 -obj-y += camera/
55 +# arch/arm/mach-s3c2440/Makefile
56 +#
57 +# Copyright 2007 Simtec Electronics
58 +#
59 +# Licensed under GPLv2
60
61 +obj-y :=
62 +obj-m :=
63 +obj-n :=
64 +obj- :=
65 +
66 +obj-$(CONFIG_CPU_S3C2440) += s3c2440.o dsc.o
67 +obj-$(CONFIG_CPU_S3C2440) += irq.o
68 +obj-$(CONFIG_CPU_S3C2440) += clock.o
69 +obj-$(CONFIG_S3C2440_DMA) += dma.o
70 +obj-$(CONFIG_S3C2440_C_FIQ) += fiq_c_isr.o
71 +
72 +# Machine support
73 +
74 +obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
75 +obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o
76 +obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
77 +obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
78 +obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
79 +obj-$(CONFIG_MACH_HXD8) += mach-hxd8.o
80 +obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
81 diff --git a/arch/arm/mach-s3c2440/camera/Makefile b/arch/arm/mach-s3c2440/camera/Makefile
82 index a46d3be..9cd6d79 100644
83 --- a/arch/arm/mach-s3c2440/camera/Makefile
84 +++ b/arch/arm/mach-s3c2440/camera/Makefile
85 @@ -1,7 +1,6 @@
86 obj-$(CONFIG_S3C2440_CAMERA) += \
87 videodev.o \
88 imgsensor.o \
89 - videodrv.o \
90 video-driver.o \
91 camif.o \
92 camif_fsm.o \
93 diff --git a/arch/arm/mach-s3c2440/camera/cam_reg.h b/arch/arm/mach-s3c2440/camera/cam_reg.h
94 index 7247a4e..93d59b8 100644
95 --- a/arch/arm/mach-s3c2440/camera/cam_reg.h
96 +++ b/arch/arm/mach-s3c2440/camera/cam_reg.h
97 @@ -7,6 +7,7 @@
98 #ifndef __FIMC20_CAMERA_H__
99 #define __FIMC20_CAMERA_H__
100
101 +extern u32 * camregs;
102
103 #ifdef CONFIG_ARCH_S3C24A0
104 #define CAM_BASE_ADD 0x48000000
105 @@ -14,10 +15,23 @@
106 #define CAM_BASE_ADD 0x4F000000
107 #endif
108
109 +#if ! defined(FExtr)
110 +#define UData(Data) ((unsigned long) (Data))
111 +#define FExtr(Data, Field) \
112 + ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
113 +#define FInsrt(Value, Field) \
114 + (UData (Value) << FShft (Field))
115 +#define FSize(Field) ((Field) >> 16)
116 +#define FShft(Field) ((Field) & 0x0000FFFF)
117 +#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
118 +#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
119 +#define F1stBit(Field) (UData (1) << FShft (Field))
120 +#define Fld(Size, Shft) (((Size) << 16) + (Shft))
121 +#endif
122
123 /*
124 * CAMERA IP
125 - * P-port is used as RGB Capturing device which including scale and crop
126 + * P-port is used as RGB Capturing device which including scale and crop
127 * those who want to see(preview ) the image on display needs RGB image.
128 *
129 * C-port is used as YCbCr(4:2:0, 4:2:2) Capturing device which including the scale and crop
130 @@ -25,45 +39,45 @@
131 YCBCB format not RGB
132 */
133
134 -#define CISRCFMT __REG(CAM_BASE_ADD+0x00) // RW Input Source Format
135 -#define CIWDOFST __REG(CAM_BASE_ADD+0x04) // Window offset register
136 -#define CIGCTRL __REG(CAM_BASE_ADD+0x08) // Global control register
137 -#define CICOYSA0 __REG(CAM_BASE_ADD+0x18) // Y 1 st frame start address
138 -#define CICOYSA1 __REG(CAM_BASE_ADD+0x1C) // Y 2 nd frame start address
139 -#define CICOYSA2 __REG(CAM_BASE_ADD+0x20) // Y 3 rd frame start address
140 -#define CICOYSA3 __REG(CAM_BASE_ADD+0x24) // Y 4 th frame start address
141 -#define CICOCBSA0 __REG(CAM_BASE_ADD+0x28) // Cb 1 st frame start address
142 -#define CICOCBSA1 __REG(CAM_BASE_ADD+0x2C) // Cb 2 nd frame start address
143 -#define CICOCBSA2 __REG(CAM_BASE_ADD+0x30) // Cb 3 rd frame start address
144 -#define CICOCBSA3 __REG(CAM_BASE_ADD+0x34) // Cb 4 th frame start address
145 -#define CICOCRSA0 __REG(CAM_BASE_ADD+0x38) // Cr 1 st frame start address
146 -#define CICOCRSA1 __REG(CAM_BASE_ADD+0x3C) // Cr 2 nd frame start address
147 -#define CICOCRSA2 __REG(CAM_BASE_ADD+0x40) // Cr 3 rd frame start address
148 -#define CICOCRSA3 __REG(CAM_BASE_ADD+0x44) // Cr 4 th frame start address
149 -#define CICOTRGFMT __REG(CAM_BASE_ADD+0x48) // Target image format of codec
150 -#define CICOCTRL __REG(CAM_BASE_ADD+0x4C) // Codec DMA control related
151 -#define CICOSCPRERATIO __REG(CAM_BASE_ADD+0x50) // Codec pre-scaler ratio control
152 -#define CICOSCPREDST __REG(CAM_BASE_ADD+0x54) // Codec pre-scaler destination
153 -#define CICOSCCTRL __REG(CAM_BASE_ADD+0x58) // Codec main-scaler control
154 -#define CICOTAREA __REG(CAM_BASE_ADD+0x5C) // Codec pre-scaler destination
155 -#define CICOSTATUS __REG(CAM_BASE_ADD+0x64) // Codec path status
156 -#define CIPRCLRSA0 __REG(CAM_BASE_ADD+0x6C) // RGB 1 st frame start address
157 -#define CIPRCLRSA1 __REG(CAM_BASE_ADD+0x70) // RGB 2 nd frame start address
158 -#define CIPRCLRSA2 __REG(CAM_BASE_ADD+0x74) // RGB 3 rd frame start address
159 -#define CIPRCLRSA3 __REG(CAM_BASE_ADD+0x78) // RGB 4 th frame start address
160 -#define CIPRTRGFMT __REG(CAM_BASE_ADD+0x7C) // Target image format of preview
161 -#define CIPRCTRL __REG(CAM_BASE_ADD+0x80) // Preview DMA control related
162 -#define CIPRSCPRERATIO __REG(CAM_BASE_ADD+0x84) // Preview pre-scaler ratio control
163 -#define CIPRSCPREDST __REG(CAM_BASE_ADD+0x88) // Preview pre-scaler destination
164 -#define CIPRSCCTRL __REG(CAM_BASE_ADD+0x8C) // Preview main-scaler control
165 -#define CIPRTAREA __REG(CAM_BASE_ADD+0x90) // Preview pre-scaler destination
166 -#define CIPRSTATUS __REG(CAM_BASE_ADD+0x98) // Preview path status
167 -#define CIIMGCPT __REG(CAM_BASE_ADD+0xA0) // Image capture enable command
168 -
169 -#define CICOYSA(__x) __REG(CAM_BASE_ADD+0x18 + (__x)*4 )
170 -#define CICOCBSA(__x) __REG(CAM_BASE_ADD+0x28 + (__x)*4 )
171 -#define CICOCRSA(__x) __REG(CAM_BASE_ADD+0x38 + (__x)*4 )
172 -#define CIPRCLRSA(__x) __REG(CAM_BASE_ADD+0x6C + (__x)*4 )
173 +#define S3C2440_CAM_REG_CISRCFMT (0x00) // RW Input Source Format
174 +#define S3C2440_CAM_REG_CIWDOFST (0x04) // Window offset register
175 +#define S3C2440_CAM_REG_CIGCTRL (0x08) // Global control register
176 +#define S3C2440_CAM_REG_CICOYSA0 (0x18) // Y 1 st frame start ads
177 +#define S3C2440_CAM_REG_CICOYSA1 (0x1C) // Y 2 nd frame start ads
178 +#define S3C2440_CAM_REG_CICOYSA2 (0x20) // Y 3 rd frame start ads
179 +#define S3C2440_CAM_REG_CICOYSA3 (0x24) // Y 4 th frame start ads
180 +#define S3C2440_CAM_REG_CICOCBSA0 (0x28) // Cb 1 st frame start ads
181 +#define S3C2440_CAM_REG_CICOCBSA1 (0x2C) // Cb 2 nd frame start ads
182 +#define S3C2440_CAM_REG_CICOCBSA2 (0x30) // Cb 3 rd frame start ads
183 +#define S3C2440_CAM_REG_CICOCBSA3 (0x34) // Cb 4 th frame start ads
184 +#define S3C2440_CAM_REG_CICOCRSA0 (0x38) // Cr 1 st frame start ads
185 +#define S3C2440_CAM_REG_CICOCRSA1 (0x3C) // Cr 2 nd frame start ads
186 +#define S3C2440_CAM_REG_CICOCRSA2 (0x40) // Cr 3 rd frame start ads
187 +#define S3C2440_CAM_REG_CICOCRSA3 (0x44) // Cr 4 th frame start ads
188 +#define S3C2440_CAM_REG_CICOTRGFMT (0x48) // Target img format of codec
189 +#define S3C2440_CAM_REG_CICOCTRL (0x4C) // Codec DMA control related
190 +#define S3C2440_CAM_REG_CICOSCPRERATIO (0x50) // Codec pre-scaler ratio
191 +#define S3C2440_CAM_REG_CICOSCPREDST (0x54) // Codec pre-scaler dest
192 +#define S3C2440_CAM_REG_CICOSCCTRL (0x58) // Codec main-scaler control
193 +#define S3C2440_CAM_REG_CICOTAREA (0x5C) // Codec pre-scaler dest
194 +#define S3C2440_CAM_REG_CICOSTATUS (0x64) // Codec path status
195 +#define S3C2440_CAM_REG_CIPRCLRSA0 (0x6C) // RGB 1 st frame start ads
196 +#define S3C2440_CAM_REG_CIPRCLRSA1 (0x70) // RGB 2 nd frame start ads
197 +#define S3C2440_CAM_REG_CIPRCLRSA2 (0x74) // RGB 3 rd frame start ads
198 +#define S3C2440_CAM_REG_CIPRCLRSA3 (0x78) // RGB 4 th frame start ads
199 +#define S3C2440_CAM_REG_CIPRTRGFMT (0x7C) // Target img fmt of preview
200 +#define S3C2440_CAM_REG_CIPRCTRL (0x80) // Preview DMA ctl related
201 +#define S3C2440_CAM_REG_CIPRSCPRERATIO (0x84) // Preview pre-scaler ratio
202 +#define S3C2440_CAM_REG_CIPRSCPREDST (0x88) // Preview pre-scaler dest
203 +#define S3C2440_CAM_REG_CIPRSCCTRL (0x8C) // Preview main-scaler ctl
204 +#define S3C2440_CAM_REG_CIPRTAREA (0x90) // Preview pre-scaler dest
205 +#define S3C2440_CAM_REG_CIPRSTATUS (0x98) // Preview path status
206 +#define S3C2440_CAM_REG_CIIMGCPT (0xA0) // Image capture enable cmd
207 +
208 +#define S3C2440_CAM_REG_CICOYSA(__x) (0x18 + (__x)*4 )
209 +#define S3C2440_CAM_REG_CICOCBSA(__x) (0x28 + (__x)*4 )
210 +#define S3C2440_CAM_REG_CICOCRSA(__x) (0x38 + (__x)*4 )
211 +#define S3C2440_CAM_REG_CIPRCLRSA(__x) (0x6C + (__x)*4 )
212
213 /* CISRCFMT BitField */
214 #define SRCFMT_ITU601 BIT31
215 diff --git a/arch/arm/mach-s3c2440/camera/camif.c b/arch/arm/mach-s3c2440/camera/camif.c
216 index 36d4ccc..2e97e21 100644
217 --- a/arch/arm/mach-s3c2440/camera/camif.c
218 +++ b/arch/arm/mach-s3c2440/camera/camif.c
219 @@ -7,14 +7,11 @@
220 * for more details.
221 */
222
223 -#include <linux/config.h>
224 #include <linux/module.h>
225 #include <linux/kernel.h>
226 #include <linux/init.h>
227 #include <linux/sched.h>
228 #include <linux/irq.h>
229 -#include <linux/tqueue.h>
230 -#include <linux/locks.h>
231 #include <linux/completion.h>
232 #include <linux/delay.h>
233 #include <linux/slab.h>
234 @@ -26,28 +23,29 @@
235 #include <asm/semaphore.h>
236 #include <asm/hardware.h>
237 #include <asm/uaccess.h>
238 +#include <linux/device.h>
239 +#include <linux/dma-mapping.h>
240 +#include <linux/clk.h>
241
242 #ifdef CONFIG_ARCH_S3C24A0A
243 #include <asm/arch/S3C24A0.h>
244 #include <asm/arch/clocks.h>
245 #else
246 -#include <asm/arch/S3C2440.h>
247 -#include <asm/arch/clocks.h>
248 +#include <asm/arch/regs-gpio.h>
249 +#include <asm/arch/regs-gpioj.h>
250 +#include <asm/arch/regs-irq.h>
251 #endif
252
253 #include "cam_reg.h"
254 //#define SW_DEBUG
255 +#define CONFIG_VIDEO_V4L1_COMPAT
256 +#include <linux/videodev.h>
257 #include "camif.h"
258 -#include "videodev.h"
259 #include "miscdevice.h"
260
261 -
262 static int camif_dma_burst(camif_cfg_t *);
263 static int camif_scaler(camif_cfg_t *);
264
265 -static const char *camif_version =
266 - "$Id: camif.c,v 1.10 2004/06/04 04:24:14 swlee Exp $";
267 -
268 /* For SXGA Image */
269 #define RESERVE_MEM 15*1024*1024
270 #define YUV_MEM 10*1024*1024
271 @@ -66,11 +64,13 @@ static int camif_malloc(camif_cfg_t *cfg)
272 t_size = t_size *cfg->pp_num;
273
274 #ifndef SAMSUNG_SXGA_CAM
275 - cfg->pp_virt_buf = consistent_alloc(GFP_KERNEL, t_size, &cfg->pp_phys_buf);
276 + cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
277 + t_size, &cfg->pp_phys_buf,
278 + GFP_KERNEL);
279 #else
280 printk(KERN_INFO "Reserving High RAM Addresses \n");
281 cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM);
282 - cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf,YUV_MEM);
283 + cfg->pp_virt_buf = ioremap_nocache(cfg->pp_phys_buf, YUV_MEM);
284 #endif
285
286 if ( !cfg->pp_virt_buf ) {
287 @@ -90,7 +90,9 @@ static int camif_malloc(camif_cfg_t *cfg)
288 }
289 t_size = t_size * cfg->pp_num;
290 #ifndef SAMSUNG_SXGA_CAM
291 - cfg->pp_virt_buf = consistent_alloc(GFP_KERNEL, t_size, &cfg->pp_phys_buf);
292 + cfg->pp_virt_buf = dma_alloc_coherent(cfg->v->dev,
293 + t_size, &cfg->pp_phys_buf,
294 + GFP_KERNEL);
295 #else
296 printk(KERN_INFO "Reserving High RAM Addresses \n");
297 cfg->pp_phys_buf = PHYS_OFFSET + (MEM_SIZE - RESERVE_MEM ) + YUV_MEM;
298 @@ -112,7 +114,8 @@ static int camif_demalloc(camif_cfg_t *cfg)
299 {
300 #ifndef SAMSUNG_SXGA_CAM
301 if ( cfg->pp_virt_buf ) {
302 - consistent_free(cfg->pp_virt_buf,cfg->pp_totalsize,cfg->pp_phys_buf);
303 + dma_free_coherent(cfg->v->dev, cfg->pp_totalsize,
304 + cfg->pp_virt_buf, cfg->pp_phys_buf);
305 cfg->pp_virt_buf = 0;
306 }
307 #else
308 @@ -131,13 +134,14 @@ int camif_g_frame_num(camif_cfg_t *cfg)
309 int index = 0;
310
311 if (cfg->dma_type & CAMIF_CODEC ) {
312 - index = FRAME_CNT(CICOSTATUS);
313 + index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
314 DPRINTK("CAMIF_CODEC frame %d \n", index);
315 }
316 else {
317 assert(cfg->dma_type & CAMIF_PREVIEW );
318 - index = FRAME_CNT(CIPRSTATUS);
319 - DPRINTK("CAMIF_PREVIEW frame %d 0x%08X \n", index, CIPRSTATUS);
320 + index = FRAME_CNT(readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
321 + DPRINTK("CAMIF_PREVIEW frame %d 0x%08X \n", index,
322 + readl(camregs + S3C2440_CAM_REG_CIPRSTATUS));
323 }
324 cfg->now_frame_num = (index + 2) % 4; /* When 4 PingPong */
325 return index; /* meaningless */
326 @@ -148,60 +152,59 @@ static int camif_pp_codec(camif_cfg_t *cfg)
327 u32 i, c_size; /* Cb,Cr size */
328 u32 one_p_size;
329 u32 daon = cfg->target_x * cfg->target_y;
330 - if (cfg->fmt & CAMIF_OUT_YCBCR420) {
331 - c_size = daon /4;
332 - }
333 + if (cfg->fmt & CAMIF_OUT_YCBCR420)
334 + c_size = daon / 4;
335 else {
336 assert(cfg->fmt & CAMIF_OUT_YCBCR422);
337 - c_size = daon /2;
338 + c_size = daon / 2;
339 }
340 switch ( cfg->pp_num ) {
341 - case 1 :
342 - for ( i =0 ; i < 4; i=i+1) {
343 - cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
344 - cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
345 - cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon;
346 - cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon;
347 - cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size;
348 - cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size;
349 - CICOYSA(i) = cfg->img_buf[i].phys_y;
350 - CICOCBSA(i) = cfg->img_buf[i].phys_cb;
351 - CICOCRSA(i) = cfg->img_buf[i].phys_cr;
352 - }
353 - break;
354 - case 2:
355 + case 1 :
356 + for (i =0 ; i < 4; i++) {
357 + cfg->img_buf[i].virt_y = cfg->pp_virt_buf;
358 + cfg->img_buf[i].phys_y = cfg->pp_phys_buf;
359 + cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon;
360 + cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon;
361 + cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size;
362 + cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size;
363 + writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
364 + writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
365 + writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
366 + }
367 + break;
368 + case 2:
369 #define TRY (( i%2 ) ? 1 :0)
370 - one_p_size = daon + 2*c_size;
371 - for (i = 0; i < 4 ; i++) {
372 - cfg->img_buf[i].virt_y = cfg->pp_virt_buf + TRY * one_p_size;
373 - cfg->img_buf[i].phys_y = cfg->pp_phys_buf + TRY * one_p_size;
374 - cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + TRY * one_p_size;
375 - cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + TRY * one_p_size;
376 - cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + TRY * one_p_size;
377 - cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + TRY * one_p_size;
378 - CICOYSA(i) = cfg->img_buf[i].phys_y;
379 - CICOCBSA(i) = cfg->img_buf[i].phys_cb;
380 - CICOCRSA(i) = cfg->img_buf[i].phys_cr;
381 - }
382 - break;
383 - case 4:
384 - one_p_size = daon + 2*c_size;
385 - for (i = 0; i < 4 ; i++) {
386 - cfg->img_buf[i].virt_y = cfg->pp_virt_buf + i * one_p_size;
387 - cfg->img_buf[i].phys_y = cfg->pp_phys_buf + i * one_p_size;
388 - cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + i * one_p_size;
389 - cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + i * one_p_size;
390 - cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + i * one_p_size;
391 - cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + i * one_p_size;
392 - CICOYSA(i) = cfg->img_buf[i].phys_y;
393 - CICOCBSA(i) = cfg->img_buf[i].phys_cb;
394 - CICOCRSA(i) = cfg->img_buf[i].phys_cr;
395 - }
396 - break;
397 - default:
398 - printk("Invalid PingPong Number %d \n",cfg->pp_num);
399 - panic("halt\n");
400 - }
401 + one_p_size = daon + 2*c_size;
402 + for (i = 0; i < 4 ; i++) {
403 + cfg->img_buf[i].virt_y = cfg->pp_virt_buf + TRY * one_p_size;
404 + cfg->img_buf[i].phys_y = cfg->pp_phys_buf + TRY * one_p_size;
405 + cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + TRY * one_p_size;
406 + cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + TRY * one_p_size;
407 + cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + TRY * one_p_size;
408 + cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + TRY * one_p_size;
409 + writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
410 + writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
411 + writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
412 + }
413 + break;
414 + case 4:
415 + one_p_size = daon + 2*c_size;
416 + for (i = 0; i < 4 ; i++) {
417 + cfg->img_buf[i].virt_y = cfg->pp_virt_buf + i * one_p_size;
418 + cfg->img_buf[i].phys_y = cfg->pp_phys_buf + i * one_p_size;
419 + cfg->img_buf[i].virt_cb = cfg->pp_virt_buf + daon + i * one_p_size;
420 + cfg->img_buf[i].phys_cb = cfg->pp_phys_buf + daon + i * one_p_size;
421 + cfg->img_buf[i].virt_cr = cfg->pp_virt_buf + daon + c_size + i * one_p_size;
422 + cfg->img_buf[i].phys_cr = cfg->pp_phys_buf + daon + c_size + i * one_p_size;
423 + writel(cfg->img_buf[i].phys_y, camregs + S3C2440_CAM_REG_CICOYSA(i));
424 + writel(cfg->img_buf[i].phys_cb, camregs + S3C2440_CAM_REG_CICOCBSA(i));
425 + writel(cfg->img_buf[i].phys_cr, camregs + S3C2440_CAM_REG_CICOCRSA(i));
426 + }
427 + break;
428 + default:
429 + printk("Invalid PingPong Number %d \n",cfg->pp_num);
430 + panic("halt\n");
431 +}
432 return 0;
433 }
434
435 @@ -222,21 +225,21 @@ static int camif_pp_preview(camif_cfg_t *cfg)
436 for ( i = 0; i < 4 ; i++ ) {
437 cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf ;
438 cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf ;
439 - CIPRCLRSA(i) = cfg->img_buf[i].phys_rgb;
440 + writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
441 }
442 break;
443 case 2:
444 for ( i = 0; i < 4 ; i++) {
445 cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + TRY * daon;
446 cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + TRY * daon;
447 - CIPRCLRSA(i) = cfg->img_buf[i].phys_rgb;
448 + writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
449 }
450 break;
451 case 4:
452 for ( i = 0; i < 4 ; i++) {
453 cfg->img_buf[i].virt_rgb = cfg->pp_virt_buf + i * daon;
454 cfg->img_buf[i].phys_rgb = cfg->pp_phys_buf + i * daon;
455 - CIPRCLRSA(i) = cfg->img_buf[i].phys_rgb;
456 + writel(cfg->img_buf[i].phys_rgb, camregs + S3C2440_CAM_REG_CICOCRSA(i));
457 }
458 break;
459 default:
460 @@ -308,7 +311,7 @@ static int camif_source_fmt(camif_gc_t *gc)
461 cmd |= SOURCE_HSIZE(gc->source_x)| SOURCE_VSIZE(gc->source_y);
462 /* Order422 */
463 cmd |= gc->order422;
464 - CISRCFMT = cmd;
465 + writel(cmd, camregs + S3C2440_CAM_REG_CISRCFMT);
466
467 return 0 ;
468 }
469 @@ -331,33 +334,24 @@ static int camif_target_fmt(camif_cfg_t *cfg)
470 assert(cfg->fmt & CAMIF_OUT_YCBCR422);
471 cmd |= OUT_YCBCR422|IN_YCBCR422;
472 }
473 - CICOTRGFMT = cmd | cfg->flip;
474 - }
475 - else {
476 + writel(cmd | cfg->flip, camregs + S3C2440_CAM_REG_CICOTRGFMT);
477 +
478 + } else {
479 assert(cfg->dma_type & CAMIF_PREVIEW);
480 - CIPRTRGFMT =
481 - TARGET_HSIZE(cfg->target_x)|TARGET_VSIZE(cfg->target_y)|cfg->flip;
482 + writel(TARGET_HSIZE(cfg->target_x)|TARGET_VSIZE(cfg->target_y)|cfg->flip,
483 + camregs + S3C2440_CAM_REG_CIPRTRGFMT);
484 }
485 return 0;
486 }
487
488 void camif_change_flip(camif_cfg_t *cfg)
489 {
490 - u32 cmd = 0;
491 + u32 cmd = readl(camregs + S3C2440_CAM_REG_CICOTRGFMT);
492
493 - if (cfg->dma_type & CAMIF_CODEC ) {
494 - /* YCBCR setting */
495 - cmd = CICOTRGFMT;
496 - cmd &= ~(BIT14|BIT15); /* Clear FLIP Mode */
497 - cmd |= cfg->flip;
498 - CICOTRGFMT = cmd;
499 - }
500 - else {
501 - cmd = CIPRTRGFMT;
502 - cmd &= ~(BIT14|BIT15);
503 - cmd |= cfg->flip;
504 - CICOTRGFMT = cmd;
505 - }
506 + cmd &= ~(BIT14|BIT15);
507 + cmd |= cfg->flip;
508 +
509 + writel(cmd, camregs + S3C2440_CAM_REG_CICOTRGFMT);
510 }
511
512
513 @@ -373,70 +367,81 @@ int camif_capture_start(camif_cfg_t *cfg)
514 u32 n_cmd = 0; /* Next Command */
515
516 switch(cfg->exec) {
517 - case CAMIF_BOTH_DMA_ON:
518 - camif_reset(CAMIF_RESET,0); /* Flush Camera Core Buffer */
519 - CIPRSCCTRL |= SCALERSTART;
520 - CICOSCCTRL |= SCALERSTART;
521 - n_cmd = CAMIF_CAP_PREVIEW_ON|CAMIF_CAP_CODEC_ON;
522 - break;
523 - case CAMIF_DMA_ON:
524 - camif_reset(CAMIF_RESET,0); /* Flush Camera Core Buffer */
525 - if (cfg->dma_type&CAMIF_CODEC) {
526 - CICOSCCTRL |= SCALERSTART;
527 - n_cmd = CAMIF_CAP_CODEC_ON;
528 - }else {
529 - CIPRSCCTRL |= SCALERSTART;
530 - n_cmd = CAMIF_CAP_PREVIEW_ON;
531 - }
532 + case CAMIF_BOTH_DMA_ON:
533 + camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
534 + writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
535 + SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
536 + writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
537 + SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
538 + n_cmd = CAMIF_CAP_PREVIEW_ON | CAMIF_CAP_CODEC_ON;
539 + break;
540 + case CAMIF_DMA_ON:
541 + camif_reset(CAMIF_RESET, 0); /* Flush Camera Core Buffer */
542 + if (cfg->dma_type&CAMIF_CODEC) {
543 + writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) |
544 + SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
545 + n_cmd = CAMIF_CAP_CODEC_ON;
546 + } else {
547 + writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) |
548 + SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
549 + n_cmd = CAMIF_CAP_PREVIEW_ON;
550 + }
551
552 - /* wait until Sync Time expires */
553 - /* First settting, to wait VSYNC fall */
554 - /* By VESA spec,in 640x480 @60Hz
555 - MAX Delay Time is around 64us which "while" has.*/
556 - while(VSYNC & CICOSTATUS);
557 - break;
558 - default:
559 - break;
560 - }
561 - CIIMGCPT = n_cmd|CAMIF_CAP_ON;
562 + /* wait until Sync Time expires */
563 + /* First settting, to wait VSYNC fall */
564 + /* By VESA spec,in 640x480 @60Hz
565 + MAX Delay Time is around 64us which "while" has.*/
566 + while(VSYNC & readl(camregs + S3C2440_CAM_REG_CICOSTATUS));
567 + break;
568 + default:
569 + break;
570 +}
571 + writel(n_cmd | CAMIF_CAP_ON, camregs + S3C2440_CAM_REG_CIIMGCPT);
572 return 0;
573 }
574
575
576 int camif_capture_stop(camif_cfg_t *cfg)
577 {
578 - u32 n_cmd = CIIMGCPT; /* Next Command */
579 + u32 n_cmd = readl(camregs + S3C2440_CAM_REG_CIIMGCPT); /* Next Command */
580
581 switch(cfg->exec) {
582 - case CAMIF_BOTH_DMA_OFF:
583 - CIPRSCCTRL &= ~SCALERSTART;
584 - CICOSCCTRL &= ~SCALERSTART;
585 - n_cmd = 0;
586 - break;
587 - case CAMIF_DMA_OFF_L_IRQ: /* fall thru */
588 - case CAMIF_DMA_OFF:
589 - if (cfg->dma_type&CAMIF_CODEC) {
590 - CICOSCCTRL &= ~SCALERSTART;
591 - n_cmd &= ~CAMIF_CAP_CODEC_ON;
592 - if (!(n_cmd & CAMIF_CAP_PREVIEW_ON))
593 - n_cmd = 0;
594 - }else {
595 - CIPRSCCTRL &= ~SCALERSTART;
596 - n_cmd &= ~CAMIF_CAP_PREVIEW_ON;
597 - if (!(n_cmd & CAMIF_CAP_CODEC_ON))
598 - n_cmd = 0;
599 - }
600 - break;
601 - default:
602 - panic("Unexpected \n");
603 - }
604 - CIIMGCPT = n_cmd;
605 - if(cfg->exec == CAMIF_DMA_OFF_L_IRQ) { /* Last IRQ */
606 - if (cfg->dma_type & CAMIF_CODEC)
607 - CICOCTRL |= LAST_IRQ_EN;
608 - else
609 - CIPRCTRL |= LAST_IRQ_EN;
610 - }
611 + case CAMIF_BOTH_DMA_OFF:
612 + writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
613 + ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
614 + writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
615 + ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
616 + n_cmd = 0;
617 + break;
618 + case CAMIF_DMA_OFF_L_IRQ: /* fall thru */
619 + case CAMIF_DMA_OFF:
620 + if (cfg->dma_type&CAMIF_CODEC) {
621 + writel(readl(camregs + S3C2440_CAM_REG_CICOSCCTRL) &
622 + ~SCALERSTART, camregs + S3C2440_CAM_REG_CICOSCCTRL);
623 + n_cmd &= ~CAMIF_CAP_CODEC_ON;
624 + if (!(n_cmd & CAMIF_CAP_PREVIEW_ON))
625 + n_cmd = 0;
626 + } else {
627 + writel(readl(camregs + S3C2440_CAM_REG_CIPRSCCTRL) &
628 + ~SCALERSTART, camregs + S3C2440_CAM_REG_CIPRSCCTRL);
629 + n_cmd &= ~CAMIF_CAP_PREVIEW_ON;
630 + if (!(n_cmd & CAMIF_CAP_CODEC_ON))
631 + n_cmd = 0;
632 + }
633 + break;
634 + default:
635 + panic("Unexpected \n");
636 + }
637 + writel(n_cmd, camregs + S3C2440_CAM_REG_CIIMGCPT);
638 +
639 + if (cfg->exec == CAMIF_DMA_OFF_L_IRQ) { /* Last IRQ */
640 + if (cfg->dma_type & CAMIF_CODEC)
641 + writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
642 + LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
643 + else
644 + writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
645 + LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
646 + }
647 #if 0
648 else { /* to make internal state machine of CAMERA stop */
649 camif_reset(CAMIF_RESET, 0);
650 @@ -449,16 +454,13 @@ int camif_capture_stop(camif_cfg_t *cfg)
651 /* LastIRQEn is autoclear */
652 void camif_last_irq_en(camif_cfg_t *cfg)
653 {
654 - if(cfg->exec == CAMIF_BOTH_DMA_ON) {
655 - CIPRCTRL |= LAST_IRQ_EN;
656 - CICOCTRL |= LAST_IRQ_EN;
657 - }
658 - else {
659 - if (cfg->dma_type & CAMIF_CODEC)
660 - CICOCTRL |= LAST_IRQ_EN;
661 - else
662 - CIPRCTRL |= LAST_IRQ_EN;
663 - }
664 + if ((cfg->exec == CAMIF_BOTH_DMA_ON) || (cfg->dma_type & CAMIF_CODEC))
665 + writel(readl(camregs + S3C2440_CAM_REG_CICOCTRL) |
666 + LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CICOCTRL);
667 +
668 + if ((cfg->exec == CAMIF_BOTH_DMA_ON) || !(cfg->dma_type & CAMIF_CODEC))
669 + writel(readl(camregs + S3C2440_CAM_REG_CIPRCTRL) |
670 + LAST_IRQ_EN, camregs + S3C2440_CAM_REG_CIPRCTRL);
671 }
672
673 static int
674 @@ -502,23 +504,33 @@ int camif_g_fifo_status(camif_cfg_t *cfg)
675 u32 reg;
676
677 if (cfg->dma_type & CAMIF_CODEC) {
678 - u32 flag = CO_OVERFLOW_Y|CO_OVERFLOW_CB|CO_OVERFLOW_CR;
679 - reg = CICOSTATUS;
680 + u32 flag = CO_OVERFLOW_Y | CO_OVERFLOW_CB | CO_OVERFLOW_CR;
681 + reg = readl(camregs + S3C2440_CAM_REG_CICOSTATUS);
682 if (reg & flag) {
683 printk("CODEC: FIFO error(0x%08x) and corrected\n",reg);
684 /* FIFO Error Count ++ */
685 - CIWDOFST |= CO_FIFO_Y|CO_FIFO_CB|CO_FIFO_CR;
686 - CIWDOFST &= ~(CO_FIFO_Y|CO_FIFO_CB|CO_FIFO_CR);
687 + writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
688 + CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR,
689 + camregs + S3C2440_CAM_REG_CIWDOFST);
690 +
691 + writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
692 + ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
693 + camregs + S3C2440_CAM_REG_CIWDOFST);
694 return 1; /* Error */
695 }
696 }
697 if (cfg->dma_type & CAMIF_PREVIEW) {
698 - u32 flag = PR_OVERFLOW_CB|PR_OVERFLOW_CR;
699 - reg = CIPRSTATUS;
700 + u32 flag = PR_OVERFLOW_CB | PR_OVERFLOW_CR;
701 + reg = readl(camregs + S3C2440_CAM_REG_CIPRSTATUS);
702 if (reg & flag) {
703 printk("PREVIEW:FIFO error(0x%08x) and corrected\n",reg);
704 - CIWDOFST |= PR_FIFO_CB|PR_FIFO_CR;
705 - CIWDOFST &= ~(CO_FIFO_Y|CO_FIFO_CB|CO_FIFO_CR);
706 + writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) |
707 + CO_FIFO_CB | CO_FIFO_CR,
708 + camregs + S3C2440_CAM_REG_CIWDOFST);
709 +
710 + writel(readl(camregs + S3C2440_CAM_REG_CIWDOFST) &
711 + ~(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR),
712 + camregs + S3C2440_CAM_REG_CIWDOFST);
713 /* FIFO Error Count ++ */
714 return 1; /* Error */
715 }
716 @@ -537,13 +549,16 @@ int camif_win_offset(camif_gc_t *gc )
717 u32 v = gc->win_ver_ofst;
718
719 /*Clear Overflow */
720 - CIWDOFST = CO_FIFO_Y|CO_FIFO_CB|CO_FIFO_CR|PR_FIFO_CB|PR_FIFO_CB;
721 - CIWDOFST = 0; /* ? Dummy */
722 + writel(CO_FIFO_Y | CO_FIFO_CB | CO_FIFO_CR | PR_FIFO_CB | PR_FIFO_CB,
723 + camregs + S3C2440_CAM_REG_CIWDOFST);
724 + writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
725 +
726 if (!h && !v) {
727 - CIWDOFST = 0;
728 + writel(0, camregs + S3C2440_CAM_REG_CIWDOFST);
729 return 0;
730 }
731 - CIWDOFST = WINOFEN | WINHOROFST(h) | WINVEROFST(v);
732 +
733 + writel(WINOFEN | WINHOROFST(h) | WINVEROFST(v), camregs + S3C2440_CAM_REG_CIWDOFST);
734 return 0;
735 }
736
737 @@ -554,7 +569,7 @@ int camif_win_offset(camif_gc_t *gc )
738 */
739 static void camif_polarity(camif_gc_t *gc)
740 {
741 - u32 cmd = CIGCTRL;
742 + u32 cmd = readl(camregs + S3C2440_CAM_REG_CIGCTRL);;
743
744 cmd = cmd & ~(BIT26|BIT25|BIT24); /* clear polarity */
745 if (gc->polarity_pclk)
746 @@ -563,7 +578,8 @@ static void camif_polarity(camif_gc_t *gc)
747 cmd |= GC_INVPOLVSYNC;
748 if (gc->polarity_href)
749 cmd |= GC_INVPOLHREF;
750 - CIGCTRL |= cmd;
751 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
752 + cmd, camregs + S3C2440_CAM_REG_CIGCTRL);
753 }
754
755
756 @@ -599,12 +615,13 @@ int camif_dynamic_close(camif_cfg_t *cfg)
757 static int camif_target_area(camif_cfg_t *cfg)
758 {
759 u32 rect = cfg->target_x * cfg->target_y;
760 - if (cfg->dma_type & CAMIF_CODEC ) {
761 - CICOTAREA = rect;
762 - }
763 - if (cfg->dma_type & CAMIF_PREVIEW) {
764 - CIPRTAREA = rect;
765 - }
766 +
767 + if (cfg->dma_type & CAMIF_CODEC)
768 + writel(rect, camregs + S3C2440_CAM_REG_CICOTAREA);
769 +
770 + if (cfg->dma_type & CAMIF_PREVIEW)
771 + writel(rect, camregs + S3C2440_CAM_REG_CIPRTAREA);
772 +
773 return 0;
774 }
775
776 @@ -613,40 +630,44 @@ static int inline camif_hw_reg(camif_cfg_t *cfg)
777 u32 cmd = 0;
778
779 if (cfg->dma_type & CAMIF_CODEC) {
780 - CICOSCPRERATIO = PRE_SHIFT(cfg->sc.shfactor)
781 - |PRE_HRATIO(cfg->sc.prehratio)|PRE_VRATIO(cfg->sc.prevratio);
782 - CICOSCPREDST =
783 - PRE_DST_WIDTH(cfg->sc.predst_x)|PRE_DST_HEIGHT(cfg->sc.predst_y);
784 + writel(PRE_SHIFT(cfg->sc.shfactor) |
785 + PRE_HRATIO(cfg->sc.prehratio) |
786 + PRE_VRATIO(cfg->sc.prevratio),
787 + camregs + S3C2440_CAM_REG_CICOSCPRERATIO);
788 + writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
789 + PRE_DST_HEIGHT(cfg->sc.predst_y),
790 + camregs + S3C2440_CAM_REG_CICOSCPREDST);
791
792 /* Differ from Preview */
793 if (cfg->sc.scalerbypass)
794 cmd |= SCALERBYPASS;
795 if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
796 cmd |= BIT30|BIT29;
797 - CICOSCCTRL = cmd | MAIN_HRATIO(cfg->sc.mainhratio)
798 - |MAIN_VRATIO(cfg->sc.mainvratio);
799 + writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) |
800 + MAIN_VRATIO(cfg->sc.mainvratio),
801 + camregs + S3C2440_CAM_REG_CICOSCCTRL);
802 return 0;
803 }
804 - else if (cfg->dma_type & CAMIF_PREVIEW) {
805 - CIPRSCPRERATIO = PRE_SHIFT(cfg->sc.shfactor)
806 - |PRE_HRATIO(cfg->sc.prehratio)|PRE_VRATIO(cfg->sc.prevratio);
807 - CIPRSCPREDST =
808 - PRE_DST_WIDTH(cfg->sc.predst_x)|PRE_DST_HEIGHT(cfg->sc.predst_y);
809 + if (cfg->dma_type & CAMIF_PREVIEW) {
810 + writel(PRE_SHIFT(cfg->sc.shfactor) |
811 + PRE_HRATIO(cfg->sc.prehratio) |
812 + PRE_VRATIO(cfg->sc.prevratio),
813 + camregs + S3C2440_CAM_REG_CIPRSCPRERATIO);
814 + writel(PRE_DST_WIDTH(cfg->sc.predst_x) |
815 + PRE_DST_HEIGHT(cfg->sc.predst_y),
816 + camregs + S3C2440_CAM_REG_CIPRSCPREDST);
817 /* Differ from Codec */
818 - if (cfg->fmt & CAMIF_RGB24) {
819 + if (cfg->fmt & CAMIF_RGB24)
820 cmd |= RGB_FMT24;
821 - }
822 - else {
823 - /* RGB16 */;
824 - }
825 if (cfg->sc.scaleup_h & cfg->sc.scaleup_v)
826 - cmd |= BIT29|BIT28;
827 - CIPRSCCTRL = cmd |MAIN_HRATIO(cfg->sc.mainhratio)|S_METHOD
828 - |MAIN_VRATIO(cfg->sc.mainvratio);
829 - }else {
830 - panic("CAMERA:DMA_TYPE Wrong \n");
831 + cmd |= BIT29 | BIT28;
832 + writel(cmd | MAIN_HRATIO(cfg->sc.mainhratio) | S_METHOD |
833 + MAIN_VRATIO(cfg->sc.mainvratio),
834 + camregs + S3C2440_CAM_REG_CIPRSCCTRL);
835 + return 0;
836 }
837
838 + panic("CAMERA:DMA_TYPE Wrong \n");
839 return 0;
840 }
841
842 @@ -654,46 +675,50 @@ static int inline camif_hw_reg(camif_cfg_t *cfg)
843 /* Configure Pre-scaler control & main scaler control register */
844 static int camif_scaler(camif_cfg_t *cfg)
845 {
846 - int tx = cfg->target_x,ty=cfg->target_y;
847 + int tx = cfg->target_x, ty = cfg->target_y;
848 int sx, sy;
849
850 - if (tx <= 0 || ty<= 0) panic("CAMERA: Invalid target size \n");
851 + if (tx <= 0 || ty <= 0)
852 + panic("CAMERA: Invalid target size \n");
853 +
854 + sx = cfg->gc->source_x - 2 * cfg->gc->win_hor_ofst;
855 + sy = cfg->gc->source_y - 2 * cfg->gc->win_ver_ofst;
856 + if (sx <= 0 || sy <= 0)
857 + panic("CAMERA: Invalid source size \n");
858
859 - sx = cfg->gc->source_x - 2*cfg->gc->win_hor_ofst;
860 - sy = cfg->gc->source_y - 2*cfg->gc->win_ver_ofst;
861 - if (sx <= 0 || sy<= 0) panic("CAMERA: Invalid source size \n");
862 cfg->sc.modified_src_x = sx;
863 cfg->sc.modified_src_y = sy;
864
865 /* Pre-scaler control register 1 */
866 - camif_scaler_internal(sx,tx,&cfg->sc.prehratio,&cfg->sc.hfactor);
867 - camif_scaler_internal(sy,ty,&cfg->sc.prevratio,&cfg->sc.vfactor);
868 + camif_scaler_internal(sx, tx, &cfg->sc.prehratio, &cfg->sc.hfactor);
869 + camif_scaler_internal(sy, ty, &cfg->sc.prevratio, &cfg->sc.vfactor);
870
871 - if (cfg->dma_type & CAMIF_PREVIEW) {
872 - if ( (sx /cfg->sc.prehratio) <= 640 ) {}
873 - else {
874 - printk(KERN_INFO "CAMERA: Internal Preview line buffer is 640 pixels\n");
875 + if (cfg->dma_type & CAMIF_PREVIEW)
876 + if ((sx / cfg->sc.prehratio) > 640) {
877 + printk(KERN_INFO "CAMERA: Internal Preview line "
878 + "buffer is 640 pixels\n");
879 return 1; /* Error */
880 }
881 - }
882
883 - cfg->sc.shfactor = 10-(cfg->sc.hfactor+cfg->sc.vfactor);
884 + cfg->sc.shfactor = 10 - (cfg->sc.hfactor + cfg->sc.vfactor);
885 /* Pre-scaler control register 2 */
886 cfg->sc.predst_x = sx / cfg->sc.prehratio;
887 cfg->sc.predst_y = sy / cfg->sc.prevratio;
888
889 /* Main-scaler control register */
890 - cfg->sc.mainhratio = (sx << 8)/(tx << cfg->sc.hfactor);
891 - cfg->sc.mainvratio = (sy << 8)/(ty << cfg->sc.vfactor);
892 - DPRINTK(" sx %d, sy %d tx %d ty %d \n",sx,sy,tx,ty);
893 - DPRINTK(" hfactor %d vfactor %d \n",cfg->sc.hfactor,cfg->sc.vfactor);
894 + cfg->sc.mainhratio = (sx << 8) / (tx << cfg->sc.hfactor);
895 + cfg->sc.mainvratio = (sy << 8) / (ty << cfg->sc.vfactor);
896 + DPRINTK(" sx %d, sy %d tx %d ty %d \n", sx, sy, tx, ty);
897 + DPRINTK(" hfactor %d vfactor %d \n",cfg->sc.hfactor, cfg->sc.vfactor);
898
899 cfg->sc.scaleup_h = (sx <= tx) ? 1: 0;
900 cfg->sc.scaleup_v = (sy <= ty) ? 1: 0;
901 - if ( cfg->sc.scaleup_h != cfg->sc.scaleup_v)
902 + if (cfg->sc.scaleup_h != cfg->sc.scaleup_v)
903 printk(KERN_ERR "scaleup_h must be same to scaleup_v \n");
904 +
905 camif_hw_reg(cfg);
906 camif_target_area(cfg);
907 +
908 return 0;
909 }
910
911 @@ -706,38 +731,38 @@ static void camif_g_bsize(u32 hsize, u32 *mburst, u32 *rburst)
912 {
913 u32 tmp;
914
915 - tmp = (hsize/4) % 16;
916 + tmp = (hsize / 4) % 16;
917 switch(tmp) {
918 + case 0:
919 + *mburst=16;
920 + *rburst=16;
921 + break;
922 + case 4:
923 + *mburst=16;
924 + *rburst=4;
925 + break;
926 + case 8:
927 + *mburst=16;
928 + *rburst=8;
929 + break;
930 + default:
931 + tmp=(hsize / 4) % 8;
932 + switch(tmp) {
933 case 0:
934 - *mburst=16;
935 - *rburst=16;
936 + *mburst = 8;
937 + *rburst = 8;
938 break;
939 case 4:
940 - *mburst=16;
941 - *rburst=4;
942 - break;
943 - case 8:
944 - *mburst=16;
945 - *rburst=8;
946 - break;
947 + *mburst = 8;
948 + *rburst = 4;
949 default:
950 - tmp=(hsize/4)%8;
951 - switch(tmp) {
952 - case 0:
953 - *mburst=8;
954 - *rburst=8;
955 - break;
956 - case 4:
957 - *mburst=8;
958 - *rburst=4;
959 - default:
960 - *mburst=4;
961 - tmp=(hsize/4)%4;
962 - *rburst= (tmp) ? tmp: 4;
963 - break;
964 - }
965 + *mburst = 4;
966 + tmp = (hsize / 4) % 4;
967 + *rburst= (tmp) ? tmp: 4;
968 break;
969 }
970 + break;
971 + }
972 }
973
974 /* SXGA 1028x1024*/
975 @@ -759,24 +784,30 @@ static int camif_dma_burst(camif_cfg_t *cfg)
976 u32 yburst_m, yburst_r;
977 u32 cburst_m, cburst_r;
978 /* CODEC DMA WIDHT is multiple of 16 */
979 - if (width %16 != 0 ) return BURST_ERR; /* DMA Burst Length Error */
980 - camif_g_bsize(width,&yburst_m,&yburst_r);
981 - camif_g_bsize(width/2,&cburst_m,&cburst_r);
982 - CICOCTRL =YBURST_M(yburst_m)|CBURST_M(cburst_m)
983 - |YBURST_R(yburst_r)|CBURST_R(cburst_r);
984 + if (width % 16)
985 + return BURST_ERR; /* DMA Burst Length Error */
986 + camif_g_bsize(width, &yburst_m, &yburst_r);
987 + camif_g_bsize(width / 2, &cburst_m, &cburst_r);
988 +
989 + writel(YBURST_M(yburst_m) | CBURST_M(cburst_m) |
990 + YBURST_R(yburst_r) | CBURST_R(cburst_r),
991 + camregs + S3C2440_CAM_REG_CICOCTRL);
992 }
993
994 if (cfg->dma_type & CAMIF_PREVIEW) {
995 u32 rgburst_m, rgburst_r;
996 if(cfg->fmt == CAMIF_RGB24) {
997 - if (width %2 != 0 ) return BURST_ERR; /* DMA Burst Length Error */
998 + if (width % 2)
999 + return BURST_ERR; /* DMA Burst Length Error */
1000 camif_g_bsize(width*4,&rgburst_m,&rgburst_r);
1001 - }
1002 - else { /* CAMIF_RGB16 */
1003 - if ((width/2) %2 != 0 ) return BURST_ERR; /* DMA Burst Length Error */
1004 + } else { /* CAMIF_RGB16 */
1005 + if ((width / 2) %2)
1006 + return BURST_ERR; /* DMA Burst Length Error */
1007 camif_g_bsize(width*2,&rgburst_m,&rgburst_r);
1008 }
1009 - CIPRCTRL = RGBURST_M(rgburst_m) | RGBURST_R(rgburst_r);
1010 +
1011 + writel(RGBURST_M(rgburst_m) | RGBURST_R(rgburst_r),
1012 + camregs + S3C2440_CAM_REG_CIPRCTRL);
1013 }
1014 return 0;
1015 }
1016 @@ -786,19 +817,20 @@ static int camif_gpio_init(void)
1017 #ifdef CONFIG_ARCH_S3C24A0A
1018 /* S3C24A0A has the dedicated signal pins for Camera */
1019 #else
1020 - set_gpio_ctrl(GPIO_CAMDATA0);
1021 - set_gpio_ctrl(GPIO_CAMDATA1);
1022 - set_gpio_ctrl(GPIO_CAMDATA2);
1023 - set_gpio_ctrl(GPIO_CAMDATA3);
1024 - set_gpio_ctrl(GPIO_CAMDATA4);
1025 - set_gpio_ctrl(GPIO_CAMDATA5);
1026 - set_gpio_ctrl(GPIO_CAMDATA6);
1027 - set_gpio_ctrl(GPIO_CAMDATA7);
1028 - set_gpio_ctrl(GPIO_CAMPCLKIN);
1029 - set_gpio_ctrl(GPIO_CAMVSYNC);
1030 - set_gpio_ctrl(GPIO_CAMHREF);
1031 - set_gpio_ctrl(GPIO_CAMPCLKOUT);
1032 - set_gpio_ctrl(GPIO_CAMRESET);
1033 + s3c2410_gpio_cfgpin(S3C2440_GPJ0, S3C2440_GPJ0_CAMDATA0);
1034 + s3c2410_gpio_cfgpin(S3C2440_GPJ1, S3C2440_GPJ1_CAMDATA1);
1035 + s3c2410_gpio_cfgpin(S3C2440_GPJ2, S3C2440_GPJ2_CAMDATA2);
1036 + s3c2410_gpio_cfgpin(S3C2440_GPJ3, S3C2440_GPJ3_CAMDATA3);
1037 + s3c2410_gpio_cfgpin(S3C2440_GPJ4, S3C2440_GPJ4_CAMDATA4);
1038 + s3c2410_gpio_cfgpin(S3C2440_GPJ5, S3C2440_GPJ5_CAMDATA5);
1039 + s3c2410_gpio_cfgpin(S3C2440_GPJ6, S3C2440_GPJ6_CAMDATA6);
1040 + s3c2410_gpio_cfgpin(S3C2440_GPJ7, S3C2440_GPJ7_CAMDATA7);
1041 +
1042 + s3c2410_gpio_cfgpin(S3C2440_GPJ8, S3C2440_GPJ8_CAMPCLK);
1043 + s3c2410_gpio_cfgpin(S3C2440_GPJ9, S3C2440_GPJ9_CAMVSYNC);
1044 + s3c2410_gpio_cfgpin(S3C2440_GPJ10, S3C2440_GPJ10_CAMHREF);
1045 + s3c2410_gpio_cfgpin(S3C2440_GPJ11, S3C2440_GPJ11_CAMCLKOUT);
1046 + s3c2410_gpio_cfgpin(S3C2440_GPJ12, S3C2440_GPJ12_CAMRESET);
1047 #endif
1048 return 0;
1049 }
1050 @@ -827,21 +859,33 @@ int camif_clock_init(camif_gc_t *gc)
1051 camclk_div = (upll+ROUND_ADD) / camclk - 1;
1052 CLKDIVN = (CLKDIVN & 0xFF) | CLKDIVN_CAM(camclk_div);
1053 printk(KERN_INFO"CAMERA:upll %d MACRO 0x%08X CLKDIVN 0x%08X \n",
1054 - upll, CLKDIVN_CAM(camclk_div),CLKDIVN);
1055 - CIIMGCPT = 0; /* Dummy ? */
1056 + upll, CLKDIVN_CAM(camclk_div), CLKDIVN);
1057 + writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT); /* Dummy ? */
1058 +
1059 return 0;
1060 }
1061 #else
1062 int camif_clock_init(camif_gc_t *gc)
1063 {
1064 - unsigned int upll, camclk_div, camclk;
1065 - if (!gc) camclk = 24000000;
1066 - else {
1067 + unsigned int camclk;
1068 + struct clk *clk_camif = clk_get(NULL, "camif");
1069 + struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
1070 +
1071 + if (!gc)
1072 + camclk = 24000000;
1073 + else {
1074 camclk = gc->camclk;
1075 if (camclk > 48000000)
1076 printk(KERN_ERR "Wrong Camera Clock\n");
1077 }
1078
1079 + clk_set_rate(clk_camif, camclk);
1080 +
1081 + clk_enable(clk_camif);
1082 + clk_enable(clk_camif_upll);
1083 +
1084 +
1085 +#if 0
1086 CLKCON |= CLKCON_CAMIF;
1087 upll = elfin_get_bus_clk(GET_UPLL);
1088 printk(KERN_INFO "CAMERA:Default UPLL %08d and Assing 96Mhz to UPLL\n",upll);
1089 @@ -854,7 +898,9 @@ int camif_clock_init(camif_gc_t *gc)
1090 camclk_div = (upll+ROUND_ADD) /(camclk * 2) -1;
1091 CAMDIVN = CAMCLK_SET_DIV|(camclk_div&0xf);
1092 printk(KERN_INFO "CAMERA:upll %08d cam_clk %08d CAMDIVN 0x%08x \n",upll,camclk, CAMDIVN);
1093 - CIIMGCPT = 0; /* Dummy ? */
1094 +#endif
1095 + writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT); /* Dummy ? */
1096 +
1097 return 0;
1098 }
1099 #endif
1100 @@ -867,23 +913,39 @@ void camif_reset(int is, int delay)
1101 {
1102 switch (is) {
1103 case CAMIF_RESET:
1104 - CIGCTRL |= GC_SWRST;
1105 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
1106 + GC_SWRST,
1107 + camregs + S3C2440_CAM_REG_CIGCTRL);
1108 mdelay(1);
1109 - CIGCTRL &= ~GC_SWRST;
1110 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
1111 + ~GC_SWRST,
1112 + camregs + S3C2440_CAM_REG_CIGCTRL);
1113 break;
1114 case CAMIF_EX_RESET_AH: /*Active High */
1115 - CIGCTRL &= ~GC_CAMRST;
1116 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
1117 + ~GC_CAMRST,
1118 + camregs + S3C2440_CAM_REG_CIGCTRL);
1119 udelay(200);
1120 - CIGCTRL |= GC_CAMRST;
1121 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
1122 + GC_CAMRST,
1123 + camregs + S3C2440_CAM_REG_CIGCTRL);
1124 udelay(delay);
1125 - CIGCTRL &= ~GC_CAMRST;
1126 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
1127 + ~GC_CAMRST,
1128 + camregs + S3C2440_CAM_REG_CIGCTRL);
1129 break;
1130 case CAMIF_EX_RESET_AL: /*Active Low */
1131 - CIGCTRL |= GC_CAMRST;
1132 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
1133 + GC_CAMRST,
1134 + camregs + S3C2440_CAM_REG_CIGCTRL);
1135 udelay(200);
1136 - CIGCTRL &= ~GC_CAMRST;
1137 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) &
1138 + ~GC_CAMRST,
1139 + camregs + S3C2440_CAM_REG_CIGCTRL);
1140 udelay(delay);
1141 - CIGCTRL |= GC_CAMRST;
1142 + writel(readl(camregs + S3C2440_CAM_REG_CIGCTRL) |
1143 + GC_CAMRST,
1144 + camregs + S3C2440_CAM_REG_CIGCTRL);
1145 break;
1146 default:
1147 break;
1148 @@ -908,10 +970,10 @@ static void camif_bus_priority(int flag)
1149 PRIORITY1 = PRIORITY_I_FIX;
1150
1151 #else
1152 - old_priority = PRIORITY;
1153 - PRIORITY &= ~(3<<7);
1154 - PRIORITY |= (1<<7); /* Arbiter 1, REQ2 first */
1155 - PRIORITY &= ~(1<<1); /* Disable Priority Rotate */
1156 + old_priority = readl(S3C2410_PRIORITY);
1157 + writel(readl(S3C2410_PRIORITY) & ~(3<<7), S3C2410_PRIORITY);
1158 + writel(readl(S3C2410_PRIORITY) | (1<<7), S3C2410_PRIORITY); /* Arbiter 1, REQ2 first */
1159 + writel(readl(S3C2410_PRIORITY) & ~(1<<1), S3C2410_PRIORITY); /* Disable Priority Rotate */
1160 #endif
1161 }
1162 else {
1163 @@ -919,19 +981,26 @@ static void camif_bus_priority(int flag)
1164 PRIORITY0 = old_priority;
1165 PRIORITY1 = old_priority;
1166 #else
1167 - PRIORITY = old_priority;
1168 + writel(old_priority, S3C2410_PRIORITY);
1169 #endif
1170 }
1171 }
1172
1173 static void inline camif_clock_off(void)
1174 {
1175 - CIIMGCPT = 0;
1176 #if defined (CONFIG_ARCH_S3C24A0A)
1177 + writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
1178 +
1179 CLKCON &= ~CLKCON_CAM_UPLL;
1180 CLKCON &= ~CLKCON_CAM_HCLK;
1181 #else
1182 - CLKCON &= ~CLKCON_CAMIF;
1183 + struct clk *clk_camif = clk_get(NULL, "camif");
1184 + struct clk *clk_camif_upll = clk_get(NULL, "camif-upll");
1185 +
1186 + writel(0, camregs + S3C2440_CAM_REG_CIIMGCPT);
1187 +
1188 + clk_disable(clk_camif);
1189 + clk_disable(clk_camif_upll);
1190 #endif
1191 }
1192
1193 diff --git a/arch/arm/mach-s3c2440/camera/camif_fsm.c b/arch/arm/mach-s3c2440/camera/camif_fsm.c
1194 index 3e2b71a..b534aca 100644
1195 --- a/arch/arm/mach-s3c2440/camera/camif_fsm.c
1196 +++ b/arch/arm/mach-s3c2440/camera/camif_fsm.c
1197 @@ -31,7 +31,12 @@
1198 #include <asm/semaphore.h>
1199 #include <linux/miscdevice.h>
1200
1201 +#define CONFIG_VIDEO_V4L1_COMPAT
1202 +#include <linux/videodev.h>
1203 +#include "camif.h"
1204 +
1205 //#define SW_DEBUG
1206 +static void camif_start_p_with_c(camif_cfg_t *cfg);
1207
1208 #include "camif.h"
1209 const char *fsm_version =
1210 diff --git a/arch/arm/mach-s3c2440/camera/imgsensor.c b/arch/arm/mach-s3c2440/camera/imgsensor.c
1211 index 44b7bee..2099b69 100644
1212 --- a/arch/arm/mach-s3c2440/camera/imgsensor.c
1213 +++ b/arch/arm/mach-s3c2440/camera/imgsensor.c
1214 @@ -11,7 +11,7 @@
1215 * Driver for FIMC20 Camera Decoder
1216 */
1217
1218 -#include <linux/config.h>
1219 +
1220 #include <linux/module.h>
1221 #include <linux/kernel.h>
1222 #include <linux/init.h>
1223 @@ -24,10 +24,12 @@
1224
1225 #ifdef CONFIG_ARCH_S3C24A0A
1226 #else
1227 -#include <asm/arch/S3C2440.h>
1228 +//#include <asm/arch/S3C2440.h>
1229 #endif
1230
1231 #define SW_DEBUG
1232 +#define CONFIG_VIDEO_V4L1_COMPAT
1233 +#include <linux/videodev.h>
1234 #include "camif.h"
1235 #include "sensor.h"
1236
1237 @@ -37,10 +39,6 @@
1238 #include "sxga.h"
1239 #endif
1240
1241 -static const char *sensor_version =
1242 - "$Id: imgsensor.c,v 1.11 2004/06/10 12:45:40 swlee Exp $";
1243 -
1244 -
1245 static struct i2c_driver s5x532_driver;
1246 static camif_gc_t data = {
1247 itu_fmt: CAMIF_ITU601,
1248 @@ -69,22 +67,18 @@ static camif_gc_t data = {
1249
1250 #define CAM_ID 0x5a
1251
1252 -static unsigned short ignore[] = { I2C_CLIENT_END };
1253 +static unsigned short ignore = I2C_CLIENT_END;
1254 static unsigned short normal_addr[] = { (CAM_ID>>1), I2C_CLIENT_END };
1255 static struct i2c_client_address_data addr_data = {
1256 normal_i2c: normal_addr,
1257 - normal_i2c_range: ignore,
1258 - probe: ignore,
1259 - probe_range: ignore,
1260 - ignore: ignore,
1261 - ignore_range: ignore,
1262 - force: ignore,
1263 + probe: &ignore,
1264 + ignore: &ignore,
1265 };
1266
1267 s5x532_t s5x532_regs_mirror[S5X532_REGS];
1268
1269 unsigned char
1270 -s5x532_read(struct i2c_client *client,unsigned char subaddr)
1271 +s5x532_read(struct i2c_client *client, unsigned char subaddr)
1272 {
1273 int ret;
1274 unsigned char buf[1];
1275 @@ -151,7 +145,7 @@ void inline s5x532_init(struct i2c_client *sam_client)
1276 }
1277
1278 static int
1279 -s5x532_attach(struct i2c_adapter *adap, int addr, unsigned short flags,int kind)
1280 +s5x532_attach(struct i2c_adapter *adap, int addr, int kind)
1281 {
1282 struct i2c_client *c;
1283
1284 @@ -159,13 +153,13 @@ s5x532_attach(struct i2c_adapter *adap, int addr, unsigned short flags,int kind)
1285 if (!c) return -ENOMEM;
1286
1287 strcpy(c->name, "S5X532");
1288 - c->id = s5x532_driver.id;
1289 - c->flags = I2C_CLIENT_ALLOW_USE;
1290 +// c->id = s5x532_driver.id;
1291 + c->flags = 0 /* I2C_CLIENT_ALLOW_USE */;
1292 c->addr = addr;
1293 c->adapter = adap;
1294 c->driver = &s5x532_driver;
1295 - c->data = &data;
1296 - data.sensor = c;
1297 + data.sensor = c;
1298 + i2c_set_clientdata(c, &data);
1299
1300 camif_register_decoder(c);
1301 return i2c_attach_client(c);
1302 @@ -192,10 +186,10 @@ s5x532_command(struct i2c_client *client, unsigned int cmd, void *arg)
1303 printk(KERN_INFO "CAMERA: S5X532 Sensor initialized\n");
1304 break;
1305 case USER_ADD:
1306 - MOD_INC_USE_COUNT;
1307 + /* MOD_INC_USE_COUNT; uh.. 2.6 deals with this, old-timer */
1308 break;
1309 case USER_EXIT:
1310 - MOD_DEC_USE_COUNT;
1311 + /* MOD_DEC_USE_COUNT; */
1312 break;
1313 /* Todo
1314 case SENSOR_BRIGHTNESS:
1315 @@ -210,9 +204,8 @@ s5x532_command(struct i2c_client *client, unsigned int cmd, void *arg)
1316 }
1317
1318 static struct i2c_driver s5x532_driver = {
1319 - name: "S5X532",
1320 - id: I2C_ALGO_S3C,
1321 - flags: I2C_DF_NOTIFY,
1322 + driver: { name: "S5X532" },
1323 + id: 0, /* optional in i2c-id.h I2C_ALGO_S3C, */
1324 attach_adapter: s5x532_probe,
1325 detach_client: s5x532_detach,
1326 command: s5x532_command
1327 @@ -220,11 +213,13 @@ static struct i2c_driver s5x532_driver = {
1328
1329 static void iic_gpio_port(void)
1330 {
1331 +/* FIXME: no gpio config for i2c !!!
1332 #ifdef CONFIG_ARCH_S3C24A0A
1333 #else
1334 GPECON &= ~(0xf <<28);
1335 GPECON |= 0xa <<28;
1336 #endif
1337 +*/
1338 }
1339
1340 static __init int camif_sensor_init(void)
1341 diff --git a/arch/arm/mach-s3c2440/camera/qt-driver.c b/arch/arm/mach-s3c2440/camera/qt-driver.c
1342 index 0c5dd40..cbf8565 100644
1343 --- a/arch/arm/mach-s3c2440/camera/qt-driver.c
1344 +++ b/arch/arm/mach-s3c2440/camera/qt-driver.c
1345 @@ -31,12 +31,15 @@
1346
1347 //#define SW_DEBUG
1348
1349 +#define CONFIG_VIDEO_V4L1_COMPAT
1350 +#include <linux/videodev.h>
1351 #include "camif.h"
1352 -#include "videodev.h"
1353 #include "miscdevice.h"
1354 #include "cam_reg.h"
1355 #include "sensor.h"
1356 #include "userapp.h"
1357 +
1358 +extern camif_cfg_t * get_camif(int nr);
1359
1360
1361 /************************* Sharp Zarus API **************************
1362 diff --git a/arch/arm/mach-s3c2440/camera/video-driver.c b/arch/arm/mach-s3c2440/camera/video-driver.c
1363 index fe9130c..9c77475 100644
1364 --- a/arch/arm/mach-s3c2440/camera/video-driver.c
1365 +++ b/arch/arm/mach-s3c2440/camera/video-driver.c
1366 @@ -29,11 +29,12 @@
1367 #include <asm/irq.h>
1368 #include <asm/semaphore.h>
1369 #include <linux/miscdevice.h>
1370 +#include <asm/arch/irqs.h>
1371
1372 //#define SW_DEBUG
1373 -
1374 +#define CONFIG_VIDEO_V4L1_COMPAT
1375 +#include <linux/videodev.h>
1376 #include "camif.h"
1377 -#include "videodev.h"
1378 #include "miscdevice.h"
1379 #include "cam_reg.h"
1380 #include "sensor.h"
1381 @@ -46,12 +47,14 @@
1382 /* Codec and Preview */
1383 #define CAMIF_NUM 2
1384 static camif_cfg_t fimc[CAMIF_NUM];
1385 +u32 *camregs;
1386
1387 static const char *driver_version =
1388 "$Id: video-driver.c,v 1.9 2004/06/02 03:10:36 swlee Exp $";
1389 extern const char *fimc_version;
1390 extern const char *fsm_version;
1391
1392 +extern void camif_start_c_with_p (camif_cfg_t *cfg, camif_cfg_t *other);
1393
1394 camif_cfg_t * get_camif(int nr)
1395 {
1396 @@ -177,28 +180,34 @@ camif_c_read(struct file *file, char *buf, size_t count, loff_t *pos)
1397 }
1398
1399
1400 -static void camif_c_irq(int irq, void *dev_id, struct pt_regs *regs)
1401 +static irqreturn_t camif_c_irq(int irq, void *dev_id)
1402 {
1403 camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
1404 +
1405 DPRINTK("\n");
1406 camif_g_fifo_status(cfg);
1407 camif_g_frame_num(cfg);
1408 - if(camif_enter_c_4fsm(cfg) == INSTANT_SKIP) return;
1409 - wake_up_interruptible(&cfg->waitq);
1410 + if(camif_enter_c_4fsm(cfg) != INSTANT_SKIP)
1411 + wake_up_interruptible(&cfg->waitq);
1412 +
1413 + return IRQ_HANDLED;
1414 }
1415
1416 -static void camif_p_irq(int irq, void *dev_id, struct pt_regs * regs)
1417 +static irqreturn_t camif_p_irq(int irq, void *dev_id)
1418 {
1419 camif_cfg_t *cfg = (camif_cfg_t *)dev_id;
1420 +
1421 DPRINTK("\n");
1422 camif_g_fifo_status(cfg);
1423 camif_g_frame_num(cfg);
1424 - if(camif_enter_p_4fsm(cfg) == INSTANT_SKIP) return;
1425 - wake_up_interruptible(&cfg->waitq);
1426 + if(camif_enter_p_4fsm(cfg) != INSTANT_SKIP)
1427 + wake_up_interruptible(&cfg->waitq);
1428 #if 0
1429 if( (cfg->perf.frames % 5) == 0)
1430 DPRINTK("5\n");
1431 #endif
1432 +
1433 + return IRQ_HANDLED;
1434 }
1435
1436 static void camif_release_irq(camif_cfg_t *cfg)
1437 @@ -213,13 +222,13 @@ static int camif_irq_request(camif_cfg_t *cfg)
1438
1439 if (cfg->dma_type & CAMIF_CODEC) {
1440 if ((ret = request_irq(cfg->irq, camif_c_irq,
1441 - SA_INTERRUPT,cfg->shortname, cfg))) {
1442 + 0, cfg->shortname, cfg))) {
1443 printk("request_irq(CAM_C) failed.\n");
1444 }
1445 }
1446 if (cfg->dma_type & CAMIF_PREVIEW) {
1447 if ((ret = request_irq(cfg->irq, camif_p_irq,
1448 - SA_INTERRUPT,cfg->shortname, cfg))) {
1449 + 0, cfg->shortname, cfg))) {
1450 printk("request_irq(CAM_P) failed.\n");
1451 }
1452 }
1453 @@ -438,7 +447,7 @@ static struct video_device codec_template =
1454 {
1455 .name = "CODEC_IF",
1456 .type = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
1457 - .hardware = VID_HARDWARE_SAMSUNG_FIMC20,
1458 +/* .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
1459 .fops = &camif_c_fops,
1460 // .release = camif_release
1461 .minor = -1,
1462 @@ -448,7 +457,7 @@ static struct video_device preview_template =
1463 {
1464 .name = "PREVIEW_IF",
1465 .type = VID_TYPE_CAPTURE|VID_TYPE_CLIPPING|VID_TYPE_SCALES,
1466 - .hardware = VID_HARDWARE_SAMSUNG_FIMC20,
1467 +/* .hardware = VID_HARDWARE_SAMSUNG_FIMC20, */
1468 .fops = &camif_p_fops,
1469 .minor = -1,
1470 };
1471 @@ -465,8 +474,8 @@ static int preview_init(camif_cfg_t *cfg)
1472 cfg->fmt = CAMIF_RGB16;
1473 cfg->flip = CAMIF_FLIP_Y;
1474 cfg->v = &preview_template;
1475 - init_MUTEX(&cfg->v->lock);
1476 - cfg->irq = IRQ_CAM_P;
1477 + mutex_init(&cfg->v->lock);
1478 + cfg->irq = IRQ_S3C2440_CAM_P;
1479
1480 strcpy(cfg->shortname,name);
1481 init_waitqueue_head(&cfg->waitq);
1482 @@ -486,8 +495,8 @@ static int codec_init(camif_cfg_t *cfg)
1483 cfg->fmt = CAMIF_IN_YCBCR422|CAMIF_OUT_YCBCR420;
1484 cfg->flip = CAMIF_FLIP_X;
1485 cfg->v = &codec_template;
1486 - init_MUTEX(&cfg->v->lock);
1487 - cfg->irq = IRQ_CAM_C;
1488 + mutex_init(&cfg->v->lock);
1489 + cfg->irq = IRQ_S3C2440_CAM_C;
1490 strcpy(cfg->shortname,name);
1491 init_waitqueue_head(&cfg->waitq);
1492 cfg->status = CAMIF_STOPPED;
1493 @@ -510,25 +519,44 @@ static void print_version(void)
1494
1495 static int camif_m_in(void)
1496 {
1497 - int ret = 0;
1498 + int ret = -EINVAL;
1499 camif_cfg_t * cfg;
1500
1501 + printk(KERN_INFO"Starting S3C2440 Camera Driver\n");
1502 +
1503 + camregs = ioremap(CAM_BASE_ADD, 0x100);
1504 + if (!camregs) {
1505 + printk(KERN_ERR"Unable to map camera regs\n");
1506 + ret = -ENOMEM;
1507 + goto bail1;
1508 + }
1509 +
1510 camif_init();
1511 cfg = get_camif(CODEC_MINOR);
1512 codec_init(cfg);
1513
1514 - if (video_register_device(cfg->v,0,CODEC_MINOR)!=0) {
1515 - DPRINTK("Couldn't register codec driver.\n");
1516 - return 0;
1517 + ret = video_register_device(cfg->v,0,CODEC_MINOR);
1518 + if (ret) {
1519 + printk(KERN_ERR"Couldn't register codec driver.\n");
1520 + goto bail2;
1521 }
1522 cfg = get_camif(PREVIEW_MINOR);
1523 preview_init(cfg);
1524 - if (video_register_device(cfg->v,0,PREVIEW_MINOR)!=0) {
1525 - DPRINTK("Couldn't register preview driver.\n");
1526 - return 0;
1527 + ret = video_register_device(cfg->v,0,PREVIEW_MINOR);
1528 + if (ret) {
1529 + printk(KERN_ERR"Couldn't register preview driver.\n");
1530 + goto bail3; /* hm seems it us unregistered the once */
1531 }
1532
1533 print_version();
1534 + return 0;
1535 +
1536 +bail3:
1537 + video_unregister_device(cfg->v);
1538 +bail2:
1539 + iounmap(camregs);
1540 + camregs = NULL;
1541 +bail1:
1542 return ret;
1543 }
1544
1545 @@ -536,7 +564,9 @@ static void unconfig_device(camif_cfg_t *cfg)
1546 {
1547 video_unregister_device(cfg->v);
1548 camif_hw_close(cfg);
1549 + iounmap(camregs);
1550 //memset(cfg, 0, sizeof(camif_cfg_t));
1551 + camregs = NULL;
1552 }
1553
1554 static void camif_m_out(void) /* module out */
1555 @@ -547,20 +577,22 @@ static void camif_m_out(void) /* module out */
1556 unconfig_device(cfg);
1557 cfg = get_camif(PREVIEW_MINOR);
1558 unconfig_device(cfg);
1559 +
1560 return;
1561 }
1562
1563 void camif_register_decoder(struct i2c_client *ptr)
1564 {
1565 camif_cfg_t *cfg;
1566 + void * data = i2c_get_clientdata(ptr);
1567
1568 cfg =get_camif(CODEC_MINOR);
1569 - cfg->gc = (camif_gc_t *)(ptr->data);
1570 + cfg->gc = (camif_gc_t *)(data);
1571
1572 cfg =get_camif(PREVIEW_MINOR);
1573 - cfg->gc = (camif_gc_t *)(ptr->data);
1574 + cfg->gc = (camif_gc_t *)(data);
1575
1576 - sema_init(&cfg->gc->lock,1); /* global lock for both Codec and Preview */
1577 + sema_init(&cfg->gc->lock, 1); /* global lock for both Codec and Preview */
1578 cfg->gc->status |= PNOTWORKING; /* Default Value */
1579 camif_hw_open(cfg->gc);
1580 }
1581 @@ -568,8 +600,9 @@ void camif_register_decoder(struct i2c_client *ptr)
1582 void camif_unregister_decoder(struct i2c_client *ptr)
1583 {
1584 camif_gc_t *gc;
1585 + void * data = i2c_get_clientdata(ptr);
1586
1587 - gc = (camif_gc_t *)(ptr->data);
1588 + gc = (camif_gc_t *)(data);
1589 gc->init_sensor = 0; /* need to modify */
1590 }
1591
1592 diff --git a/arch/arm/mach-s3c2440/camera/videodev.c b/arch/arm/mach-s3c2440/camera/videodev.c
1593 index 0b3498f..6f862e4 100644
1594 --- a/arch/arm/mach-s3c2440/camera/videodev.c
1595 +++ b/arch/arm/mach-s3c2440/camera/videodev.c
1596 @@ -22,7 +22,7 @@
1597 #include <linux/init.h>
1598 #include <linux/kmod.h>
1599 #include <linux/slab.h>
1600 -#include <linux/devfs_fs_kernel.h>
1601 +/* #include <linux/devfs_fs_kernel.h> */
1602 #include <linux/miscdevice.h>
1603 #include <asm/uaccess.h>
1604 #include <asm/system.h>
1605 @@ -30,8 +30,9 @@
1606
1607
1608
1609 +#define CONFIG_VIDEO_V4L1_COMPAT
1610 +#include <linux/videodev.h>
1611 #include "camif.h"
1612 -#include "videodev.h"
1613 #include "miscdevice.h"
1614
1615
1616 @@ -42,18 +43,7 @@ const char *fimc_version = "$Id: videodev.c,v 1.1.1.1 2004/04/27 03:52:50 swlee
1617 #define VIDEO_NAME "video4linux"
1618
1619
1620 -static inline unsigned iminor(struct inode *inode)
1621 -{
1622 - return MINOR(inode->i_rdev);
1623 -}
1624 -
1625 -static inline unsigned imajor(struct inode *inode)
1626 -{
1627 - return MAJOR(inode->i_rdev);
1628 -}
1629 -
1630 -
1631 -#define VIDEO_NUM_DEVICES 2
1632 +#define VIDEO_NUM_DEVICES 2
1633 static struct video_device *video_device[VIDEO_NUM_DEVICES];
1634
1635 static inline struct video_device * get_vd(int nr)
1636 @@ -104,7 +94,7 @@ static int video_open(struct inode *inode, struct file *file)
1637 int minor = MINOR(inode->i_rdev);
1638 int err = 0;
1639 struct video_device *vfl;
1640 - struct file_operations *old_fops;
1641 + struct file_operations const *old_fops;
1642
1643 down(&videodev_lock);
1644
1645 @@ -131,13 +121,13 @@ extern int video_exclusive_open(struct inode *inode, struct file *file)
1646 struct video_device *vfl = get_vd(MINOR(inode->i_rdev));
1647 int retval = 0;
1648
1649 - down(&vfl->lock);
1650 + mutex_lock(&vfl->lock);
1651 if (vfl->users) {
1652 retval = -EBUSY;
1653 } else {
1654 vfl->users++;
1655 }
1656 - up(&vfl->lock);
1657 + mutex_unlock(&vfl->lock);
1658 return retval;
1659 }
1660
1661 diff --git a/arch/arm/mach-s3c2440/camera/videodev.h b/arch/arm/mach-s3c2440/camera/videodev.h
1662 index f12db43..1c2e35a 100644
1663 --- a/arch/arm/mach-s3c2440/camera/videodev.h
1664 +++ b/arch/arm/mach-s3c2440/camera/videodev.h
1665 @@ -1,11 +1,11 @@
1666 -#ifndef __LINUX_S3C_VIDEODEV_H
1667 -#define __LINUX_S3C_VIDEODEV_H
1668 +//#ifndef __LINUX_S3C_VIDEODEV_H
1669 +//#define __LINUX_S3C_VIDEODEV_H
1670
1671 #include <linux/types.h>
1672 #include <linux/version.h>
1673 -#include "videodev2.h"
1674 -
1675 +#include <media/v4l2-dev.h>
1676
1677 +#if 0
1678 struct video_device
1679 {
1680 /* device info */
1681 @@ -96,12 +96,10 @@ extern int video_usercopy(struct inode *inode, struct file *file,
1682
1683
1684
1685 -#define VID_HARDWARE_SAMSUNG_FIMC 255
1686 -
1687 -
1688 -
1689 -#endif
1690 +#endif
1691 +//#endif
1692
1693 +#define VID_HARDWARE_SAMSUNG_FIMC 255
1694
1695 /*
1696 * Local variables:
1697 --
1698 1.5.6.5
1699
Personal OpenWRT clone
This page took 0.163851 seconds and 5 git commands to generate.