2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
21 #include <asm/irq_cpu.h>
22 #include <asm/mipsregs.h>
24 #include <asm/mach-ar71xx/ar71xx.h>
26 static void ar71xx_gpio_irq_dispatch(void)
28 void __iomem
*base
= ar71xx_gpio_base
;
31 pending
= __raw_readl(base
+ GPIO_REG_INT_PENDING
) &
32 __raw_readl(base
+ GPIO_REG_INT_ENABLE
);
35 do_IRQ(AR71XX_GPIO_IRQ_BASE
+ fls(pending
) - 1);
40 static void ar71xx_gpio_irq_unmask(unsigned int irq
)
42 void __iomem
*base
= ar71xx_gpio_base
;
45 irq
-= AR71XX_GPIO_IRQ_BASE
;
47 t
= __raw_readl(base
+ GPIO_REG_INT_ENABLE
);
48 __raw_writel(t
| (1 << irq
), base
+ GPIO_REG_INT_ENABLE
);
51 (void) __raw_readl(base
+ GPIO_REG_INT_ENABLE
);
54 static void ar71xx_gpio_irq_mask(unsigned int irq
)
56 void __iomem
*base
= ar71xx_gpio_base
;
59 irq
-= AR71XX_GPIO_IRQ_BASE
;
61 t
= __raw_readl(base
+ GPIO_REG_INT_ENABLE
);
62 __raw_writel(t
& ~(1 << irq
), base
+ GPIO_REG_INT_ENABLE
);
65 (void) __raw_readl(base
+ GPIO_REG_INT_ENABLE
);
69 static int ar71xx_gpio_irq_set_type(unsigned int irq
, unsigned int flow_type
)
75 #define ar71xx_gpio_irq_set_type NULL
78 static struct irq_chip ar71xx_gpio_irq_chip
= {
79 .name
= "AR71XX GPIO",
80 .unmask
= ar71xx_gpio_irq_unmask
,
81 .mask
= ar71xx_gpio_irq_mask
,
82 .mask_ack
= ar71xx_gpio_irq_mask
,
83 .set_type
= ar71xx_gpio_irq_set_type
,
86 static struct irqaction ar71xx_gpio_irqaction
= {
88 .name
= "cascade [AR71XX GPIO]",
91 #define GPIO_INT_ALL 0xffff
93 static void __init
ar71xx_gpio_irq_init(void)
95 void __iomem
*base
= ar71xx_gpio_base
;
98 __raw_writel(0, base
+ GPIO_REG_INT_ENABLE
);
99 __raw_writel(0, base
+ GPIO_REG_INT_PENDING
);
101 /* setup type of all GPIO interrupts to level sensitive */
102 __raw_writel(GPIO_INT_ALL
, base
+ GPIO_REG_INT_TYPE
);
104 /* setup polarity of all GPIO interrupts to active high */
105 __raw_writel(GPIO_INT_ALL
, base
+ GPIO_REG_INT_POLARITY
);
107 for (i
= AR71XX_GPIO_IRQ_BASE
;
108 i
< AR71XX_GPIO_IRQ_BASE
+ AR71XX_GPIO_IRQ_COUNT
; i
++)
109 set_irq_chip_and_handler(i
, &ar71xx_gpio_irq_chip
,
112 setup_irq(AR71XX_MISC_IRQ_GPIO
, &ar71xx_gpio_irqaction
);
115 static void ar71xx_misc_irq_dispatch(void)
119 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
)
120 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
122 if (pending
& MISC_INT_UART
)
123 do_IRQ(AR71XX_MISC_IRQ_UART
);
125 else if (pending
& MISC_INT_DMA
)
126 do_IRQ(AR71XX_MISC_IRQ_DMA
);
128 else if (pending
& MISC_INT_PERFC
)
129 do_IRQ(AR71XX_MISC_IRQ_PERFC
);
131 else if (pending
& MISC_INT_TIMER
)
132 do_IRQ(AR71XX_MISC_IRQ_TIMER
);
134 else if (pending
& MISC_INT_OHCI
)
135 do_IRQ(AR71XX_MISC_IRQ_OHCI
);
137 else if (pending
& MISC_INT_ERROR
)
138 do_IRQ(AR71XX_MISC_IRQ_ERROR
);
140 else if (pending
& MISC_INT_GPIO
)
141 ar71xx_gpio_irq_dispatch();
143 else if (pending
& MISC_INT_WDOG
)
144 do_IRQ(AR71XX_MISC_IRQ_WDOG
);
146 else if (pending
& MISC_INT_TIMER2
)
147 do_IRQ(AR71XX_MISC_IRQ_TIMER2
);
149 else if (pending
& MISC_INT_TIMER3
)
150 do_IRQ(AR71XX_MISC_IRQ_TIMER3
);
152 else if (pending
& MISC_INT_TIMER4
)
153 do_IRQ(AR71XX_MISC_IRQ_TIMER4
);
155 else if (pending
& MISC_INT_DDR_PERF
)
156 do_IRQ(AR71XX_MISC_IRQ_DDR_PERF
);
158 else if (pending
& MISC_INT_ENET_LINK
)
159 do_IRQ(AR71XX_MISC_IRQ_ENET_LINK
);
162 spurious_interrupt();
165 static void ar71xx_misc_irq_unmask(unsigned int irq
)
167 void __iomem
*base
= ar71xx_reset_base
;
170 irq
-= AR71XX_MISC_IRQ_BASE
;
172 t
= __raw_readl(base
+ AR71XX_RESET_REG_MISC_INT_ENABLE
);
173 __raw_writel(t
| (1 << irq
), base
+ AR71XX_RESET_REG_MISC_INT_ENABLE
);
176 (void) __raw_readl(base
+ AR71XX_RESET_REG_MISC_INT_ENABLE
);
179 static void ar71xx_misc_irq_mask(unsigned int irq
)
181 void __iomem
*base
= ar71xx_reset_base
;
184 irq
-= AR71XX_MISC_IRQ_BASE
;
186 t
= __raw_readl(base
+ AR71XX_RESET_REG_MISC_INT_ENABLE
);
187 __raw_writel(t
& ~(1 << irq
), base
+ AR71XX_RESET_REG_MISC_INT_ENABLE
);
190 (void) __raw_readl(base
+ AR71XX_RESET_REG_MISC_INT_ENABLE
);
193 static void ar724x_misc_irq_ack(unsigned int irq
)
195 void __iomem
*base
= ar71xx_reset_base
;
198 irq
-= AR71XX_MISC_IRQ_BASE
;
200 t
= __raw_readl(base
+ AR71XX_RESET_REG_MISC_INT_STATUS
);
201 __raw_writel(t
& ~(1 << irq
), base
+ AR71XX_RESET_REG_MISC_INT_STATUS
);
204 (void) __raw_readl(base
+ AR71XX_RESET_REG_MISC_INT_STATUS
);
207 static struct irq_chip ar71xx_misc_irq_chip
= {
208 .name
= "AR71XX MISC",
209 .unmask
= ar71xx_misc_irq_unmask
,
210 .mask
= ar71xx_misc_irq_mask
,
213 static struct irqaction ar71xx_misc_irqaction
= {
214 .handler
= no_action
,
215 .name
= "cascade [AR71XX MISC]",
218 static void __init
ar71xx_misc_irq_init(void)
220 void __iomem
*base
= ar71xx_reset_base
;
223 __raw_writel(0, base
+ AR71XX_RESET_REG_MISC_INT_ENABLE
);
224 __raw_writel(0, base
+ AR71XX_RESET_REG_MISC_INT_STATUS
);
226 switch (ar71xx_soc
) {
227 case AR71XX_SOC_AR7240
:
228 case AR71XX_SOC_AR7241
:
229 case AR71XX_SOC_AR7242
:
230 case AR71XX_SOC_AR9330
:
231 case AR71XX_SOC_AR9331
:
232 case AR71XX_SOC_AR9341
:
233 case AR71XX_SOC_AR9342
:
234 case AR71XX_SOC_AR9344
:
235 ar71xx_misc_irq_chip
.ack
= ar724x_misc_irq_ack
;
238 ar71xx_misc_irq_chip
.mask_ack
= ar71xx_misc_irq_mask
;
242 for (i
= AR71XX_MISC_IRQ_BASE
;
243 i
< AR71XX_MISC_IRQ_BASE
+ AR71XX_MISC_IRQ_COUNT
; i
++)
244 set_irq_chip_and_handler(i
, &ar71xx_misc_irq_chip
,
247 setup_irq(AR71XX_CPU_IRQ_MISC
, &ar71xx_misc_irqaction
);
251 * The IP2 line is tied to a PCI/WMAC device. Drivers for these
252 * devices typically allocate coherent DMA memory for the descriptor
253 * ring, however the DMA controller may still have some unsynchronized
255 * Issue a flush in the handlers to ensure that the driver sees
258 static void ar71xx_ip2_handler(void)
260 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_PCI
);
261 do_IRQ(AR71XX_CPU_IRQ_IP2
);
264 static void ar724x_ip2_handler(void)
266 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_PCIE
);
267 do_IRQ(AR71XX_CPU_IRQ_IP2
);
270 static void ar913x_ip2_handler(void)
272 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_WMAC
);
273 do_IRQ(AR71XX_CPU_IRQ_IP2
);
276 static void ar933x_ip2_handler(void)
278 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC
);
279 do_IRQ(AR71XX_CPU_IRQ_IP2
);
282 static void ar934x_ip2_handler(void)
284 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_PCIE
);
285 do_IRQ(AR71XX_CPU_IRQ_IP2
);
288 static void (*ip2_handler
)(void);
290 asmlinkage
void plat_irq_dispatch(void)
292 unsigned long pending
;
294 pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
296 if (pending
& STATUSF_IP7
)
297 do_IRQ(AR71XX_CPU_IRQ_TIMER
);
299 else if (pending
& STATUSF_IP2
)
302 else if (pending
& STATUSF_IP4
)
303 do_IRQ(AR71XX_CPU_IRQ_GE0
);
305 else if (pending
& STATUSF_IP5
)
306 do_IRQ(AR71XX_CPU_IRQ_GE1
);
308 else if (pending
& STATUSF_IP3
)
309 do_IRQ(AR71XX_CPU_IRQ_USB
);
311 else if (pending
& STATUSF_IP6
)
312 ar71xx_misc_irq_dispatch();
314 spurious_interrupt();
317 void __init
arch_init_irq(void)
319 switch (ar71xx_soc
) {
320 case AR71XX_SOC_AR7130
:
321 case AR71XX_SOC_AR7141
:
322 case AR71XX_SOC_AR7161
:
323 ip2_handler
= ar71xx_ip2_handler
;
326 case AR71XX_SOC_AR7240
:
327 case AR71XX_SOC_AR7241
:
328 case AR71XX_SOC_AR7242
:
329 ip2_handler
= ar724x_ip2_handler
;
332 case AR71XX_SOC_AR9130
:
333 case AR71XX_SOC_AR9132
:
334 ip2_handler
= ar913x_ip2_handler
;
337 case AR71XX_SOC_AR9330
:
338 case AR71XX_SOC_AR9331
:
339 ip2_handler
= ar933x_ip2_handler
;
342 case AR71XX_SOC_AR9341
:
343 case AR71XX_SOC_AR9342
:
344 case AR71XX_SOC_AR9344
:
345 ip2_handler
= ar934x_ip2_handler
;
354 ar71xx_misc_irq_init();
356 cp0_perfcount_irq
= AR71XX_MISC_IRQ_PERFC
;
358 ar71xx_gpio_irq_init();