target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/mvOs.h

   1 /*******************************************************************************
   2 Copyright (C) Marvell International Ltd. and its affiliates
   3
   4 This software file (the "File") is owned and distributed by Marvell
   5 International Ltd. and/or its affiliates ("Marvell") under the following
   6 alternative licensing terms.  Once you have made an election to distribute the
   7 File under one of the following license alternatives, please (i) delete this
   8 introductory statement regarding license alternatives, (ii) delete the two
   9 license alternatives that you have not elected to use and (iii) preserve the
  10 Marvell copyright notice above.
  11
  12
  13 ********************************************************************************
  14 Marvell GPL License Option
  15
  16 If you received this File from Marvell, you may opt to use, redistribute and/or
  17 modify this File in accordance with the terms and conditions of the General
  18 Public License Version 2, June 1991 (the "GPL License"), a copy of which is
  19 available along with the File in the license.txt file or by writing to the Free
  20 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
  21 on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
  22
  23 THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
  24 WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
  25 DISCLAIMED.  The GPL License provides additional details about this warranty
  26 disclaimer.
  27 *******************************************************************************/
  28 #ifndef _MV_OS_LNX_H_
  29 #define _MV_OS_LNX_H_
  30
  31
  32 #ifdef __KERNEL__
  33 /* for kernel space */
  34 #include <linux/autoconf.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/stddef.h>
  37 #include <linux/kernel.h>
  38 #include <linux/init.h>
  39 #include <linux/errno.h>
  40 #include <linux/reboot.h>
  41 #include <linux/pci.h>
  42 #include <linux/kdev_t.h>
  43 #include <linux/major.h>
  44 #include <linux/blkdev.h>
  45 #include <linux/console.h>
  46 #include <linux/delay.h>
  47 #include <linux/seq_file.h>
  48 #include <linux/string.h>
  49 #include <linux/slab.h>
  50 #include <linux/kernel.h>
  51 #include <linux/string.h>
  52 #include <linux/slab.h>
  53 #include <linux/mm.h>
  54
  55 #include <asm/system.h>
  56 #include <asm/pgtable.h>
  57 #include <asm/page.h>
  58 #include <asm/hardirq.h>
  59 #include <asm/dma.h>
  60 #include <asm/io.h>
  61
  62 #include <linux/random.h>
  63
  64 #include "dbg-trace.h"
  65
  66 extern void mv_early_printk(char *fmt,...);
  67
  68 #define MV_ASM              __asm__ __volatile__
  69 #define INLINE              inline
  70 #define MV_TRC_REC              TRC_REC
  71 #define mvOsPrintf          printk
  72 #define mvOsEarlyPrintf     mv_early_printk
  73 #define mvOsOutput          printk
  74 #define mvOsSPrintf         sprintf
  75 #define mvOsMalloc(_size_)  kmalloc(_size_,GFP_ATOMIC)
  76 #define mvOsFree            kfree
  77 #define mvOsMemcpy          memcpy
  78 #define mvOsSleep(_mils_)   mdelay(_mils_)
  79 #define mvOsTaskLock()
  80 #define mvOsTaskUnlock()
  81 #define strtol              simple_strtoul
  82 #define mvOsDelay(x)        mdelay(x)
  83 #define mvOsUDelay(x)       udelay(x)
  84 #define mvCopyFromOs        copy_from_user
  85 #define mvCopyToOs          copy_to_user
  86
  87
  88 #include "mvTypes.h"
  89 #include "mvCommon.h"
  90
  91 #ifdef MV_NDEBUG
  92 #define mvOsAssert(cond)
  93 #else
  94 #define mvOsAssert(cond) { do { if(!(cond)) { BUG(); } }while(0); }
  95 #endif /* MV_NDEBUG */
  96
  97 #else /* __KERNEL__ */
  98
  99 /* for user space applications */
 100 #include <stdlib.h>
 101 #include <stdio.h>
 102 #include <assert.h>
 103 #include <string.h>
 104
 105 #define INLINE inline
 106 #define mvOsPrintf printf
 107 #define mvOsOutput printf
 108 #define mvOsMalloc(_size_) malloc(_size_)
 109 #define mvOsFree free
 110 #define mvOsAssert(cond) assert(cond)
 111
 112 #endif /* __KERNEL__ */
 113 #define mvOsIoVirtToPhy(pDev, pVirtAddr)                            \
 114     pci_map_single( (pDev), (pVirtAddr), 0, PCI_DMA_BIDIRECTIONAL )
 115
 116 #define mvOsCacheClear(pDev, p, size )                              \
 117     pci_map_single( (pDev), (p), (size), PCI_DMA_BIDIRECTIONAL)
 118
 119 #define mvOsCacheFlush(pDev, p, size )                              \
 120     pci_map_single( (pDev), (p), (size), PCI_DMA_TODEVICE)
 121
 122 #define mvOsCacheInvalidate(pDev, p, size)                          \
 123     pci_map_single( (pDev), (p), (size), PCI_DMA_FROMDEVICE )
 124
 125 #define mvOsCacheUnmap(pDev, phys, size)                          \
 126     pci_unmap_single( (pDev), (dma_addr_t)(phys), (size), PCI_DMA_FROMDEVICE )
 127
 128
 129 #define CPU_PHY_MEM(x)              (MV_U32)x
 130 #define CPU_MEMIO_CACHED_ADDR(x)    (void*)x
 131 #define CPU_MEMIO_UNCACHED_ADDR(x)  (void*)x
 132
 133
 134 /* CPU architecture dependent 32, 16, 8 bit read/write IO addresses */
 135 #define MV_MEMIO32_WRITE(addr, data)    \
 136     ((*((volatile unsigned int*)(addr))) = ((unsigned int)(data)))
 137
 138 #define MV_MEMIO32_READ(addr)           \
 139     ((*((volatile unsigned int*)(addr))))
 140
 141 #define MV_MEMIO16_WRITE(addr, data)    \
 142     ((*((volatile unsigned short*)(addr))) = ((unsigned short)(data)))
 143
 144 #define MV_MEMIO16_READ(addr)           \
 145     ((*((volatile unsigned short*)(addr))))
 146
 147 #define MV_MEMIO8_WRITE(addr, data)     \
 148     ((*((volatile unsigned char*)(addr))) = ((unsigned char)(data)))
 149
 150 #define MV_MEMIO8_READ(addr)            \
 151     ((*((volatile unsigned char*)(addr))))
 152
 153
 154 /* No Fast Swap implementation (in assembler) for ARM */
 155 #define MV_32BIT_LE_FAST(val)            MV_32BIT_LE(val)
 156 #define MV_16BIT_LE_FAST(val)            MV_16BIT_LE(val)
 157 #define MV_32BIT_BE_FAST(val)            MV_32BIT_BE(val)
 158 #define MV_16BIT_BE_FAST(val)            MV_16BIT_BE(val)
 159
 160 /* 32 and 16 bit read/write in big/little endian mode */
 161
 162 /* 16bit write in little endian mode */
 163 #define MV_MEMIO_LE16_WRITE(addr, data) \
 164         MV_MEMIO16_WRITE(addr, MV_16BIT_LE_FAST(data))
 165
 166 /* 16bit read in little endian mode */
 167 static __inline MV_U16 MV_MEMIO_LE16_READ(MV_U32 addr)
 168 {
 169     MV_U16 data;
 170
 171     data= (MV_U16)MV_MEMIO16_READ(addr);
 172
 173     return (MV_U16)MV_16BIT_LE_FAST(data);
 174 }
 175
 176 /* 32bit write in little endian mode */
 177 #define MV_MEMIO_LE32_WRITE(addr, data) \
 178         MV_MEMIO32_WRITE(addr, MV_32BIT_LE_FAST(data))
 179
 180 /* 32bit read in little endian mode */
 181 static __inline MV_U32 MV_MEMIO_LE32_READ(MV_U32 addr)
 182 {
 183     MV_U32 data;
 184
 185     data= (MV_U32)MV_MEMIO32_READ(addr);
 186
 187     return (MV_U32)MV_32BIT_LE_FAST(data);
 188 }
 189
 190 static __inline void mvOsBCopy(char* srcAddr, char* dstAddr, int byteCount)
 191 {
 192     while(byteCount != 0)
 193     {
 194         *dstAddr = *srcAddr;
 195         dstAddr++;
 196         srcAddr++;
 197         byteCount--;
 198     }
 199 }
 200
 201 static INLINE MV_U64 mvOsDivMod64(MV_U64 divided, MV_U64 divisor, MV_U64* modulu)
 202 {
 203     MV_U64  division = 0;
 204
 205     if(divisor == 1)
 206         return divided;
 207
 208     while(divided >= divisor)
 209     {
 210             division++;
 211             divided -= divisor;
 212     }
 213     if (modulu != NULL)
 214         *modulu = divided;
 215
 216     return division;
 217 }
 218
 219 #if defined(MV_BRIDGE_SYNC_REORDER)
 220 extern MV_U32 *mvUncachedParam;
 221
 222 static __inline void mvOsBridgeReorderWA(void)
 223 {
 224         volatile MV_U32 val = 0;
 225
 226         val = mvUncachedParam[0];
 227 }
 228 #endif
 229
 230
 231 /* Flash APIs */
 232 #define MV_FL_8_READ            MV_MEMIO8_READ
 233 #define MV_FL_16_READ           MV_MEMIO_LE16_READ
 234 #define MV_FL_32_READ           MV_MEMIO_LE32_READ
 235 #define MV_FL_8_DATA_READ       MV_MEMIO8_READ
 236 #define MV_FL_16_DATA_READ      MV_MEMIO16_READ
 237 #define MV_FL_32_DATA_READ      MV_MEMIO32_READ
 238 #define MV_FL_8_WRITE           MV_MEMIO8_WRITE
 239 #define MV_FL_16_WRITE          MV_MEMIO_LE16_WRITE
 240 #define MV_FL_32_WRITE          MV_MEMIO_LE32_WRITE
 241 #define MV_FL_8_DATA_WRITE      MV_MEMIO8_WRITE
 242 #define MV_FL_16_DATA_WRITE     MV_MEMIO16_WRITE
 243 #define MV_FL_32_DATA_WRITE     MV_MEMIO32_WRITE
 244
 245
 246 /* CPU cache information */
 247 #define CPU_I_CACHE_LINE_SIZE   32    /* 2do: replace 32 with linux core macro */
 248 #define CPU_D_CACHE_LINE_SIZE   32    /* 2do: replace 32 with linux core macro */
 249
 250 #ifdef CONFIG_L2_CACHE_ENABLE
 251 /* Data cache flush one line */
 252 #define mvOsCacheLineFlushInv(handle, addr)                     \
 253 {                                                               \
 254   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\
 255   __asm__ __volatile__ ("mcr p15, 1, %0, c15, c10, 1" : : "r" (addr));\
 256   __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4");          \
 257 }
 258
 259 #else
 260
 261 /* Data cache flush one line */
 262 #define mvOsCacheLineFlushInv(handle, addr)                     \
 263 {                                                               \
 264   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c14, 1" : : "r" (addr));\
 265   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \
 266 }
 267 #endif
 268
 269 #ifdef CONFIG_L2_CACHE_ENABLE
 270 #define mvOsCacheLineInv(handle,addr)                           \
 271 {                                                               \
 272   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \
 273  __asm__ __volatile__ ("mcr p15, 1, %0, c15, c11, 1" : : "r" (addr)); \
 274 }
 275 #else
 276 #define mvOsCacheLineInv(handle,addr)                           \
 277 {                                                               \
 278   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c6, 1" : : "r" (addr)); \
 279 }
 280 #endif
 281
 282 #ifdef CONFIG_L2_CACHE_ENABLE
 283 /* Data cache flush one line */
 284 #define mvOsCacheLineFlush(handle, addr)                     \
 285 {                                                               \
 286   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\
 287   __asm__ __volatile__ ("mcr p15, 1, %0, c15, c9, 1" : : "r" (addr));\
 288   __asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 4");          \
 289 }
 290
 291 #else
 292 /* Data cache flush one line */
 293 #define mvOsCacheLineFlush(handle, addr)                     \
 294 {                                                               \
 295   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 1" : : "r" (addr));\
 296   __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (addr)); \
 297 }
 298 #endif
 299
 300 static __inline void mvOsPrefetch(const void *ptr)
 301 {
 302 #ifdef CONFIG_USE_DSP
 303         __asm__ __volatile__(
 304                 "pld\t%0"
 305                 :
 306                 : "o" (*(char *)ptr)
 307                 : "cc");
 308 #else
 309         return;
 310 #endif
 311 }
 312
 313
 314 /* Flush CPU pipe */
 315 #define CPU_PIPE_FLUSH
 316
 317
 318
 319
 320
 321 /* register manipulations  */
 322
 323 /******************************************************************************
 324 * This debug function enable the write of each register that u-boot access to
 325 * to an array in the DRAM, the function record only MV_REG_WRITE access.
 326 * The function could not be operate when booting from flash.
 327 * In order to print the array we use the printreg command.
 328 ******************************************************************************/
 329 /* #define REG_DEBUG */
 330 #if defined(REG_DEBUG)
 331 extern int reg_arry[2048][2];
 332 extern int reg_arry_index;
 333 #endif
 334
 335 /* Marvell controller register read/write macros */
 336 #define MV_REG_VALUE(offset)          \
 337                 (MV_MEMIO32_READ((INTER_REGS_BASE | (offset))))
 338
 339 #define MV_REG_READ(offset)             \
 340         (MV_MEMIO_LE32_READ(INTER_REGS_BASE | (offset)))
 341
 342 #if defined(REG_DEBUG)
 343 #define MV_REG_WRITE(offset, val)    \
 344         MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val)); \
 345         { \
 346                 reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\
 347                 reg_arry[reg_arry_index][1] = (val);\
 348                 reg_arry_index++;\
 349         }
 350 #else
 351 #define MV_REG_WRITE(offset, val)    \
 352         MV_MEMIO_LE32_WRITE((INTER_REGS_BASE | (offset)), (val));
 353 #endif
 354
 355 #define MV_REG_BYTE_READ(offset)        \
 356         (MV_MEMIO8_READ((INTER_REGS_BASE | (offset))))
 357
 358 #if defined(REG_DEBUG)
 359 #define MV_REG_BYTE_WRITE(offset, val)  \
 360         MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val)); \
 361         { \
 362                 reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\
 363                 reg_arry[reg_arry_index][1] = (val);\
 364                 reg_arry_index++;\
 365         }
 366 #else
 367 #define MV_REG_BYTE_WRITE(offset, val)  \
 368         MV_MEMIO8_WRITE((INTER_REGS_BASE | (offset)), (val))
 369 #endif
 370
 371 #if defined(REG_DEBUG)
 372 #define MV_REG_BIT_SET(offset, bitMask)                 \
 373         (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
 374          (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \
 375           MV_32BIT_LE_FAST(bitMask)))); \
 376         { \
 377                 reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\
 378                 reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\
 379                 reg_arry_index++;\
 380         }
 381 #else
 382 #define MV_REG_BIT_SET(offset, bitMask)                 \
 383         (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
 384          (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) | \
 385           MV_32BIT_LE_FAST(bitMask))))
 386 #endif
 387
 388 #if defined(REG_DEBUG)
 389 #define MV_REG_BIT_RESET(offset,bitMask)                \
 390         (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
 391          (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \
 392           MV_32BIT_LE_FAST(~bitMask)))); \
 393         { \
 394                 reg_arry[reg_arry_index][0] = (INTER_REGS_BASE | (offset));\
 395                 reg_arry[reg_arry_index][1] = (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)));\
 396                 reg_arry_index++;\
 397         }
 398 #else
 399 #define MV_REG_BIT_RESET(offset,bitMask)                \
 400         (MV_MEMIO32_WRITE((INTER_REGS_BASE | (offset)), \
 401          (MV_MEMIO32_READ(INTER_REGS_BASE | (offset)) & \
 402           MV_32BIT_LE_FAST(~bitMask))))
 403 #endif
 404
 405
 406
 407 /* ARM architecture APIs */
 408 MV_U32  mvOsCpuRevGet (MV_VOID);
 409 MV_U32  mvOsCpuPartGet (MV_VOID);
 410 MV_U32  mvOsCpuArchGet (MV_VOID);
 411 MV_U32  mvOsCpuVarGet (MV_VOID);
 412 MV_U32  mvOsCpuAsciiGet (MV_VOID);
 413
 414 /*  Other APIs  */
 415 void* mvOsIoCachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle);
 416 void* mvOsIoUncachedMalloc( void* osHandle, MV_U32 size, MV_ULONG* pPhyAddr, MV_U32 *memHandle );
 417 void mvOsIoUncachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle );
 418 void mvOsIoCachedFree( void* osHandle, MV_U32 size, MV_ULONG phyAddr, void* pVirtAddr, MV_U32 memHandle );
 419 int mvOsRand(void);
 420
 421 #endif /* _MV_OS_LNX_H_ */
 422
 423