2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
60 #define AR7240_REG_ATU 0x50
61 #define AR7240_ATU_FLUSH_ALL 0x1
63 #define AR7240_REG_AT_CTRL 0x5c
64 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
65 #define AR7240_AT_CTRL_AGE_EN BIT(17)
66 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
67 #define AR7240_AT_CTRL_ARP_EN BIT(20)
69 #define AR7240_REG_TAG_PRIORITY 0x70
71 #define AR7240_REG_SERVICE_TAG 0x74
72 #define AR7240_SERVICE_TAG_M BITM(16)
74 #define AR7240_REG_CPU_PORT 0x78
75 #define AR7240_MIRROR_PORT_S 4
76 #define AR7240_CPU_PORT_EN BIT(8)
78 #define AR7240_REG_MIB_FUNCTION0 0x80
79 #define AR7240_MIB_TIMER_M BITM(16)
80 #define AR7240_MIB_AT_HALF_EN BIT(16)
81 #define AR7240_MIB_BUSY BIT(17)
82 #define AR7240_MIB_FUNC_S 24
83 #define AR7240_MIB_FUNC_NO_OP 0x0
84 #define AR7240_MIB_FUNC_FLUSH 0x1
85 #define AR7240_MIB_FUNC_CAPTURE 0x3
87 #define AR7240_REG_MDIO_CTRL 0x98
88 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
89 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
90 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
91 #define AR7240_MDIO_CTRL_CMD_WRITE 0
92 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
93 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
94 #define AR7240_MDIO_CTRL_BUSY BIT(31)
96 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
98 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
99 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
100 #define AR7240_PORT_STATUS_SPEED_10 0
101 #define AR7240_PORT_STATUS_SPEED_100 1
102 #define AR7240_PORT_STATUS_SPEED_1000 2
103 #define AR7240_PORT_STATUS_TXMAC BIT(2)
104 #define AR7240_PORT_STATUS_RXMAC BIT(3)
105 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
106 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
107 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
108 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
109 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
110 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
112 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
113 #define AR7240_PORT_CTRL_STATE_M BITM(3)
114 #define AR7240_PORT_CTRL_STATE_DISABLED 0
115 #define AR7240_PORT_CTRL_STATE_BLOCK 1
116 #define AR7240_PORT_CTRL_STATE_LISTEN 2
117 #define AR7240_PORT_CTRL_STATE_LEARN 3
118 #define AR7240_PORT_CTRL_STATE_FORWARD 4
119 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
120 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
121 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
122 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
123 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
124 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
125 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
126 #define AR7240_PORT_CTRL_HEADER BIT(11)
127 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
128 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
129 #define AR7240_PORT_CTRL_LEARN BIT(14)
130 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
131 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
132 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
134 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
136 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
137 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
138 #define AR7240_PORT_VLAN_MODE_S 30
139 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
140 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
141 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
142 #define AR7240_PORT_VLAN_MODE_SECURE 3
145 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
147 #define AR7240_STATS_RXBROAD 0x00
148 #define AR7240_STATS_RXPAUSE 0x04
149 #define AR7240_STATS_RXMULTI 0x08
150 #define AR7240_STATS_RXFCSERR 0x0c
151 #define AR7240_STATS_RXALIGNERR 0x10
152 #define AR7240_STATS_RXRUNT 0x14
153 #define AR7240_STATS_RXFRAGMENT 0x18
154 #define AR7240_STATS_RX64BYTE 0x1c
155 #define AR7240_STATS_RX128BYTE 0x20
156 #define AR7240_STATS_RX256BYTE 0x24
157 #define AR7240_STATS_RX512BYTE 0x28
158 #define AR7240_STATS_RX1024BYTE 0x2c
159 #define AR7240_STATS_RX1518BYTE 0x30
160 #define AR7240_STATS_RXMAXBYTE 0x34
161 #define AR7240_STATS_RXTOOLONG 0x38
162 #define AR7240_STATS_RXGOODBYTE 0x3c
163 #define AR7240_STATS_RXBADBYTE 0x44
164 #define AR7240_STATS_RXOVERFLOW 0x4c
165 #define AR7240_STATS_FILTERED 0x50
166 #define AR7240_STATS_TXBROAD 0x54
167 #define AR7240_STATS_TXPAUSE 0x58
168 #define AR7240_STATS_TXMULTI 0x5c
169 #define AR7240_STATS_TXUNDERRUN 0x60
170 #define AR7240_STATS_TX64BYTE 0x64
171 #define AR7240_STATS_TX128BYTE 0x68
172 #define AR7240_STATS_TX256BYTE 0x6c
173 #define AR7240_STATS_TX512BYTE 0x70
174 #define AR7240_STATS_TX1024BYTE 0x74
175 #define AR7240_STATS_TX1518BYTE 0x78
176 #define AR7240_STATS_TXMAXBYTE 0x7c
177 #define AR7240_STATS_TXOVERSIZE 0x80
178 #define AR7240_STATS_TXBYTE 0x84
179 #define AR7240_STATS_TXCOLLISION 0x8c
180 #define AR7240_STATS_TXABORTCOL 0x90
181 #define AR7240_STATS_TXMULTICOL 0x94
182 #define AR7240_STATS_TXSINGLECOL 0x98
183 #define AR7240_STATS_TXEXCDEFER 0x9c
184 #define AR7240_STATS_TXDEFER 0xa0
185 #define AR7240_STATS_TXLATECOL 0xa4
187 #define AR7240_PORT_CPU 0
188 #define AR7240_NUM_PORTS 6
189 #define AR7240_NUM_PHYS 5
191 #define AR7240_PHY_ID1 0x004d
192 #define AR7240_PHY_ID2 0xd041
194 #define AR7240_PORT_MASK(_port) BIT((_port))
195 #define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
196 #define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
198 #define AR7240_MAX_VLANS 16
200 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
203 struct mii_bus
*mii_bus
;
204 struct switch_dev swdev
;
206 u16 vlan_id
[AR7240_MAX_VLANS
];
207 u8 vlan_table
[AR7240_MAX_VLANS
];
209 u16 pvid
[AR7240_NUM_PORTS
];
212 struct ar7240sw_hw_stat
{
213 char string
[ETH_GSTRING_LEN
];
218 static DEFINE_MUTEX(reg_mutex
);
220 static inline void ar7240sw_init(struct ar7240sw
*as
, struct mii_bus
*mii
)
225 static inline u16
mk_phy_addr(u32 reg
)
227 return 0x17 & ((reg
>> 4) | 0x10);
230 static inline u16
mk_phy_reg(u32 reg
)
232 return (reg
<< 1) & 0x1e;
235 static inline u16
mk_high_addr(u32 reg
)
237 return (reg
>> 7) & 0x1ff;
240 static u32
__ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg
)
247 reg
= (reg
& 0xfffffffc) >> 2;
248 phy_addr
= mk_phy_addr(reg
);
249 phy_reg
= mk_phy_reg(reg
);
251 local_irq_save(flags
);
252 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
253 lo
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
);
254 hi
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
+ 1);
255 local_irq_restore(flags
);
257 return (hi
<< 16) | lo
;
260 static void __ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg
, u32 val
)
266 reg
= (reg
& 0xfffffffc) >> 2;
267 phy_addr
= mk_phy_addr(reg
);
268 phy_reg
= mk_phy_reg(reg
);
270 local_irq_save(flags
);
271 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
272 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
+ 1, (val
>> 16));
273 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
, (val
& 0xffff));
274 local_irq_restore(flags
);
277 static u32
ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg_addr
)
281 mutex_lock(®_mutex
);
282 ret
= __ar7240sw_reg_read(mii
, reg_addr
);
283 mutex_unlock(®_mutex
);
288 static void ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg_addr
, u32 reg_val
)
290 mutex_lock(®_mutex
);
291 __ar7240sw_reg_write(mii
, reg_addr
, reg_val
);
292 mutex_unlock(®_mutex
);
295 static u32
ar7240sw_reg_rmw(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
)
299 mutex_lock(®_mutex
);
300 t
= __ar7240sw_reg_read(mii
, reg
);
303 __ar7240sw_reg_write(mii
, reg
, t
);
304 mutex_unlock(®_mutex
);
309 static void ar7240sw_reg_set(struct mii_bus
*mii
, u32 reg
, u32 val
)
313 mutex_lock(®_mutex
);
314 t
= __ar7240sw_reg_read(mii
, reg
);
316 __ar7240sw_reg_write(mii
, reg
, t
);
317 mutex_unlock(®_mutex
);
320 static int __ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
325 for (i
= 0; i
< timeout
; i
++) {
328 t
= __ar7240sw_reg_read(mii
, reg
);
329 if ((t
& mask
) == val
)
338 static int ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
343 mutex_lock(®_mutex
);
344 ret
= __ar7240sw_reg_wait(mii
, reg
, mask
, val
, timeout
);
345 mutex_unlock(®_mutex
);
349 u16
ar7240sw_phy_read(struct mii_bus
*mii
, unsigned phy_addr
,
355 if (phy_addr
>= AR7240_NUM_PHYS
)
358 mutex_lock(®_mutex
);
359 t
= (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
360 (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
361 AR7240_MDIO_CTRL_MASTER_EN
|
362 AR7240_MDIO_CTRL_BUSY
|
363 AR7240_MDIO_CTRL_CMD_READ
;
365 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
366 err
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
367 AR7240_MDIO_CTRL_BUSY
, 0, 5);
369 val
= __ar7240sw_reg_read(mii
, AR7240_REG_MDIO_CTRL
);
370 mutex_unlock(®_mutex
);
372 return val
& AR7240_MDIO_CTRL_DATA_M
;
375 int ar7240sw_phy_write(struct mii_bus
*mii
, unsigned phy_addr
,
376 unsigned reg_addr
, u16 reg_val
)
381 if (phy_addr
>= AR7240_NUM_PHYS
)
384 mutex_lock(®_mutex
);
385 t
= (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
386 (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
387 AR7240_MDIO_CTRL_MASTER_EN
|
388 AR7240_MDIO_CTRL_BUSY
|
389 AR7240_MDIO_CTRL_CMD_WRITE
|
392 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
393 ret
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
394 AR7240_MDIO_CTRL_BUSY
, 0, 5);
395 mutex_unlock(®_mutex
);
400 static int ar7240sw_capture_stats(struct ar7240sw
*as
)
402 struct mii_bus
*mii
= as
->mii_bus
;
405 /* Capture the hardware statistics for all ports */
406 ar7240sw_reg_write(mii
, AR7240_REG_MIB_FUNCTION0
,
407 (AR7240_MIB_FUNC_CAPTURE
<< AR7240_MIB_FUNC_S
));
409 /* Wait for the capturing to complete. */
410 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MIB_FUNCTION0
,
411 AR7240_MIB_BUSY
, 0, 10);
415 static void ar7240sw_disable_port(struct ar7240sw
*as
, unsigned port
)
417 ar7240sw_reg_write(as
->mii_bus
, AR7240_REG_PORT_CTRL(port
),
418 AR7240_PORT_CTRL_STATE_DISABLED
);
421 static int ar7240sw_reset(struct ar7240sw
*as
)
423 struct mii_bus
*mii
= as
->mii_bus
;
427 /* Set all ports to disabled state. */
428 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++)
429 ar7240sw_disable_port(as
, i
);
431 /* Wait for transmit queues to drain. */
434 /* Reset the switch. */
435 ar7240sw_reg_write(mii
, AR7240_REG_MASK_CTRL
,
436 AR7240_MASK_CTRL_SOFT_RESET
);
438 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MASK_CTRL
,
439 AR7240_MASK_CTRL_SOFT_RESET
, 0, 1000);
443 static void ar7240sw_setup(struct ar7240sw
*as
)
445 struct mii_bus
*mii
= as
->mii_bus
;
447 /* Enable CPU port, and disable mirror port */
448 ar7240sw_reg_write(mii
, AR7240_REG_CPU_PORT
,
450 (15 << AR7240_MIRROR_PORT_S
));
452 /* Setup TAG priority mapping */
453 ar7240sw_reg_write(mii
, AR7240_REG_TAG_PRIORITY
, 0xfa50);
455 /* Enable ARP frame acknowledge, aging, MAC replacing */
456 ar7240sw_reg_write(mii
, AR7240_REG_AT_CTRL
,
457 0x2b /* 5 min age time */ |
458 AR7240_AT_CTRL_AGE_EN
|
459 AR7240_AT_CTRL_ARP_EN
|
460 AR7240_AT_CTRL_LEARN_CHANGE
);
462 /* Enable Broadcast frames transmitted to the CPU */
463 ar7240sw_reg_set(mii
, AR7240_REG_FLOOD_MASK
,
464 AR7240_FLOOD_MASK_BROAD_TO_CPU
);
467 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
, AR7240_GLOBAL_CTRL_MTU_M
,
470 /* setup Service TAG */
471 ar7240sw_reg_rmw(mii
, AR7240_REG_SERVICE_TAG
, AR7240_SERVICE_TAG_M
, 0);
474 static void ar7240sw_setup_port(struct ar7240sw
*as
, unsigned port
, u8 portmask
)
476 struct mii_bus
*mii
= as
->mii_bus
;
481 ctrl
= AR7240_PORT_CTRL_STATE_FORWARD
| AR7240_PORT_CTRL_LEARN
|
482 AR7240_PORT_CTRL_SINGLE_VLAN
;
484 if (port
== AR7240_PORT_CPU
) {
485 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
486 AR7240_PORT_STATUS_SPEED_1000
|
487 AR7240_PORT_STATUS_TXFLOW
|
488 AR7240_PORT_STATUS_RXFLOW
|
489 AR7240_PORT_STATUS_TXMAC
|
490 AR7240_PORT_STATUS_RXMAC
|
491 AR7240_PORT_STATUS_DUPLEX
);
493 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
494 AR7240_PORT_STATUS_LINK_AUTO
);
497 /* Set the default VID for this port */
499 vlan
= as
->vlan_id
[as
->pvid
[port
]];
500 vlan
|= AR7240_PORT_VLAN_MODE_SECURE
<<
501 AR7240_PORT_VLAN_MODE_S
;
504 vlan
|= AR7240_PORT_VLAN_MODE_PORT_ONLY
<<
505 AR7240_PORT_VLAN_MODE_S
;
508 if (as
->vlan
&& (as
->vlan_tagged
& BIT(port
))) {
509 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_ADD
<<
510 AR7240_PORT_CTRL_VLAN_MODE_S
;
512 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_STRIP
<<
513 AR7240_PORT_CTRL_VLAN_MODE_S
;
517 if (port
== AR7240_PORT_CPU
)
518 portmask
= AR7240_PORT_MASK_BUT(AR7240_PORT_CPU
);
520 portmask
= AR7240_PORT_MASK(AR7240_PORT_CPU
);
523 /* allow the port to talk to all other ports, but exclude its
524 * own ID to prevent frames from being reflected back to the
525 * port that they came from */
526 dest_ports
= AR7240_PORT_MASK_BUT(port
);
528 /* set default VID and and destination ports for this VLAN */
529 vlan
|= (portmask
<< AR7240_PORT_VLAN_DEST_PORTS_S
);
531 ar7240sw_reg_write(mii
, AR7240_REG_PORT_CTRL(port
), ctrl
);
532 ar7240sw_reg_write(mii
, AR7240_REG_PORT_VLAN(port
), vlan
);
535 static int ar7240_set_addr(struct ar7240sw
*as
, u8
*addr
)
537 struct mii_bus
*mii
= as
->mii_bus
;
540 t
= (addr
[4] << 8) | addr
[5];
541 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR0
, t
);
543 t
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
544 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR1
, t
);
550 ar7240_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
551 struct switch_val
*val
)
553 struct ar7240sw
*as
= sw_to_ar7240(dev
);
554 as
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
559 ar7240_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
560 struct switch_val
*val
)
562 struct ar7240sw
*as
= sw_to_ar7240(dev
);
563 val
->value
.i
= as
->vlan_id
[val
->port_vlan
];
568 ar7240_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
570 struct ar7240sw
*as
= sw_to_ar7240(dev
);
572 /* make sure no invalid PVIDs get set */
574 if (vlan
>= dev
->vlans
)
577 as
->pvid
[port
] = vlan
;
582 ar7240_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
584 struct ar7240sw
*as
= sw_to_ar7240(dev
);
585 *vlan
= as
->pvid
[port
];
590 ar7240_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
592 struct ar7240sw
*as
= sw_to_ar7240(dev
);
593 u8 ports
= as
->vlan_table
[val
->port_vlan
];
597 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++) {
598 struct switch_port
*p
;
600 if (!(ports
& (1 << i
)))
603 p
= &val
->value
.ports
[val
->len
++];
605 if (as
->vlan_tagged
& (1 << i
))
606 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
614 ar7240_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
616 struct ar7240sw
*as
= sw_to_ar7240(dev
);
617 u8
*vt
= &as
->vlan_table
[val
->port_vlan
];
621 for (i
= 0; i
< val
->len
; i
++) {
622 struct switch_port
*p
= &val
->value
.ports
[i
];
624 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
))
625 as
->vlan_tagged
|= (1 << p
->id
);
627 as
->vlan_tagged
&= ~(1 << p
->id
);
628 as
->pvid
[p
->id
] = val
->port_vlan
;
630 /* make sure that an untagged port does not
631 * appear in other vlans */
632 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
633 if (j
== val
->port_vlan
)
635 as
->vlan_table
[j
] &= ~(1 << p
->id
);
645 ar7240_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
646 struct switch_val
*val
)
648 struct ar7240sw
*as
= sw_to_ar7240(dev
);
649 as
->vlan
= !!val
->value
.i
;
654 ar7240_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
655 struct switch_val
*val
)
657 struct ar7240sw
*as
= sw_to_ar7240(dev
);
658 val
->value
.i
= as
->vlan
;
664 ar7240_vtu_op(struct ar7240sw
*as
, u32 op
, u32 val
)
666 struct mii_bus
*mii
= as
->mii_bus
;
668 if (ar7240sw_reg_wait(mii
, AR7240_REG_VTU
, AR7240_VTU_ACTIVE
, 0, 5))
671 if ((op
& AR7240_VTU_OP
) == AR7240_VTU_OP_LOAD
) {
672 val
&= AR7240_VTUDATA_MEMBER
;
673 val
|= AR7240_VTUDATA_VALID
;
674 ar7240sw_reg_write(mii
, AR7240_REG_VTU_DATA
, val
);
676 op
|= AR7240_VTU_ACTIVE
;
677 ar7240sw_reg_write(mii
, AR7240_REG_VTU
, op
);
681 ar7240_hw_apply(struct switch_dev
*dev
)
683 struct ar7240sw
*as
= sw_to_ar7240(dev
);
684 u8 portmask
[AR7240_NUM_PORTS
];
687 /* flush all vlan translation unit entries */
688 ar7240_vtu_op(as
, AR7240_VTU_OP_FLUSH
, 0);
690 memset(portmask
, 0, sizeof(portmask
));
692 /* calculate the port destination masks and load vlans
693 * into the vlan translation unit */
694 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
695 u8 vp
= as
->vlan_table
[j
];
700 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++) {
703 portmask
[i
] |= vp
& ~mask
;
708 (as
->vlan_id
[j
] << AR7240_VTU_VID_S
),
713 * isolate all ports, but connect them to the cpu port */
714 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++) {
715 if (i
== AR7240_PORT_CPU
)
718 portmask
[i
] = 1 << AR7240_PORT_CPU
;
719 portmask
[AR7240_PORT_CPU
] |= (1 << i
);
723 /* update the port destination mask registers and tag settings */
724 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++)
725 ar7240sw_setup_port(as
, i
, portmask
[i
]);
731 ar7240_reset_switch(struct switch_dev
*dev
)
733 struct ar7240sw
*as
= sw_to_ar7240(dev
);
738 static struct switch_attr ar7240_globals
[] = {
740 .type
= SWITCH_TYPE_INT
,
741 .name
= "enable_vlan",
742 .description
= "Enable VLAN mode",
743 .set
= ar7240_set_vlan
,
744 .get
= ar7240_get_vlan
,
749 static struct switch_attr ar7240_port
[] = {
752 static struct switch_attr ar7240_vlan
[] = {
754 .type
= SWITCH_TYPE_INT
,
756 .description
= "VLAN ID",
757 .set
= ar7240_set_vid
,
758 .get
= ar7240_get_vid
,
763 static const struct switch_dev_ops ar7240_ops
= {
765 .attr
= ar7240_globals
,
766 .n_attr
= ARRAY_SIZE(ar7240_globals
),
770 .n_attr
= ARRAY_SIZE(ar7240_port
),
774 .n_attr
= ARRAY_SIZE(ar7240_vlan
),
776 .get_port_pvid
= ar7240_get_pvid
,
777 .set_port_pvid
= ar7240_set_pvid
,
778 .get_vlan_ports
= ar7240_get_ports
,
779 .set_vlan_ports
= ar7240_set_ports
,
780 .apply_config
= ar7240_hw_apply
,
781 .reset_switch
= ar7240_reset_switch
,
784 static struct ar7240sw
*ar7240_probe(struct ag71xx
*ag
)
786 struct mii_bus
*mii
= ag
->mii_bus
;
788 struct switch_dev
*swdev
;
795 as
= kzalloc(sizeof(*as
), GFP_KERNEL
);
799 ar7240sw_init(as
, mii
);
801 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_MASK_CTRL
);
803 ver
= (ctrl
>> AR7240_MASK_CTRL_VERSION_S
) & AR7240_MASK_CTRL_VERSION_M
;
805 pr_err("%s: unsupported chip, ctrl=%08x\n",
806 ag
->dev
->name
, ctrl
);
810 phy_id1
= ar7240sw_phy_read(mii
, 0, MII_PHYSID1
);
811 phy_id2
= ar7240sw_phy_read(mii
, 0, MII_PHYSID2
);
812 if (phy_id1
!= AR7240_PHY_ID1
|| phy_id2
!= AR7240_PHY_ID2
) {
813 pr_err("%s: unknown phy id '%04x:%04x'\n",
814 ag
->dev
->name
, phy_id1
, phy_id2
);
819 swdev
->name
= "AR7240 built-in switch";
820 swdev
->ports
= AR7240_NUM_PORTS
;
821 swdev
->cpu_port
= AR7240_PORT_CPU
;
822 swdev
->vlans
= AR7240_MAX_VLANS
;
823 swdev
->ops
= &ar7240_ops
;
825 if (register_switch(&as
->swdev
, ag
->dev
) < 0) {
830 pr_info("%s: Found an AR7240 built-in switch\n", ag
->dev
->name
);
832 /* initialize defaults */
833 for (i
= 0; i
< AR7240_MAX_VLANS
; i
++)
836 as
->vlan_table
[0] = AR7240_PORT_MASK_ALL
;
841 static void link_function(struct work_struct
*work
) {
842 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, link_work
.work
);
847 for (i
= 0; i
< 4; i
++) {
848 int link
= ar7240sw_phy_read(ag
->mii_bus
, i
, MII_BMSR
);
849 if(link
& BMSR_LSTATUS
) {
855 spin_lock_irqsave(&ag
->lock
, flags
);
856 if(status
!= ag
->link
) {
858 ag71xx_link_adjust(ag
);
860 spin_unlock_irqrestore(&ag
->lock
, flags
);
862 schedule_delayed_work(&ag
->link_work
, HZ
/ 2);
865 void ag71xx_ar7240_start(struct ag71xx
*ag
)
867 struct ar7240sw
*as
= ag
->phy_priv
;
872 ag
->speed
= SPEED_1000
;
875 ar7240_set_addr(as
, ag
->dev
->dev_addr
);
876 ar7240_hw_apply(&as
->swdev
);
878 schedule_delayed_work(&ag
->link_work
, HZ
/ 10);
881 void ag71xx_ar7240_stop(struct ag71xx
*ag
)
883 cancel_delayed_work_sync(&ag
->link_work
);
886 int __devinit
ag71xx_ar7240_init(struct ag71xx
*ag
)
890 as
= ar7240_probe(ag
);
897 INIT_DELAYED_WORK(&ag
->link_work
, link_function
);
902 void ag71xx_ar7240_cleanup(struct ag71xx
*ag
)
904 struct ar7240sw
*as
= ag
->phy_priv
;
909 unregister_switch(&as
->swdev
);