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ar71xx: configure address aging on ar7240
[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
94 {
95 int err;
96 int i;
97
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104 }
105
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
115 if (!ring->buf) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
125 }
126
127 return 0;
128
129 err:
130 return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137
138 while (ring->curr != ring->dirty) {
139 u32 i = ring->dirty % ring->size;
140
141 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142 ring->buf[i].desc->ctrl = 0;
143 dev->stats.tx_errors++;
144 }
145
146 if (ring->buf[i].skb)
147 dev_kfree_skb_any(ring->buf[i].skb);
148
149 ring->buf[i].skb = NULL;
150
151 ring->dirty++;
152 }
153
154 /* flush descriptors */
155 wmb();
156
157 }
158
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
160 {
161 struct ag71xx_ring *ring = &ag->tx_ring;
162 int i;
163
164 for (i = 0; i < ring->size; i++) {
165 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166 ring->desc_size * ((i + 1) % ring->size));
167
168 ring->buf[i].desc->ctrl = DESC_EMPTY;
169 ring->buf[i].skb = NULL;
170 }
171
172 /* flush descriptors */
173 wmb();
174
175 ring->curr = 0;
176 ring->dirty = 0;
177 }
178
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 int i;
183
184 if (!ring->buf)
185 return;
186
187 for (i = 0; i < ring->size; i++)
188 if (ring->buf[i].skb) {
189 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191 kfree_skb(ring->buf[i].skb);
192 }
193 }
194
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
196 {
197 int reserve = 0;
198
199 if (ag71xx_get_pdata(ag)->is_ar724x) {
200 if (!ag71xx_has_ar8216(ag))
201 reserve = 2;
202
203 if (ag->phy_dev)
204 reserve += 4 - (ag->phy_dev->pkt_align % 4);
205
206 reserve %= 4;
207 }
208
209 return reserve + AG71XX_RX_PKT_RESERVE;
210 }
211
212
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
214 {
215 struct ag71xx_ring *ring = &ag->rx_ring;
216 unsigned int reserve = ag71xx_rx_reserve(ag);
217 unsigned int i;
218 int ret;
219
220 ret = 0;
221 for (i = 0; i < ring->size; i++) {
222 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223 ring->desc_size * ((i + 1) % ring->size));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 ring->buf[i].desc,
227 ring->buf[i].desc->next);
228 }
229
230 for (i = 0; i < ring->size; i++) {
231 struct sk_buff *skb;
232 dma_addr_t dma_addr;
233
234 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
235 if (!skb) {
236 ret = -ENOMEM;
237 break;
238 }
239
240 skb->dev = ag->dev;
241 skb_reserve(skb, reserve);
242
243 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
244 AG71XX_RX_PKT_SIZE,
245 DMA_FROM_DEVICE);
246 ring->buf[i].skb = skb;
247 ring->buf[i].dma_addr = dma_addr;
248 ring->buf[i].desc->data = (u32) dma_addr;
249 ring->buf[i].desc->ctrl = DESC_EMPTY;
250 }
251
252 /* flush descriptors */
253 wmb();
254
255 ring->curr = 0;
256 ring->dirty = 0;
257
258 return ret;
259 }
260
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
262 {
263 struct ag71xx_ring *ring = &ag->rx_ring;
264 unsigned int reserve = ag71xx_rx_reserve(ag);
265 unsigned int count;
266
267 count = 0;
268 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
269 unsigned int i;
270
271 i = ring->dirty % ring->size;
272
273 if (ring->buf[i].skb == NULL) {
274 dma_addr_t dma_addr;
275 struct sk_buff *skb;
276
277 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
278 if (skb == NULL)
279 break;
280
281 skb_reserve(skb, reserve);
282 skb->dev = ag->dev;
283
284 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
285 AG71XX_RX_PKT_SIZE,
286 DMA_FROM_DEVICE);
287
288 ring->buf[i].skb = skb;
289 ring->buf[i].dma_addr = dma_addr;
290 ring->buf[i].desc->data = (u32) dma_addr;
291 }
292
293 ring->buf[i].desc->ctrl = DESC_EMPTY;
294 count++;
295 }
296
297 /* flush descriptors */
298 wmb();
299
300 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
301
302 return count;
303 }
304
305 static int ag71xx_rings_init(struct ag71xx *ag)
306 {
307 int ret;
308
309 ret = ag71xx_ring_alloc(&ag->tx_ring);
310 if (ret)
311 return ret;
312
313 ag71xx_ring_tx_init(ag);
314
315 ret = ag71xx_ring_alloc(&ag->rx_ring);
316 if (ret)
317 return ret;
318
319 ret = ag71xx_ring_rx_init(ag);
320 return ret;
321 }
322
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
324 {
325 ag71xx_ring_rx_clean(ag);
326 ag71xx_ring_free(&ag->rx_ring);
327
328 ag71xx_ring_tx_clean(ag);
329 ag71xx_ring_free(&ag->tx_ring);
330 }
331
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
333 {
334 switch (ag->speed) {
335 case SPEED_1000:
336 return "1000";
337 case SPEED_100:
338 return "100";
339 case SPEED_10:
340 return "10";
341 }
342
343 return "?";
344 }
345
346 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
347 {
348 u32 t;
349
350 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
351 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
352
353 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
354
355 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
356 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
357 }
358
359 static void ag71xx_dma_reset(struct ag71xx *ag)
360 {
361 u32 val;
362 int i;
363
364 ag71xx_dump_dma_regs(ag);
365
366 /* stop RX and TX */
367 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
368 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
369
370 /*
371 * give the hardware some time to really stop all rx/tx activity
372 * clearing the descriptors too early causes random memory corruption
373 */
374 mdelay(1);
375
376 /* clear descriptor addresses */
377 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
378 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
379
380 /* clear pending RX/TX interrupts */
381 for (i = 0; i < 256; i++) {
382 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
383 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
384 }
385
386 /* clear pending errors */
387 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
388 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
389
390 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
391 if (val)
392 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
393 ag->dev->name, val);
394
395 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
396
397 /* mask out reserved bits */
398 val &= ~0xff000000;
399
400 if (val)
401 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
402 ag->dev->name, val);
403
404 ag71xx_dump_dma_regs(ag);
405 }
406
407 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
408 MAC_CFG1_SRX | MAC_CFG1_STX)
409
410 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
411
412 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
413 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
414 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
415 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
416 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
417 FIFO_CFG4_VT)
418
419 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
420 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
421 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
422 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
423 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
424 FIFO_CFG5_17 | FIFO_CFG5_SF)
425
426 static void ag71xx_hw_stop(struct ag71xx *ag)
427 {
428 /* disable all interrupts and stop the rx engine */
429 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
430 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
431 }
432
433 static void ag71xx_hw_init(struct ag71xx *ag)
434 {
435 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
436 u32 reset_mask = pdata->reset_bit;
437
438 ag71xx_hw_stop(ag);
439
440 if (pdata->is_ar724x) {
441 u32 reset_phy = reset_mask;
442
443 reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY;
444 reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY);
445
446 ar71xx_device_stop(reset_phy);
447 mdelay(50);
448 ar71xx_device_start(reset_phy);
449 mdelay(200);
450 }
451
452 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
453 udelay(20);
454
455 ar71xx_device_stop(pdata->reset_bit);
456 mdelay(100);
457 ar71xx_device_start(pdata->reset_bit);
458 mdelay(200);
459
460 /* setup MAC configuration registers */
461 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
462
463 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
464 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
465
466 /* setup max frame length */
467 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
468
469 /* setup MII interface type */
470 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
471
472 /* setup FIFO configuration registers */
473 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
474 if (pdata->is_ar724x) {
475 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
476 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
477 } else {
478 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
479 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
480 }
481 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
482 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
483
484 ag71xx_dma_reset(ag);
485 }
486
487 static void ag71xx_hw_start(struct ag71xx *ag)
488 {
489 /* start RX engine */
490 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
491
492 /* enable interrupts */
493 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
494 }
495
496 void ag71xx_link_adjust(struct ag71xx *ag)
497 {
498 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
499 u32 cfg2;
500 u32 ifctl;
501 u32 fifo5;
502 u32 mii_speed;
503
504 if (!ag->link) {
505 ag71xx_hw_stop(ag);
506 netif_carrier_off(ag->dev);
507 if (netif_msg_link(ag))
508 printk(KERN_INFO "%s: link down\n", ag->dev->name);
509 return;
510 }
511
512 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
513 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
514 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
515
516 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
517 ifctl &= ~(MAC_IFCTL_SPEED);
518
519 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
520 fifo5 &= ~FIFO_CFG5_BM;
521
522 switch (ag->speed) {
523 case SPEED_1000:
524 mii_speed = MII_CTRL_SPEED_1000;
525 cfg2 |= MAC_CFG2_IF_1000;
526 fifo5 |= FIFO_CFG5_BM;
527 break;
528 case SPEED_100:
529 mii_speed = MII_CTRL_SPEED_100;
530 cfg2 |= MAC_CFG2_IF_10_100;
531 ifctl |= MAC_IFCTL_SPEED;
532 break;
533 case SPEED_10:
534 mii_speed = MII_CTRL_SPEED_10;
535 cfg2 |= MAC_CFG2_IF_10_100;
536 break;
537 default:
538 BUG();
539 return;
540 }
541
542 if (pdata->is_ar91xx)
543 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
544 else if (pdata->is_ar724x)
545 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
546 else
547 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
548
549 if (pdata->set_pll)
550 pdata->set_pll(ag->speed);
551
552 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
553
554 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
555 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
556 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
557 ag71xx_hw_start(ag);
558
559 netif_carrier_on(ag->dev);
560 if (netif_msg_link(ag))
561 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
562 ag->dev->name,
563 ag71xx_speed_str(ag),
564 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
565
566 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
567 ag->dev->name,
568 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
569 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
570 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
571
572 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
573 ag->dev->name,
574 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
575 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
576 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
577
578 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
579 ag->dev->name,
580 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
581 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
582 ag71xx_mii_ctrl_rr(ag));
583 }
584
585 static int ag71xx_open(struct net_device *dev)
586 {
587 struct ag71xx *ag = netdev_priv(dev);
588 int ret;
589
590 ret = ag71xx_rings_init(ag);
591 if (ret)
592 goto err;
593
594 napi_enable(&ag->napi);
595
596 netif_carrier_off(dev);
597 ag71xx_phy_start(ag);
598
599 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
600 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
601
602 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
603
604 netif_start_queue(dev);
605
606 return 0;
607
608 err:
609 ag71xx_rings_cleanup(ag);
610 return ret;
611 }
612
613 static int ag71xx_stop(struct net_device *dev)
614 {
615 struct ag71xx *ag = netdev_priv(dev);
616 unsigned long flags;
617
618 netif_carrier_off(dev);
619 ag71xx_phy_stop(ag);
620
621 spin_lock_irqsave(&ag->lock, flags);
622
623 netif_stop_queue(dev);
624
625 ag71xx_hw_stop(ag);
626 ag71xx_dma_reset(ag);
627
628 napi_disable(&ag->napi);
629 del_timer_sync(&ag->oom_timer);
630
631 spin_unlock_irqrestore(&ag->lock, flags);
632
633 ag71xx_rings_cleanup(ag);
634
635 return 0;
636 }
637
638 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
639 struct net_device *dev)
640 {
641 struct ag71xx *ag = netdev_priv(dev);
642 struct ag71xx_ring *ring = &ag->tx_ring;
643 struct ag71xx_desc *desc;
644 dma_addr_t dma_addr;
645 int i;
646
647 i = ring->curr % ring->size;
648 desc = ring->buf[i].desc;
649
650 if (!ag71xx_desc_empty(desc))
651 goto err_drop;
652
653 if (ag71xx_has_ar8216(ag))
654 ag71xx_add_ar8216_header(ag, skb);
655
656 if (skb->len <= 0) {
657 DBG("%s: packet len is too small\n", ag->dev->name);
658 goto err_drop;
659 }
660
661 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
662 DMA_TO_DEVICE);
663
664 ring->buf[i].skb = skb;
665 ring->buf[i].timestamp = jiffies;
666
667 /* setup descriptor fields */
668 desc->data = (u32) dma_addr;
669 desc->ctrl = (skb->len & DESC_PKTLEN_M);
670
671 /* flush descriptor */
672 wmb();
673
674 ring->curr++;
675 if (ring->curr == (ring->dirty + ring->size)) {
676 DBG("%s: tx queue full\n", ag->dev->name);
677 netif_stop_queue(dev);
678 }
679
680 DBG("%s: packet injected into TX queue\n", ag->dev->name);
681
682 /* enable TX engine */
683 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
684
685 return NETDEV_TX_OK;
686
687 err_drop:
688 dev->stats.tx_dropped++;
689
690 dev_kfree_skb(skb);
691 return NETDEV_TX_OK;
692 }
693
694 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
695 {
696 struct ag71xx *ag = netdev_priv(dev);
697 int ret;
698
699 switch (cmd) {
700 case SIOCETHTOOL:
701 if (ag->phy_dev == NULL)
702 break;
703
704 spin_lock_irq(&ag->lock);
705 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
706 spin_unlock_irq(&ag->lock);
707 return ret;
708
709 case SIOCSIFHWADDR:
710 if (copy_from_user
711 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
712 return -EFAULT;
713 return 0;
714
715 case SIOCGIFHWADDR:
716 if (copy_to_user
717 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
718 return -EFAULT;
719 return 0;
720
721 case SIOCGMIIPHY:
722 case SIOCGMIIREG:
723 case SIOCSMIIREG:
724 if (ag->phy_dev == NULL)
725 break;
726
727 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
728
729 default:
730 break;
731 }
732
733 return -EOPNOTSUPP;
734 }
735
736 static void ag71xx_oom_timer_handler(unsigned long data)
737 {
738 struct net_device *dev = (struct net_device *) data;
739 struct ag71xx *ag = netdev_priv(dev);
740
741 napi_schedule(&ag->napi);
742 }
743
744 static void ag71xx_tx_timeout(struct net_device *dev)
745 {
746 struct ag71xx *ag = netdev_priv(dev);
747
748 if (netif_msg_tx_err(ag))
749 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
750
751 schedule_work(&ag->restart_work);
752 }
753
754 static void ag71xx_restart_work_func(struct work_struct *work)
755 {
756 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
757
758 ag71xx_stop(ag->dev);
759 ag71xx_open(ag->dev);
760 }
761
762 static int ag71xx_tx_packets(struct ag71xx *ag)
763 {
764 struct ag71xx_ring *ring = &ag->tx_ring;
765 int sent;
766
767 DBG("%s: processing TX ring\n", ag->dev->name);
768
769 sent = 0;
770 while (ring->dirty != ring->curr) {
771 unsigned int i = ring->dirty % ring->size;
772 struct ag71xx_desc *desc = ring->buf[i].desc;
773 struct sk_buff *skb = ring->buf[i].skb;
774
775 if (!ag71xx_desc_empty(desc))
776 break;
777
778 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
779
780 ag->dev->stats.tx_bytes += skb->len;
781 ag->dev->stats.tx_packets++;
782
783 dev_kfree_skb_any(skb);
784 ring->buf[i].skb = NULL;
785
786 ring->dirty++;
787 sent++;
788 }
789
790 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
791
792 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
793 netif_wake_queue(ag->dev);
794
795 return sent;
796 }
797
798 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
799 {
800 struct net_device *dev = ag->dev;
801 struct ag71xx_ring *ring = &ag->rx_ring;
802 int done = 0;
803
804 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
805 dev->name, limit, ring->curr, ring->dirty);
806
807 while (done < limit) {
808 unsigned int i = ring->curr % ring->size;
809 struct ag71xx_desc *desc = ring->buf[i].desc;
810 struct sk_buff *skb;
811 int pktlen;
812 int err = 0;
813
814 if (ag71xx_desc_empty(desc))
815 break;
816
817 if ((ring->dirty + ring->size) == ring->curr) {
818 ag71xx_assert(0);
819 break;
820 }
821
822 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
823
824 skb = ring->buf[i].skb;
825 pktlen = ag71xx_desc_pktlen(desc);
826 pktlen -= ETH_FCS_LEN;
827
828 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
829 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
830
831 dev->last_rx = jiffies;
832 dev->stats.rx_packets++;
833 dev->stats.rx_bytes += pktlen;
834
835 skb_put(skb, pktlen);
836 if (ag71xx_has_ar8216(ag))
837 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
838
839 if (err) {
840 dev->stats.rx_dropped++;
841 kfree_skb(skb);
842 } else {
843 skb->dev = dev;
844 skb->ip_summed = CHECKSUM_NONE;
845 if (ag->phy_dev) {
846 ag->phy_dev->netif_receive_skb(skb);
847 } else {
848 skb->protocol = eth_type_trans(skb, dev);
849 netif_receive_skb(skb);
850 }
851 }
852
853 ring->buf[i].skb = NULL;
854 done++;
855
856 ring->curr++;
857 }
858
859 ag71xx_ring_rx_refill(ag);
860
861 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
862 dev->name, ring->curr, ring->dirty, done);
863
864 return done;
865 }
866
867 static int ag71xx_poll(struct napi_struct *napi, int limit)
868 {
869 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
870 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
871 struct net_device *dev = ag->dev;
872 struct ag71xx_ring *rx_ring;
873 unsigned long flags;
874 u32 status;
875 int tx_done;
876 int rx_done;
877
878 pdata->ddr_flush();
879 tx_done = ag71xx_tx_packets(ag);
880
881 DBG("%s: processing RX ring\n", dev->name);
882 rx_done = ag71xx_rx_packets(ag, limit);
883
884 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
885
886 rx_ring = &ag->rx_ring;
887 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
888 goto oom;
889
890 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
891 if (unlikely(status & RX_STATUS_OF)) {
892 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
893 dev->stats.rx_fifo_errors++;
894
895 /* restart RX */
896 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
897 }
898
899 if (rx_done < limit) {
900 if (status & RX_STATUS_PR)
901 goto more;
902
903 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
904 if (status & TX_STATUS_PS)
905 goto more;
906
907 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
908 dev->name, rx_done, tx_done, limit);
909
910 napi_complete(napi);
911
912 /* enable interrupts */
913 spin_lock_irqsave(&ag->lock, flags);
914 ag71xx_int_enable(ag, AG71XX_INT_POLL);
915 spin_unlock_irqrestore(&ag->lock, flags);
916 return rx_done;
917 }
918
919 more:
920 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
921 dev->name, rx_done, tx_done, limit);
922 return rx_done;
923
924 oom:
925 if (netif_msg_rx_err(ag))
926 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
927
928 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
929 napi_complete(napi);
930 return 0;
931 }
932
933 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
934 {
935 struct net_device *dev = dev_id;
936 struct ag71xx *ag = netdev_priv(dev);
937 u32 status;
938
939 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
940 ag71xx_dump_intr(ag, "raw", status);
941
942 if (unlikely(!status))
943 return IRQ_NONE;
944
945 if (unlikely(status & AG71XX_INT_ERR)) {
946 if (status & AG71XX_INT_TX_BE) {
947 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
948 dev_err(&dev->dev, "TX BUS error\n");
949 }
950 if (status & AG71XX_INT_RX_BE) {
951 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
952 dev_err(&dev->dev, "RX BUS error\n");
953 }
954 }
955
956 if (likely(status & AG71XX_INT_POLL)) {
957 ag71xx_int_disable(ag, AG71XX_INT_POLL);
958 DBG("%s: enable polling mode\n", dev->name);
959 napi_schedule(&ag->napi);
960 }
961
962 ag71xx_debugfs_update_int_stats(ag, status);
963
964 return IRQ_HANDLED;
965 }
966
967 static void ag71xx_set_multicast_list(struct net_device *dev)
968 {
969 /* TODO */
970 }
971
972 #ifdef CONFIG_NET_POLL_CONTROLLER
973 /*
974 * Polling 'interrupt' - used by things like netconsole to send skbs
975 * without having to re-enable interrupts. It's not called while
976 * the interrupt routine is executing.
977 */
978 static void ag71xx_netpoll(struct net_device *dev)
979 {
980 disable_irq(dev->irq);
981 ag71xx_interrupt(dev->irq, dev);
982 enable_irq(dev->irq);
983 }
984 #endif
985
986 static const struct net_device_ops ag71xx_netdev_ops = {
987 .ndo_open = ag71xx_open,
988 .ndo_stop = ag71xx_stop,
989 .ndo_start_xmit = ag71xx_hard_start_xmit,
990 .ndo_set_multicast_list = ag71xx_set_multicast_list,
991 .ndo_do_ioctl = ag71xx_do_ioctl,
992 .ndo_tx_timeout = ag71xx_tx_timeout,
993 .ndo_change_mtu = eth_change_mtu,
994 .ndo_set_mac_address = eth_mac_addr,
995 .ndo_validate_addr = eth_validate_addr,
996 #ifdef CONFIG_NET_POLL_CONTROLLER
997 .ndo_poll_controller = ag71xx_netpoll,
998 #endif
999 };
1000
1001 static int __devinit ag71xx_probe(struct platform_device *pdev)
1002 {
1003 struct net_device *dev;
1004 struct resource *res;
1005 struct ag71xx *ag;
1006 struct ag71xx_platform_data *pdata;
1007 int err;
1008
1009 pdata = pdev->dev.platform_data;
1010 if (!pdata) {
1011 dev_err(&pdev->dev, "no platform data specified\n");
1012 err = -ENXIO;
1013 goto err_out;
1014 }
1015
1016 if (pdata->mii_bus_dev == NULL) {
1017 dev_err(&pdev->dev, "no MII bus device specified\n");
1018 err = -EINVAL;
1019 goto err_out;
1020 }
1021
1022 dev = alloc_etherdev(sizeof(*ag));
1023 if (!dev) {
1024 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1025 err = -ENOMEM;
1026 goto err_out;
1027 }
1028
1029 SET_NETDEV_DEV(dev, &pdev->dev);
1030
1031 ag = netdev_priv(dev);
1032 ag->pdev = pdev;
1033 ag->dev = dev;
1034 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1035 AG71XX_DEFAULT_MSG_ENABLE);
1036 spin_lock_init(&ag->lock);
1037
1038 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1039 if (!res) {
1040 dev_err(&pdev->dev, "no mac_base resource found\n");
1041 err = -ENXIO;
1042 goto err_out;
1043 }
1044
1045 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1046 if (!ag->mac_base) {
1047 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1048 err = -ENOMEM;
1049 goto err_free_dev;
1050 }
1051
1052 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1053 if (!res) {
1054 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1055 err = -ENXIO;
1056 goto err_unmap_base;
1057 }
1058
1059 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1060 if (!ag->mii_ctrl) {
1061 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1062 err = -ENOMEM;
1063 goto err_unmap_base;
1064 }
1065
1066 dev->irq = platform_get_irq(pdev, 0);
1067 err = request_irq(dev->irq, ag71xx_interrupt,
1068 IRQF_DISABLED,
1069 dev->name, dev);
1070 if (err) {
1071 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1072 goto err_unmap_mii_ctrl;
1073 }
1074
1075 dev->base_addr = (unsigned long)ag->mac_base;
1076 dev->netdev_ops = &ag71xx_netdev_ops;
1077 dev->ethtool_ops = &ag71xx_ethtool_ops;
1078
1079 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1080
1081 init_timer(&ag->oom_timer);
1082 ag->oom_timer.data = (unsigned long) dev;
1083 ag->oom_timer.function = ag71xx_oom_timer_handler;
1084
1085 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1086 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1087
1088 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1089
1090 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1091
1092 err = register_netdev(dev);
1093 if (err) {
1094 dev_err(&pdev->dev, "unable to register net device\n");
1095 goto err_free_irq;
1096 }
1097
1098 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1099 dev->name, dev->base_addr, dev->irq);
1100
1101 ag71xx_dump_regs(ag);
1102
1103 ag71xx_hw_init(ag);
1104
1105 ag71xx_dump_regs(ag);
1106
1107 err = ag71xx_phy_connect(ag);
1108 if (err)
1109 goto err_unregister_netdev;
1110
1111 err = ag71xx_debugfs_init(ag);
1112 if (err)
1113 goto err_phy_disconnect;
1114
1115 platform_set_drvdata(pdev, dev);
1116
1117 return 0;
1118
1119 err_phy_disconnect:
1120 ag71xx_phy_disconnect(ag);
1121 err_unregister_netdev:
1122 unregister_netdev(dev);
1123 err_free_irq:
1124 free_irq(dev->irq, dev);
1125 err_unmap_mii_ctrl:
1126 iounmap(ag->mii_ctrl);
1127 err_unmap_base:
1128 iounmap(ag->mac_base);
1129 err_free_dev:
1130 kfree(dev);
1131 err_out:
1132 platform_set_drvdata(pdev, NULL);
1133 return err;
1134 }
1135
1136 static int __devexit ag71xx_remove(struct platform_device *pdev)
1137 {
1138 struct net_device *dev = platform_get_drvdata(pdev);
1139
1140 if (dev) {
1141 struct ag71xx *ag = netdev_priv(dev);
1142
1143 ag71xx_debugfs_exit(ag);
1144 ag71xx_phy_disconnect(ag);
1145 unregister_netdev(dev);
1146 free_irq(dev->irq, dev);
1147 iounmap(ag->mii_ctrl);
1148 iounmap(ag->mac_base);
1149 kfree(dev);
1150 platform_set_drvdata(pdev, NULL);
1151 }
1152
1153 return 0;
1154 }
1155
1156 static struct platform_driver ag71xx_driver = {
1157 .probe = ag71xx_probe,
1158 .remove = __exit_p(ag71xx_remove),
1159 .driver = {
1160 .name = AG71XX_DRV_NAME,
1161 }
1162 };
1163
1164 static int __init ag71xx_module_init(void)
1165 {
1166 int ret;
1167
1168 ret = ag71xx_debugfs_root_init();
1169 if (ret)
1170 goto err_out;
1171
1172 ret = ag71xx_mdio_driver_init();
1173 if (ret)
1174 goto err_debugfs_exit;
1175
1176 ret = platform_driver_register(&ag71xx_driver);
1177 if (ret)
1178 goto err_mdio_exit;
1179
1180 return 0;
1181
1182 err_mdio_exit:
1183 ag71xx_mdio_driver_exit();
1184 err_debugfs_exit:
1185 ag71xx_debugfs_root_exit();
1186 err_out:
1187 return ret;
1188 }
1189
1190 static void __exit ag71xx_module_exit(void)
1191 {
1192 platform_driver_unregister(&ag71xx_driver);
1193 ag71xx_mdio_driver_exit();
1194 ag71xx_debugfs_root_exit();
1195 }
1196
1197 module_init(ag71xx_module_init);
1198 module_exit(ag71xx_module_exit);
1199
1200 MODULE_VERSION(AG71XX_DRV_VERSION);
1201 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1202 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1203 MODULE_LICENSE("GPL v2");
1204 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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