target/linux/atheros/files/drivers/mtd/devices/spiflash.c

   1
   2 /*
   3  * MTD driver for the SPI Flash Memory support.
   4  *
   5  * Copyright (c) 2005-2006 Atheros Communications Inc.
   6  * Copyright (C) 2006-2007 FON Technology, SL.
   7  * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
   8  * Copyright (C) 2006-2007 Felix Fietkau <nbd@openwrt.org>
   9  *
  10  * This code is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  */
  15
  16 /*===========================================================================
  17 ** !!!!  VERY IMPORTANT NOTICE !!!!  FLASH DATA STORED IN LITTLE ENDIAN FORMAT
  18 **
  19 ** This module contains the Serial Flash access routines for the Atheros SOC.
  20 ** The Atheros SOC integrates a SPI flash controller that is used to access
  21 ** serial flash parts. The SPI flash controller executes in "Little Endian"
  22 ** mode. THEREFORE, all WRITES and READS from the MIPS CPU must be
  23 ** BYTESWAPPED! The SPI Flash controller hardware by default performs READ
  24 ** ONLY byteswapping when accessed via the SPI Flash Alias memory region
  25 ** (Physical Address 0x0800_0000 - 0x0fff_ffff). The data stored in the
  26 ** flash sectors is stored in "Little Endian" format.
  27 **
  28 ** The spiflash_write() routine performs byteswapping on all write
  29 ** operations.
  30 **===========================================================================*/
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/types.h>
  35 #include <linux/version.h>
  36 #include <linux/errno.h>
  37 #include <linux/slab.h>
  38 #include <linux/mtd/mtd.h>
  39 #include <linux/mtd/partitions.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/sched.h>
  42 #include <linux/squashfs_fs.h>
  43 #include <linux/root_dev.h>
  44 #include <linux/delay.h>
  45 #include <asm/delay.h>
  46 #include <asm/io.h>
  47 #include "spiflash.h"
  48
  49 #ifndef __BIG_ENDIAN
  50 #error This driver currently only works with big endian CPU.
  51 #endif
  52
  53 #define MAX_PARTS 32
  54
  55 #define SPIFLASH "spiflash: "
  56
  57 #define MIN(a,b)        ((a) < (b) ? (a) : (b))
  58
  59 #define busy_wait(condition, wait) \
  60         do { \
  61                 while (condition) { \
  62                         spin_unlock_bh(&spidata->mutex); \
  63                         if (wait > 1) \
  64                                 msleep(wait); \
  65                         else if ((wait == 1) && need_resched()) \
  66                                 schedule(); \
  67                         else \
  68                                 udelay(1); \
  69                         spin_lock_bh(&spidata->mutex); \
  70                 } \
  71         } while (0)
  72
  73
  74 static __u32 spiflash_regread32(int reg);
  75 static void spiflash_regwrite32(int reg, __u32 data);
  76 static __u32 spiflash_sendcmd (int op, u32 addr);
  77
  78 int __init spiflash_init (void);
  79 void __exit spiflash_exit (void);
  80 static int spiflash_probe_chip (void);
  81 static int spiflash_erase (struct mtd_info *mtd,struct erase_info *instr);
  82 static int spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf);
  83 static int spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf);
  84
  85 /* Flash configuration table */
  86 struct flashconfig {
  87     __u32 byte_cnt;
  88     __u32 sector_cnt;
  89     __u32 sector_size;
  90     __u32 cs_addrmask;
  91 } flashconfig_tbl[MAX_FLASH] =
  92     {
  93         { 0, 0, 0, 0},
  94         { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE, 0x0},
  95         { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE, 0x0},
  96         { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE, 0x0},
  97         { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE, 0x0},
  98         { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT, STM_16MB_SECTOR_SIZE, 0x0}
  99     };
 100
 101 /* Mapping of generic opcodes to STM serial flash opcodes */
 102 #define SPI_WRITE_ENABLE    0
 103 #define SPI_WRITE_DISABLE   1
 104 #define SPI_RD_STATUS       2
 105 #define SPI_WR_STATUS       3
 106 #define SPI_RD_DATA         4
 107 #define SPI_FAST_RD_DATA    5
 108 #define SPI_PAGE_PROGRAM    6
 109 #define SPI_SECTOR_ERASE    7
 110 #define SPI_BULK_ERASE      8
 111 #define SPI_DEEP_PWRDOWN    9
 112 #define SPI_RD_SIG          10
 113 #define SPI_MAX_OPCODES     11
 114
 115 struct opcodes {
 116     __u16 code;
 117     __s8 tx_cnt;
 118     __s8 rx_cnt;
 119 } stm_opcodes[] = {
 120         {STM_OP_WR_ENABLE, 1, 0},
 121         {STM_OP_WR_DISABLE, 1, 0},
 122         {STM_OP_RD_STATUS, 1, 1},
 123         {STM_OP_WR_STATUS, 1, 0},
 124         {STM_OP_RD_DATA, 4, 4},
 125         {STM_OP_FAST_RD_DATA, 5, 0},
 126         {STM_OP_PAGE_PGRM, 8, 0},
 127         {STM_OP_SECTOR_ERASE, 4, 0},
 128         {STM_OP_BULK_ERASE, 1, 0},
 129         {STM_OP_DEEP_PWRDOWN, 1, 0},
 130         {STM_OP_RD_SIG, 4, 1},
 131 };
 132
 133 /* Driver private data structure */
 134 struct spiflash_data {
 135         struct  mtd_info       *mtd;
 136         struct  mtd_partition  *parsed_parts;     /* parsed partitions */
 137         void    *readaddr; /* memory mapped data for read  */
 138         void    *mmraddr;  /* memory mapped register space */
 139         wait_queue_head_t wq;
 140         spinlock_t mutex;
 141         int state;
 142 };
 143 enum {
 144         FL_READY,
 145         FL_READING,
 146         FL_ERASING,
 147         FL_WRITING
 148 };
 149
 150 static struct spiflash_data *spidata;
 151
 152 extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
 153
 154 /***************************************************************************************************/
 155
 156 static __u32
 157 spiflash_regread32(int reg)
 158 {
 159         volatile __u32 *data = (__u32 *)(spidata->mmraddr + reg);
 160
 161         return (*data);
 162 }
 163
 164 static void
 165 spiflash_regwrite32(int reg, __u32 data)
 166 {
 167         volatile __u32 *addr = (__u32 *)(spidata->mmraddr + reg);
 168
 169         *addr = data;
 170         return;
 171 }
 172
 173
 174 static __u32
 175 spiflash_sendcmd (int op, u32 addr)
 176 {
 177          u32 reg;
 178          u32 mask;
 179         struct opcodes *ptr_opcode;
 180
 181         ptr_opcode = &stm_opcodes[op];
 182         busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
 183         spiflash_regwrite32(SPI_FLASH_OPCODE, ((u32) ptr_opcode->code) | (addr << 8));
 184
 185         reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |
 186                 (ptr_opcode->rx_cnt << 4) | SPI_CTL_START;
 187
 188         spiflash_regwrite32(SPI_FLASH_CTL, reg);
 189         busy_wait(spiflash_regread32(SPI_FLASH_CTL) & SPI_CTL_BUSY, 0);
 190
 191         if (!ptr_opcode->rx_cnt)
 192                 return 0;
 193
 194         reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
 195
 196         switch (ptr_opcode->rx_cnt) {
 197         case 1:
 198                         mask = 0x000000ff;
 199                         break;
 200         case 2:
 201                         mask = 0x0000ffff;
 202                         break;
 203         case 3:
 204                         mask = 0x00ffffff;
 205                         break;
 206         default:
 207                         mask = 0xffffffff;
 208                         break;
 209         }
 210         reg &= mask;
 211
 212         return reg;
 213 }
 214
 215
 216
 217 /* Probe SPI flash device
 218  * Function returns 0 for failure.
 219  * and flashconfig_tbl array index for success.
 220  */
 221 static int
 222 spiflash_probe_chip (void)
 223 {
 224         __u32 sig;
 225         int flash_size;
 226
 227         /* Read the signature on the flash device */
 228         spin_lock_bh(&spidata->mutex);
 229         sig = spiflash_sendcmd(SPI_RD_SIG, 0);
 230         spin_unlock_bh(&spidata->mutex);
 231
 232         switch (sig) {
 233         case STM_8MBIT_SIGNATURE:
 234                 flash_size = FLASH_1MB;
 235                 break;
 236         case STM_16MBIT_SIGNATURE:
 237                 flash_size = FLASH_2MB;
 238                 break;
 239         case STM_32MBIT_SIGNATURE:
 240                 flash_size = FLASH_4MB;
 241                 break;
 242         case STM_64MBIT_SIGNATURE:
 243                 flash_size = FLASH_8MB;
 244                 break;
 245         case STM_128MBIT_SIGNATURE:
 246                 flash_size = FLASH_16MB;
 247                 break;
 248         default:
 249                 printk (KERN_WARNING SPIFLASH "Read of flash device signature failed!\n");
 250                 return (0);
 251         }
 252
 253         return (flash_size);
 254 }
 255
 256
 257 /* wait until the flash chip is ready and grab a lock */
 258 static int spiflash_wait_ready(int state)
 259 {
 260         DECLARE_WAITQUEUE(wait, current);
 261
 262 retry:
 263         spin_lock_bh(&spidata->mutex);
 264         if (spidata->state != FL_READY) {
 265                 set_current_state(TASK_UNINTERRUPTIBLE);
 266                 add_wait_queue(&spidata->wq, &wait);
 267                 spin_unlock_bh(&spidata->mutex);
 268                 schedule();
 269                 remove_wait_queue(&spidata->wq, &wait);
 270
 271                 if(signal_pending(current))
 272                         return 0;
 273
 274                 goto retry;
 275         }
 276         spidata->state = state;
 277
 278         return 1;
 279 }
 280
 281 static inline void spiflash_done(void)
 282 {
 283         spidata->state = FL_READY;
 284         spin_unlock_bh(&spidata->mutex);
 285         wake_up(&spidata->wq);
 286 }
 287
 288 static int
 289 spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
 290 {
 291         struct opcodes *ptr_opcode;
 292         u32 temp, reg;
 293
 294         /* sanity checks */
 295         if (instr->addr + instr->len > mtd->size) return (-EINVAL);
 296
 297         if (!spiflash_wait_ready(FL_ERASING))
 298                 return -EINTR;
 299
 300         spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
 301         busy_wait((reg = spiflash_regread32(SPI_FLASH_CTL)) & SPI_CTL_BUSY, 0);
 302         reg = spiflash_regread32(SPI_FLASH_CTL);
 303
 304         ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];
 305         temp = ((__u32)instr->addr << 8) | (__u32)(ptr_opcode->code);
 306         spiflash_regwrite32(SPI_FLASH_OPCODE, temp);
 307
 308         reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START;
 309         spiflash_regwrite32(SPI_FLASH_CTL, reg);
 310
 311         /* this will take some time */
 312         spin_unlock_bh(&spidata->mutex);
 313         msleep(800);
 314         spin_lock_bh(&spidata->mutex);
 315
 316         busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 20);
 317         spiflash_done();
 318
 319         instr->state = MTD_ERASE_DONE;
 320         if (instr->callback) instr->callback (instr);
 321
 322         return 0;
 323 }
 324
 325 static int
 326 spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf)
 327 {
 328         u8 *read_addr;
 329
 330         /* sanity checks */
 331         if (!len) return (0);
 332         if (from + len > mtd->size) return (-EINVAL);
 333
 334         /* we always read len bytes */
 335         *retlen = len;
 336
 337         if (!spiflash_wait_ready(FL_READING))
 338                 return -EINTR;
 339         read_addr = (u8 *)(spidata->readaddr + from);
 340         memcpy(buf, read_addr, len);
 341         spiflash_done();
 342
 343         return 0;
 344 }
 345
 346 static int
 347 spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
 348 {
 349         u32 opcode, bytes_left;
 350
 351         *retlen = 0;
 352
 353         /* sanity checks */
 354         if (!len) return (0);
 355         if (to + len > mtd->size) return (-EINVAL);
 356
 357         opcode = stm_opcodes[SPI_PAGE_PROGRAM].code;
 358         bytes_left = len;
 359
 360         do {
 361                 u32 xact_len, reg, page_offset, spi_data = 0;
 362
 363                 xact_len = MIN(bytes_left, sizeof(__u32));
 364
 365                 /* 32-bit writes cannot span across a page boundary
 366                  * (256 bytes). This types of writes require two page
 367                  * program operations to handle it correctly. The STM part
 368                  * will write the overflow data to the beginning of the
 369                  * current page as opposed to the subsequent page.
 370                  */
 371                 page_offset = (to & (STM_PAGE_SIZE - 1)) + xact_len;
 372
 373                 if (page_offset > STM_PAGE_SIZE) {
 374                         xact_len -= (page_offset - STM_PAGE_SIZE);
 375                 }
 376
 377                 if (!spiflash_wait_ready(FL_WRITING))
 378                         return -EINTR;
 379
 380                 spiflash_sendcmd(SPI_WRITE_ENABLE, 0);
 381                 switch (xact_len) {
 382                         case 1:
 383                                 spi_data = (u32) ((u8) *buf);
 384                                 break;
 385                         case 2:
 386                                 spi_data = (buf[1] << 8) | buf[0];
 387                                 break;
 388                         case 3:
 389                                 spi_data = (buf[2] << 16) | (buf[1] << 8) | buf[0];
 390                                 break;
 391                         case 4:
 392                                 spi_data = (buf[3] << 24) | (buf[2] << 16) |
 393                                                         (buf[1] << 8) | buf[0];
 394                                 break;
 395                         default:
 396                                 spi_data = 0;
 397                                 break;
 398                 }
 399
 400                 spiflash_regwrite32(SPI_FLASH_DATA, spi_data);
 401                 opcode = (opcode & SPI_OPCODE_MASK) | ((__u32)to << 8);
 402                 spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
 403
 404                 reg = spiflash_regread32(SPI_FLASH_CTL);
 405                 reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | (xact_len + 4) | SPI_CTL_START;
 406                 spiflash_regwrite32(SPI_FLASH_CTL, reg);
 407
 408                 /* give the chip some time before we start busy waiting */
 409                 spin_unlock_bh(&spidata->mutex);
 410                 schedule();
 411                 spin_lock_bh(&spidata->mutex);
 412
 413                 busy_wait(spiflash_sendcmd(SPI_RD_STATUS, 0) & SPI_STATUS_WIP, 0);
 414                 spiflash_done();
 415
 416                 bytes_left -= xact_len;
 417                 to += xact_len;
 418                 buf += xact_len;
 419
 420                 *retlen += xact_len;
 421         } while (bytes_left != 0);
 422
 423         return 0;
 424 }
 425
 426
 427 #ifdef CONFIG_MTD_PARTITIONS
 428 static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "MyLoader", NULL };
 429 #endif
 430
 431
 432 static int spiflash_probe(struct platform_device *pdev)
 433 {
 434         int result = -1;
 435         int index, num_parts;
 436         struct mtd_info *mtd;
 437
 438         spidata->mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
 439         spin_lock_init(&spidata->mutex);
 440         init_waitqueue_head(&spidata->wq);
 441         spidata->state = FL_READY;
 442
 443         if (!spidata->mmraddr) {
 444                 printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
 445                 kfree(spidata);
 446                 spidata = NULL;
 447         }
 448
 449         mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
 450         if (!mtd) {
 451                 kfree(spidata);
 452                 return -ENXIO;
 453         }
 454
 455         if (!(index = spiflash_probe_chip())) {
 456         printk (KERN_WARNING SPIFLASH "Found no serial flash device\n");
 457                 goto error;
 458         }
 459
 460         spidata->readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
 461         if (!spidata->readaddr) {
 462                 printk (KERN_WARNING SPIFLASH "Failed to map flash device\n");
 463                 goto error;
 464         }
 465
 466         mtd->name = "spiflash";
 467         mtd->type = MTD_NORFLASH;
 468         mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
 469         mtd->size = flashconfig_tbl[index].byte_cnt;
 470         mtd->erasesize = flashconfig_tbl[index].sector_size;
 471         mtd->writesize = 1;
 472         mtd->numeraseregions = 0;
 473         mtd->eraseregions = NULL;
 474         mtd->erase = spiflash_erase;
 475         mtd->read = spiflash_read;
 476         mtd->write = spiflash_write;
 477         mtd->owner = THIS_MODULE;
 478
 479         /* parse redboot partitions */
 480         num_parts = parse_mtd_partitions(mtd, part_probe_types, &spidata->parsed_parts, 0);
 481         if (!num_parts)
 482                 goto error;
 483
 484         result = add_mtd_partitions(mtd, spidata->parsed_parts, num_parts);
 485         spidata->mtd = mtd;
 486
 487         return (result);
 488
 489 error:
 490         kfree(mtd);
 491         kfree(spidata);
 492         return -ENXIO;
 493 }
 494
 495 static int spiflash_remove (struct platform_device *pdev)
 496 {
 497         del_mtd_partitions (spidata->mtd);
 498         kfree(spidata->mtd);
 499         return 0;
 500 }
 501
 502 struct platform_driver spiflash_driver = {
 503         .driver.name = "spiflash",
 504         .probe = spiflash_probe,
 505         .remove = spiflash_remove,
 506 };
 507
 508 int __init
 509 spiflash_init (void)
 510 {
 511         spidata = kmalloc(sizeof(struct spiflash_data), GFP_KERNEL);
 512         if (!spidata)
 513                 return (-ENXIO);
 514
 515         spin_lock_init(&spidata->mutex);
 516         platform_driver_register(&spiflash_driver);
 517
 518         return 0;
 519 }
 520
 521 void __exit
 522 spiflash_exit (void)
 523 {
 524         kfree(spidata);
 525 }
 526
 527 module_init (spiflash_init);
 528 module_exit (spiflash_exit);
 529
 530 MODULE_LICENSE("GPL");
 531 MODULE_AUTHOR("OpenWrt.org, Atheros Communications Inc");
 532 MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
 533