target/linux/lantiq/patches-2.6.32/100-falcon_header.patch

   1 --- /dev/null
   2 +++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
   3 @@ -0,0 +1,277 @@
   4 +/*
   5 + *   This program is free software; you can redistribute it and/or modify
   6 + *   it under the terms of the GNU General Public License as published by
   7 + *   the Free Software Foundation; either version 2 of the License, or
   8 + *   (at your option) any later version.
   9 + *
  10 + *   This program is distributed in the hope that it will be useful,
  11 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 + *   GNU General Public License for more details.
  14 + *
  15 + *   You should have received a copy of the GNU General Public License
  16 + *   along with this program; if not, write to the Free Software
  17 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  18 + *
  19 + *   Copyright (C) 2010 Lantiq
  20 + */
  21 +#ifndef _FALCON_IRQ__
  22 +#define _FALCON_IRQ__
  23 +
  24 +#define INT_NUM_IRQ0                   8
  25 +#define INT_NUM_IM0_IRL0               (INT_NUM_IRQ0 + 0)
  26 +#define INT_NUM_IM1_IRL0               (INT_NUM_IM0_IRL0 + 32)
  27 +#define INT_NUM_IM2_IRL0               (INT_NUM_IM1_IRL0 + 32)
  28 +#define INT_NUM_IM3_IRL0               (INT_NUM_IM2_IRL0 + 32)
  29 +#define INT_NUM_IM4_IRL0               (INT_NUM_IM3_IRL0 + 32)
  30 +#define INT_NUM_EXTRA_START            (INT_NUM_IM4_IRL0 + 32)
  31 +#define INT_NUM_IM_OFFSET              (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
  32 +
  33 +#define MIPS_CPU_TIMER_IRQ                     7
  34 +
  35 +/* HOST IF Event Interrupt */
  36 +#define FALCON_IRQ_HOST                                (INT_NUM_IM0_IRL0 + 0)
  37 +/* HOST IF Mailbox0 Receive Interrupt */
  38 +#define FALCON_IRQ_HOST_MB0_RX                 (INT_NUM_IM0_IRL0 + 1)
  39 +/* HOST IF Mailbox0 Transmit Interrupt */
  40 +#define FALCON_IRQ_HOST_MB0_TX                 (INT_NUM_IM0_IRL0 + 2)
  41 +/* HOST IF Mailbox1 Receive Interrupt */
  42 +#define FALCON_IRQ_HOST_MB1_RX                 (INT_NUM_IM0_IRL0 + 3)
  43 +/* HOST IF Mailbox1 Transmit Interrupt */
  44 +#define FALCON_IRQ_HOST_MB1_TX                 (INT_NUM_IM0_IRL0 + 4)
  45 +/* I2C Last Single Data Transfer Request */
  46 +#define FALCON_IRQ_I2C_LSREQ                   (INT_NUM_IM0_IRL0 + 8)
  47 +/* I2C Single Data Transfer Request */
  48 +#define FALCON_IRQ_I2C_SREQ                    (INT_NUM_IM0_IRL0 + 9)
  49 +/* I2C Last Burst Data Transfer Request */
  50 +#define FALCON_IRQ_I2C_LBREQ                   (INT_NUM_IM0_IRL0 + 10)
  51 +/* I2C Burst Data Transfer Request */
  52 +#define FALCON_IRQ_I2C_BREQ                    (INT_NUM_IM0_IRL0 + 11)
  53 +/* I2C Error Interrupt */
  54 +#define FALCON_IRQ_I2C_I2C_ERR                 (INT_NUM_IM0_IRL0 + 12)
  55 +/* I2C Protocol Interrupt */
  56 +#define FALCON_IRQ_I2C_I2C_P                   (INT_NUM_IM0_IRL0 + 13)
  57 +/* SSC Transmit Interrupt */
  58 +#define FALCON_IRQ_SSC_T                       (INT_NUM_IM0_IRL0 + 14)
  59 +/* SSC Receive Interrupt */
  60 +#define FALCON_IRQ_SSC_R                       (INT_NUM_IM0_IRL0 + 15)
  61 +/* SSC Error Interrupt */
  62 +#define FALCON_IRQ_SSC_E                       (INT_NUM_IM0_IRL0 + 16)
  63 +/* SSC Frame Interrupt */
  64 +#define FALCON_IRQ_SSC_F                       (INT_NUM_IM0_IRL0 + 17)
  65 +/* Advanced Encryption Standard Interrupt */
  66 +#define FALCON_IRQ_AES_AES                     (INT_NUM_IM0_IRL0 + 27)
  67 +/* Secure Hash Algorithm Interrupt */
  68 +#define FALCON_IRQ_SHA_HASH                    (INT_NUM_IM0_IRL0 + 28)
  69 +/* PCM Receive Interrupt */
  70 +#define FALCON_IRQ_PCM_RX                      (INT_NUM_IM0_IRL0 + 29)
  71 +/* PCM Transmit Interrupt */
  72 +#define FALCON_IRQ_PCM_TX                      (INT_NUM_IM0_IRL0 + 30)
  73 +/* PCM Transmit Crash Interrupt */
  74 +#define FALCON_IRQ_PCM_HW2_CRASH               (INT_NUM_IM0_IRL0 + 31)
  75 +
  76 +/* EBU Serial Flash Command Error */
  77 +#define FALCON_IRQ_EBU_SF_CMDERR               (INT_NUM_IM1_IRL0 + 0)
  78 +/* EBU Serial Flash Command Overwrite Error */
  79 +#define FALCON_IRQ_EBU_SF_COVERR               (INT_NUM_IM1_IRL0 + 1)
  80 +/* EBU Serial Flash Busy */
  81 +#define FALCON_IRQ_EBU_SF_BUSY                 (INT_NUM_IM1_IRL0 + 2)
  82 +/* External Interrupt from GPIO P0 */
  83 +#define FALCON_IRQ_GPIO_P0                     (INT_NUM_IM1_IRL0 + 4)
  84 +/* External Interrupt from GPIO P1 */
  85 +#define FALCON_IRQ_GPIO_P1                     (INT_NUM_IM1_IRL0 + 5)
  86 +/* External Interrupt from GPIO P2 */
  87 +#define FALCON_IRQ_GPIO_P2                     (INT_NUM_IM1_IRL0 + 6)
  88 +/* External Interrupt from GPIO P3 */
  89 +#define FALCON_IRQ_GPIO_P3                     (INT_NUM_IM1_IRL0 + 7)
  90 +/* External Interrupt from GPIO P4 */
  91 +#define FALCON_IRQ_GPIO_P4                     (INT_NUM_IM1_IRL0 + 8)
  92 +/* 8kHz backup interrupt derived from core-PLL */
  93 +#define FALCON_IRQ_FSC_BKP                     (INT_NUM_IM1_IRL0 + 10)
  94 +/* FSC Timer Interrupt 0 */
  95 +#define FALCON_IRQ_FSCT_CMP0                   (INT_NUM_IM1_IRL0 + 11)
  96 +/* FSC Timer Interrupt 1 */
  97 +#define FALCON_IRQ_FSCT_CMP1                   (INT_NUM_IM1_IRL0 + 12)
  98 +/* 8kHz root interrupt derived from GPON interface */
  99 +#define FALCON_IRQ_FSC_ROOT                    (INT_NUM_IM1_IRL0 + 13)
 100 +/* Time of Day */
 101 +#define FALCON_IRQ_TOD                         (INT_NUM_IM1_IRL0 + 14)
 102 +/* PMA Interrupt from IntNode of the 200MHz Domain */
 103 +#define FALCON_IRQ_PMA_200M                    (INT_NUM_IM1_IRL0 + 15)
 104 +/* PMA Interrupt from IntNode of the TX Clk Domain */
 105 +#define FALCON_IRQ_PMA_TX                      (INT_NUM_IM1_IRL0 + 16)
 106 +/* PMA Interrupt from IntNode of the RX Clk Domain */
 107 +#define FALCON_IRQ_PMA_RX                      (INT_NUM_IM1_IRL0 + 17)
 108 +/* SYS1 Interrupt */
 109 +#define FALCON_IRQ_SYS1                                (INT_NUM_IM1_IRL0 + 20)
 110 +/* SYS GPE Interrupt */
 111 +#define FALCON_IRQ_SYS_GPE                     (INT_NUM_IM1_IRL0 + 21)
 112 +/* Watchdog Access Error Interrupt */
 113 +#define FALCON_IRQ_WDT_AEIR                    (INT_NUM_IM1_IRL0 + 24)
 114 +/* Watchdog Prewarning Interrupt */
 115 +#define FALCON_IRQ_WDT_PIR                     (INT_NUM_IM1_IRL0 + 25)
 116 +/* SBIU interrupt */
 117 +#define FALCON_IRQ_SBIU0                       (INT_NUM_IM1_IRL0 + 27)
 118 +/* FPI Bus Control Unit Interrupt */
 119 +#define FALCON_IRQ_BCU0                                (INT_NUM_IM1_IRL0 + 29)
 120 +/* DDR Controller Interrupt */
 121 +#define FALCON_IRQ_DDR                         (INT_NUM_IM1_IRL0 + 30)
 122 +/* Crossbar Error Interrupt */
 123 +#define FALCON_IRQ_XBAR_ERROR                  (INT_NUM_IM1_IRL0 + 31)
 124 +
 125 +/* ICTRLL 0 Interrupt */
 126 +#define FALCON_IRQ_ICTRLL0                     (INT_NUM_IM2_IRL0 + 0)
 127 +/* ICTRLL 1 Interrupt */
 128 +#define FALCON_IRQ_ICTRLL1                     (INT_NUM_IM2_IRL0 + 1)
 129 +/* ICTRLL 2 Interrupt */
 130 +#define FALCON_IRQ_ICTRLL2                     (INT_NUM_IM2_IRL0 + 2)
 131 +/* ICTRLL 3 Interrupt */
 132 +#define FALCON_IRQ_ICTRLL3                     (INT_NUM_IM2_IRL0 + 3)
 133 +/* OCTRLL 0 Interrupt */
 134 +#define FALCON_IRQ_OCTRLL0                     (INT_NUM_IM2_IRL0 + 4)
 135 +/* OCTRLL 1 Interrupt */
 136 +#define FALCON_IRQ_OCTRLL1                     (INT_NUM_IM2_IRL0 + 5)
 137 +/* OCTRLL 2 Interrupt */
 138 +#define FALCON_IRQ_OCTRLL2                     (INT_NUM_IM2_IRL0 + 6)
 139 +/* OCTRLL 3 Interrupt */
 140 +#define FALCON_IRQ_OCTRLL3                     (INT_NUM_IM2_IRL0 + 7)
 141 +/* OCTRLG Interrupt */
 142 +#define FALCON_IRQ_OCTRLG                      (INT_NUM_IM2_IRL0 + 9)
 143 +/* IQM Interrupt */
 144 +#define FALCON_IRQ_IQM                         (INT_NUM_IM2_IRL0 + 10)
 145 +/* FSQM Interrupt */
 146 +#define FALCON_IRQ_FSQM                                (INT_NUM_IM2_IRL0 + 11)
 147 +/* TMU Interrupt */
 148 +#define FALCON_IRQ_TMU                         (INT_NUM_IM2_IRL0 + 12)
 149 +/* LINK1 Interrupt */
 150 +#define FALCON_IRQ_LINK1                       (INT_NUM_IM2_IRL0 + 14)
 151 +/* ICTRLC 0 Interrupt */
 152 +#define FALCON_IRQ_ICTRLC0                     (INT_NUM_IM2_IRL0 + 16)
 153 +/* ICTRLC 1 Interrupt */
 154 +#define FALCON_IRQ_ICTRLC1                     (INT_NUM_IM2_IRL0 + 17)
 155 +/* OCTRLC Interrupt */
 156 +#define FALCON_IRQ_OCTRLC                      (INT_NUM_IM2_IRL0 + 18)
 157 +/* CONFIG Break Interrupt */
 158 +#define FALCON_IRQ_CONFIG_BREAK                        (INT_NUM_IM2_IRL0 + 19)
 159 +/* CONFIG Interrupt */
 160 +#define FALCON_IRQ_CONFIG                      (INT_NUM_IM2_IRL0 + 20)
 161 +/* Dispatcher Interrupt */
 162 +#define FALCON_IRQ_DISP                                (INT_NUM_IM2_IRL0 + 21)
 163 +/* TBM Interrupt */
 164 +#define FALCON_IRQ_TBM                         (INT_NUM_IM2_IRL0 + 22)
 165 +/* GTC Downstream Interrupt */
 166 +#define FALCON_IRQ_GTC_DS                      (INT_NUM_IM2_IRL0 + 29)
 167 +/* GTC Upstream Interrupt */
 168 +#define FALCON_IRQ_GTC_US                      (INT_NUM_IM2_IRL0 + 30)
 169 +/* EIM Interrupt */
 170 +#define FALCON_IRQ_EIM                         (INT_NUM_IM2_IRL0 + 31)
 171 +
 172 +/* ASC0 Transmit Interrupt */
 173 +#define FALCON_IRQ_ASC0_T                      (INT_NUM_IM3_IRL0 + 0)
 174 +/* ASC0 Receive Interrupt */
 175 +#define FALCON_IRQ_ASC0_R                      (INT_NUM_IM3_IRL0 + 1)
 176 +/* ASC0 Error Interrupt */
 177 +#define FALCON_IRQ_ASC0_E                      (INT_NUM_IM3_IRL0 + 2)
 178 +/* ASC0 Transmit Buffer Interrupt */
 179 +#define FALCON_IRQ_ASC0_TB                     (INT_NUM_IM3_IRL0 + 3)
 180 +/* ASC0 Autobaud Start Interrupt */
 181 +#define FALCON_IRQ_ASC0_ABST                   (INT_NUM_IM3_IRL0 + 4)
 182 +/* ASC0 Autobaud Detection Interrupt */
 183 +#define FALCON_IRQ_ASC0_ABDET                  (INT_NUM_IM3_IRL0 + 5)
 184 +/* ASC1 Modem Status Interrupt */
 185 +#define FALCON_IRQ_ASC0_MS                     (INT_NUM_IM3_IRL0 + 6)
 186 +/* ASC0 Soft Flow Control Interrupt */
 187 +#define FALCON_IRQ_ASC0_SFC                    (INT_NUM_IM3_IRL0 + 7)
 188 +/* ASC1 Transmit Interrupt */
 189 +#define FALCON_IRQ_ASC1_T                      (INT_NUM_IM3_IRL0 + 8)
 190 +/* ASC1 Receive Interrupt */
 191 +#define FALCON_IRQ_ASC1_R                      (INT_NUM_IM3_IRL0 + 9)
 192 +/* ASC1 Error Interrupt */
 193 +#define FALCON_IRQ_ASC1_E                      (INT_NUM_IM3_IRL0 + 10)
 194 +/* ASC1 Transmit Buffer Interrupt */
 195 +#define FALCON_IRQ_ASC1_TB                     (INT_NUM_IM3_IRL0 + 11)
 196 +/* ASC1 Autobaud Start Interrupt */
 197 +#define FALCON_IRQ_ASC1_ABST                   (INT_NUM_IM3_IRL0 + 12)
 198 +/* ASC1 Autobaud Detection Interrupt */
 199 +#define FALCON_IRQ_ASC1_ABDET                  (INT_NUM_IM3_IRL0 + 13)
 200 +/* ASC1 Modem Status Interrupt */
 201 +#define FALCON_IRQ_ASC1_MS                     (INT_NUM_IM3_IRL0 + 14)
 202 +/* ASC1 Soft Flow Control Interrupt */
 203 +#define FALCON_IRQ_ASC1_SFC                    (INT_NUM_IM3_IRL0 + 15)
 204 +/* GPTC Timer/Counter 1A Interrupt */
 205 +#define FALCON_IRQ_GPTC_TC1A                   (INT_NUM_IM3_IRL0 + 16)
 206 +/* GPTC Timer/Counter 1B Interrupt */
 207 +#define FALCON_IRQ_GPTC_TC1B                   (INT_NUM_IM3_IRL0 + 17)
 208 +/* GPTC Timer/Counter 2A Interrupt */
 209 +#define FALCON_IRQ_GPTC_TC2A                   (INT_NUM_IM3_IRL0 + 18)
 210 +/* GPTC Timer/Counter 2B Interrupt */
 211 +#define FALCON_IRQ_GPTC_TC2B                   (INT_NUM_IM3_IRL0 + 19)
 212 +/* GPTC Timer/Counter 3A Interrupt */
 213 +#define FALCON_IRQ_GPTC_TC3A                   (INT_NUM_IM3_IRL0 + 20)
 214 +/* GPTC Timer/Counter 3B Interrupt */
 215 +#define FALCON_IRQ_GPTC_TC3B                   (INT_NUM_IM3_IRL0 + 21)
 216 +/* DFEV0, Channel 1 Transmit Interrupt */
 217 +#define FALCON_IRQ_DFEV0_2TX                   (INT_NUM_IM3_IRL0 + 26)
 218 +/* DFEV0, Channel 1 Receive Interrupt */
 219 +#define FALCON_IRQ_DFEV0_2RX                   (INT_NUM_IM3_IRL0 + 27)
 220 +/* DFEV0, Channel 1 General Purpose Interrupt */
 221 +#define FALCON_IRQ_DFEV0_2GP                   (INT_NUM_IM3_IRL0 + 28)
 222 +/* DFEV0, Channel 0 Transmit Interrupt */
 223 +#define FALCON_IRQ_DFEV0_1TX                   (INT_NUM_IM3_IRL0 + 29)
 224 +/* DFEV0, Channel 0 Receive Interrupt */
 225 +#define FALCON_IRQ_DFEV0_1RX                   (INT_NUM_IM3_IRL0 + 30)
 226 +/* DFEV0, Channel 0 General Purpose Interrupt */
 227 +#define FALCON_IRQ_DFEV0_1GP                   (INT_NUM_IM3_IRL0 + 31)
 228 +
 229 +/* ICTRLL 0 Error */
 230 +#define FALCON_IRQ_ICTRLL0_ERR                 (INT_NUM_IM4_IRL0 + 0)
 231 +/* ICTRLL 1 Error */
 232 +#define FALCON_IRQ_ICTRLL1_ERR                 (INT_NUM_IM4_IRL0 + 1)
 233 +/* ICTRLL 2 Error */
 234 +#define FALCON_IRQ_ICTRLL2_ERR                 (INT_NUM_IM4_IRL0 + 2)
 235 +/* ICTRLL 3 Error */
 236 +#define FALCON_IRQ_ICTRLL3_ERR                 (INT_NUM_IM4_IRL0 + 3)
 237 +/* OCTRLL 0 Error */
 238 +#define FALCON_IRQ_OCTRLL0_ERR                 (INT_NUM_IM4_IRL0 + 4)
 239 +/* OCTRLL 1 Error */
 240 +#define FALCON_IRQ_OCTRLL1_ERR                 (INT_NUM_IM4_IRL0 + 5)
 241 +/* OCTRLL 2 Error */
 242 +#define FALCON_IRQ_OCTRLL2_ERR                 (INT_NUM_IM4_IRL0 + 6)
 243 +/* OCTRLL 3 Error */
 244 +#define FALCON_IRQ_OCTRLL3_ERR                 (INT_NUM_IM4_IRL0 + 7)
 245 +/* ICTRLG Error */
 246 +#define FALCON_IRQ_ICTRLG_ERR                  (INT_NUM_IM4_IRL0 + 8)
 247 +/* OCTRLG Error */
 248 +#define FALCON_IRQ_OCTRLG_ERR                  (INT_NUM_IM4_IRL0 + 9)
 249 +/* IQM Error */
 250 +#define FALCON_IRQ_IQM_ERR                     (INT_NUM_IM4_IRL0 + 10)
 251 +/* FSQM Error */
 252 +#define FALCON_IRQ_FSQM_ERR                    (INT_NUM_IM4_IRL0 + 11)
 253 +/* TMU Error */
 254 +#define FALCON_IRQ_TMU_ERR                     (INT_NUM_IM4_IRL0 + 12)
 255 +/* MPS Status Interrupt #0 (VPE1 to VPE0) */
 256 +#define FALCON_IRQ_MPS_IR0                     (INT_NUM_IM4_IRL0 + 14)
 257 +/* MPS Status Interrupt #1 (VPE1 to VPE0) */
 258 +#define FALCON_IRQ_MPS_IR1                     (INT_NUM_IM4_IRL0 + 15)
 259 +/* MPS Status Interrupt #2 (VPE1 to VPE0) */
 260 +#define FALCON_IRQ_MPS_IR2                     (INT_NUM_IM4_IRL0 + 16)
 261 +/* MPS Status Interrupt #3 (VPE1 to VPE0) */
 262 +#define FALCON_IRQ_MPS_IR3                     (INT_NUM_IM4_IRL0 + 17)
 263 +/* MPS Status Interrupt #4 (VPE1 to VPE0) */
 264 +#define FALCON_IRQ_MPS_IR4                     (INT_NUM_IM4_IRL0 + 18)
 265 +/* MPS Status Interrupt #5 (VPE1 to VPE0) */
 266 +#define FALCON_IRQ_MPS_IR5                     (INT_NUM_IM4_IRL0 + 19)
 267 +/* MPS Status Interrupt #6 (VPE1 to VPE0) */
 268 +#define FALCON_IRQ_MPS_IR6                     (INT_NUM_IM4_IRL0 + 20)
 269 +/* MPS Status Interrupt #7 (VPE1 to VPE0) */
 270 +#define FALCON_IRQ_MPS_IR7                     (INT_NUM_IM4_IRL0 + 21)
 271 +/* MPS Status Interrupt #8 (VPE1 to VPE0) */
 272 +#define FALCON_IRQ_MPS_IR8                     (INT_NUM_IM4_IRL0 + 22)
 273 +/* VPE0 Exception Level Flag Interrupt */
 274 +#define FALCON_IRQ_VPE0_EXL                    (INT_NUM_IM4_IRL0 + 29)
 275 +/* VPE0 Error Level Flag Interrupt */
 276 +#define FALCON_IRQ_VPE0_ERL                    (INT_NUM_IM4_IRL0 + 30)
 277 +/* VPE0 Performance Monitoring Counter Interrupt */
 278 +#define FALCON_IRQ_VPE0_PMCIR                  (INT_NUM_IM4_IRL0 + 31)
 279 +
 280 +#endif /* _FALCON_IRQ__ */
 281 --- /dev/null
 282 +++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h
 283 @@ -0,0 +1,376 @@
 284 +/******************************************************************************
 285 +
 286 +                               Copyright (c) 2010
 287 +                            Lantiq Deutschland GmbH
 288 +
 289 +  For licensing information, see the file 'LICENSE' in the root folder of
 290 +  this software module.
 291 +
 292 +******************************************************************************/
 293 +
 294 +#ifndef _gpon_reg_base_h
 295 +#define _gpon_reg_base_h
 296 +
 297 +/** \addtogroup GPON_BASE
 298 +   @{
 299 +*/
 300 +
 301 +#ifndef KSEG1
 302 +#define KSEG1 0xA0000000
 303 +#endif
 304 +
 305 +/** address range for ebu
 306 +    0x18000000--0x180000FF */
 307 +#define GPON_EBU_BASE          (KSEG1 | 0x18000000)
 308 +#define GPON_EBU_END           (KSEG1 | 0x180000FF)
 309 +#define GPON_EBU_SIZE          0x00000100
 310 +/** address range for gpearb
 311 +    0x1D400100--0x1D4001FF */
 312 +#define GPON_GPEARB_BASE               (KSEG1 | 0x1D400100)
 313 +#define GPON_GPEARB_END                (KSEG1 | 0x1D4001FF)
 314 +#define GPON_GPEARB_SIZE               0x00000100
 315 +/** address range for tmu
 316 +    0x1D404000--0x1D404FFF */
 317 +#define GPON_TMU_BASE          (KSEG1 | 0x1D404000)
 318 +#define GPON_TMU_END           (KSEG1 | 0x1D404FFF)
 319 +#define GPON_TMU_SIZE          0x00001000
 320 +/** address range for iqm
 321 +    0x1D410000--0x1D41FFFF */
 322 +#define GPON_IQM_BASE          (KSEG1 | 0x1D410000)
 323 +#define GPON_IQM_END           (KSEG1 | 0x1D41FFFF)
 324 +#define GPON_IQM_SIZE          0x00010000
 325 +/** address range for octrlg
 326 +    0x1D420000--0x1D42FFFF */
 327 +#define GPON_OCTRLG_BASE               (KSEG1 | 0x1D420000)
 328 +#define GPON_OCTRLG_END                (KSEG1 | 0x1D42FFFF)
 329 +#define GPON_OCTRLG_SIZE               0x00010000
 330 +/** address range for octrll0
 331 +    0x1D440000--0x1D4400FF */
 332 +#define GPON_OCTRLL0_BASE              (KSEG1 | 0x1D440000)
 333 +#define GPON_OCTRLL0_END               (KSEG1 | 0x1D4400FF)
 334 +#define GPON_OCTRLL0_SIZE              0x00000100
 335 +/** address range for octrll1
 336 +    0x1D440100--0x1D4401FF */
 337 +#define GPON_OCTRLL1_BASE              (KSEG1 | 0x1D440100)
 338 +#define GPON_OCTRLL1_END               (KSEG1 | 0x1D4401FF)
 339 +#define GPON_OCTRLL1_SIZE              0x00000100
 340 +/** address range for octrll2
 341 +    0x1D440200--0x1D4402FF */
 342 +#define GPON_OCTRLL2_BASE              (KSEG1 | 0x1D440200)
 343 +#define GPON_OCTRLL2_END               (KSEG1 | 0x1D4402FF)
 344 +#define GPON_OCTRLL2_SIZE              0x00000100
 345 +/** address range for octrll3
 346 +    0x1D440300--0x1D4403FF */
 347 +#define GPON_OCTRLL3_BASE              (KSEG1 | 0x1D440300)
 348 +#define GPON_OCTRLL3_END               (KSEG1 | 0x1D4403FF)
 349 +#define GPON_OCTRLL3_SIZE              0x00000100
 350 +/** address range for octrlc
 351 +    0x1D441000--0x1D4410FF */
 352 +#define GPON_OCTRLC_BASE               (KSEG1 | 0x1D441000)
 353 +#define GPON_OCTRLC_END                (KSEG1 | 0x1D4410FF)
 354 +#define GPON_OCTRLC_SIZE               0x00000100
 355 +/** address range for ictrlg
 356 +    0x1D450000--0x1D45FFFF */
 357 +#define GPON_ICTRLG_BASE               (KSEG1 | 0x1D450000)
 358 +#define GPON_ICTRLG_END                (KSEG1 | 0x1D45FFFF)
 359 +#define GPON_ICTRLG_SIZE               0x00010000
 360 +/** address range for ictrll0
 361 +    0x1D460000--0x1D4601FF */
 362 +#define GPON_ICTRLL0_BASE              (KSEG1 | 0x1D460000)
 363 +#define GPON_ICTRLL0_END               (KSEG1 | 0x1D4601FF)
 364 +#define GPON_ICTRLL0_SIZE              0x00000200
 365 +/** address range for ictrll1
 366 +    0x1D460200--0x1D4603FF */
 367 +#define GPON_ICTRLL1_BASE              (KSEG1 | 0x1D460200)
 368 +#define GPON_ICTRLL1_END               (KSEG1 | 0x1D4603FF)
 369 +#define GPON_ICTRLL1_SIZE              0x00000200
 370 +/** address range for ictrll2
 371 +    0x1D460400--0x1D4605FF */
 372 +#define GPON_ICTRLL2_BASE              (KSEG1 | 0x1D460400)
 373 +#define GPON_ICTRLL2_END               (KSEG1 | 0x1D4605FF)
 374 +#define GPON_ICTRLL2_SIZE              0x00000200
 375 +/** address range for ictrll3
 376 +    0x1D460600--0x1D4607FF */
 377 +#define GPON_ICTRLL3_BASE              (KSEG1 | 0x1D460600)
 378 +#define GPON_ICTRLL3_END               (KSEG1 | 0x1D4607FF)
 379 +#define GPON_ICTRLL3_SIZE              0x00000200
 380 +/** address range for ictrlc0
 381 +    0x1D461000--0x1D4610FF */
 382 +#define GPON_ICTRLC0_BASE              (KSEG1 | 0x1D461000)
 383 +#define GPON_ICTRLC0_END               (KSEG1 | 0x1D4610FF)
 384 +#define GPON_ICTRLC0_SIZE              0x00000100
 385 +/** address range for ictrlc1
 386 +    0x1D461100--0x1D4611FF */
 387 +#define GPON_ICTRLC1_BASE              (KSEG1 | 0x1D461100)
 388 +#define GPON_ICTRLC1_END               (KSEG1 | 0x1D4611FF)
 389 +#define GPON_ICTRLC1_SIZE              0x00000100
 390 +/** address range for fsqm
 391 +    0x1D500000--0x1D5FFFFF */
 392 +#define GPON_FSQM_BASE         (KSEG1 | 0x1D500000)
 393 +#define GPON_FSQM_END          (KSEG1 | 0x1D5FFFFF)
 394 +#define GPON_FSQM_SIZE         0x00100000
 395 +/** address range for pctrl
 396 +    0x1D600000--0x1D6001FF */
 397 +#define GPON_PCTRL_BASE                (KSEG1 | 0x1D600000)
 398 +#define GPON_PCTRL_END         (KSEG1 | 0x1D6001FF)
 399 +#define GPON_PCTRL_SIZE                0x00000200
 400 +/** address range for link0
 401 +    0x1D600200--0x1D6002FF */
 402 +#define GPON_LINK0_BASE                (KSEG1 | 0x1D600200)
 403 +#define GPON_LINK0_END         (KSEG1 | 0x1D6002FF)
 404 +#define GPON_LINK0_SIZE                0x00000100
 405 +/** address range for link1
 406 +    0x1D600300--0x1D6003FF */
 407 +#define GPON_LINK1_BASE                (KSEG1 | 0x1D600300)
 408 +#define GPON_LINK1_END         (KSEG1 | 0x1D6003FF)
 409 +#define GPON_LINK1_SIZE                0x00000100
 410 +/** address range for link2
 411 +    0x1D600400--0x1D6004FF */
 412 +#define GPON_LINK2_BASE                (KSEG1 | 0x1D600400)
 413 +#define GPON_LINK2_END         (KSEG1 | 0x1D6004FF)
 414 +#define GPON_LINK2_SIZE                0x00000100
 415 +/** address range for disp
 416 +    0x1D600500--0x1D6005FF */
 417 +#define GPON_DISP_BASE         (KSEG1 | 0x1D600500)
 418 +#define GPON_DISP_END          (KSEG1 | 0x1D6005FF)
 419 +#define GPON_DISP_SIZE         0x00000100
 420 +/** address range for merge
 421 +    0x1D600600--0x1D6006FF */
 422 +#define GPON_MERGE_BASE                (KSEG1 | 0x1D600600)
 423 +#define GPON_MERGE_END         (KSEG1 | 0x1D6006FF)
 424 +#define GPON_MERGE_SIZE                0x00000100
 425 +/** address range for tbm
 426 +    0x1D600700--0x1D6007FF */
 427 +#define GPON_TBM_BASE          (KSEG1 | 0x1D600700)
 428 +#define GPON_TBM_END           (KSEG1 | 0x1D6007FF)
 429 +#define GPON_TBM_SIZE          0x00000100
 430 +/** address range for pe0
 431 +    0x1D610000--0x1D61FFFF */
 432 +#define GPON_PE0_BASE          (KSEG1 | 0x1D610000)
 433 +#define GPON_PE0_END           (KSEG1 | 0x1D61FFFF)
 434 +#define GPON_PE0_SIZE          0x00010000
 435 +/** address range for pe1
 436 +    0x1D620000--0x1D62FFFF */
 437 +#define GPON_PE1_BASE          (KSEG1 | 0x1D620000)
 438 +#define GPON_PE1_END           (KSEG1 | 0x1D62FFFF)
 439 +#define GPON_PE1_SIZE          0x00010000
 440 +/** address range for pe2
 441 +    0x1D630000--0x1D63FFFF */
 442 +#define GPON_PE2_BASE          (KSEG1 | 0x1D630000)
 443 +#define GPON_PE2_END           (KSEG1 | 0x1D63FFFF)
 444 +#define GPON_PE2_SIZE          0x00010000
 445 +/** address range for pe3
 446 +    0x1D640000--0x1D64FFFF */
 447 +#define GPON_PE3_BASE          (KSEG1 | 0x1D640000)
 448 +#define GPON_PE3_END           (KSEG1 | 0x1D64FFFF)
 449 +#define GPON_PE3_SIZE          0x00010000
 450 +/** address range for pe4
 451 +    0x1D650000--0x1D65FFFF */
 452 +#define GPON_PE4_BASE          (KSEG1 | 0x1D650000)
 453 +#define GPON_PE4_END           (KSEG1 | 0x1D65FFFF)
 454 +#define GPON_PE4_SIZE          0x00010000
 455 +/** address range for pe5
 456 +    0x1D660000--0x1D66FFFF */
 457 +#define GPON_PE5_BASE          (KSEG1 | 0x1D660000)
 458 +#define GPON_PE5_END           (KSEG1 | 0x1D66FFFF)
 459 +#define GPON_PE5_SIZE          0x00010000
 460 +/** address range for sys_gpe
 461 +    0x1D700000--0x1D7000FF */
 462 +#define GPON_SYS_GPE_BASE              (KSEG1 | 0x1D700000)
 463 +#define GPON_SYS_GPE_END               (KSEG1 | 0x1D7000FF)
 464 +#define GPON_SYS_GPE_SIZE              0x00000100
 465 +/** address range for eim
 466 +    0x1D800000--0x1D800FFF */
 467 +#define GPON_EIM_BASE          (KSEG1 | 0x1D800000)
 468 +#define GPON_EIM_END           (KSEG1 | 0x1D800FFF)
 469 +#define GPON_EIM_SIZE          0x00001000
 470 +/** address range for sxgmii
 471 +    0x1D808800--0x1D8088FF */
 472 +#define GPON_SXGMII_BASE               (KSEG1 | 0x1D808800)
 473 +#define GPON_SXGMII_END                (KSEG1 | 0x1D8088FF)
 474 +#define GPON_SXGMII_SIZE               0x00000100
 475 +/** address range for sgmii
 476 +    0x1D808C00--0x1D808CFF */
 477 +#define GPON_SGMII_BASE                (KSEG1 | 0x1D808C00)
 478 +#define GPON_SGMII_END         (KSEG1 | 0x1D808CFF)
 479 +#define GPON_SGMII_SIZE                0x00000100
 480 +/** address range for gpio0
 481 +    0x1D810000--0x1D81007F */
 482 +#define GPON_GPIO0_BASE                (KSEG1 | 0x1D810000)
 483 +#define GPON_GPIO0_END         (KSEG1 | 0x1D81007F)
 484 +#define GPON_GPIO0_SIZE                0x00000080
 485 +/** address range for gpio2
 486 +    0x1D810100--0x1D81017F */
 487 +#define GPON_GPIO2_BASE                (KSEG1 | 0x1D810100)
 488 +#define GPON_GPIO2_END         (KSEG1 | 0x1D81017F)
 489 +#define GPON_GPIO2_SIZE                0x00000080
 490 +/** address range for sys_eth
 491 +    0x1DB00000--0x1DB000FF */
 492 +#define GPON_SYS_ETH_BASE              (KSEG1 | 0x1DB00000)
 493 +#define GPON_SYS_ETH_END               (KSEG1 | 0x1DB000FF)
 494 +#define GPON_SYS_ETH_SIZE              0x00000100
 495 +/** address range for padctrl0
 496 +    0x1DB01000--0x1DB010FF */
 497 +#define GPON_PADCTRL0_BASE             (KSEG1 | 0x1DB01000)
 498 +#define GPON_PADCTRL0_END              (KSEG1 | 0x1DB010FF)
 499 +#define GPON_PADCTRL0_SIZE             0x00000100
 500 +/** address range for padctrl2
 501 +    0x1DB02000--0x1DB020FF */
 502 +#define GPON_PADCTRL2_BASE             (KSEG1 | 0x1DB02000)
 503 +#define GPON_PADCTRL2_END              (KSEG1 | 0x1DB020FF)
 504 +#define GPON_PADCTRL2_SIZE             0x00000100
 505 +/** address range for gtc
 506 +    0x1DC05000--0x1DC052D4 */
 507 +#define GPON_GTC_BASE          (KSEG1 | 0x1DC05000)
 508 +#define GPON_GTC_END           (KSEG1 | 0x1DC052D4)
 509 +#define GPON_GTC_SIZE          0x000002D5
 510 +/** address range for pma
 511 +    0x1DD00000--0x1DD003FF */
 512 +#define GPON_PMA_BASE          (KSEG1 | 0x1DD00000)
 513 +#define GPON_PMA_END           (KSEG1 | 0x1DD003FF)
 514 +#define GPON_PMA_SIZE          0x00000400
 515 +/** address range for fcsic
 516 +    0x1DD00600--0x1DD0061F */
 517 +#define GPON_FCSIC_BASE                (KSEG1 | 0x1DD00600)
 518 +#define GPON_FCSIC_END         (KSEG1 | 0x1DD0061F)
 519 +#define GPON_FCSIC_SIZE                0x00000020
 520 +/** address range for pma_int200
 521 +    0x1DD00700--0x1DD0070F */
 522 +#define GPON_PMA_INT200_BASE           (KSEG1 | 0x1DD00700)
 523 +#define GPON_PMA_INT200_END            (KSEG1 | 0x1DD0070F)
 524 +#define GPON_PMA_INT200_SIZE           0x00000010
 525 +/** address range for pma_inttx
 526 +    0x1DD00720--0x1DD0072F */
 527 +#define GPON_PMA_INTTX_BASE            (KSEG1 | 0x1DD00720)
 528 +#define GPON_PMA_INTTX_END             (KSEG1 | 0x1DD0072F)
 529 +#define GPON_PMA_INTTX_SIZE            0x00000010
 530 +/** address range for pma_intrx
 531 +    0x1DD00740--0x1DD0074F */
 532 +#define GPON_PMA_INTRX_BASE            (KSEG1 | 0x1DD00740)
 533 +#define GPON_PMA_INTRX_END             (KSEG1 | 0x1DD0074F)
 534 +#define GPON_PMA_INTRX_SIZE            0x00000010
 535 +/** address range for gtc_pma
 536 +    0x1DEFFF00--0x1DEFFFFF */
 537 +#define GPON_GTC_PMA_BASE              (KSEG1 | 0x1DEFFF00)
 538 +#define GPON_GTC_PMA_END               (KSEG1 | 0x1DEFFFFF)
 539 +#define GPON_GTC_PMA_SIZE              0x00000100
 540 +/** address range for sys
 541 +    0x1DF00000--0x1DF000FF */
 542 +#define GPON_SYS_BASE          (KSEG1 | 0x1DF00000)
 543 +#define GPON_SYS_END           (KSEG1 | 0x1DF000FF)
 544 +#define GPON_SYS_SIZE          0x00000100
 545 +/** address range for asc1
 546 +    0x1E100B00--0x1E100BFF */
 547 +#define GPON_ASC1_BASE         (KSEG1 | 0x1E100B00)
 548 +#define GPON_ASC1_END          (KSEG1 | 0x1E100BFF)
 549 +#define GPON_ASC1_SIZE         0x00000100
 550 +/** address range for asc0
 551 +    0x1E100C00--0x1E100CFF */
 552 +#define GPON_ASC0_BASE         (KSEG1 | 0x1E100C00)
 553 +#define GPON_ASC0_END          (KSEG1 | 0x1E100CFF)
 554 +#define GPON_ASC0_SIZE         0x00000100
 555 +/** address range for i2c
 556 +    0x1E200000--0x1E20FFFF */
 557 +#define GPON_I2C_BASE          (KSEG1 | 0x1E200000)
 558 +#define GPON_I2C_END           (KSEG1 | 0x1E20FFFF)
 559 +#define GPON_I2C_SIZE          0x00010000
 560 +/** address range for gpio1
 561 +    0x1E800100--0x1E80017F */
 562 +#define GPON_GPIO1_BASE                (KSEG1 | 0x1E800100)
 563 +#define GPON_GPIO1_END         (KSEG1 | 0x1E80017F)
 564 +#define GPON_GPIO1_SIZE                0x00000080
 565 +/** address range for gpio3
 566 +    0x1E800200--0x1E80027F */
 567 +#define GPON_GPIO3_BASE                (KSEG1 | 0x1E800200)
 568 +#define GPON_GPIO3_END         (KSEG1 | 0x1E80027F)
 569 +#define GPON_GPIO3_SIZE                0x00000080
 570 +/** address range for gpio4
 571 +    0x1E800300--0x1E80037F */
 572 +#define GPON_GPIO4_BASE                (KSEG1 | 0x1E800300)
 573 +#define GPON_GPIO4_END         (KSEG1 | 0x1E80037F)
 574 +#define GPON_GPIO4_SIZE                0x00000080
 575 +/** address range for padctrl1
 576 +    0x1E800400--0x1E8004FF */
 577 +#define GPON_PADCTRL1_BASE             (KSEG1 | 0x1E800400)
 578 +#define GPON_PADCTRL1_END              (KSEG1 | 0x1E8004FF)
 579 +#define GPON_PADCTRL1_SIZE             0x00000100
 580 +/** address range for padctrl3
 581 +    0x1E800500--0x1E8005FF */
 582 +#define GPON_PADCTRL3_BASE             (KSEG1 | 0x1E800500)
 583 +#define GPON_PADCTRL3_END              (KSEG1 | 0x1E8005FF)
 584 +#define GPON_PADCTRL3_SIZE             0x00000100
 585 +/** address range for padctrl4
 586 +    0x1E800600--0x1E8006FF */
 587 +#define GPON_PADCTRL4_BASE             (KSEG1 | 0x1E800600)
 588 +#define GPON_PADCTRL4_END              (KSEG1 | 0x1E8006FF)
 589 +#define GPON_PADCTRL4_SIZE             0x00000100
 590 +/** address range for status
 591 +    0x1E802000--0x1E80207F */
 592 +#define GPON_STATUS_BASE               (KSEG1 | 0x1E802000)
 593 +#define GPON_STATUS_END                (KSEG1 | 0x1E80207F)
 594 +#define GPON_STATUS_SIZE               0x00000080
 595 +/** address range for dcdc_1v0
 596 +    0x1E803000--0x1E8033FF */
 597 +#define GPON_DCDC_1V0_BASE             (KSEG1 | 0x1E803000)
 598 +#define GPON_DCDC_1V0_END              (KSEG1 | 0x1E8033FF)
 599 +#define GPON_DCDC_1V0_SIZE             0x00000400
 600 +/** address range for dcdc_ddr
 601 +    0x1E804000--0x1E8043FF */
 602 +#define GPON_DCDC_DDR_BASE             (KSEG1 | 0x1E804000)
 603 +#define GPON_DCDC_DDR_END              (KSEG1 | 0x1E8043FF)
 604 +#define GPON_DCDC_DDR_SIZE             0x00000400
 605 +/** address range for dcdc_apd
 606 +    0x1E805000--0x1E8053FF */
 607 +#define GPON_DCDC_APD_BASE             (KSEG1 | 0x1E805000)
 608 +#define GPON_DCDC_APD_END              (KSEG1 | 0x1E8053FF)
 609 +#define GPON_DCDC_APD_SIZE             0x00000400
 610 +/** address range for sys1
 611 +    0x1EF00000--0x1EF000FF */
 612 +#define GPON_SYS1_BASE         (KSEG1 | 0x1EF00000)
 613 +#define GPON_SYS1_END          (KSEG1 | 0x1EF000FF)
 614 +#define GPON_SYS1_SIZE         0x00000100
 615 +/** address range for sbs0ctrl
 616 +    0x1F080000--0x1F0801FF */
 617 +#define GPON_SBS0CTRL_BASE             (KSEG1 | 0x1F080000)
 618 +#define GPON_SBS0CTRL_END              (KSEG1 | 0x1F0801FF)
 619 +#define GPON_SBS0CTRL_SIZE             0x00000200
 620 +/** address range for sbs0red
 621 +    0x1F080200--0x1F08027F */
 622 +#define GPON_SBS0RED_BASE              (KSEG1 | 0x1F080200)
 623 +#define GPON_SBS0RED_END               (KSEG1 | 0x1F08027F)
 624 +#define GPON_SBS0RED_SIZE              0x00000080
 625 +/** address range for sbs0ram
 626 +    0x1F200000--0x1F32FFFF */
 627 +#define GPON_SBS0RAM_BASE              (KSEG1 | 0x1F200000)
 628 +#define GPON_SBS0RAM_END               (KSEG1 | 0x1F32FFFF)
 629 +#define GPON_SBS0RAM_SIZE              0x00130000
 630 +/** address range for ddrdb
 631 +    0x1F701000--0x1F701FFF */
 632 +#define GPON_DDRDB_BASE                (KSEG1 | 0x1F701000)
 633 +#define GPON_DDRDB_END         (KSEG1 | 0x1F701FFF)
 634 +#define GPON_DDRDB_SIZE                0x00001000
 635 +/** address range for sbiu
 636 +    0x1F880000--0x1F8800FF */
 637 +#define GPON_SBIU_BASE         (KSEG1 | 0x1F880000)
 638 +#define GPON_SBIU_END          (KSEG1 | 0x1F8800FF)
 639 +#define GPON_SBIU_SIZE         0x00000100
 640 +/** address range for icu0
 641 +    0x1F880200--0x1F8802DF */
 642 +#define GPON_ICU0_BASE         (KSEG1 | 0x1F880200)
 643 +#define GPON_ICU0_END          (KSEG1 | 0x1F8802DF)
 644 +#define GPON_ICU0_SIZE         0x000000E0
 645 +/** address range for icu1
 646 +    0x1F880300--0x1F8803DF */
 647 +#define GPON_ICU1_BASE         (KSEG1 | 0x1F880300)
 648 +#define GPON_ICU1_END          (KSEG1 | 0x1F8803DF)
 649 +#define GPON_ICU1_SIZE         0x000000E0
 650 +/** address range for wdt
 651 +    0x1F8803F0--0x1F8803FF */
 652 +#define GPON_WDT_BASE          (KSEG1 | 0x1F8803F0)
 653 +#define GPON_WDT_END           (KSEG1 | 0x1F8803FF)
 654 +#define GPON_WDT_SIZE          0x00000010
 655 +
 656 +/*! @} */ /* GPON_BASE */
 657 +
 658 +#endif /* _gpon_reg_base_h */
 659 +
 660 --- /dev/null
 661 +++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h
 662 @@ -0,0 +1,830 @@
 663 +/******************************************************************************
 664 +
 665 +                               Copyright (c) 2010
 666 +                            Lantiq Deutschland GmbH
 667 +
 668 +  For licensing information, see the file 'LICENSE' in the root folder of
 669 +  this software module.
 670 +
 671 +******************************************************************************/
 672 +
 673 +#ifndef _i2c_reg_h
 674 +#define _i2c_reg_h
 675 +
 676 +/** \addtogroup I2C_REGISTER
 677 +   @{
 678 +*/
 679 +/* access macros */
 680 +#define i2c_r32(reg) reg_r32(&i2c->reg)
 681 +#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
 682 +#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
 683 +#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx)
 684 +#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx)
 685 +#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx)
 686 +#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx)
 687 +
 688 +
 689 +/** I2C register structure */
 690 +struct gpon_reg_i2c
 691 +{
 692 +   /** I2C Kernel Clock Control Register */
 693 +   unsigned int clc; /* 0x00000000 */
 694 +   /** Reserved */
 695 +   unsigned int res_0; /* 0x00000004 */
 696 +   /** I2C Identification Register */
 697 +   unsigned int id; /* 0x00000008 */
 698 +   /** Reserved */
 699 +   unsigned int res_1; /* 0x0000000C */
 700 +   /** I2C RUN Control Register
 701 +       This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */
 702 +   unsigned int run_ctrl; /* 0x00000010 */
 703 +   /** I2C End Data Control Register
 704 +       This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */
 705 +   unsigned int endd_ctrl; /* 0x00000014 */
 706 +   /** I2C Fractional Divider Configuration Register
 707 +       These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */
 708 +   unsigned int fdiv_cfg; /* 0x00000018 */
 709 +   /** I2C Fractional Divider (highspeed mode) Configuration Register
 710 +       These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */
 711 +   unsigned int fdiv_high_cfg; /* 0x0000001C */
 712 +   /** I2C Address Configuration Register */
 713 +   unsigned int addr_cfg; /* 0x00000020 */
 714 +   /** I2C Bus Status Register
 715 +       This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */
 716 +   unsigned int bus_stat; /* 0x00000024 */
 717 +   /** I2C FIFO Configuration Register */
 718 +   unsigned int fifo_cfg; /* 0x00000028 */
 719 +   /** I2C Maximum Received Packet Size Register */
 720 +   unsigned int mrps_ctrl; /* 0x0000002C */
 721 +   /** I2C Received Packet Size Status Register */
 722 +   unsigned int rps_stat; /* 0x00000030 */
 723 +   /** I2C Transmit Packet Size Register */
 724 +   unsigned int tps_ctrl; /* 0x00000034 */
 725 +   /** I2C Filled FIFO Stages Status Register */
 726 +   unsigned int ffs_stat; /* 0x00000038 */
 727 +   /** Reserved */
 728 +   unsigned int res_2; /* 0x0000003C */
 729 +   /** I2C Timing Configuration Register */
 730 +   unsigned int tim_cfg; /* 0x00000040 */
 731 +   /** Reserved */
 732 +   unsigned int res_3[7]; /* 0x00000044 */
 733 +   /** I2C Error Interrupt Request Source Mask Register */
 734 +   unsigned int err_irqsm; /* 0x00000060 */
 735 +   /** I2C Error Interrupt Request Source Status Register */
 736 +   unsigned int err_irqss; /* 0x00000064 */
 737 +   /** I2C Error Interrupt Request Source Clear Register */
 738 +   unsigned int err_irqsc; /* 0x00000068 */
 739 +   /** Reserved */
 740 +   unsigned int res_4; /* 0x0000006C */
 741 +   /** I2C Protocol Interrupt Request Source Mask Register */
 742 +   unsigned int p_irqsm; /* 0x00000070 */
 743 +   /** I2C Protocol Interrupt Request Source Status Register */
 744 +   unsigned int p_irqss; /* 0x00000074 */
 745 +   /** I2C Protocol Interrupt Request Source Clear Register */
 746 +   unsigned int p_irqsc; /* 0x00000078 */
 747 +   /** Reserved */
 748 +   unsigned int res_5; /* 0x0000007C */
 749 +   /** I2C Raw Interrupt Status Register */
 750 +   unsigned int ris; /* 0x00000080 */
 751 +   /** I2C Interrupt Mask Control Register */
 752 +   unsigned int imsc; /* 0x00000084 */
 753 +   /** I2C Masked Interrupt Status Register */
 754 +   unsigned int mis; /* 0x00000088 */
 755 +   /** I2C Interrupt Clear Register */
 756 +   unsigned int icr; /* 0x0000008C */
 757 +   /** I2C Interrupt Set Register */
 758 +   unsigned int isr; /* 0x00000090 */
 759 +   /** I2C DMA Enable Register */
 760 +   unsigned int dmae; /* 0x00000094 */
 761 +   /** Reserved */
 762 +   unsigned int res_6[8154]; /* 0x00000098 */
 763 +   /** I2C Transmit Data Register */
 764 +   unsigned int txd; /* 0x00008000 */
 765 +   /** Reserved */
 766 +   unsigned int res_7[4095]; /* 0x00008004 */
 767 +   /** I2C Receive Data Register */
 768 +   unsigned int rxd; /* 0x0000C000 */
 769 +   /** Reserved */
 770 +   unsigned int res_8[4095]; /* 0x0000C004 */
 771 +};
 772 +
 773 +
 774 +/* Fields of "I2C Kernel Clock Control Register" */
 775 +/** Clock Divider for Optional Run Mode (AHB peripherals)
 776 +    Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */
 777 +#define I2C_CLC_ORMC_MASK 0x00FF0000
 778 +/** field offset */
 779 +#define I2C_CLC_ORMC_OFFSET 16
 780 +/** Clock Divider for Normal Run Mode
 781 +    Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */
 782 +#define I2C_CLC_RMC_MASK 0x0000FF00
 783 +/** field offset */
 784 +#define I2C_CLC_RMC_OFFSET 8
 785 +/** Fast Shut-Off Enable Bit */
 786 +#define I2C_CLC_FSOE 0x00000020
 787 +/* Disable
 788 +#define I2C_CLC_FSOE_DIS 0x00000000 */
 789 +/** Enable */
 790 +#define I2C_CLC_FSOE_EN 0x00000020
 791 +/** Suspend Bit Write Enable for OCDS */
 792 +#define I2C_CLC_SBWE 0x00000010
 793 +/* Disable
 794 +#define I2C_CLC_SBWE_DIS 0x00000000 */
 795 +/** Enable */
 796 +#define I2C_CLC_SBWE_EN 0x00000010
 797 +/** Disable External Request Disable */
 798 +#define I2C_CLC_EDIS 0x00000008
 799 +/* Enable
 800 +#define I2C_CLC_EDIS_EN 0x00000000 */
 801 +/** Disable */
 802 +#define I2C_CLC_EDIS_DIS 0x00000008
 803 +/** Suspend Enable Bit for OCDS */
 804 +#define I2C_CLC_SPEN 0x00000004
 805 +/* Disable
 806 +#define I2C_CLC_SPEN_DIS 0x00000000 */
 807 +/** Enable */
 808 +#define I2C_CLC_SPEN_EN 0x00000004
 809 +/** Disable Status Bit
 810 +    Bit DISS can be modified only by writing to bit DISR */
 811 +#define I2C_CLC_DISS 0x00000002
 812 +/* Enable
 813 +#define I2C_CLC_DISS_EN 0x00000000 */
 814 +/** Disable */
 815 +#define I2C_CLC_DISS_DIS 0x00000002
 816 +/** Disable Request Bit */
 817 +#define I2C_CLC_DISR 0x00000001
 818 +/* Module disable not requested
 819 +#define I2C_CLC_DISR_OFF 0x00000000 */
 820 +/** Module disable requested */
 821 +#define I2C_CLC_DISR_ON 0x00000001
 822 +
 823 +/* Fields of "I2C Identification Register" */
 824 +/** Module ID */
 825 +#define I2C_ID_ID_MASK 0x0000FF00
 826 +/** field offset */
 827 +#define I2C_ID_ID_OFFSET 8
 828 +/** Revision */
 829 +#define I2C_ID_REV_MASK 0x000000FF
 830 +/** field offset */
 831 +#define I2C_ID_REV_OFFSET 0
 832 +
 833 +/* Fields of "I2C RUN Control Register" */
 834 +/** Enabling I2C Interface
 835 +    Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */
 836 +#define I2C_RUN_CTRL_RUN 0x00000001
 837 +/* Disable
 838 +#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */
 839 +/** Enable */
 840 +#define I2C_RUN_CTRL_RUN_EN 0x00000001
 841 +
 842 +/* Fields of "I2C End Data Control Register" */
 843 +/** Set End of Transmission
 844 +    Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */
 845 +#define I2C_ENDD_CTRL_SETEND 0x00000002
 846 +/* No-Operation
 847 +#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */
 848 +/** Master Receives Bytes */
 849 +#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002
 850 +/** Set Restart Condition */
 851 +#define I2C_ENDD_CTRL_SETRSC 0x00000001
 852 +/* No-Operation
 853 +#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */
 854 +/** Master Restart */
 855 +#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001
 856 +
 857 +/* Fields of "I2C Fractional Divider Configuration Register" */
 858 +/** Decrement Value of fractional divider */
 859 +#define I2C_FDIV_CFG_INC_MASK 0x00FF0000
 860 +/** field offset */
 861 +#define I2C_FDIV_CFG_INC_OFFSET 16
 862 +/** Increment Value of fractional divider */
 863 +#define I2C_FDIV_CFG_DEC_MASK 0x000007FF
 864 +/** field offset */
 865 +#define I2C_FDIV_CFG_DEC_OFFSET 0
 866 +
 867 +/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */
 868 +/** Decrement Value of fractional divider */
 869 +#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000
 870 +/** field offset */
 871 +#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
 872 +/** Increment Value of fractional divider */
 873 +#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF
 874 +/** field offset */
 875 +#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
 876 +
 877 +/* Fields of "I2C Address Configuration Register" */
 878 +/** Stop on Packet End
 879 +    If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */
 880 +#define I2C_ADDR_CFG_SOPE 0x00200000
 881 +/* Disable
 882 +#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */
 883 +/** Enable */
 884 +#define I2C_ADDR_CFG_SOPE_EN 0x00200000
 885 +/** Stop on Not Acknowledge
 886 +    After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */
 887 +#define I2C_ADDR_CFG_SONA 0x00100000
 888 +/* Disable
 889 +#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */
 890 +/** Enable */
 891 +#define I2C_ADDR_CFG_SONA_EN 0x00100000
 892 +/** Master Enable */
 893 +#define I2C_ADDR_CFG_MnS 0x00080000
 894 +/* Disable
 895 +#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */
 896 +/** Enable */
 897 +#define I2C_ADDR_CFG_MnS_EN 0x00080000
 898 +/** Master Code Enable */
 899 +#define I2C_ADDR_CFG_MCE 0x00040000
 900 +/* Disable
 901 +#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */
 902 +/** Enable */
 903 +#define I2C_ADDR_CFG_MCE_EN 0x00040000
 904 +/** General Call Enable */
 905 +#define I2C_ADDR_CFG_GCE 0x00020000
 906 +/* Disable
 907 +#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */
 908 +/** Enable */
 909 +#define I2C_ADDR_CFG_GCE_EN 0x00020000
 910 +/** Ten Bit Address Mode */
 911 +#define I2C_ADDR_CFG_TBAM 0x00010000
 912 +/* 7-bit address mode enabled.
 913 +#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */
 914 +/** 10-bit address mode enabled. */
 915 +#define I2C_ADDR_CFG_TBAM_10bit 0x00010000
 916 +/** I2C Bus device address
 917 +    This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */
 918 +#define I2C_ADDR_CFG_ADR_MASK 0x000003FF
 919 +/** field offset */
 920 +#define I2C_ADDR_CFG_ADR_OFFSET 0
 921 +
 922 +/* Fields of "I2C Bus Status Register" */
 923 +/** Read / not Write */
 924 +#define I2C_BUS_STAT_RNW 0x00000004
 925 +/* Write to I2C Bus.
 926 +#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */
 927 +/** Read from I2C Bus. */
 928 +#define I2C_BUS_STAT_RNW_READ 0x00000004
 929 +/** Bus Status */
 930 +#define I2C_BUS_STAT_BS_MASK 0x00000003
 931 +/** field offset */
 932 +#define I2C_BUS_STAT_BS_OFFSET 0
 933 +/** I2C Bus is free. */
 934 +#define I2C_BUS_STAT_BS_FREE 0x00000000
 935 +/** A start condition has been detected on the bus (bus busy). */
 936 +#define I2C_BUS_STAT_BS_SC 0x00000001
 937 +/** The device is working as master and has claimed the control on the I2C-bus (busy master). */
 938 +#define I2C_BUS_STAT_BS_BM 0x00000002
 939 +/** A remote master has accessed this device as slave. */
 940 +#define I2C_BUS_STAT_BS_RM 0x00000003
 941 +
 942 +/* Fields of "I2C FIFO Configuration Register" */
 943 +/** TX FIFO Flow Control */
 944 +#define I2C_FIFO_CFG_TXFC 0x00020000
 945 +/* TX FIFO not as Flow Controller
 946 +#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */
 947 +/** RX FIFO Flow Control */
 948 +#define I2C_FIFO_CFG_RXFC 0x00010000
 949 +/* RX FIFO not as Flow Controller
 950 +#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */
 951 +/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
 952 +#define I2C_FIFO_CFG_TXFA_MASK 0x00003000
 953 +/** field offset */
 954 +#define I2C_FIFO_CFG_TXFA_OFFSET 12
 955 +/** Byte aligned (character alignment) */
 956 +#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000
 957 +/** Half word aligned (character alignment of two characters) */
 958 +#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000
 959 +/** Word aligned (character alignment of four characters) */
 960 +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
 961 +/** Double word aligned (character alignment of eight */
 962 +#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000
 963 +/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
 964 +#define I2C_FIFO_CFG_RXFA_MASK 0x00000300
 965 +/** field offset */
 966 +#define I2C_FIFO_CFG_RXFA_OFFSET 8
 967 +/** Byte aligned (character alignment) */
 968 +#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000
 969 +/** Half word aligned (character alignment of two characters) */
 970 +#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100
 971 +/** Word aligned (character alignment of four characters) */
 972 +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
 973 +/** Double word aligned (character alignment of eight */
 974 +#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300
 975 +/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
 976 +#define I2C_FIFO_CFG_TXBS_MASK 0x00000030
 977 +/** field offset */
 978 +#define I2C_FIFO_CFG_TXBS_OFFSET 4
 979 +/** 1 word */
 980 +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
 981 +/** 2 words */
 982 +#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010
 983 +/** 4 words */
 984 +#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020
 985 +/** 8 words */
 986 +#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030
 987 +/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
 988 +#define I2C_FIFO_CFG_RXBS_MASK 0x00000003
 989 +/** field offset */
 990 +#define I2C_FIFO_CFG_RXBS_OFFSET 0
 991 +/** 1 word */
 992 +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
 993 +/** 2 words */
 994 +#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001
 995 +/** 4 words */
 996 +#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002
 997 +/** 8 words */
 998 +#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003
 999 +
1000 +/* Fields of "I2C Maximum Received Packet Size Register" */
1001 +/** MRPS */
1002 +#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF
1003 +/** field offset */
1004 +#define I2C_MRPS_CTRL_MRPS_OFFSET 0
1005 +
1006 +/* Fields of "I2C Received Packet Size Status Register" */
1007 +/** RPS */
1008 +#define I2C_RPS_STAT_RPS_MASK 0x00003FFF
1009 +/** field offset */
1010 +#define I2C_RPS_STAT_RPS_OFFSET 0
1011 +
1012 +/* Fields of "I2C Transmit Packet Size Register" */
1013 +/** TPS */
1014 +#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF
1015 +/** field offset */
1016 +#define I2C_TPS_CTRL_TPS_OFFSET 0
1017 +
1018 +/* Fields of "I2C Filled FIFO Stages Status Register" */
1019 +/** FFS */
1020 +#define I2C_FFS_STAT_FFS_MASK 0x0000000F
1021 +/** field offset */
1022 +#define I2C_FFS_STAT_FFS_OFFSET 0
1023 +
1024 +/* Fields of "I2C Timing Configuration Register" */
1025 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
1026 +    The actual delay is calculated as the value of this field + 3 */
1027 +#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000
1028 +/** field offset */
1029 +#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16
1030 +/** Enable Fast Mode SCL Low period timing */
1031 +#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000
1032 +/* Disable
1033 +#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */
1034 +/** Enable */
1035 +#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000
1036 +/** SCL Delay Stages for Hold Time Start (Restart) Bit.
1037 +    The actual delay is calculated as the value of this field + 2 */
1038 +#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00
1039 +/** field offset */
1040 +#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9
1041 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
1042 +    The actual delay is calculated as the value of this field + 3 */
1043 +#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0
1044 +/** field offset */
1045 +#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6
1046 +/** SDA Delay Stages for Start/Stop bit in High Speed Mode
1047 +    The actual delay is calculated as the value of this field + 3 */
1048 +#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F
1049 +/** field offset */
1050 +#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0
1051 +
1052 +/* Fields of "I2C Error Interrupt Request Source Mask Register" */
1053 +/** Enables the corresponding error interrupt. */
1054 +#define I2C_ERR_IRQSM_TXF_OFL 0x00000008
1055 +/* Disable
1056 +#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */
1057 +/** Enable */
1058 +#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008
1059 +/** Enables the corresponding error interrupt. */
1060 +#define I2C_ERR_IRQSM_TXF_UFL 0x00000004
1061 +/* Disable
1062 +#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */
1063 +/** Enable */
1064 +#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004
1065 +/** Enables the corresponding error interrupt. */
1066 +#define I2C_ERR_IRQSM_RXF_OFL 0x00000002
1067 +/* Disable
1068 +#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */
1069 +/** Enable */
1070 +#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002
1071 +/** Enables the corresponding error interrupt. */
1072 +#define I2C_ERR_IRQSM_RXF_UFL 0x00000001
1073 +/* Disable
1074 +#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */
1075 +/** Enable */
1076 +#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001
1077 +
1078 +/* Fields of "I2C Error Interrupt Request Source Status Register" */
1079 +/** TXF_OFL */
1080 +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
1081 +/* Nothing
1082 +#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */
1083 +/** Read: Interrupt occurred. */
1084 +#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008
1085 +/** TXF_UFL */
1086 +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
1087 +/* Nothing
1088 +#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */
1089 +/** Read: Interrupt occurred. */
1090 +#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004
1091 +/** RXF_OFL */
1092 +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
1093 +/* Nothing
1094 +#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */
1095 +/** Read: Interrupt occurred. */
1096 +#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002
1097 +/** RXF_UFL */
1098 +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
1099 +/* Nothing
1100 +#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */
1101 +/** Read: Interrupt occurred. */
1102 +#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001
1103 +
1104 +/* Fields of "I2C Error Interrupt Request Source Clear Register" */
1105 +/** TXF_OFL */
1106 +#define I2C_ERR_IRQSC_TXF_OFL 0x00000008
1107 +/* No-Operation
1108 +#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */
1109 +/** Clear */
1110 +#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008
1111 +/** TXF_UFL */
1112 +#define I2C_ERR_IRQSC_TXF_UFL 0x00000004
1113 +/* No-Operation
1114 +#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */
1115 +/** Clear */
1116 +#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004
1117 +/** RXF_OFL */
1118 +#define I2C_ERR_IRQSC_RXF_OFL 0x00000002
1119 +/* No-Operation
1120 +#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */
1121 +/** Clear */
1122 +#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002
1123 +/** RXF_UFL */
1124 +#define I2C_ERR_IRQSC_RXF_UFL 0x00000001
1125 +/* No-Operation
1126 +#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */
1127 +/** Clear */
1128 +#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001
1129 +
1130 +/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */
1131 +/** Enables the corresponding interrupt. */
1132 +#define I2C_P_IRQSM_RX 0x00000040
1133 +/* Disable
1134 +#define I2C_P_IRQSM_RX_DIS 0x00000000 */
1135 +/** Enable */
1136 +#define I2C_P_IRQSM_RX_EN 0x00000040
1137 +/** Enables the corresponding interrupt. */
1138 +#define I2C_P_IRQSM_TX_END 0x00000020
1139 +/* Disable
1140 +#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */
1141 +/** Enable */
1142 +#define I2C_P_IRQSM_TX_END_EN 0x00000020
1143 +/** Enables the corresponding interrupt. */
1144 +#define I2C_P_IRQSM_NACK 0x00000010
1145 +/* Disable
1146 +#define I2C_P_IRQSM_NACK_DIS 0x00000000 */
1147 +/** Enable */
1148 +#define I2C_P_IRQSM_NACK_EN 0x00000010
1149 +/** Enables the corresponding interrupt. */
1150 +#define I2C_P_IRQSM_AL 0x00000008
1151 +/* Disable
1152 +#define I2C_P_IRQSM_AL_DIS 0x00000000 */
1153 +/** Enable */
1154 +#define I2C_P_IRQSM_AL_EN 0x00000008
1155 +/** Enables the corresponding interrupt. */
1156 +#define I2C_P_IRQSM_MC 0x00000004
1157 +/* Disable
1158 +#define I2C_P_IRQSM_MC_DIS 0x00000000 */
1159 +/** Enable */
1160 +#define I2C_P_IRQSM_MC_EN 0x00000004
1161 +/** Enables the corresponding interrupt. */
1162 +#define I2C_P_IRQSM_GC 0x00000002
1163 +/* Disable
1164 +#define I2C_P_IRQSM_GC_DIS 0x00000000 */
1165 +/** Enable */
1166 +#define I2C_P_IRQSM_GC_EN 0x00000002
1167 +/** Enables the corresponding interrupt. */
1168 +#define I2C_P_IRQSM_AM 0x00000001
1169 +/* Disable
1170 +#define I2C_P_IRQSM_AM_DIS 0x00000000 */
1171 +/** Enable */
1172 +#define I2C_P_IRQSM_AM_EN 0x00000001
1173 +
1174 +/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
1175 +/** RX */
1176 +#define I2C_P_IRQSS_RX 0x00000040
1177 +/* Nothing
1178 +#define I2C_P_IRQSS_RX_NULL 0x00000000 */
1179 +/** Read: Interrupt occurred. */
1180 +#define I2C_P_IRQSS_RX_INTOCC 0x00000040
1181 +/** TX_END */
1182 +#define I2C_P_IRQSS_TX_END 0x00000020
1183 +/* Nothing
1184 +#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */
1185 +/** Read: Interrupt occurred. */
1186 +#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020
1187 +/** NACK */
1188 +#define I2C_P_IRQSS_NACK 0x00000010
1189 +/* Nothing
1190 +#define I2C_P_IRQSS_NACK_NULL 0x00000000 */
1191 +/** Read: Interrupt occurred. */
1192 +#define I2C_P_IRQSS_NACK_INTOCC 0x00000010
1193 +/** AL */
1194 +#define I2C_P_IRQSS_AL 0x00000008
1195 +/* Nothing
1196 +#define I2C_P_IRQSS_AL_NULL 0x00000000 */
1197 +/** Read: Interrupt occurred. */
1198 +#define I2C_P_IRQSS_AL_INTOCC 0x00000008
1199 +/** MC */
1200 +#define I2C_P_IRQSS_MC 0x00000004
1201 +/* Nothing
1202 +#define I2C_P_IRQSS_MC_NULL 0x00000000 */
1203 +/** Read: Interrupt occurred. */
1204 +#define I2C_P_IRQSS_MC_INTOCC 0x00000004
1205 +/** GC */
1206 +#define I2C_P_IRQSS_GC 0x00000002
1207 +/* Nothing
1208 +#define I2C_P_IRQSS_GC_NULL 0x00000000 */
1209 +/** Read: Interrupt occurred. */
1210 +#define I2C_P_IRQSS_GC_INTOCC 0x00000002
1211 +/** AM */
1212 +#define I2C_P_IRQSS_AM 0x00000001
1213 +/* Nothing
1214 +#define I2C_P_IRQSS_AM_NULL 0x00000000 */
1215 +/** Read: Interrupt occurred. */
1216 +#define I2C_P_IRQSS_AM_INTOCC 0x00000001
1217 +
1218 +/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */
1219 +/** RX */
1220 +#define I2C_P_IRQSC_RX 0x00000040
1221 +/* No-Operation
1222 +#define I2C_P_IRQSC_RX_NOP 0x00000000 */
1223 +/** Clear */
1224 +#define I2C_P_IRQSC_RX_CLR 0x00000040
1225 +/** TX_END */
1226 +#define I2C_P_IRQSC_TX_END 0x00000020
1227 +/* No-Operation
1228 +#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */
1229 +/** Clear */
1230 +#define I2C_P_IRQSC_TX_END_CLR 0x00000020
1231 +/** NACK */
1232 +#define I2C_P_IRQSC_NACK 0x00000010
1233 +/* No-Operation
1234 +#define I2C_P_IRQSC_NACK_NOP 0x00000000 */
1235 +/** Clear */
1236 +#define I2C_P_IRQSC_NACK_CLR 0x00000010
1237 +/** AL */
1238 +#define I2C_P_IRQSC_AL 0x00000008
1239 +/* No-Operation
1240 +#define I2C_P_IRQSC_AL_NOP 0x00000000 */
1241 +/** Clear */
1242 +#define I2C_P_IRQSC_AL_CLR 0x00000008
1243 +/** MC */
1244 +#define I2C_P_IRQSC_MC 0x00000004
1245 +/* No-Operation
1246 +#define I2C_P_IRQSC_MC_NOP 0x00000000 */
1247 +/** Clear */
1248 +#define I2C_P_IRQSC_MC_CLR 0x00000004
1249 +/** GC */
1250 +#define I2C_P_IRQSC_GC 0x00000002
1251 +/* No-Operation
1252 +#define I2C_P_IRQSC_GC_NOP 0x00000000 */
1253 +/** Clear */
1254 +#define I2C_P_IRQSC_GC_CLR 0x00000002
1255 +/** AM */
1256 +#define I2C_P_IRQSC_AM 0x00000001
1257 +/* No-Operation
1258 +#define I2C_P_IRQSC_AM_NOP 0x00000000 */
1259 +/** Clear */
1260 +#define I2C_P_IRQSC_AM_CLR 0x00000001
1261 +
1262 +/* Fields of "I2C Raw Interrupt Status Register" */
1263 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1264 +#define I2C_RIS_I2C_P_INT 0x00000020
1265 +/* Nothing
1266 +#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */
1267 +/** Read: Interrupt occurred. */
1268 +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
1269 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1270 +#define I2C_RIS_I2C_ERR_INT 0x00000010
1271 +/* Nothing
1272 +#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */
1273 +/** Read: Interrupt occurred. */
1274 +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
1275 +/** BREQ_INT */
1276 +#define I2C_RIS_BREQ_INT 0x00000008
1277 +/* Nothing
1278 +#define I2C_RIS_BREQ_INT_NULL 0x00000000 */
1279 +/** Read: Interrupt occurred. */
1280 +#define I2C_RIS_BREQ_INT_INTOCC 0x00000008
1281 +/** LBREQ_INT */
1282 +#define I2C_RIS_LBREQ_INT 0x00000004
1283 +/* Nothing
1284 +#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */
1285 +/** Read: Interrupt occurred. */
1286 +#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004
1287 +/** SREQ_INT */
1288 +#define I2C_RIS_SREQ_INT 0x00000002
1289 +/* Nothing
1290 +#define I2C_RIS_SREQ_INT_NULL 0x00000000 */
1291 +/** Read: Interrupt occurred. */
1292 +#define I2C_RIS_SREQ_INT_INTOCC 0x00000002
1293 +/** LSREQ_INT */
1294 +#define I2C_RIS_LSREQ_INT 0x00000001
1295 +/* Nothing
1296 +#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */
1297 +/** Read: Interrupt occurred. */
1298 +#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001
1299 +
1300 +/* Fields of "I2C Interrupt Mask Control Register" */
1301 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1302 +#define I2C_IMSC_I2C_P_INT 0x00000020
1303 +/* Disable
1304 +#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */
1305 +/** Enable */
1306 +#define I2C_IMSC_I2C_P_INT_EN 0x00000020
1307 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1308 +#define I2C_IMSC_I2C_ERR_INT 0x00000010
1309 +/* Disable
1310 +#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */
1311 +/** Enable */
1312 +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
1313 +/** BREQ_INT */
1314 +#define I2C_IMSC_BREQ_INT 0x00000008
1315 +/* Disable
1316 +#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */
1317 +/** Enable */
1318 +#define I2C_IMSC_BREQ_INT_EN 0x00000008
1319 +/** LBREQ_INT */
1320 +#define I2C_IMSC_LBREQ_INT 0x00000004
1321 +/* Disable
1322 +#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */
1323 +/** Enable */
1324 +#define I2C_IMSC_LBREQ_INT_EN 0x00000004
1325 +/** SREQ_INT */
1326 +#define I2C_IMSC_SREQ_INT 0x00000002
1327 +/* Disable
1328 +#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */
1329 +/** Enable */
1330 +#define I2C_IMSC_SREQ_INT_EN 0x00000002
1331 +/** LSREQ_INT */
1332 +#define I2C_IMSC_LSREQ_INT 0x00000001
1333 +/* Disable
1334 +#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */
1335 +/** Enable */
1336 +#define I2C_IMSC_LSREQ_INT_EN 0x00000001
1337 +
1338 +/* Fields of "I2C Masked Interrupt Status Register" */
1339 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1340 +#define I2C_MIS_I2C_P_INT 0x00000020
1341 +/* Nothing
1342 +#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */
1343 +/** Read: Interrupt occurred. */
1344 +#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020
1345 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1346 +#define I2C_MIS_I2C_ERR_INT 0x00000010
1347 +/* Nothing
1348 +#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */
1349 +/** Read: Interrupt occurred. */
1350 +#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010
1351 +/** BREQ_INT */
1352 +#define I2C_MIS_BREQ_INT 0x00000008
1353 +/* Nothing
1354 +#define I2C_MIS_BREQ_INT_NULL 0x00000000 */
1355 +/** Read: Interrupt occurred. */
1356 +#define I2C_MIS_BREQ_INT_INTOCC 0x00000008
1357 +/** LBREQ_INT */
1358 +#define I2C_MIS_LBREQ_INT 0x00000004
1359 +/* Nothing
1360 +#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */
1361 +/** Read: Interrupt occurred. */
1362 +#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004
1363 +/** SREQ_INT */
1364 +#define I2C_MIS_SREQ_INT 0x00000002
1365 +/* Nothing
1366 +#define I2C_MIS_SREQ_INT_NULL 0x00000000 */
1367 +/** Read: Interrupt occurred. */
1368 +#define I2C_MIS_SREQ_INT_INTOCC 0x00000002
1369 +/** LSREQ_INT */
1370 +#define I2C_MIS_LSREQ_INT 0x00000001
1371 +/* Nothing
1372 +#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */
1373 +/** Read: Interrupt occurred. */
1374 +#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001
1375 +
1376 +/* Fields of "I2C Interrupt Clear Register" */
1377 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1378 +#define I2C_ICR_I2C_P_INT 0x00000020
1379 +/* No-Operation
1380 +#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */
1381 +/** Clear */
1382 +#define I2C_ICR_I2C_P_INT_CLR 0x00000020
1383 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1384 +#define I2C_ICR_I2C_ERR_INT 0x00000010
1385 +/* No-Operation
1386 +#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */
1387 +/** Clear */
1388 +#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010
1389 +/** BREQ_INT */
1390 +#define I2C_ICR_BREQ_INT 0x00000008
1391 +/* No-Operation
1392 +#define I2C_ICR_BREQ_INT_NOP 0x00000000 */
1393 +/** Clear */
1394 +#define I2C_ICR_BREQ_INT_CLR 0x00000008
1395 +/** LBREQ_INT */
1396 +#define I2C_ICR_LBREQ_INT 0x00000004
1397 +/* No-Operation
1398 +#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */
1399 +/** Clear */
1400 +#define I2C_ICR_LBREQ_INT_CLR 0x00000004
1401 +/** SREQ_INT */
1402 +#define I2C_ICR_SREQ_INT 0x00000002
1403 +/* No-Operation
1404 +#define I2C_ICR_SREQ_INT_NOP 0x00000000 */
1405 +/** Clear */
1406 +#define I2C_ICR_SREQ_INT_CLR 0x00000002
1407 +/** LSREQ_INT */
1408 +#define I2C_ICR_LSREQ_INT 0x00000001
1409 +/* No-Operation
1410 +#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */
1411 +/** Clear */
1412 +#define I2C_ICR_LSREQ_INT_CLR 0x00000001
1413 +
1414 +/* Fields of "I2C Interrupt Set Register" */
1415 +/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
1416 +#define I2C_ISR_I2C_P_INT 0x00000020
1417 +/* No-Operation
1418 +#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */
1419 +/** Set */
1420 +#define I2C_ISR_I2C_P_INT_SET 0x00000020
1421 +/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
1422 +#define I2C_ISR_I2C_ERR_INT 0x00000010
1423 +/* No-Operation
1424 +#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */
1425 +/** Set */
1426 +#define I2C_ISR_I2C_ERR_INT_SET 0x00000010
1427 +/** BREQ_INT */
1428 +#define I2C_ISR_BREQ_INT 0x00000008
1429 +/* No-Operation
1430 +#define I2C_ISR_BREQ_INT_NOP 0x00000000 */
1431 +/** Set */
1432 +#define I2C_ISR_BREQ_INT_SET 0x00000008
1433 +/** LBREQ_INT */
1434 +#define I2C_ISR_LBREQ_INT 0x00000004
1435 +/* No-Operation
1436 +#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */
1437 +/** Set */
1438 +#define I2C_ISR_LBREQ_INT_SET 0x00000004
1439 +/** SREQ_INT */
1440 +#define I2C_ISR_SREQ_INT 0x00000002
1441 +/* No-Operation
1442 +#define I2C_ISR_SREQ_INT_NOP 0x00000000 */
1443 +/** Set */
1444 +#define I2C_ISR_SREQ_INT_SET 0x00000002
1445 +/** LSREQ_INT */
1446 +#define I2C_ISR_LSREQ_INT 0x00000001
1447 +/* No-Operation
1448 +#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */
1449 +/** Set */
1450 +#define I2C_ISR_LSREQ_INT_SET 0x00000001
1451 +
1452 +/* Fields of "I2C DMA Enable Register" */
1453 +/** BREQ_INT */
1454 +#define I2C_DMAE_BREQ_INT 0x00000008
1455 +/* Disable
1456 +#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */
1457 +/** Enable */
1458 +#define I2C_DMAE_BREQ_INT_EN 0x00000008
1459 +/** LBREQ_INT */
1460 +#define I2C_DMAE_LBREQ_INT 0x00000004
1461 +/* Disable
1462 +#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */
1463 +/** Enable */
1464 +#define I2C_DMAE_LBREQ_INT_EN 0x00000004
1465 +/** SREQ_INT */
1466 +#define I2C_DMAE_SREQ_INT 0x00000002
1467 +/* Disable
1468 +#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */
1469 +/** Enable */
1470 +#define I2C_DMAE_SREQ_INT_EN 0x00000002
1471 +/** LSREQ_INT */
1472 +#define I2C_DMAE_LSREQ_INT 0x00000001
1473 +/* Disable
1474 +#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */
1475 +/** Enable */
1476 +#define I2C_DMAE_LSREQ_INT_EN 0x00000001
1477 +
1478 +/* Fields of "I2C Transmit Data Register" */
1479 +/** Characters to be transmitted */
1480 +#define I2C_TXD_TXD_MASK 0xFFFFFFFF
1481 +/** field offset */
1482 +#define I2C_TXD_TXD_OFFSET 0
1483 +
1484 +/* Fields of "I2C Receive Data Register" */
1485 +/** Received characters */
1486 +#define I2C_RXD_RXD_MASK 0xFFFFFFFF
1487 +/** field offset */
1488 +#define I2C_RXD_RXD_OFFSET 0
1489 +
1490 +/*! @} */ /* I2C_REGISTER */
1491 +
1492 +#endif /* _i2c_reg_h */
1493 --- /dev/null
1494 +++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h
1495 @@ -0,0 +1,4324 @@
1496 +/******************************************************************************
1497 +
1498 +                               Copyright (c) 2010
1499 +                            Lantiq Deutschland GmbH
1500 +
1501 +  For licensing information, see the file 'LICENSE' in the root folder of
1502 +  this software module.
1503 +
1504 +******************************************************************************/
1505 +
1506 +#ifndef _icu0_reg_h
1507 +#define _icu0_reg_h
1508 +
1509 +/** \addtogroup ICU0_REGISTER
1510 +   @{
1511 +*/
1512 +/* access macros */
1513 +#define icu0_r32(reg) reg_r32(&icu0->reg)
1514 +#define icu0_w32(val, reg) reg_w32(val, &icu0->reg)
1515 +#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg)
1516 +#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx)
1517 +#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx)
1518 +#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx)
1519 +#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx)
1520 +
1521 +
1522 +/** ICU0 register structure */
1523 +struct gpon_reg_icu0
1524 +{
1525 +   /** IM0 Interrupt Status Register
1526 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1527 +   unsigned int im0_isr; /* 0x00000000 */
1528 +   /** Reserved */
1529 +   unsigned int res_0; /* 0x00000004 */
1530 +   /** IM0 Interrupt Enable Register
1531 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */
1532 +   unsigned int im0_ier; /* 0x00000008 */
1533 +   /** Reserved */
1534 +   unsigned int res_1; /* 0x0000000C */
1535 +   /** IM0 Interrupt Output Status Register
1536 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */
1537 +   unsigned int im0_iosr; /* 0x00000010 */
1538 +   /** Reserved */
1539 +   unsigned int res_2; /* 0x00000014 */
1540 +   /** IM0 Interrupt Request Set Register
1541 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1542 +   unsigned int im0_irsr; /* 0x00000018 */
1543 +   /** Reserved */
1544 +   unsigned int res_3; /* 0x0000001C */
1545 +   /** IM0 Interrupt Mode Register
1546 +       This register shows the type of interrupt for each bit. */
1547 +   unsigned int im0_imr; /* 0x00000020 */
1548 +   /** Reserved */
1549 +   unsigned int res_4; /* 0x00000024 */
1550 +   /** IM1 Interrupt Status Register
1551 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1552 +   unsigned int im1_isr; /* 0x00000028 */
1553 +   /** Reserved */
1554 +   unsigned int res_5; /* 0x0000002C */
1555 +   /** IM1 Interrupt Enable Register
1556 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */
1557 +   unsigned int im1_ier; /* 0x00000030 */
1558 +   /** Reserved */
1559 +   unsigned int res_6; /* 0x00000034 */
1560 +   /** IM1 Interrupt Output Status Register
1561 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */
1562 +   unsigned int im1_iosr; /* 0x00000038 */
1563 +   /** Reserved */
1564 +   unsigned int res_7; /* 0x0000003C */
1565 +   /** IM1 Interrupt Request Set Register
1566 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1567 +   unsigned int im1_irsr; /* 0x00000040 */
1568 +   /** Reserved */
1569 +   unsigned int res_8; /* 0x00000044 */
1570 +   /** IM1 Interrupt Mode Register
1571 +       This register shows the type of interrupt for each bit. */
1572 +   unsigned int im1_imr; /* 0x00000048 */
1573 +   /** Reserved */
1574 +   unsigned int res_9; /* 0x0000004C */
1575 +   /** IM2 Interrupt Status Register
1576 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1577 +   unsigned int im2_isr; /* 0x00000050 */
1578 +   /** Reserved */
1579 +   unsigned int res_10; /* 0x00000054 */
1580 +   /** IM2 Interrupt Enable Register
1581 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */
1582 +   unsigned int im2_ier; /* 0x00000058 */
1583 +   /** Reserved */
1584 +   unsigned int res_11; /* 0x0000005C */
1585 +   /** IM2 Interrupt Output Status Register
1586 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */
1587 +   unsigned int im2_iosr; /* 0x00000060 */
1588 +   /** Reserved */
1589 +   unsigned int res_12; /* 0x00000064 */
1590 +   /** IM2 Interrupt Request Set Register
1591 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1592 +   unsigned int im2_irsr; /* 0x00000068 */
1593 +   /** Reserved */
1594 +   unsigned int res_13; /* 0x0000006C */
1595 +   /** IM2 Interrupt Mode Register
1596 +       This register shows the type of interrupt for each bit. */
1597 +   unsigned int im2_imr; /* 0x00000070 */
1598 +   /** Reserved */
1599 +   unsigned int res_14; /* 0x00000074 */
1600 +   /** IM3 Interrupt Status Register
1601 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1602 +   unsigned int im3_isr; /* 0x00000078 */
1603 +   /** Reserved */
1604 +   unsigned int res_15; /* 0x0000007C */
1605 +   /** IM3 Interrupt Enable Register
1606 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */
1607 +   unsigned int im3_ier; /* 0x00000080 */
1608 +   /** Reserved */
1609 +   unsigned int res_16; /* 0x00000084 */
1610 +   /** IM3 Interrupt Output Status Register
1611 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */
1612 +   unsigned int im3_iosr; /* 0x00000088 */
1613 +   /** Reserved */
1614 +   unsigned int res_17; /* 0x0000008C */
1615 +   /** IM3 Interrupt Request Set Register
1616 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1617 +   unsigned int im3_irsr; /* 0x00000090 */
1618 +   /** Reserved */
1619 +   unsigned int res_18; /* 0x00000094 */
1620 +   /** IM3 Interrupt Mode Register
1621 +       This register shows the type of interrupt for each bit. */
1622 +   unsigned int im3_imr; /* 0x00000098 */
1623 +   /** Reserved */
1624 +   unsigned int res_19; /* 0x0000009C */
1625 +   /** IM4 Interrupt Status Register
1626 +       A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
1627 +   unsigned int im4_isr; /* 0x000000A0 */
1628 +   /** Reserved */
1629 +   unsigned int res_20; /* 0x000000A4 */
1630 +   /** IM4 Interrupt Enable Register
1631 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */
1632 +   unsigned int im4_ier; /* 0x000000A8 */
1633 +   /** Reserved */
1634 +   unsigned int res_21; /* 0x000000AC */
1635 +   /** IM4 Interrupt Output Status Register
1636 +       This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */
1637 +   unsigned int im4_iosr; /* 0x000000B0 */
1638 +   /** Reserved */
1639 +   unsigned int res_22; /* 0x000000B4 */
1640 +   /** IM4 Interrupt Request Set Register
1641 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
1642 +   unsigned int im4_irsr; /* 0x000000B8 */
1643 +   /** Reserved */
1644 +   unsigned int res_23; /* 0x000000BC */
1645 +   /** IM4 Interrupt Mode Register
1646 +       This register shows the type of interrupt for each bit. */
1647 +   unsigned int im4_imr; /* 0x000000C0 */
1648 +   /** Reserved */
1649 +   unsigned int res_24; /* 0x000000C4 */
1650 +   /** ICU Interrupt Vector Register (5 bit variant)
1651 +       Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
1652 +   unsigned int icu_ivec; /* 0x000000C8 */
1653 +   /** Reserved */
1654 +   unsigned int res_25; /* 0x000000CC */
1655 +   /** ICU Interrupt Vector Register (6 bit variant)
1656 +       Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
1657 +   unsigned int icu_ivec_6; /* 0x000000D0 */
1658 +   /** Reserved */
1659 +   unsigned int res_26[3]; /* 0x000000D4 */
1660 +};
1661 +
1662 +
1663 +/* Fields of "IM0 Interrupt Status Register" */
1664 +/** PCM Transmit Crash Interrupt
1665 +    This bit is an indirect interrupt. */
1666 +#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000
1667 +/* Nothing
1668 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */
1669 +/** Write: Acknowledge the interrupt. */
1670 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000
1671 +/** Read: Interrupt occurred. */
1672 +#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000
1673 +/** PCM Transmit Interrupt
1674 +    This bit is an indirect interrupt. */
1675 +#define ICU0_IM0_ISR_PCM_TX 0x40000000
1676 +/* Nothing
1677 +#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */
1678 +/** Write: Acknowledge the interrupt. */
1679 +#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000
1680 +/** Read: Interrupt occurred. */
1681 +#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000
1682 +/** PCM Receive Interrupt
1683 +    This bit is an indirect interrupt. */
1684 +#define ICU0_IM0_ISR_PCM_RX 0x20000000
1685 +/* Nothing
1686 +#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */
1687 +/** Write: Acknowledge the interrupt. */
1688 +#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000
1689 +/** Read: Interrupt occurred. */
1690 +#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000
1691 +/** Secure Hash Algorithm Interrupt
1692 +    This bit is a direct interrupt. */
1693 +#define ICU0_IM0_ISR_SHA1_HASH 0x10000000
1694 +/* Nothing
1695 +#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */
1696 +/** Write: Acknowledge the interrupt. */
1697 +#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000
1698 +/** Read: Interrupt occurred. */
1699 +#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000
1700 +/** Advanced Encryption Standard Interrupt
1701 +    This bit is a direct interrupt. */
1702 +#define ICU0_IM0_ISR_AES_AES 0x08000000
1703 +/* Nothing
1704 +#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */
1705 +/** Write: Acknowledge the interrupt. */
1706 +#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000
1707 +/** Read: Interrupt occurred. */
1708 +#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000
1709 +/** SSC Frame Interrupt
1710 +    This bit is a direct interrupt. */
1711 +#define ICU0_IM0_ISR_SSC0_F 0x00020000
1712 +/* Nothing
1713 +#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */
1714 +/** Write: Acknowledge the interrupt. */
1715 +#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000
1716 +/** Read: Interrupt occurred. */
1717 +#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000
1718 +/** SSC Error Interrupt
1719 +    This bit is a direct interrupt. */
1720 +#define ICU0_IM0_ISR_SSC0_E 0x00010000
1721 +/* Nothing
1722 +#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */
1723 +/** Write: Acknowledge the interrupt. */
1724 +#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000
1725 +/** Read: Interrupt occurred. */
1726 +#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000
1727 +/** SSC Receive Interrupt
1728 +    This bit is a direct interrupt. */
1729 +#define ICU0_IM0_ISR_SSC0_R 0x00008000
1730 +/* Nothing
1731 +#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */
1732 +/** Write: Acknowledge the interrupt. */
1733 +#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000
1734 +/** Read: Interrupt occurred. */
1735 +#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000
1736 +/** SSC Transmit Interrupt
1737 +    This bit is a direct interrupt. */
1738 +#define ICU0_IM0_ISR_SSC0_T 0x00004000
1739 +/* Nothing
1740 +#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */
1741 +/** Write: Acknowledge the interrupt. */
1742 +#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000
1743 +/** Read: Interrupt occurred. */
1744 +#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000
1745 +/** I2C Peripheral Interrupt
1746 +    This bit is an indirect interrupt. */
1747 +#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000
1748 +/* Nothing
1749 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */
1750 +/** Write: Acknowledge the interrupt. */
1751 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000
1752 +/** Read: Interrupt occurred. */
1753 +#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000
1754 +/** I2C Error Interrupt
1755 +    This bit is an indirect interrupt. */
1756 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000
1757 +/* Nothing
1758 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */
1759 +/** Write: Acknowledge the interrupt. */
1760 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000
1761 +/** Read: Interrupt occurred. */
1762 +#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000
1763 +/** I2C Burst Data Transfer Request
1764 +    This bit is an indirect interrupt. */
1765 +#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800
1766 +/* Nothing
1767 +#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */
1768 +/** Write: Acknowledge the interrupt. */
1769 +#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800
1770 +/** Read: Interrupt occurred. */
1771 +#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800
1772 +/** I2C Last Burst Data Transfer Request
1773 +    This bit is an indirect interrupt. */
1774 +#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400
1775 +/* Nothing
1776 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */
1777 +/** Write: Acknowledge the interrupt. */
1778 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400
1779 +/** Read: Interrupt occurred. */
1780 +#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400
1781 +/** I2C Single Data Transfer Request
1782 +    This bit is an indirect interrupt. */
1783 +#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200
1784 +/* Nothing
1785 +#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */
1786 +/** Write: Acknowledge the interrupt. */
1787 +#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200
1788 +/** Read: Interrupt occurred. */
1789 +#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200
1790 +/** I2C Last Single Data Transfer Request
1791 +    This bit is an indirect interrupt. */
1792 +#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100
1793 +/* Nothing
1794 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */
1795 +/** Write: Acknowledge the interrupt. */
1796 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100
1797 +/** Read: Interrupt occurred. */
1798 +#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100
1799 +/** HOST IF Mailbox1 Transmit Interrupt
1800 +    This bit is an indirect interrupt. */
1801 +#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010
1802 +/* Nothing
1803 +#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */
1804 +/** Write: Acknowledge the interrupt. */
1805 +#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010
1806 +/** Read: Interrupt occurred. */
1807 +#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010
1808 +/** HOST IF Mailbox1 Receive Interrupt
1809 +    This bit is an indirect interrupt. */
1810 +#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008
1811 +/* Nothing
1812 +#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */
1813 +/** Write: Acknowledge the interrupt. */
1814 +#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008
1815 +/** Read: Interrupt occurred. */
1816 +#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008
1817 +/** HOST IF Mailbox0 Transmit Interrupt
1818 +    This bit is an indirect interrupt. */
1819 +#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004
1820 +/* Nothing
1821 +#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */
1822 +/** Write: Acknowledge the interrupt. */
1823 +#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004
1824 +/** Read: Interrupt occurred. */
1825 +#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004
1826 +/** HOST IF Mailbox0 Receive Interrupt
1827 +    This bit is an indirect interrupt. */
1828 +#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002
1829 +/* Nothing
1830 +#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */
1831 +/** Write: Acknowledge the interrupt. */
1832 +#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002
1833 +/** Read: Interrupt occurred. */
1834 +#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002
1835 +/** HOST IF Event Interrupt
1836 +    This bit is an indirect interrupt. */
1837 +#define ICU0_IM0_ISR_HOST_EIR 0x00000001
1838 +/* Nothing
1839 +#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */
1840 +/** Write: Acknowledge the interrupt. */
1841 +#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001
1842 +/** Read: Interrupt occurred. */
1843 +#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001
1844 +
1845 +/* Fields of "IM0 Interrupt Enable Register" */
1846 +/** PCM Transmit Crash Interrupt
1847 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1848 +#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000
1849 +/* Disable
1850 +#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */
1851 +/** Enable */
1852 +#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000
1853 +/** PCM Transmit Interrupt
1854 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1855 +#define ICU0_IM0_IER_PCM_TX 0x40000000
1856 +/* Disable
1857 +#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */
1858 +/** Enable */
1859 +#define ICU0_IM0_IER_PCM_TX_EN 0x40000000
1860 +/** PCM Receive Interrupt
1861 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1862 +#define ICU0_IM0_IER_PCM_RX 0x20000000
1863 +/* Disable
1864 +#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */
1865 +/** Enable */
1866 +#define ICU0_IM0_IER_PCM_RX_EN 0x20000000
1867 +/** Secure Hash Algorithm Interrupt
1868 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1869 +#define ICU0_IM0_IER_SHA1_HASH 0x10000000
1870 +/* Disable
1871 +#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */
1872 +/** Enable */
1873 +#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000
1874 +/** Advanced Encryption Standard Interrupt
1875 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1876 +#define ICU0_IM0_IER_AES_AES 0x08000000
1877 +/* Disable
1878 +#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */
1879 +/** Enable */
1880 +#define ICU0_IM0_IER_AES_AES_EN 0x08000000
1881 +/** SSC Frame Interrupt
1882 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1883 +#define ICU0_IM0_IER_SSC0_F 0x00020000
1884 +/* Disable
1885 +#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */
1886 +/** Enable */
1887 +#define ICU0_IM0_IER_SSC0_F_EN 0x00020000
1888 +/** SSC Error Interrupt
1889 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1890 +#define ICU0_IM0_IER_SSC0_E 0x00010000
1891 +/* Disable
1892 +#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */
1893 +/** Enable */
1894 +#define ICU0_IM0_IER_SSC0_E_EN 0x00010000
1895 +/** SSC Receive Interrupt
1896 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1897 +#define ICU0_IM0_IER_SSC0_R 0x00008000
1898 +/* Disable
1899 +#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */
1900 +/** Enable */
1901 +#define ICU0_IM0_IER_SSC0_R_EN 0x00008000
1902 +/** SSC Transmit Interrupt
1903 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1904 +#define ICU0_IM0_IER_SSC0_T 0x00004000
1905 +/* Disable
1906 +#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */
1907 +/** Enable */
1908 +#define ICU0_IM0_IER_SSC0_T_EN 0x00004000
1909 +/** I2C Peripheral Interrupt
1910 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1911 +#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000
1912 +/* Disable
1913 +#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */
1914 +/** Enable */
1915 +#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000
1916 +/** I2C Error Interrupt
1917 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1918 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000
1919 +/* Disable
1920 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */
1921 +/** Enable */
1922 +#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000
1923 +/** I2C Burst Data Transfer Request
1924 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1925 +#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800
1926 +/* Disable
1927 +#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */
1928 +/** Enable */
1929 +#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800
1930 +/** I2C Last Burst Data Transfer Request
1931 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1932 +#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400
1933 +/* Disable
1934 +#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */
1935 +/** Enable */
1936 +#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400
1937 +/** I2C Single Data Transfer Request
1938 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1939 +#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200
1940 +/* Disable
1941 +#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */
1942 +/** Enable */
1943 +#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200
1944 +/** I2C Last Single Data Transfer Request
1945 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1946 +#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100
1947 +/* Disable
1948 +#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */
1949 +/** Enable */
1950 +#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100
1951 +/** HOST IF Mailbox1 Transmit Interrupt
1952 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1953 +#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010
1954 +/* Disable
1955 +#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */
1956 +/** Enable */
1957 +#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010
1958 +/** HOST IF Mailbox1 Receive Interrupt
1959 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1960 +#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008
1961 +/* Disable
1962 +#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */
1963 +/** Enable */
1964 +#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008
1965 +/** HOST IF Mailbox0 Transmit Interrupt
1966 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1967 +#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004
1968 +/* Disable
1969 +#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */
1970 +/** Enable */
1971 +#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004
1972 +/** HOST IF Mailbox0 Receive Interrupt
1973 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1974 +#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002
1975 +/* Disable
1976 +#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */
1977 +/** Enable */
1978 +#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002
1979 +/** HOST IF Event Interrupt
1980 +    Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
1981 +#define ICU0_IM0_IER_HOST_EIR 0x00000001
1982 +/* Disable
1983 +#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */
1984 +/** Enable */
1985 +#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001
1986 +
1987 +/* Fields of "IM0 Interrupt Output Status Register" */
1988 +/** PCM Transmit Crash Interrupt
1989 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1990 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000
1991 +/* Nothing
1992 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */
1993 +/** Read: Interrupt occurred. */
1994 +#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000
1995 +/** PCM Transmit Interrupt
1996 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
1997 +#define ICU0_IM0_IOSR_PCM_TX 0x40000000
1998 +/* Nothing
1999 +#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */
2000 +/** Read: Interrupt occurred. */
2001 +#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000
2002 +/** PCM Receive Interrupt
2003 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2004 +#define ICU0_IM0_IOSR_PCM_RX 0x20000000
2005 +/* Nothing
2006 +#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */
2007 +/** Read: Interrupt occurred. */
2008 +#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000
2009 +/** Secure Hash Algorithm Interrupt
2010 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2011 +#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000
2012 +/* Nothing
2013 +#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */
2014 +/** Read: Interrupt occurred. */
2015 +#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000
2016 +/** Advanced Encryption Standard Interrupt
2017 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2018 +#define ICU0_IM0_IOSR_AES_AES 0x08000000
2019 +/* Nothing
2020 +#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */
2021 +/** Read: Interrupt occurred. */
2022 +#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000
2023 +/** SSC Frame Interrupt
2024 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2025 +#define ICU0_IM0_IOSR_SSC0_F 0x00020000
2026 +/* Nothing
2027 +#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */
2028 +/** Read: Interrupt occurred. */
2029 +#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000
2030 +/** SSC Error Interrupt
2031 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2032 +#define ICU0_IM0_IOSR_SSC0_E 0x00010000
2033 +/* Nothing
2034 +#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */
2035 +/** Read: Interrupt occurred. */
2036 +#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000
2037 +/** SSC Receive Interrupt
2038 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2039 +#define ICU0_IM0_IOSR_SSC0_R 0x00008000
2040 +/* Nothing
2041 +#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */
2042 +/** Read: Interrupt occurred. */
2043 +#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000
2044 +/** SSC Transmit Interrupt
2045 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2046 +#define ICU0_IM0_IOSR_SSC0_T 0x00004000
2047 +/* Nothing
2048 +#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */
2049 +/** Read: Interrupt occurred. */
2050 +#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000
2051 +/** I2C Peripheral Interrupt
2052 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2053 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000
2054 +/* Nothing
2055 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */
2056 +/** Read: Interrupt occurred. */
2057 +#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000
2058 +/** I2C Error Interrupt
2059 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2060 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000
2061 +/* Nothing
2062 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */
2063 +/** Read: Interrupt occurred. */
2064 +#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000
2065 +/** I2C Burst Data Transfer Request
2066 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2067 +#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800
2068 +/* Nothing
2069 +#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */
2070 +/** Read: Interrupt occurred. */
2071 +#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800
2072 +/** I2C Last Burst Data Transfer Request
2073 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2074 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400
2075 +/* Nothing
2076 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */
2077 +/** Read: Interrupt occurred. */
2078 +#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400
2079 +/** I2C Single Data Transfer Request
2080 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2081 +#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200
2082 +/* Nothing
2083 +#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */
2084 +/** Read: Interrupt occurred. */
2085 +#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200
2086 +/** I2C Last Single Data Transfer Request
2087 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2088 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100
2089 +/* Nothing
2090 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */
2091 +/** Read: Interrupt occurred. */
2092 +#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100
2093 +/** HOST IF Mailbox1 Transmit Interrupt
2094 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2095 +#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010
2096 +/* Nothing
2097 +#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */
2098 +/** Read: Interrupt occurred. */
2099 +#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010
2100 +/** HOST IF Mailbox1 Receive Interrupt
2101 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2102 +#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008
2103 +/* Nothing
2104 +#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */
2105 +/** Read: Interrupt occurred. */
2106 +#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008
2107 +/** HOST IF Mailbox0 Transmit Interrupt
2108 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2109 +#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004
2110 +/* Nothing
2111 +#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */
2112 +/** Read: Interrupt occurred. */
2113 +#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004
2114 +/** HOST IF Mailbox0 Receive Interrupt
2115 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2116 +#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002
2117 +/* Nothing
2118 +#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */
2119 +/** Read: Interrupt occurred. */
2120 +#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002
2121 +/** HOST IF Event Interrupt
2122 +    Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
2123 +#define ICU0_IM0_IOSR_HOST_EIR 0x00000001
2124 +/* Nothing
2125 +#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */
2126 +/** Read: Interrupt occurred. */
2127 +#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001
2128 +
2129 +/* Fields of "IM0 Interrupt Request Set Register" */
2130 +/** PCM Transmit Crash Interrupt
2131 +    Software control for the corresponding bit in the IM0_ISR register. */
2132 +#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000
2133 +/** PCM Transmit Interrupt
2134 +    Software control for the corresponding bit in the IM0_ISR register. */
2135 +#define ICU0_IM0_IRSR_PCM_TX 0x40000000
2136 +/** PCM Receive Interrupt
2137 +    Software control for the corresponding bit in the IM0_ISR register. */
2138 +#define ICU0_IM0_IRSR_PCM_RX 0x20000000
2139 +/** Secure Hash Algorithm Interrupt
2140 +    Software control for the corresponding bit in the IM0_ISR register. */
2141 +#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000
2142 +/** Advanced Encryption Standard Interrupt
2143 +    Software control for the corresponding bit in the IM0_ISR register. */
2144 +#define ICU0_IM0_IRSR_AES_AES 0x08000000
2145 +/** SSC Frame Interrupt
2146 +    Software control for the corresponding bit in the IM0_ISR register. */
2147 +#define ICU0_IM0_IRSR_SSC0_F 0x00020000
2148 +/** SSC Error Interrupt
2149 +    Software control for the corresponding bit in the IM0_ISR register. */
2150 +#define ICU0_IM0_IRSR_SSC0_E 0x00010000
2151 +/** SSC Receive Interrupt
2152 +    Software control for the corresponding bit in the IM0_ISR register. */
2153 +#define ICU0_IM0_IRSR_SSC0_R 0x00008000
2154 +/** SSC Transmit Interrupt
2155 +    Software control for the corresponding bit in the IM0_ISR register. */
2156 +#define ICU0_IM0_IRSR_SSC0_T 0x00004000
2157 +/** I2C Peripheral Interrupt
2158 +    Software control for the corresponding bit in the IM0_ISR register. */
2159 +#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000
2160 +/** I2C Error Interrupt
2161 +    Software control for the corresponding bit in the IM0_ISR register. */
2162 +#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000
2163 +/** I2C Burst Data Transfer Request
2164 +    Software control for the corresponding bit in the IM0_ISR register. */
2165 +#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800
2166 +/** I2C Last Burst Data Transfer Request
2167 +    Software control for the corresponding bit in the IM0_ISR register. */
2168 +#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400
2169 +/** I2C Single Data Transfer Request
2170 +    Software control for the corresponding bit in the IM0_ISR register. */
2171 +#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200
2172 +/** I2C Last Single Data Transfer Request
2173 +    Software control for the corresponding bit in the IM0_ISR register. */
2174 +#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100
2175 +/** HOST IF Mailbox1 Transmit Interrupt
2176 +    Software control for the corresponding bit in the IM0_ISR register. */
2177 +#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010
2178 +/** HOST IF Mailbox1 Receive Interrupt
2179 +    Software control for the corresponding bit in the IM0_ISR register. */
2180 +#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008
2181 +/** HOST IF Mailbox0 Transmit Interrupt
2182 +    Software control for the corresponding bit in the IM0_ISR register. */
2183 +#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004
2184 +/** HOST IF Mailbox0 Receive Interrupt
2185 +    Software control for the corresponding bit in the IM0_ISR register. */
2186 +#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002
2187 +/** HOST IF Event Interrupt
2188 +    Software control for the corresponding bit in the IM0_ISR register. */
2189 +#define ICU0_IM0_IRSR_HOST_EIR 0x00000001
2190 +
2191 +/* Fields of "IM0 Interrupt Mode Register" */
2192 +/** PCM Transmit Crash Interrupt
2193 +    Type of interrupt. */
2194 +#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000
2195 +/* Indirect Interrupt.
2196 +#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */
2197 +/** Direct Interrupt. */
2198 +#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000
2199 +/** PCM Transmit Interrupt
2200 +    Type of interrupt. */
2201 +#define ICU0_IM0_IMR_PCM_TX 0x40000000
2202 +/* Indirect Interrupt.
2203 +#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */
2204 +/** Direct Interrupt. */
2205 +#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000
2206 +/** PCM Receive Interrupt
2207 +    Type of interrupt. */
2208 +#define ICU0_IM0_IMR_PCM_RX 0x20000000
2209 +/* Indirect Interrupt.
2210 +#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */
2211 +/** Direct Interrupt. */
2212 +#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000
2213 +/** Secure Hash Algorithm Interrupt
2214 +    Type of interrupt. */
2215 +#define ICU0_IM0_IMR_SHA1_HASH 0x10000000
2216 +/* Indirect Interrupt.
2217 +#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */
2218 +/** Direct Interrupt. */
2219 +#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000
2220 +/** Advanced Encryption Standard Interrupt
2221 +    Type of interrupt. */
2222 +#define ICU0_IM0_IMR_AES_AES 0x08000000
2223 +/* Indirect Interrupt.
2224 +#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */
2225 +/** Direct Interrupt. */
2226 +#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000
2227 +/** SSC Frame Interrupt
2228 +    Type of interrupt. */
2229 +#define ICU0_IM0_IMR_SSC0_F 0x00020000
2230 +/* Indirect Interrupt.
2231 +#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */
2232 +/** Direct Interrupt. */
2233 +#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000
2234 +/** SSC Error Interrupt
2235 +    Type of interrupt. */
2236 +#define ICU0_IM0_IMR_SSC0_E 0x00010000
2237 +/* Indirect Interrupt.
2238 +#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */
2239 +/** Direct Interrupt. */
2240 +#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000
2241 +/** SSC Receive Interrupt
2242 +    Type of interrupt. */
2243 +#define ICU0_IM0_IMR_SSC0_R 0x00008000
2244 +/* Indirect Interrupt.
2245 +#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */
2246 +/** Direct Interrupt. */
2247 +#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000
2248 +/** SSC Transmit Interrupt
2249 +    Type of interrupt. */
2250 +#define ICU0_IM0_IMR_SSC0_T 0x00004000
2251 +/* Indirect Interrupt.
2252 +#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */
2253 +/** Direct Interrupt. */
2254 +#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000
2255 +/** I2C Peripheral Interrupt
2256 +    Type of interrupt. */
2257 +#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000
2258 +/* Indirect Interrupt.
2259 +#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */
2260 +/** Direct Interrupt. */
2261 +#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000
2262 +/** I2C Error Interrupt
2263 +    Type of interrupt. */
2264 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000
2265 +/* Indirect Interrupt.
2266 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */
2267 +/** Direct Interrupt. */
2268 +#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000
2269 +/** I2C Burst Data Transfer Request
2270 +    Type of interrupt. */
2271 +#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800
2272 +/* Indirect Interrupt.
2273 +#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */
2274 +/** Direct Interrupt. */
2275 +#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800
2276 +/** I2C Last Burst Data Transfer Request
2277 +    Type of interrupt. */
2278 +#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400
2279 +/* Indirect Interrupt.
2280 +#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */
2281 +/** Direct Interrupt. */
2282 +#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400
2283 +/** I2C Single Data Transfer Request
2284 +    Type of interrupt. */
2285 +#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200
2286 +/* Indirect Interrupt.
2287 +#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */
2288 +/** Direct Interrupt. */
2289 +#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200
2290 +/** I2C Last Single Data Transfer Request
2291 +    Type of interrupt. */
2292 +#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100
2293 +/* Indirect Interrupt.
2294 +#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */
2295 +/** Direct Interrupt. */
2296 +#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100
2297 +/** HOST IF Mailbox1 Transmit Interrupt
2298 +    Type of interrupt. */
2299 +#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010
2300 +/* Indirect Interrupt.
2301 +#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */
2302 +/** Direct Interrupt. */
2303 +#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010
2304 +/** HOST IF Mailbox1 Receive Interrupt
2305 +    Type of interrupt. */
2306 +#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008
2307 +/* Indirect Interrupt.
2308 +#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */
2309 +/** Direct Interrupt. */
2310 +#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008
2311 +/** HOST IF Mailbox0 Transmit Interrupt
2312 +    Type of interrupt. */
2313 +#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004
2314 +/* Indirect Interrupt.
2315 +#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */
2316 +/** Direct Interrupt. */
2317 +#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004
2318 +/** HOST IF Mailbox0 Receive Interrupt
2319 +    Type of interrupt. */
2320 +#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002
2321 +/* Indirect Interrupt.
2322 +#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */
2323 +/** Direct Interrupt. */
2324 +#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002
2325 +/** HOST IF Event Interrupt
2326 +    Type of interrupt. */
2327 +#define ICU0_IM0_IMR_HOST_EIR 0x00000001
2328 +/* Indirect Interrupt.
2329 +#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */
2330 +/** Direct Interrupt. */
2331 +#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001
2332 +
2333 +/* Fields of "IM1 Interrupt Status Register" */
2334 +/** Crossbar Error Interrupt
2335 +    This bit is an indirect interrupt. */
2336 +#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000
2337 +/* Nothing
2338 +#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */
2339 +/** Write: Acknowledge the interrupt. */
2340 +#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000
2341 +/** Read: Interrupt occurred. */
2342 +#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000
2343 +/** DDR Controller Interrupt
2344 +    This bit is an indirect interrupt. */
2345 +#define ICU0_IM1_ISR_DDR 0x40000000
2346 +/* Nothing
2347 +#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */
2348 +/** Write: Acknowledge the interrupt. */
2349 +#define ICU0_IM1_ISR_DDR_INTACK 0x40000000
2350 +/** Read: Interrupt occurred. */
2351 +#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000
2352 +/** FPI Bus Control Unit Interrupt
2353 +    This bit is a direct interrupt. */
2354 +#define ICU0_IM1_ISR_BCU0 0x20000000
2355 +/* Nothing
2356 +#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */
2357 +/** Write: Acknowledge the interrupt. */
2358 +#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000
2359 +/** Read: Interrupt occurred. */
2360 +#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000
2361 +/** SBIU interrupt
2362 +    This bit is an indirect interrupt. */
2363 +#define ICU0_IM1_ISR_SBIU0 0x08000000
2364 +/* Nothing
2365 +#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */
2366 +/** Write: Acknowledge the interrupt. */
2367 +#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000
2368 +/** Read: Interrupt occurred. */
2369 +#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000
2370 +/** Watchdog Prewarning Interrupt
2371 +    This bit is an indirect interrupt. */
2372 +#define ICU0_IM1_ISR_WDT_PIR 0x02000000
2373 +/* Nothing
2374 +#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */
2375 +/** Write: Acknowledge the interrupt. */
2376 +#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000
2377 +/** Read: Interrupt occurred. */
2378 +#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000
2379 +/** Watchdog Access Error Interrupt
2380 +    This bit is an indirect interrupt. */
2381 +#define ICU0_IM1_ISR_WDT_AEIR 0x01000000
2382 +/* Nothing
2383 +#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */
2384 +/** Write: Acknowledge the interrupt. */
2385 +#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000
2386 +/** Read: Interrupt occurred. */
2387 +#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000
2388 +/** SYS GPE Interrupt
2389 +    This bit is an indirect interrupt. */
2390 +#define ICU0_IM1_ISR_SYS_GPE 0x00200000
2391 +/* Nothing
2392 +#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */
2393 +/** Write: Acknowledge the interrupt. */
2394 +#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000
2395 +/** Read: Interrupt occurred. */
2396 +#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000
2397 +/** SYS1 Interrupt
2398 +    This bit is an indirect interrupt. */
2399 +#define ICU0_IM1_ISR_SYS1 0x00100000
2400 +/* Nothing
2401 +#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */
2402 +/** Write: Acknowledge the interrupt. */
2403 +#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000
2404 +/** Read: Interrupt occurred. */
2405 +#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000
2406 +/** PMA Interrupt from IntNode of the RX Clk Domain
2407 +    This bit is an indirect interrupt. */
2408 +#define ICU0_IM1_ISR_PMA_RX 0x00020000
2409 +/* Nothing
2410 +#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */
2411 +/** Write: Acknowledge the interrupt. */
2412 +#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000
2413 +/** Read: Interrupt occurred. */
2414 +#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000
2415 +/** PMA Interrupt from IntNode of the TX Clk Domain
2416 +    This bit is an indirect interrupt. */
2417 +#define ICU0_IM1_ISR_PMA_TX 0x00010000
2418 +/* Nothing
2419 +#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */
2420 +/** Write: Acknowledge the interrupt. */
2421 +#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000
2422 +/** Read: Interrupt occurred. */
2423 +#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000
2424 +/** PMA Interrupt from IntNode of the 200MHz Domain
2425 +    This bit is an indirect interrupt. */
2426 +#define ICU0_IM1_ISR_PMA_200M 0x00008000
2427 +/* Nothing
2428 +#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */
2429 +/** Write: Acknowledge the interrupt. */
2430 +#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000
2431 +/** Read: Interrupt occurred. */
2432 +#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000
2433 +/** Time of Day
2434 +    This bit is an indirect interrupt. */
2435 +#define ICU0_IM1_ISR_TOD 0x00004000
2436 +/* Nothing
2437 +#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */
2438 +/** Write: Acknowledge the interrupt. */
2439 +#define ICU0_IM1_ISR_TOD_INTACK 0x00004000
2440 +/** Read: Interrupt occurred. */
2441 +#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000
2442 +/** 8kHz root interrupt derived from GPON interface
2443 +    This bit is a direct interrupt. */
2444 +#define ICU0_IM1_ISR_FSC_ROOT 0x00002000
2445 +/* Nothing
2446 +#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */
2447 +/** Write: Acknowledge the interrupt. */
2448 +#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000
2449 +/** Read: Interrupt occurred. */
2450 +#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000
2451 +/** FSC Timer Interrupt 1
2452 +    Delayed version of FSCROOT. This bit is a direct interrupt. */
2453 +#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000
2454 +/* Nothing
2455 +#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */
2456 +/** Write: Acknowledge the interrupt. */
2457 +#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000
2458 +/** Read: Interrupt occurred. */
2459 +#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000
2460 +/** FSC Timer Interrupt 0
2461 +    Delayed version of FSCROOT. This bit is a direct interrupt. */
2462 +#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800
2463 +/* Nothing
2464 +#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */
2465 +/** Write: Acknowledge the interrupt. */
2466 +#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800
2467 +/** Read: Interrupt occurred. */
2468 +#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800
2469 +/** 8kHz backup interrupt derived from core-PLL
2470 +    This bit is an indirect interrupt. */
2471 +#define ICU0_IM1_ISR_FSC_BKP 0x00000400
2472 +/* Nothing
2473 +#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */
2474 +/** Write: Acknowledge the interrupt. */
2475 +#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400
2476 +/** Read: Interrupt occurred. */
2477 +#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400
2478 +/** External Interrupt from GPIO P4
2479 +    This bit is an indirect interrupt. */
2480 +#define ICU0_IM1_ISR_P4 0x00000100
2481 +/* Nothing
2482 +#define ICU0_IM1_ISR_P4_NULL 0x00000000 */
2483 +/** Write: Acknowledge the interrupt. */
2484 +#define ICU0_IM1_ISR_P4_INTACK 0x00000100
2485 +/** Read: Interrupt occurred. */
2486 +#define ICU0_IM1_ISR_P4_INTOCC 0x00000100
2487 +/** External Interrupt from GPIO P3
2488 +    This bit is an indirect interrupt. */
2489 +#define ICU0_IM1_ISR_P3 0x00000080
2490 +/* Nothing
2491 +#define ICU0_IM1_ISR_P3_NULL 0x00000000 */
2492 +/** Write: Acknowledge the interrupt. */
2493 +#define ICU0_IM1_ISR_P3_INTACK 0x00000080
2494 +/** Read: Interrupt occurred. */
2495 +#define ICU0_IM1_ISR_P3_INTOCC 0x00000080
2496 +/** External Interrupt from GPIO P2
2497 +    This bit is an indirect interrupt. */
2498 +#define ICU0_IM1_ISR_P2 0x00000040
2499 +/* Nothing
2500 +#define ICU0_IM1_ISR_P2_NULL 0x00000000 */
2501 +/** Write: Acknowledge the interrupt. */
2502 +#define ICU0_IM1_ISR_P2_INTACK 0x00000040
2503 +/** Read: Interrupt occurred. */
2504 +#define ICU0_IM1_ISR_P2_INTOCC 0x00000040
2505 +/** External Interrupt from GPIO P1
2506 +    This bit is an indirect interrupt. */
2507 +#define ICU0_IM1_ISR_P1 0x00000020
2508 +/* Nothing
2509 +#define ICU0_IM1_ISR_P1_NULL 0x00000000 */
2510 +/** Write: Acknowledge the interrupt. */
2511 +#define ICU0_IM1_ISR_P1_INTACK 0x00000020
2512 +/** Read: Interrupt occurred. */
2513 +#define ICU0_IM1_ISR_P1_INTOCC 0x00000020
2514 +/** External Interrupt from GPIO P0
2515 +    This bit is an indirect interrupt. */
2516 +#define ICU0_IM1_ISR_P0 0x00000010
2517 +/* Nothing
2518 +#define ICU0_IM1_ISR_P0_NULL 0x00000000 */
2519 +/** Write: Acknowledge the interrupt. */
2520 +#define ICU0_IM1_ISR_P0_INTACK 0x00000010
2521 +/** Read: Interrupt occurred. */
2522 +#define ICU0_IM1_ISR_P0_INTOCC 0x00000010
2523 +/** EBU Serial Flash Busy
2524 +    This bit is an indirect interrupt. */
2525 +#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004
2526 +/* Nothing
2527 +#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */
2528 +/** Write: Acknowledge the interrupt. */
2529 +#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004
2530 +/** Read: Interrupt occurred. */
2531 +#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004
2532 +/** EBU Serial Flash Command Overwrite Error
2533 +    This bit is an indirect interrupt. */
2534 +#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002
2535 +/* Nothing
2536 +#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */
2537 +/** Write: Acknowledge the interrupt. */
2538 +#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002
2539 +/** Read: Interrupt occurred. */
2540 +#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002
2541 +/** EBU Serial Flash Command Error
2542 +    This bit is an indirect interrupt. */
2543 +#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001
2544 +/* Nothing
2545 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */
2546 +/** Write: Acknowledge the interrupt. */
2547 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001
2548 +/** Read: Interrupt occurred. */
2549 +#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001
2550 +
2551 +/* Fields of "IM1 Interrupt Enable Register" */
2552 +/** Crossbar Error Interrupt
2553 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2554 +#define ICU0_IM1_IER_XBAR_ERROR 0x80000000
2555 +/* Disable
2556 +#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */
2557 +/** Enable */
2558 +#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000
2559 +/** DDR Controller Interrupt
2560 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2561 +#define ICU0_IM1_IER_DDR 0x40000000
2562 +/* Disable
2563 +#define ICU0_IM1_IER_DDR_DIS 0x00000000 */
2564 +/** Enable */
2565 +#define ICU0_IM1_IER_DDR_EN 0x40000000
2566 +/** FPI Bus Control Unit Interrupt
2567 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2568 +#define ICU0_IM1_IER_BCU0 0x20000000
2569 +/* Disable
2570 +#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */
2571 +/** Enable */
2572 +#define ICU0_IM1_IER_BCU0_EN 0x20000000
2573 +/** SBIU interrupt
2574 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2575 +#define ICU0_IM1_IER_SBIU0 0x08000000
2576 +/* Disable
2577 +#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */
2578 +/** Enable */
2579 +#define ICU0_IM1_IER_SBIU0_EN 0x08000000
2580 +/** Watchdog Prewarning Interrupt
2581 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2582 +#define ICU0_IM1_IER_WDT_PIR 0x02000000
2583 +/* Disable
2584 +#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */
2585 +/** Enable */
2586 +#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000
2587 +/** Watchdog Access Error Interrupt
2588 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2589 +#define ICU0_IM1_IER_WDT_AEIR 0x01000000
2590 +/* Disable
2591 +#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */
2592 +/** Enable */
2593 +#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000
2594 +/** SYS GPE Interrupt
2595 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2596 +#define ICU0_IM1_IER_SYS_GPE 0x00200000
2597 +/* Disable
2598 +#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */
2599 +/** Enable */
2600 +#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000
2601 +/** SYS1 Interrupt
2602 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2603 +#define ICU0_IM1_IER_SYS1 0x00100000
2604 +/* Disable
2605 +#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */
2606 +/** Enable */
2607 +#define ICU0_IM1_IER_SYS1_EN 0x00100000
2608 +/** PMA Interrupt from IntNode of the RX Clk Domain
2609 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2610 +#define ICU0_IM1_IER_PMA_RX 0x00020000
2611 +/* Disable
2612 +#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */
2613 +/** Enable */
2614 +#define ICU0_IM1_IER_PMA_RX_EN 0x00020000
2615 +/** PMA Interrupt from IntNode of the TX Clk Domain
2616 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2617 +#define ICU0_IM1_IER_PMA_TX 0x00010000
2618 +/* Disable
2619 +#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */
2620 +/** Enable */
2621 +#define ICU0_IM1_IER_PMA_TX_EN 0x00010000
2622 +/** PMA Interrupt from IntNode of the 200MHz Domain
2623 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2624 +#define ICU0_IM1_IER_PMA_200M 0x00008000
2625 +/* Disable
2626 +#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */
2627 +/** Enable */
2628 +#define ICU0_IM1_IER_PMA_200M_EN 0x00008000
2629 +/** Time of Day
2630 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2631 +#define ICU0_IM1_IER_TOD 0x00004000
2632 +/* Disable
2633 +#define ICU0_IM1_IER_TOD_DIS 0x00000000 */
2634 +/** Enable */
2635 +#define ICU0_IM1_IER_TOD_EN 0x00004000
2636 +/** 8kHz root interrupt derived from GPON interface
2637 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2638 +#define ICU0_IM1_IER_FSC_ROOT 0x00002000
2639 +/* Disable
2640 +#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */
2641 +/** Enable */
2642 +#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000
2643 +/** FSC Timer Interrupt 1
2644 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2645 +#define ICU0_IM1_IER_FSCT_CMP1 0x00001000
2646 +/* Disable
2647 +#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */
2648 +/** Enable */
2649 +#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000
2650 +/** FSC Timer Interrupt 0
2651 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2652 +#define ICU0_IM1_IER_FSCT_CMP0 0x00000800
2653 +/* Disable
2654 +#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */
2655 +/** Enable */
2656 +#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800
2657 +/** 8kHz backup interrupt derived from core-PLL
2658 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2659 +#define ICU0_IM1_IER_FSC_BKP 0x00000400
2660 +/* Disable
2661 +#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */
2662 +/** Enable */
2663 +#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400
2664 +/** External Interrupt from GPIO P4
2665 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2666 +#define ICU0_IM1_IER_P4 0x00000100
2667 +/* Disable
2668 +#define ICU0_IM1_IER_P4_DIS 0x00000000 */
2669 +/** Enable */
2670 +#define ICU0_IM1_IER_P4_EN 0x00000100
2671 +/** External Interrupt from GPIO P3
2672 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2673 +#define ICU0_IM1_IER_P3 0x00000080
2674 +/* Disable
2675 +#define ICU0_IM1_IER_P3_DIS 0x00000000 */
2676 +/** Enable */
2677 +#define ICU0_IM1_IER_P3_EN 0x00000080
2678 +/** External Interrupt from GPIO P2
2679 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2680 +#define ICU0_IM1_IER_P2 0x00000040
2681 +/* Disable
2682 +#define ICU0_IM1_IER_P2_DIS 0x00000000 */
2683 +/** Enable */
2684 +#define ICU0_IM1_IER_P2_EN 0x00000040
2685 +/** External Interrupt from GPIO P1
2686 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2687 +#define ICU0_IM1_IER_P1 0x00000020
2688 +/* Disable
2689 +#define ICU0_IM1_IER_P1_DIS 0x00000000 */
2690 +/** Enable */
2691 +#define ICU0_IM1_IER_P1_EN 0x00000020
2692 +/** External Interrupt from GPIO P0
2693 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2694 +#define ICU0_IM1_IER_P0 0x00000010
2695 +/* Disable
2696 +#define ICU0_IM1_IER_P0_DIS 0x00000000 */
2697 +/** Enable */
2698 +#define ICU0_IM1_IER_P0_EN 0x00000010
2699 +/** EBU Serial Flash Busy
2700 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2701 +#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004
2702 +/* Disable
2703 +#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */
2704 +/** Enable */
2705 +#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004
2706 +/** EBU Serial Flash Command Overwrite Error
2707 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2708 +#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002
2709 +/* Disable
2710 +#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */
2711 +/** Enable */
2712 +#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002
2713 +/** EBU Serial Flash Command Error
2714 +    Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
2715 +#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001
2716 +/* Disable
2717 +#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */
2718 +/** Enable */
2719 +#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001
2720 +
2721 +/* Fields of "IM1 Interrupt Output Status Register" */
2722 +/** Crossbar Error Interrupt
2723 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2724 +#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000
2725 +/* Nothing
2726 +#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */
2727 +/** Read: Interrupt occurred. */
2728 +#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000
2729 +/** DDR Controller Interrupt
2730 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2731 +#define ICU0_IM1_IOSR_DDR 0x40000000
2732 +/* Nothing
2733 +#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */
2734 +/** Read: Interrupt occurred. */
2735 +#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000
2736 +/** FPI Bus Control Unit Interrupt
2737 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2738 +#define ICU0_IM1_IOSR_BCU0 0x20000000
2739 +/* Nothing
2740 +#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */
2741 +/** Read: Interrupt occurred. */
2742 +#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000
2743 +/** SBIU interrupt
2744 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2745 +#define ICU0_IM1_IOSR_SBIU0 0x08000000
2746 +/* Nothing
2747 +#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */
2748 +/** Read: Interrupt occurred. */
2749 +#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000
2750 +/** Watchdog Prewarning Interrupt
2751 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2752 +#define ICU0_IM1_IOSR_WDT_PIR 0x02000000
2753 +/* Nothing
2754 +#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */
2755 +/** Read: Interrupt occurred. */
2756 +#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000
2757 +/** Watchdog Access Error Interrupt
2758 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2759 +#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000
2760 +/* Nothing
2761 +#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */
2762 +/** Read: Interrupt occurred. */
2763 +#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000
2764 +/** SYS GPE Interrupt
2765 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2766 +#define ICU0_IM1_IOSR_SYS_GPE 0x00200000
2767 +/* Nothing
2768 +#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */
2769 +/** Read: Interrupt occurred. */
2770 +#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000
2771 +/** SYS1 Interrupt
2772 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2773 +#define ICU0_IM1_IOSR_SYS1 0x00100000
2774 +/* Nothing
2775 +#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */
2776 +/** Read: Interrupt occurred. */
2777 +#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000
2778 +/** PMA Interrupt from IntNode of the RX Clk Domain
2779 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2780 +#define ICU0_IM1_IOSR_PMA_RX 0x00020000
2781 +/* Nothing
2782 +#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */
2783 +/** Read: Interrupt occurred. */
2784 +#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000
2785 +/** PMA Interrupt from IntNode of the TX Clk Domain
2786 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2787 +#define ICU0_IM1_IOSR_PMA_TX 0x00010000
2788 +/* Nothing
2789 +#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */
2790 +/** Read: Interrupt occurred. */
2791 +#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000
2792 +/** PMA Interrupt from IntNode of the 200MHz Domain
2793 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2794 +#define ICU0_IM1_IOSR_PMA_200M 0x00008000
2795 +/* Nothing
2796 +#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */
2797 +/** Read: Interrupt occurred. */
2798 +#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000
2799 +/** Time of Day
2800 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2801 +#define ICU0_IM1_IOSR_TOD 0x00004000
2802 +/* Nothing
2803 +#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */
2804 +/** Read: Interrupt occurred. */
2805 +#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000
2806 +/** 8kHz root interrupt derived from GPON interface
2807 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2808 +#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000
2809 +/* Nothing
2810 +#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */
2811 +/** Read: Interrupt occurred. */
2812 +#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000
2813 +/** FSC Timer Interrupt 1
2814 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2815 +#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000
2816 +/* Nothing
2817 +#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */
2818 +/** Read: Interrupt occurred. */
2819 +#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000
2820 +/** FSC Timer Interrupt 0
2821 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2822 +#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800
2823 +/* Nothing
2824 +#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */
2825 +/** Read: Interrupt occurred. */
2826 +#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800
2827 +/** 8kHz backup interrupt derived from core-PLL
2828 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2829 +#define ICU0_IM1_IOSR_FSC_BKP 0x00000400
2830 +/* Nothing
2831 +#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */
2832 +/** Read: Interrupt occurred. */
2833 +#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400
2834 +/** External Interrupt from GPIO P4
2835 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2836 +#define ICU0_IM1_IOSR_P4 0x00000100
2837 +/* Nothing
2838 +#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */
2839 +/** Read: Interrupt occurred. */
2840 +#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100
2841 +/** External Interrupt from GPIO P3
2842 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2843 +#define ICU0_IM1_IOSR_P3 0x00000080
2844 +/* Nothing
2845 +#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */
2846 +/** Read: Interrupt occurred. */
2847 +#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080
2848 +/** External Interrupt from GPIO P2
2849 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2850 +#define ICU0_IM1_IOSR_P2 0x00000040
2851 +/* Nothing
2852 +#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */
2853 +/** Read: Interrupt occurred. */
2854 +#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040
2855 +/** External Interrupt from GPIO P1
2856 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2857 +#define ICU0_IM1_IOSR_P1 0x00000020
2858 +/* Nothing
2859 +#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */
2860 +/** Read: Interrupt occurred. */
2861 +#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020
2862 +/** External Interrupt from GPIO P0
2863 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2864 +#define ICU0_IM1_IOSR_P0 0x00000010
2865 +/* Nothing
2866 +#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */
2867 +/** Read: Interrupt occurred. */
2868 +#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010
2869 +/** EBU Serial Flash Busy
2870 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2871 +#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004
2872 +/* Nothing
2873 +#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */
2874 +/** Read: Interrupt occurred. */
2875 +#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004
2876 +/** EBU Serial Flash Command Overwrite Error
2877 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2878 +#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002
2879 +/* Nothing
2880 +#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */
2881 +/** Read: Interrupt occurred. */
2882 +#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002
2883 +/** EBU Serial Flash Command Error
2884 +    Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
2885 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001
2886 +/* Nothing
2887 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */
2888 +/** Read: Interrupt occurred. */
2889 +#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001
2890 +
2891 +/* Fields of "IM1 Interrupt Request Set Register" */
2892 +/** Crossbar Error Interrupt
2893 +    Software control for the corresponding bit in the IM1_ISR register. */
2894 +#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000
2895 +/** DDR Controller Interrupt
2896 +    Software control for the corresponding bit in the IM1_ISR register. */
2897 +#define ICU0_IM1_IRSR_DDR 0x40000000
2898 +/** FPI Bus Control Unit Interrupt
2899 +    Software control for the corresponding bit in the IM1_ISR register. */
2900 +#define ICU0_IM1_IRSR_BCU0 0x20000000
2901 +/** SBIU interrupt
2902 +    Software control for the corresponding bit in the IM1_ISR register. */
2903 +#define ICU0_IM1_IRSR_SBIU0 0x08000000
2904 +/** Watchdog Prewarning Interrupt
2905 +    Software control for the corresponding bit in the IM1_ISR register. */
2906 +#define ICU0_IM1_IRSR_WDT_PIR 0x02000000
2907 +/** Watchdog Access Error Interrupt
2908 +    Software control for the corresponding bit in the IM1_ISR register. */
2909 +#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000
2910 +/** SYS GPE Interrupt
2911 +    Software control for the corresponding bit in the IM1_ISR register. */
2912 +#define ICU0_IM1_IRSR_SYS_GPE 0x00200000
2913 +/** SYS1 Interrupt
2914 +    Software control for the corresponding bit in the IM1_ISR register. */
2915 +#define ICU0_IM1_IRSR_SYS1 0x00100000
2916 +/** PMA Interrupt from IntNode of the RX Clk Domain
2917 +    Software control for the corresponding bit in the IM1_ISR register. */
2918 +#define ICU0_IM1_IRSR_PMA_RX 0x00020000
2919 +/** PMA Interrupt from IntNode of the TX Clk Domain
2920 +    Software control for the corresponding bit in the IM1_ISR register. */
2921 +#define ICU0_IM1_IRSR_PMA_TX 0x00010000
2922 +/** PMA Interrupt from IntNode of the 200MHz Domain
2923 +    Software control for the corresponding bit in the IM1_ISR register. */
2924 +#define ICU0_IM1_IRSR_PMA_200M 0x00008000
2925 +/** Time of Day
2926 +    Software control for the corresponding bit in the IM1_ISR register. */
2927 +#define ICU0_IM1_IRSR_TOD 0x00004000
2928 +/** 8kHz root interrupt derived from GPON interface
2929 +    Software control for the corresponding bit in the IM1_ISR register. */
2930 +#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000
2931 +/** FSC Timer Interrupt 1
2932 +    Software control for the corresponding bit in the IM1_ISR register. */
2933 +#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000
2934 +/** FSC Timer Interrupt 0
2935 +    Software control for the corresponding bit in the IM1_ISR register. */
2936 +#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800
2937 +/** 8kHz backup interrupt derived from core-PLL
2938 +    Software control for the corresponding bit in the IM1_ISR register. */
2939 +#define ICU0_IM1_IRSR_FSC_BKP 0x00000400
2940 +/** External Interrupt from GPIO P4
2941 +    Software control for the corresponding bit in the IM1_ISR register. */
2942 +#define ICU0_IM1_IRSR_P4 0x00000100
2943 +/** External Interrupt from GPIO P3
2944 +    Software control for the corresponding bit in the IM1_ISR register. */
2945 +#define ICU0_IM1_IRSR_P3 0x00000080
2946 +/** External Interrupt from GPIO P2
2947 +    Software control for the corresponding bit in the IM1_ISR register. */
2948 +#define ICU0_IM1_IRSR_P2 0x00000040
2949 +/** External Interrupt from GPIO P1
2950 +    Software control for the corresponding bit in the IM1_ISR register. */
2951 +#define ICU0_IM1_IRSR_P1 0x00000020
2952 +/** External Interrupt from GPIO P0
2953 +    Software control for the corresponding bit in the IM1_ISR register. */
2954 +#define ICU0_IM1_IRSR_P0 0x00000010
2955 +/** EBU Serial Flash Busy
2956 +    Software control for the corresponding bit in the IM1_ISR register. */
2957 +#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004
2958 +/** EBU Serial Flash Command Overwrite Error
2959 +    Software control for the corresponding bit in the IM1_ISR register. */
2960 +#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002
2961 +/** EBU Serial Flash Command Error
2962 +    Software control for the corresponding bit in the IM1_ISR register. */
2963 +#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001
2964 +
2965 +/* Fields of "IM1 Interrupt Mode Register" */
2966 +/** Crossbar Error Interrupt
2967 +    Type of interrupt. */
2968 +#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000
2969 +/* Indirect Interrupt.
2970 +#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */
2971 +/** Direct Interrupt. */
2972 +#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000
2973 +/** DDR Controller Interrupt
2974 +    Type of interrupt. */
2975 +#define ICU0_IM1_IMR_DDR 0x40000000
2976 +/* Indirect Interrupt.
2977 +#define ICU0_IM1_IMR_DDR_IND 0x00000000 */
2978 +/** Direct Interrupt. */
2979 +#define ICU0_IM1_IMR_DDR_DIR 0x40000000
2980 +/** FPI Bus Control Unit Interrupt
2981 +    Type of interrupt. */
2982 +#define ICU0_IM1_IMR_BCU0 0x20000000
2983 +/* Indirect Interrupt.
2984 +#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */
2985 +/** Direct Interrupt. */
2986 +#define ICU0_IM1_IMR_BCU0_DIR 0x20000000
2987 +/** SBIU interrupt
2988 +    Type of interrupt. */
2989 +#define ICU0_IM1_IMR_SBIU0 0x08000000
2990 +/* Indirect Interrupt.
2991 +#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */
2992 +/** Direct Interrupt. */
2993 +#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000
2994 +/** Watchdog Prewarning Interrupt
2995 +    Type of interrupt. */
2996 +#define ICU0_IM1_IMR_WDT_PIR 0x02000000
2997 +/* Indirect Interrupt.
2998 +#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */
2999 +/** Direct Interrupt. */
3000 +#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000
3001 +/** Watchdog Access Error Interrupt
3002 +    Type of interrupt. */
3003 +#define ICU0_IM1_IMR_WDT_AEIR 0x01000000
3004 +/* Indirect Interrupt.
3005 +#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */
3006 +/** Direct Interrupt. */
3007 +#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000
3008 +/** SYS GPE Interrupt
3009 +    Type of interrupt. */
3010 +#define ICU0_IM1_IMR_SYS_GPE 0x00200000
3011 +/* Indirect Interrupt.
3012 +#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */
3013 +/** Direct Interrupt. */
3014 +#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000
3015 +/** SYS1 Interrupt
3016 +    Type of interrupt. */
3017 +#define ICU0_IM1_IMR_SYS1 0x00100000
3018 +/* Indirect Interrupt.
3019 +#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */
3020 +/** Direct Interrupt. */
3021 +#define ICU0_IM1_IMR_SYS1_DIR 0x00100000
3022 +/** PMA Interrupt from IntNode of the RX Clk Domain
3023 +    Type of interrupt. */
3024 +#define ICU0_IM1_IMR_PMA_RX 0x00020000
3025 +/* Indirect Interrupt.
3026 +#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */
3027 +/** Direct Interrupt. */
3028 +#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000
3029 +/** PMA Interrupt from IntNode of the TX Clk Domain
3030 +    Type of interrupt. */
3031 +#define ICU0_IM1_IMR_PMA_TX 0x00010000
3032 +/* Indirect Interrupt.
3033 +#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */
3034 +/** Direct Interrupt. */
3035 +#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000
3036 +/** PMA Interrupt from IntNode of the 200MHz Domain
3037 +    Type of interrupt. */
3038 +#define ICU0_IM1_IMR_PMA_200M 0x00008000
3039 +/* Indirect Interrupt.
3040 +#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */
3041 +/** Direct Interrupt. */
3042 +#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000
3043 +/** Time of Day
3044 +    Type of interrupt. */
3045 +#define ICU0_IM1_IMR_TOD 0x00004000
3046 +/* Indirect Interrupt.
3047 +#define ICU0_IM1_IMR_TOD_IND 0x00000000 */
3048 +/** Direct Interrupt. */
3049 +#define ICU0_IM1_IMR_TOD_DIR 0x00004000
3050 +/** 8kHz root interrupt derived from GPON interface
3051 +    Type of interrupt. */
3052 +#define ICU0_IM1_IMR_FSC_ROOT 0x00002000
3053 +/* Indirect Interrupt.
3054 +#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */
3055 +/** Direct Interrupt. */
3056 +#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000
3057 +/** FSC Timer Interrupt 1
3058 +    Type of interrupt. */
3059 +#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000
3060 +/* Indirect Interrupt.
3061 +#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */
3062 +/** Direct Interrupt. */
3063 +#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000
3064 +/** FSC Timer Interrupt 0
3065 +    Type of interrupt. */
3066 +#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800
3067 +/* Indirect Interrupt.
3068 +#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */
3069 +/** Direct Interrupt. */
3070 +#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800
3071 +/** 8kHz backup interrupt derived from core-PLL
3072 +    Type of interrupt. */
3073 +#define ICU0_IM1_IMR_FSC_BKP 0x00000400
3074 +/* Indirect Interrupt.
3075 +#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */
3076 +/** Direct Interrupt. */
3077 +#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400
3078 +/** External Interrupt from GPIO P4
3079 +    Type of interrupt. */
3080 +#define ICU0_IM1_IMR_P4 0x00000100
3081 +/* Indirect Interrupt.
3082 +#define ICU0_IM1_IMR_P4_IND 0x00000000 */
3083 +/** Direct Interrupt. */
3084 +#define ICU0_IM1_IMR_P4_DIR 0x00000100
3085 +/** External Interrupt from GPIO P3
3086 +    Type of interrupt. */
3087 +#define ICU0_IM1_IMR_P3 0x00000080
3088 +/* Indirect Interrupt.
3089 +#define ICU0_IM1_IMR_P3_IND 0x00000000 */
3090 +/** Direct Interrupt. */
3091 +#define ICU0_IM1_IMR_P3_DIR 0x00000080
3092 +/** External Interrupt from GPIO P2
3093 +    Type of interrupt. */
3094 +#define ICU0_IM1_IMR_P2 0x00000040
3095 +/* Indirect Interrupt.
3096 +#define ICU0_IM1_IMR_P2_IND 0x00000000 */
3097 +/** Direct Interrupt. */
3098 +#define ICU0_IM1_IMR_P2_DIR 0x00000040
3099 +/** External Interrupt from GPIO P1
3100 +    Type of interrupt. */
3101 +#define ICU0_IM1_IMR_P1 0x00000020
3102 +/* Indirect Interrupt.
3103 +#define ICU0_IM1_IMR_P1_IND 0x00000000 */
3104 +/** Direct Interrupt. */
3105 +#define ICU0_IM1_IMR_P1_DIR 0x00000020
3106 +/** External Interrupt from GPIO P0
3107 +    Type of interrupt. */
3108 +#define ICU0_IM1_IMR_P0 0x00000010
3109 +/* Indirect Interrupt.
3110 +#define ICU0_IM1_IMR_P0_IND 0x00000000 */
3111 +/** Direct Interrupt. */
3112 +#define ICU0_IM1_IMR_P0_DIR 0x00000010
3113 +/** EBU Serial Flash Busy
3114 +    Type of interrupt. */
3115 +#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004
3116 +/* Indirect Interrupt.
3117 +#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */
3118 +/** Direct Interrupt. */
3119 +#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004
3120 +/** EBU Serial Flash Command Overwrite Error
3121 +    Type of interrupt. */
3122 +#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002
3123 +/* Indirect Interrupt.
3124 +#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */
3125 +/** Direct Interrupt. */
3126 +#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002
3127 +/** EBU Serial Flash Command Error
3128 +    Type of interrupt. */
3129 +#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001
3130 +/* Indirect Interrupt.
3131 +#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */
3132 +/** Direct Interrupt. */
3133 +#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001
3134 +
3135 +/* Fields of "IM2 Interrupt Status Register" */
3136 +/** EIM Interrupt
3137 +    This bit is an indirect interrupt. */
3138 +#define ICU0_IM2_ISR_EIM 0x80000000
3139 +/* Nothing
3140 +#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */
3141 +/** Write: Acknowledge the interrupt. */
3142 +#define ICU0_IM2_ISR_EIM_INTACK 0x80000000
3143 +/** Read: Interrupt occurred. */
3144 +#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000
3145 +/** GTC Upstream Interrupt
3146 +    This bit is an indirect interrupt. */
3147 +#define ICU0_IM2_ISR_GTC_US 0x40000000
3148 +/* Nothing
3149 +#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */
3150 +/** Write: Acknowledge the interrupt. */
3151 +#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000
3152 +/** Read: Interrupt occurred. */
3153 +#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000
3154 +/** GTC Downstream Interrupt
3155 +    This bit is an indirect interrupt. */
3156 +#define ICU0_IM2_ISR_GTC_DS 0x20000000
3157 +/* Nothing
3158 +#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */
3159 +/** Write: Acknowledge the interrupt. */
3160 +#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000
3161 +/** Read: Interrupt occurred. */
3162 +#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000
3163 +/** TBM Interrupt
3164 +    This bit is an indirect interrupt. */
3165 +#define ICU0_IM2_ISR_TBM 0x00400000
3166 +/* Nothing
3167 +#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */
3168 +/** Write: Acknowledge the interrupt. */
3169 +#define ICU0_IM2_ISR_TBM_INTACK 0x00400000
3170 +/** Read: Interrupt occurred. */
3171 +#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000
3172 +/** Dispatcher Interrupt
3173 +    This bit is an indirect interrupt. */
3174 +#define ICU0_IM2_ISR_DISP 0x00200000
3175 +/* Nothing
3176 +#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */
3177 +/** Write: Acknowledge the interrupt. */
3178 +#define ICU0_IM2_ISR_DISP_INTACK 0x00200000
3179 +/** Read: Interrupt occurred. */
3180 +#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000
3181 +/** CONFIG Interrupt
3182 +    This bit is an indirect interrupt. */
3183 +#define ICU0_IM2_ISR_CONFIG 0x00100000
3184 +/* Nothing
3185 +#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */
3186 +/** Write: Acknowledge the interrupt. */
3187 +#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000
3188 +/** Read: Interrupt occurred. */
3189 +#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000
3190 +/** CONFIG Break Interrupt
3191 +    This bit is an indirect interrupt. */
3192 +#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000
3193 +/* Nothing
3194 +#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */
3195 +/** Write: Acknowledge the interrupt. */
3196 +#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000
3197 +/** Read: Interrupt occurred. */
3198 +#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000
3199 +/** OCTRLC Interrupt
3200 +    This bit is an indirect interrupt. */
3201 +#define ICU0_IM2_ISR_OCTRLC 0x00040000
3202 +/* Nothing
3203 +#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */
3204 +/** Write: Acknowledge the interrupt. */
3205 +#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000
3206 +/** Read: Interrupt occurred. */
3207 +#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000
3208 +/** ICTRLC 1 Interrupt
3209 +    This bit is an indirect interrupt. */
3210 +#define ICU0_IM2_ISR_ICTRLC1 0x00020000
3211 +/* Nothing
3212 +#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */
3213 +/** Write: Acknowledge the interrupt. */
3214 +#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000
3215 +/** Read: Interrupt occurred. */
3216 +#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000
3217 +/** ICTRLC 0 Interrupt
3218 +    This bit is an indirect interrupt. */
3219 +#define ICU0_IM2_ISR_ICTRLC0 0x00010000
3220 +/* Nothing
3221 +#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */
3222 +/** Write: Acknowledge the interrupt. */
3223 +#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000
3224 +/** Read: Interrupt occurred. */
3225 +#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000
3226 +/** LINK 1 Interrupt
3227 +    This bit is an indirect interrupt. */
3228 +#define ICU0_IM2_ISR_LINK1 0x00004000
3229 +/* Nothing
3230 +#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */
3231 +/** Write: Acknowledge the interrupt. */
3232 +#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000
3233 +/** Read: Interrupt occurred. */
3234 +#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000
3235 +/** TMU Interrupt
3236 +    This bit is an indirect interrupt. */
3237 +#define ICU0_IM2_ISR_TMU 0x00001000
3238 +/* Nothing
3239 +#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */
3240 +/** Write: Acknowledge the interrupt. */
3241 +#define ICU0_IM2_ISR_TMU_INTACK 0x00001000
3242 +/** Read: Interrupt occurred. */
3243 +#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000
3244 +/** FSQM Interrupt
3245 +    This bit is an indirect interrupt. */
3246 +#define ICU0_IM2_ISR_FSQM 0x00000800
3247 +/* Nothing
3248 +#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */
3249 +/** Write: Acknowledge the interrupt. */
3250 +#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800
3251 +/** Read: Interrupt occurred. */
3252 +#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800
3253 +/** IQM Interrupt
3254 +    This bit is an indirect interrupt. */
3255 +#define ICU0_IM2_ISR_IQM 0x00000400
3256 +/* Nothing
3257 +#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */
3258 +/** Write: Acknowledge the interrupt. */
3259 +#define ICU0_IM2_ISR_IQM_INTACK 0x00000400
3260 +/** Read: Interrupt occurred. */
3261 +#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400
3262 +/** OCTRLG Interrupt
3263 +    This bit is an indirect interrupt. */
3264 +#define ICU0_IM2_ISR_OCTRLG 0x00000200
3265 +/* Nothing
3266 +#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */
3267 +/** Write: Acknowledge the interrupt. */
3268 +#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200
3269 +/** Read: Interrupt occurred. */
3270 +#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200
3271 +/** OCTRLL 3 Interrupt
3272 +    This bit is an indirect interrupt. */
3273 +#define ICU0_IM2_ISR_OCTRLL3 0x00000080
3274 +/* Nothing
3275 +#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */
3276 +/** Write: Acknowledge the interrupt. */
3277 +#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080
3278 +/** Read: Interrupt occurred. */
3279 +#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080
3280 +/** OCTRLL 2 Interrupt
3281 +    This bit is an indirect interrupt. */
3282 +#define ICU0_IM2_ISR_OCTRLL2 0x00000040
3283 +/* Nothing
3284 +#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */
3285 +/** Write: Acknowledge the interrupt. */
3286 +#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040
3287 +/** Read: Interrupt occurred. */
3288 +#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040
3289 +/** OCTRLL 1 Interrupt
3290 +    This bit is an indirect interrupt. */
3291 +#define ICU0_IM2_ISR_OCTRLL1 0x00000020
3292 +/* Nothing
3293 +#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */
3294 +/** Write: Acknowledge the interrupt. */
3295 +#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020
3296 +/** Read: Interrupt occurred. */
3297 +#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020
3298 +/** OCTRLL 0 Interrupt
3299 +    This bit is an indirect interrupt. */
3300 +#define ICU0_IM2_ISR_OCTRLL0 0x00000010
3301 +/* Nothing
3302 +#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */
3303 +/** Write: Acknowledge the interrupt. */
3304 +#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010
3305 +/** Read: Interrupt occurred. */
3306 +#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010
3307 +/** ICTRLL 3 Interrupt
3308 +    This bit is an indirect interrupt. */
3309 +#define ICU0_IM2_ISR_ICTRLL3 0x00000008
3310 +/* Nothing
3311 +#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */
3312 +/** Write: Acknowledge the interrupt. */
3313 +#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008
3314 +/** Read: Interrupt occurred. */
3315 +#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008
3316 +/** ICTRLL 2 Interrupt
3317 +    This bit is an indirect interrupt. */
3318 +#define ICU0_IM2_ISR_ICTRLL2 0x00000004
3319 +/* Nothing
3320 +#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */
3321 +/** Write: Acknowledge the interrupt. */
3322 +#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004
3323 +/** Read: Interrupt occurred. */
3324 +#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004
3325 +/** ICTRLL 1 Interrupt
3326 +    This bit is an indirect interrupt. */
3327 +#define ICU0_IM2_ISR_ICTRLL1 0x00000002
3328 +/* Nothing
3329 +#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */
3330 +/** Write: Acknowledge the interrupt. */
3331 +#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002
3332 +/** Read: Interrupt occurred. */
3333 +#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002
3334 +/** ICTRLL 0 Interrupt
3335 +    This bit is an indirect interrupt. */
3336 +#define ICU0_IM2_ISR_ICTRLL0 0x00000001
3337 +/* Nothing
3338 +#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */
3339 +/** Write: Acknowledge the interrupt. */
3340 +#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001
3341 +/** Read: Interrupt occurred. */
3342 +#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001
3343 +
3344 +/* Fields of "IM2 Interrupt Enable Register" */
3345 +/** EIM Interrupt
3346 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3347 +#define ICU0_IM2_IER_EIM 0x80000000
3348 +/* Disable
3349 +#define ICU0_IM2_IER_EIM_DIS 0x00000000 */
3350 +/** Enable */
3351 +#define ICU0_IM2_IER_EIM_EN 0x80000000
3352 +/** GTC Upstream Interrupt
3353 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3354 +#define ICU0_IM2_IER_GTC_US 0x40000000
3355 +/* Disable
3356 +#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */
3357 +/** Enable */
3358 +#define ICU0_IM2_IER_GTC_US_EN 0x40000000
3359 +/** GTC Downstream Interrupt
3360 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3361 +#define ICU0_IM2_IER_GTC_DS 0x20000000
3362 +/* Disable
3363 +#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */
3364 +/** Enable */
3365 +#define ICU0_IM2_IER_GTC_DS_EN 0x20000000
3366 +/** TBM Interrupt
3367 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3368 +#define ICU0_IM2_IER_TBM 0x00400000
3369 +/* Disable
3370 +#define ICU0_IM2_IER_TBM_DIS 0x00000000 */
3371 +/** Enable */
3372 +#define ICU0_IM2_IER_TBM_EN 0x00400000
3373 +/** Dispatcher Interrupt
3374 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3375 +#define ICU0_IM2_IER_DISP 0x00200000
3376 +/* Disable
3377 +#define ICU0_IM2_IER_DISP_DIS 0x00000000 */
3378 +/** Enable */
3379 +#define ICU0_IM2_IER_DISP_EN 0x00200000
3380 +/** CONFIG Interrupt
3381 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3382 +#define ICU0_IM2_IER_CONFIG 0x00100000
3383 +/* Disable
3384 +#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */
3385 +/** Enable */
3386 +#define ICU0_IM2_IER_CONFIG_EN 0x00100000
3387 +/** CONFIG Break Interrupt
3388 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3389 +#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000
3390 +/* Disable
3391 +#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */
3392 +/** Enable */
3393 +#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000
3394 +/** OCTRLC Interrupt
3395 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3396 +#define ICU0_IM2_IER_OCTRLC 0x00040000
3397 +/* Disable
3398 +#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */
3399 +/** Enable */
3400 +#define ICU0_IM2_IER_OCTRLC_EN 0x00040000
3401 +/** ICTRLC 1 Interrupt
3402 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3403 +#define ICU0_IM2_IER_ICTRLC1 0x00020000
3404 +/* Disable
3405 +#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */
3406 +/** Enable */
3407 +#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000
3408 +/** ICTRLC 0 Interrupt
3409 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3410 +#define ICU0_IM2_IER_ICTRLC0 0x00010000
3411 +/* Disable
3412 +#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */
3413 +/** Enable */
3414 +#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000
3415 +/** LINK 1 Interrupt
3416 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3417 +#define ICU0_IM2_IER_LINK1 0x00004000
3418 +/* Disable
3419 +#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */
3420 +/** Enable */
3421 +#define ICU0_IM2_IER_LINK1_EN 0x00004000
3422 +/** TMU Interrupt
3423 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3424 +#define ICU0_IM2_IER_TMU 0x00001000
3425 +/* Disable
3426 +#define ICU0_IM2_IER_TMU_DIS 0x00000000 */
3427 +/** Enable */
3428 +#define ICU0_IM2_IER_TMU_EN 0x00001000
3429 +/** FSQM Interrupt
3430 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3431 +#define ICU0_IM2_IER_FSQM 0x00000800
3432 +/* Disable
3433 +#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */
3434 +/** Enable */
3435 +#define ICU0_IM2_IER_FSQM_EN 0x00000800
3436 +/** IQM Interrupt
3437 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3438 +#define ICU0_IM2_IER_IQM 0x00000400
3439 +/* Disable
3440 +#define ICU0_IM2_IER_IQM_DIS 0x00000000 */
3441 +/** Enable */
3442 +#define ICU0_IM2_IER_IQM_EN 0x00000400
3443 +/** OCTRLG Interrupt
3444 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3445 +#define ICU0_IM2_IER_OCTRLG 0x00000200
3446 +/* Disable
3447 +#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */
3448 +/** Enable */
3449 +#define ICU0_IM2_IER_OCTRLG_EN 0x00000200
3450 +/** OCTRLL 3 Interrupt
3451 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3452 +#define ICU0_IM2_IER_OCTRLL3 0x00000080
3453 +/* Disable
3454 +#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */
3455 +/** Enable */
3456 +#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080
3457 +/** OCTRLL 2 Interrupt
3458 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3459 +#define ICU0_IM2_IER_OCTRLL2 0x00000040
3460 +/* Disable
3461 +#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */
3462 +/** Enable */
3463 +#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040
3464 +/** OCTRLL 1 Interrupt
3465 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3466 +#define ICU0_IM2_IER_OCTRLL1 0x00000020
3467 +/* Disable
3468 +#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */
3469 +/** Enable */
3470 +#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020
3471 +/** OCTRLL 0 Interrupt
3472 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3473 +#define ICU0_IM2_IER_OCTRLL0 0x00000010
3474 +/* Disable
3475 +#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */
3476 +/** Enable */
3477 +#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010
3478 +/** ICTRLL 3 Interrupt
3479 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3480 +#define ICU0_IM2_IER_ICTRLL3 0x00000008
3481 +/* Disable
3482 +#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */
3483 +/** Enable */
3484 +#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008
3485 +/** ICTRLL 2 Interrupt
3486 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3487 +#define ICU0_IM2_IER_ICTRLL2 0x00000004
3488 +/* Disable
3489 +#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */
3490 +/** Enable */
3491 +#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004
3492 +/** ICTRLL 1 Interrupt
3493 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3494 +#define ICU0_IM2_IER_ICTRLL1 0x00000002
3495 +/* Disable
3496 +#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */
3497 +/** Enable */
3498 +#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002
3499 +/** ICTRLL 0 Interrupt
3500 +    Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
3501 +#define ICU0_IM2_IER_ICTRLL0 0x00000001
3502 +/* Disable
3503 +#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */
3504 +/** Enable */
3505 +#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001
3506 +
3507 +/* Fields of "IM2 Interrupt Output Status Register" */
3508 +/** EIM Interrupt
3509 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3510 +#define ICU0_IM2_IOSR_EIM 0x80000000
3511 +/* Nothing
3512 +#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */
3513 +/** Read: Interrupt occurred. */
3514 +#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000
3515 +/** GTC Upstream Interrupt
3516 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3517 +#define ICU0_IM2_IOSR_GTC_US 0x40000000
3518 +/* Nothing
3519 +#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */
3520 +/** Read: Interrupt occurred. */
3521 +#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000
3522 +/** GTC Downstream Interrupt
3523 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3524 +#define ICU0_IM2_IOSR_GTC_DS 0x20000000
3525 +/* Nothing
3526 +#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */
3527 +/** Read: Interrupt occurred. */
3528 +#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000
3529 +/** TBM Interrupt
3530 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3531 +#define ICU0_IM2_IOSR_TBM 0x00400000
3532 +/* Nothing
3533 +#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */
3534 +/** Read: Interrupt occurred. */
3535 +#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000
3536 +/** Dispatcher Interrupt
3537 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3538 +#define ICU0_IM2_IOSR_DISP 0x00200000
3539 +/* Nothing
3540 +#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */
3541 +/** Read: Interrupt occurred. */
3542 +#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000
3543 +/** CONFIG Interrupt
3544 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3545 +#define ICU0_IM2_IOSR_CONFIG 0x00100000
3546 +/* Nothing
3547 +#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */
3548 +/** Read: Interrupt occurred. */
3549 +#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000
3550 +/** CONFIG Break Interrupt
3551 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3552 +#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000
3553 +/* Nothing
3554 +#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */
3555 +/** Read: Interrupt occurred. */
3556 +#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000
3557 +/** OCTRLC Interrupt
3558 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3559 +#define ICU0_IM2_IOSR_OCTRLC 0x00040000
3560 +/* Nothing
3561 +#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */
3562 +/** Read: Interrupt occurred. */
3563 +#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000
3564 +/** ICTRLC 1 Interrupt
3565 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3566 +#define ICU0_IM2_IOSR_ICTRLC1 0x00020000
3567 +/* Nothing
3568 +#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */
3569 +/** Read: Interrupt occurred. */
3570 +#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000
3571 +/** ICTRLC 0 Interrupt
3572 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3573 +#define ICU0_IM2_IOSR_ICTRLC0 0x00010000
3574 +/* Nothing
3575 +#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */
3576 +/** Read: Interrupt occurred. */
3577 +#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000
3578 +/** LINK 1 Interrupt
3579 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3580 +#define ICU0_IM2_IOSR_LINK1 0x00004000
3581 +/* Nothing
3582 +#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */
3583 +/** Read: Interrupt occurred. */
3584 +#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000
3585 +/** TMU Interrupt
3586 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3587 +#define ICU0_IM2_IOSR_TMU 0x00001000
3588 +/* Nothing
3589 +#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */
3590 +/** Read: Interrupt occurred. */
3591 +#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000
3592 +/** FSQM Interrupt
3593 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3594 +#define ICU0_IM2_IOSR_FSQM 0x00000800
3595 +/* Nothing
3596 +#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */
3597 +/** Read: Interrupt occurred. */
3598 +#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800
3599 +/** IQM Interrupt
3600 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3601 +#define ICU0_IM2_IOSR_IQM 0x00000400
3602 +/* Nothing
3603 +#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */
3604 +/** Read: Interrupt occurred. */
3605 +#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400
3606 +/** OCTRLG Interrupt
3607 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3608 +#define ICU0_IM2_IOSR_OCTRLG 0x00000200
3609 +/* Nothing
3610 +#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */
3611 +/** Read: Interrupt occurred. */
3612 +#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200
3613 +/** OCTRLL 3 Interrupt
3614 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3615 +#define ICU0_IM2_IOSR_OCTRLL3 0x00000080
3616 +/* Nothing
3617 +#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */
3618 +/** Read: Interrupt occurred. */
3619 +#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080
3620 +/** OCTRLL 2 Interrupt
3621 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3622 +#define ICU0_IM2_IOSR_OCTRLL2 0x00000040
3623 +/* Nothing
3624 +#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */
3625 +/** Read: Interrupt occurred. */
3626 +#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040
3627 +/** OCTRLL 1 Interrupt
3628 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3629 +#define ICU0_IM2_IOSR_OCTRLL1 0x00000020
3630 +/* Nothing
3631 +#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */
3632 +/** Read: Interrupt occurred. */
3633 +#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020
3634 +/** OCTRLL 0 Interrupt
3635 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3636 +#define ICU0_IM2_IOSR_OCTRLL0 0x00000010
3637 +/* Nothing
3638 +#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */
3639 +/** Read: Interrupt occurred. */
3640 +#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010
3641 +/** ICTRLL 3 Interrupt
3642 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3643 +#define ICU0_IM2_IOSR_ICTRLL3 0x00000008
3644 +/* Nothing
3645 +#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */
3646 +/** Read: Interrupt occurred. */
3647 +#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008
3648 +/** ICTRLL 2 Interrupt
3649 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3650 +#define ICU0_IM2_IOSR_ICTRLL2 0x00000004
3651 +/* Nothing
3652 +#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */
3653 +/** Read: Interrupt occurred. */
3654 +#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004
3655 +/** ICTRLL 1 Interrupt
3656 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3657 +#define ICU0_IM2_IOSR_ICTRLL1 0x00000002
3658 +/* Nothing
3659 +#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */
3660 +/** Read: Interrupt occurred. */
3661 +#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002
3662 +/** ICTRLL 0 Interrupt
3663 +    Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
3664 +#define ICU0_IM2_IOSR_ICTRLL0 0x00000001
3665 +/* Nothing
3666 +#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */
3667 +/** Read: Interrupt occurred. */
3668 +#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001
3669 +
3670 +/* Fields of "IM2 Interrupt Request Set Register" */
3671 +/** EIM Interrupt
3672 +    Software control for the corresponding bit in the IM2_ISR register. */
3673 +#define ICU0_IM2_IRSR_EIM 0x80000000
3674 +/** GTC Upstream Interrupt
3675 +    Software control for the corresponding bit in the IM2_ISR register. */
3676 +#define ICU0_IM2_IRSR_GTC_US 0x40000000
3677 +/** GTC Downstream Interrupt
3678 +    Software control for the corresponding bit in the IM2_ISR register. */
3679 +#define ICU0_IM2_IRSR_GTC_DS 0x20000000
3680 +/** TBM Interrupt
3681 +    Software control for the corresponding bit in the IM2_ISR register. */
3682 +#define ICU0_IM2_IRSR_TBM 0x00400000
3683 +/** Dispatcher Interrupt
3684 +    Software control for the corresponding bit in the IM2_ISR register. */
3685 +#define ICU0_IM2_IRSR_DISP 0x00200000
3686 +/** CONFIG Interrupt
3687 +    Software control for the corresponding bit in the IM2_ISR register. */
3688 +#define ICU0_IM2_IRSR_CONFIG 0x00100000
3689 +/** CONFIG Break Interrupt
3690 +    Software control for the corresponding bit in the IM2_ISR register. */
3691 +#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000
3692 +/** OCTRLC Interrupt
3693 +    Software control for the corresponding bit in the IM2_ISR register. */
3694 +#define ICU0_IM2_IRSR_OCTRLC 0x00040000
3695 +/** ICTRLC 1 Interrupt
3696 +    Software control for the corresponding bit in the IM2_ISR register. */
3697 +#define ICU0_IM2_IRSR_ICTRLC1 0x00020000
3698 +/** ICTRLC 0 Interrupt
3699 +    Software control for the corresponding bit in the IM2_ISR register. */
3700 +#define ICU0_IM2_IRSR_ICTRLC0 0x00010000
3701 +/** LINK 1 Interrupt
3702 +    Software control for the corresponding bit in the IM2_ISR register. */
3703 +#define ICU0_IM2_IRSR_LINK1 0x00004000
3704 +/** TMU Interrupt
3705 +    Software control for the corresponding bit in the IM2_ISR register. */
3706 +#define ICU0_IM2_IRSR_TMU 0x00001000
3707 +/** FSQM Interrupt
3708 +    Software control for the corresponding bit in the IM2_ISR register. */
3709 +#define ICU0_IM2_IRSR_FSQM 0x00000800
3710 +/** IQM Interrupt
3711 +    Software control for the corresponding bit in the IM2_ISR register. */
3712 +#define ICU0_IM2_IRSR_IQM 0x00000400
3713 +/** OCTRLG Interrupt
3714 +    Software control for the corresponding bit in the IM2_ISR register. */
3715 +#define ICU0_IM2_IRSR_OCTRLG 0x00000200
3716 +/** OCTRLL 3 Interrupt
3717 +    Software control for the corresponding bit in the IM2_ISR register. */
3718 +#define ICU0_IM2_IRSR_OCTRLL3 0x00000080
3719 +/** OCTRLL 2 Interrupt
3720 +    Software control for the corresponding bit in the IM2_ISR register. */
3721 +#define ICU0_IM2_IRSR_OCTRLL2 0x00000040
3722 +/** OCTRLL 1 Interrupt
3723 +    Software control for the corresponding bit in the IM2_ISR register. */
3724 +#define ICU0_IM2_IRSR_OCTRLL1 0x00000020
3725 +/** OCTRLL 0 Interrupt
3726 +    Software control for the corresponding bit in the IM2_ISR register. */
3727 +#define ICU0_IM2_IRSR_OCTRLL0 0x00000010
3728 +/** ICTRLL 3 Interrupt
3729 +    Software control for the corresponding bit in the IM2_ISR register. */
3730 +#define ICU0_IM2_IRSR_ICTRLL3 0x00000008
3731 +/** ICTRLL 2 Interrupt
3732 +    Software control for the corresponding bit in the IM2_ISR register. */
3733 +#define ICU0_IM2_IRSR_ICTRLL2 0x00000004
3734 +/** ICTRLL 1 Interrupt
3735 +    Software control for the corresponding bit in the IM2_ISR register. */
3736 +#define ICU0_IM2_IRSR_ICTRLL1 0x00000002
3737 +/** ICTRLL 0 Interrupt
3738 +    Software control for the corresponding bit in the IM2_ISR register. */
3739 +#define ICU0_IM2_IRSR_ICTRLL0 0x00000001
3740 +
3741 +/* Fields of "IM2 Interrupt Mode Register" */
3742 +/** EIM Interrupt
3743 +    Type of interrupt. */
3744 +#define ICU0_IM2_IMR_EIM 0x80000000
3745 +/* Indirect Interrupt.
3746 +#define ICU0_IM2_IMR_EIM_IND 0x00000000 */
3747 +/** Direct Interrupt. */
3748 +#define ICU0_IM2_IMR_EIM_DIR 0x80000000
3749 +/** GTC Upstream Interrupt
3750 +    Type of interrupt. */
3751 +#define ICU0_IM2_IMR_GTC_US 0x40000000
3752 +/* Indirect Interrupt.
3753 +#define ICU0_IM2_IMR_GTC_US_IND 0x00000000 */
3754 +/** Direct Interrupt. */
3755 +#define ICU0_IM2_IMR_GTC_US_DIR 0x40000000
3756 +/** GTC Downstream Interrupt
3757 +    Type of interrupt. */
3758 +#define ICU0_IM2_IMR_GTC_DS 0x20000000
3759 +/* Indirect Interrupt.
3760 +#define ICU0_IM2_IMR_GTC_DS_IND 0x00000000 */
3761 +/** Direct Interrupt. */
3762 +#define ICU0_IM2_IMR_GTC_DS_DIR 0x20000000
3763 +/** TBM Interrupt
3764 +    Type of interrupt. */
3765 +#define ICU0_IM2_IMR_TBM 0x00400000
3766 +/* Indirect Interrupt.
3767 +#define ICU0_IM2_IMR_TBM_IND 0x00000000 */
3768 +/** Direct Interrupt. */
3769 +#define ICU0_IM2_IMR_TBM_DIR 0x00400000
3770 +/** Dispatcher Interrupt
3771 +    Type of interrupt. */
3772 +#define ICU0_IM2_IMR_DISP 0x00200000
3773 +/* Indirect Interrupt.
3774 +#define ICU0_IM2_IMR_DISP_IND 0x00000000 */
3775 +/** Direct Interrupt. */
3776 +#define ICU0_IM2_IMR_DISP_DIR 0x00200000
3777 +/** CONFIG Interrupt
3778 +    Type of interrupt. */
3779 +#define ICU0_IM2_IMR_CONFIG 0x00100000
3780 +/* Indirect Interrupt.
3781 +#define ICU0_IM2_IMR_CONFIG_IND 0x00000000 */
3782 +/** Direct Interrupt. */
3783 +#define ICU0_IM2_IMR_CONFIG_DIR 0x00100000
3784 +/** CONFIG Break Interrupt
3785 +    Type of interrupt. */
3786 +#define ICU0_IM2_IMR_CONFIG_BREAK 0x00080000
3787 +/* Indirect Interrupt.
3788 +#define ICU0_IM2_IMR_CONFIG_BREAK_IND 0x00000000 */
3789 +/** Direct Interrupt. */
3790 +#define ICU0_IM2_IMR_CONFIG_BREAK_DIR 0x00080000
3791 +/** OCTRLC Interrupt
3792 +    Type of interrupt. */
3793 +#define ICU0_IM2_IMR_OCTRLC 0x00040000
3794 +/* Indirect Interrupt.
3795 +#define ICU0_IM2_IMR_OCTRLC_IND 0x00000000 */
3796 +/** Direct Interrupt. */
3797 +#define ICU0_IM2_IMR_OCTRLC_DIR 0x00040000
3798 +/** ICTRLC 1 Interrupt
3799 +    Type of interrupt. */
3800 +#define ICU0_IM2_IMR_ICTRLC1 0x00020000
3801 +/* Indirect Interrupt.
3802 +#define ICU0_IM2_IMR_ICTRLC1_IND 0x00000000 */
3803 +/** Direct Interrupt. */
3804 +#define ICU0_IM2_IMR_ICTRLC1_DIR 0x00020000
3805 +/** ICTRLC 0 Interrupt
3806 +    Type of interrupt. */
3807 +#define ICU0_IM2_IMR_ICTRLC0 0x00010000
3808 +/* Indirect Interrupt.
3809 +#define ICU0_IM2_IMR_ICTRLC0_IND 0x00000000 */
3810 +/** Direct Interrupt. */
3811 +#define ICU0_IM2_IMR_ICTRLC0_DIR 0x00010000
3812 +/** LINK 1 Interrupt
3813 +    Type of interrupt. */
3814 +#define ICU0_IM2_IMR_LINK1 0x00004000
3815 +/* Indirect Interrupt.
3816 +#define ICU0_IM2_IMR_LINK1_IND 0x00000000 */
3817 +/** Direct Interrupt. */
3818 +#define ICU0_IM2_IMR_LINK1_DIR 0x00004000
3819 +/** TMU Interrupt
3820 +    Type of interrupt. */
3821 +#define ICU0_IM2_IMR_TMU 0x00001000
3822 +/* Indirect Interrupt.
3823 +#define ICU0_IM2_IMR_TMU_IND 0x00000000 */
3824 +/** Direct Interrupt. */
3825 +#define ICU0_IM2_IMR_TMU_DIR 0x00001000
3826 +/** FSQM Interrupt
3827 +    Type of interrupt. */
3828 +#define ICU0_IM2_IMR_FSQM 0x00000800
3829 +/* Indirect Interrupt.
3830 +#define ICU0_IM2_IMR_FSQM_IND 0x00000000 */
3831 +/** Direct Interrupt. */
3832 +#define ICU0_IM2_IMR_FSQM_DIR 0x00000800
3833 +/** IQM Interrupt
3834 +    Type of interrupt. */
3835 +#define ICU0_IM2_IMR_IQM 0x00000400
3836 +/* Indirect Interrupt.
3837 +#define ICU0_IM2_IMR_IQM_IND 0x00000000 */
3838 +/** Direct Interrupt. */
3839 +#define ICU0_IM2_IMR_IQM_DIR 0x00000400
3840 +/** OCTRLG Interrupt
3841 +    Type of interrupt. */
3842 +#define ICU0_IM2_IMR_OCTRLG 0x00000200
3843 +/* Indirect Interrupt.
3844 +#define ICU0_IM2_IMR_OCTRLG_IND 0x00000000 */
3845 +/** Direct Interrupt. */
3846 +#define ICU0_IM2_IMR_OCTRLG_DIR 0x00000200
3847 +/** OCTRLL 3 Interrupt
3848 +    Type of interrupt. */
3849 +#define ICU0_IM2_IMR_OCTRLL3 0x00000080
3850 +/* Indirect Interrupt.
3851 +#define ICU0_IM2_IMR_OCTRLL3_IND 0x00000000 */
3852 +/** Direct Interrupt. */
3853 +#define ICU0_IM2_IMR_OCTRLL3_DIR 0x00000080
3854 +/** OCTRLL 2 Interrupt
3855 +    Type of interrupt. */
3856 +#define ICU0_IM2_IMR_OCTRLL2 0x00000040
3857 +/* Indirect Interrupt.
3858 +#define ICU0_IM2_IMR_OCTRLL2_IND 0x00000000 */
3859 +/** Direct Interrupt. */
3860 +#define ICU0_IM2_IMR_OCTRLL2_DIR 0x00000040
3861 +/** OCTRLL 1 Interrupt
3862 +    Type of interrupt. */
3863 +#define ICU0_IM2_IMR_OCTRLL1 0x00000020
3864 +/* Indirect Interrupt.
3865 +#define ICU0_IM2_IMR_OCTRLL1_IND 0x00000000 */
3866 +/** Direct Interrupt. */
3867 +#define ICU0_IM2_IMR_OCTRLL1_DIR 0x00000020
3868 +/** OCTRLL 0 Interrupt
3869 +    Type of interrupt. */
3870 +#define ICU0_IM2_IMR_OCTRLL0 0x00000010
3871 +/* Indirect Interrupt.
3872 +#define ICU0_IM2_IMR_OCTRLL0_IND 0x00000000 */
3873 +/** Direct Interrupt. */
3874 +#define ICU0_IM2_IMR_OCTRLL0_DIR 0x00000010
3875 +/** ICTRLL 3 Interrupt
3876 +    Type of interrupt. */
3877 +#define ICU0_IM2_IMR_ICTRLL3 0x00000008
3878 +/* Indirect Interrupt.
3879 +#define ICU0_IM2_IMR_ICTRLL3_IND 0x00000000 */
3880 +/** Direct Interrupt. */
3881 +#define ICU0_IM2_IMR_ICTRLL3_DIR 0x00000008
3882 +/** ICTRLL 2 Interrupt
3883 +    Type of interrupt. */
3884 +#define ICU0_IM2_IMR_ICTRLL2 0x00000004
3885 +/* Indirect Interrupt.
3886 +#define ICU0_IM2_IMR_ICTRLL2_IND 0x00000000 */
3887 +/** Direct Interrupt. */
3888 +#define ICU0_IM2_IMR_ICTRLL2_DIR 0x00000004
3889 +/** ICTRLL 1 Interrupt
3890 +    Type of interrupt. */
3891 +#define ICU0_IM2_IMR_ICTRLL1 0x00000002
3892 +/* Indirect Interrupt.
3893 +#define ICU0_IM2_IMR_ICTRLL1_IND 0x00000000 */
3894 +/** Direct Interrupt. */
3895 +#define ICU0_IM2_IMR_ICTRLL1_DIR 0x00000002
3896 +/** ICTRLL 0 Interrupt
3897 +    Type of interrupt. */
3898 +#define ICU0_IM2_IMR_ICTRLL0 0x00000001
3899 +/* Indirect Interrupt.
3900 +#define ICU0_IM2_IMR_ICTRLL0_IND 0x00000000 */
3901 +/** Direct Interrupt. */
3902 +#define ICU0_IM2_IMR_ICTRLL0_DIR 0x00000001
3903 +
3904 +/* Fields of "IM3 Interrupt Status Register" */
3905 +/** DFEV0, Channel 0 General Purpose Interrupt
3906 +    This bit is an indirect interrupt. */
3907 +#define ICU0_IM3_ISR_DFEV0_1GP 0x80000000
3908 +/* Nothing
3909 +#define ICU0_IM3_ISR_DFEV0_1GP_NULL 0x00000000 */
3910 +/** Write: Acknowledge the interrupt. */
3911 +#define ICU0_IM3_ISR_DFEV0_1GP_INTACK 0x80000000
3912 +/** Read: Interrupt occurred. */
3913 +#define ICU0_IM3_ISR_DFEV0_1GP_INTOCC 0x80000000
3914 +/** DFEV0, Channel 0 Receive Interrupt
3915 +    This bit is an indirect interrupt. */
3916 +#define ICU0_IM3_ISR_DFEV0_1RX 0x40000000
3917 +/* Nothing
3918 +#define ICU0_IM3_ISR_DFEV0_1RX_NULL 0x00000000 */
3919 +/** Write: Acknowledge the interrupt. */
3920 +#define ICU0_IM3_ISR_DFEV0_1RX_INTACK 0x40000000
3921 +/** Read: Interrupt occurred. */
3922 +#define ICU0_IM3_ISR_DFEV0_1RX_INTOCC 0x40000000
3923 +/** DFEV0, Channel 0 Transmit Interrupt
3924 +    This bit is an indirect interrupt. */
3925 +#define ICU0_IM3_ISR_DFEV0_1TX 0x20000000
3926 +/* Nothing
3927 +#define ICU0_IM3_ISR_DFEV0_1TX_NULL 0x00000000 */
3928 +/** Write: Acknowledge the interrupt. */
3929 +#define ICU0_IM3_ISR_DFEV0_1TX_INTACK 0x20000000
3930 +/** Read: Interrupt occurred. */
3931 +#define ICU0_IM3_ISR_DFEV0_1TX_INTOCC 0x20000000
3932 +/** DFEV0, Channel 1 General Purpose Interrupt
3933 +    This bit is an indirect interrupt. */
3934 +#define ICU0_IM3_ISR_DFEV0_2GP 0x10000000
3935 +/* Nothing
3936 +#define ICU0_IM3_ISR_DFEV0_2GP_NULL 0x00000000 */
3937 +/** Write: Acknowledge the interrupt. */
3938 +#define ICU0_IM3_ISR_DFEV0_2GP_INTACK 0x10000000
3939 +/** Read: Interrupt occurred. */
3940 +#define ICU0_IM3_ISR_DFEV0_2GP_INTOCC 0x10000000
3941 +/** DFEV0, Channel 1 Receive Interrupt
3942 +    This bit is an indirect interrupt. */
3943 +#define ICU0_IM3_ISR_DFEV0_2RX 0x08000000
3944 +/* Nothing
3945 +#define ICU0_IM3_ISR_DFEV0_2RX_NULL 0x00000000 */
3946 +/** Write: Acknowledge the interrupt. */
3947 +#define ICU0_IM3_ISR_DFEV0_2RX_INTACK 0x08000000
3948 +/** Read: Interrupt occurred. */
3949 +#define ICU0_IM3_ISR_DFEV0_2RX_INTOCC 0x08000000
3950 +/** DFEV0, Channel 1 Transmit Interrupt
3951 +    This bit is an indirect interrupt. */
3952 +#define ICU0_IM3_ISR_DFEV0_2TX 0x04000000
3953 +/* Nothing
3954 +#define ICU0_IM3_ISR_DFEV0_2TX_NULL 0x00000000 */
3955 +/** Write: Acknowledge the interrupt. */
3956 +#define ICU0_IM3_ISR_DFEV0_2TX_INTACK 0x04000000
3957 +/** Read: Interrupt occurred. */
3958 +#define ICU0_IM3_ISR_DFEV0_2TX_INTOCC 0x04000000
3959 +/** GPTC Timer/Counter 3B Interrupt
3960 +    This bit is a direct interrupt. */
3961 +#define ICU0_IM3_ISR_GPTC_TC3B 0x00200000
3962 +/* Nothing
3963 +#define ICU0_IM3_ISR_GPTC_TC3B_NULL 0x00000000 */
3964 +/** Write: Acknowledge the interrupt. */
3965 +#define ICU0_IM3_ISR_GPTC_TC3B_INTACK 0x00200000
3966 +/** Read: Interrupt occurred. */
3967 +#define ICU0_IM3_ISR_GPTC_TC3B_INTOCC 0x00200000
3968 +/** GPTC Timer/Counter 3A Interrupt
3969 +    This bit is a direct interrupt. */
3970 +#define ICU0_IM3_ISR_GPTC_TC3A 0x00100000
3971 +/* Nothing
3972 +#define ICU0_IM3_ISR_GPTC_TC3A_NULL 0x00000000 */
3973 +/** Write: Acknowledge the interrupt. */
3974 +#define ICU0_IM3_ISR_GPTC_TC3A_INTACK 0x00100000
3975 +/** Read: Interrupt occurred. */
3976 +#define ICU0_IM3_ISR_GPTC_TC3A_INTOCC 0x00100000
3977 +/** GPTC Timer/Counter 2B Interrupt
3978 +    This bit is a direct interrupt. */
3979 +#define ICU0_IM3_ISR_GPTC_TC2B 0x00080000
3980 +/* Nothing
3981 +#define ICU0_IM3_ISR_GPTC_TC2B_NULL 0x00000000 */
3982 +/** Write: Acknowledge the interrupt. */
3983 +#define ICU0_IM3_ISR_GPTC_TC2B_INTACK 0x00080000
3984 +/** Read: Interrupt occurred. */
3985 +#define ICU0_IM3_ISR_GPTC_TC2B_INTOCC 0x00080000
3986 +/** GPTC Timer/Counter 2A Interrupt
3987 +    This bit is a direct interrupt. */
3988 +#define ICU0_IM3_ISR_GPTC_TC2A 0x00040000
3989 +/* Nothing
3990 +#define ICU0_IM3_ISR_GPTC_TC2A_NULL 0x00000000 */
3991 +/** Write: Acknowledge the interrupt. */
3992 +#define ICU0_IM3_ISR_GPTC_TC2A_INTACK 0x00040000
3993 +/** Read: Interrupt occurred. */
3994 +#define ICU0_IM3_ISR_GPTC_TC2A_INTOCC 0x00040000
3995 +/** GPTC Timer/Counter 1B Interrupt
3996 +    This bit is a direct interrupt. */
3997 +#define ICU0_IM3_ISR_GPTC_TC1B 0x00020000
3998 +/* Nothing
3999 +#define ICU0_IM3_ISR_GPTC_TC1B_NULL 0x00000000 */
4000 +/** Write: Acknowledge the interrupt. */
4001 +#define ICU0_IM3_ISR_GPTC_TC1B_INTACK 0x00020000
4002 +/** Read: Interrupt occurred. */
4003 +#define ICU0_IM3_ISR_GPTC_TC1B_INTOCC 0x00020000
4004 +/** GPTC Timer/Counter 1A Interrupt
4005 +    This bit is a direct interrupt. */
4006 +#define ICU0_IM3_ISR_GPTC_TC1A 0x00010000
4007 +/* Nothing
4008 +#define ICU0_IM3_ISR_GPTC_TC1A_NULL 0x00000000 */
4009 +/** Write: Acknowledge the interrupt. */
4010 +#define ICU0_IM3_ISR_GPTC_TC1A_INTACK 0x00010000
4011 +/** Read: Interrupt occurred. */
4012 +#define ICU0_IM3_ISR_GPTC_TC1A_INTOCC 0x00010000
4013 +/** ASC1 Soft Flow Control Interrupt
4014 +    This bit is a direct interrupt. */
4015 +#define ICU0_IM3_ISR_ASC1_SFC 0x00008000
4016 +/* Nothing
4017 +#define ICU0_IM3_ISR_ASC1_SFC_NULL 0x00000000 */
4018 +/** Write: Acknowledge the interrupt. */
4019 +#define ICU0_IM3_ISR_ASC1_SFC_INTACK 0x00008000
4020 +/** Read: Interrupt occurred. */
4021 +#define ICU0_IM3_ISR_ASC1_SFC_INTOCC 0x00008000
4022 +/** ASC1 Modem Status Interrupt
4023 +    This bit is a direct interrupt. */
4024 +#define ICU0_IM3_ISR_ASC1_MS 0x00004000
4025 +/* Nothing
4026 +#define ICU0_IM3_ISR_ASC1_MS_NULL 0x00000000 */
4027 +/** Write: Acknowledge the interrupt. */
4028 +#define ICU0_IM3_ISR_ASC1_MS_INTACK 0x00004000
4029 +/** Read: Interrupt occurred. */
4030 +#define ICU0_IM3_ISR_ASC1_MS_INTOCC 0x00004000
4031 +/** ASC1 Autobaud Detection Interrupt
4032 +    This bit is a direct interrupt. */
4033 +#define ICU0_IM3_ISR_ASC1_ABDET 0x00002000
4034 +/* Nothing
4035 +#define ICU0_IM3_ISR_ASC1_ABDET_NULL 0x00000000 */
4036 +/** Write: Acknowledge the interrupt. */
4037 +#define ICU0_IM3_ISR_ASC1_ABDET_INTACK 0x00002000
4038 +/** Read: Interrupt occurred. */
4039 +#define ICU0_IM3_ISR_ASC1_ABDET_INTOCC 0x00002000
4040 +/** ASC1 Autobaud Start Interrupt
4041 +    This bit is a direct interrupt. */
4042 +#define ICU0_IM3_ISR_ASC1_ABST 0x00001000
4043 +/* Nothing
4044 +#define ICU0_IM3_ISR_ASC1_ABST_NULL 0x00000000 */
4045 +/** Write: Acknowledge the interrupt. */
4046 +#define ICU0_IM3_ISR_ASC1_ABST_INTACK 0x00001000
4047 +/** Read: Interrupt occurred. */
4048 +#define ICU0_IM3_ISR_ASC1_ABST_INTOCC 0x00001000
4049 +/** ASC1 Transmit Buffer Interrupt
4050 +    This bit is a direct interrupt. */
4051 +#define ICU0_IM3_ISR_ASC1_TB 0x00000800
4052 +/* Nothing
4053 +#define ICU0_IM3_ISR_ASC1_TB_NULL 0x00000000 */
4054 +/** Write: Acknowledge the interrupt. */
4055 +#define ICU0_IM3_ISR_ASC1_TB_INTACK 0x00000800
4056 +/** Read: Interrupt occurred. */
4057 +#define ICU0_IM3_ISR_ASC1_TB_INTOCC 0x00000800
4058 +/** ASC1 Error Interrupt
4059 +    This bit is a direct interrupt. */
4060 +#define ICU0_IM3_ISR_ASC1_E 0x00000400
4061 +/* Nothing
4062 +#define ICU0_IM3_ISR_ASC1_E_NULL 0x00000000 */
4063 +/** Write: Acknowledge the interrupt. */
4064 +#define ICU0_IM3_ISR_ASC1_E_INTACK 0x00000400
4065 +/** Read: Interrupt occurred. */
4066 +#define ICU0_IM3_ISR_ASC1_E_INTOCC 0x00000400
4067 +/** ASC1 Receive Interrupt
4068 +    This bit is a direct interrupt. */
4069 +#define ICU0_IM3_ISR_ASC1_R 0x00000200
4070 +/* Nothing
4071 +#define ICU0_IM3_ISR_ASC1_R_NULL 0x00000000 */
4072 +/** Write: Acknowledge the interrupt. */
4073 +#define ICU0_IM3_ISR_ASC1_R_INTACK 0x00000200
4074 +/** Read: Interrupt occurred. */
4075 +#define ICU0_IM3_ISR_ASC1_R_INTOCC 0x00000200
4076 +/** ASC1 Transmit Interrupt
4077 +    This bit is a direct interrupt. */
4078 +#define ICU0_IM3_ISR_ASC1_T 0x00000100
4079 +/* Nothing
4080 +#define ICU0_IM3_ISR_ASC1_T_NULL 0x00000000 */
4081 +/** Write: Acknowledge the interrupt. */
4082 +#define ICU0_IM3_ISR_ASC1_T_INTACK 0x00000100
4083 +/** Read: Interrupt occurred. */
4084 +#define ICU0_IM3_ISR_ASC1_T_INTOCC 0x00000100
4085 +/** ASC0 Soft Flow Control Interrupt
4086 +    This bit is a direct interrupt. */
4087 +#define ICU0_IM3_ISR_ASC0_SFC 0x00000080
4088 +/* Nothing
4089 +#define ICU0_IM3_ISR_ASC0_SFC_NULL 0x00000000 */
4090 +/** Write: Acknowledge the interrupt. */
4091 +#define ICU0_IM3_ISR_ASC0_SFC_INTACK 0x00000080
4092 +/** Read: Interrupt occurred. */
4093 +#define ICU0_IM3_ISR_ASC0_SFC_INTOCC 0x00000080
4094 +/** ASC1 Modem Status Interrupt
4095 +    This bit is a direct interrupt. */
4096 +#define ICU0_IM3_ISR_ASC0_MS 0x00000040
4097 +/* Nothing
4098 +#define ICU0_IM3_ISR_ASC0_MS_NULL 0x00000000 */
4099 +/** Write: Acknowledge the interrupt. */
4100 +#define ICU0_IM3_ISR_ASC0_MS_INTACK 0x00000040
4101 +/** Read: Interrupt occurred. */
4102 +#define ICU0_IM3_ISR_ASC0_MS_INTOCC 0x00000040
4103 +/** ASC0 Autobaud Detection Interrupt
4104 +    This bit is a direct interrupt. */
4105 +#define ICU0_IM3_ISR_ASC0_ABDET 0x00000020
4106 +/* Nothing
4107 +#define ICU0_IM3_ISR_ASC0_ABDET_NULL 0x00000000 */
4108 +/** Write: Acknowledge the interrupt. */
4109 +#define ICU0_IM3_ISR_ASC0_ABDET_INTACK 0x00000020
4110 +/** Read: Interrupt occurred. */
4111 +#define ICU0_IM3_ISR_ASC0_ABDET_INTOCC 0x00000020
4112 +/** ASC0 Autobaud Start Interrupt
4113 +    This bit is a direct interrupt. */
4114 +#define ICU0_IM3_ISR_ASC0_ABST 0x00000010
4115 +/* Nothing
4116 +#define ICU0_IM3_ISR_ASC0_ABST_NULL 0x00000000 */
4117 +/** Write: Acknowledge the interrupt. */
4118 +#define ICU0_IM3_ISR_ASC0_ABST_INTACK 0x00000010
4119 +/** Read: Interrupt occurred. */
4120 +#define ICU0_IM3_ISR_ASC0_ABST_INTOCC 0x00000010
4121 +/** ASC0 Transmit Buffer Interrupt
4122 +    This bit is a direct interrupt. */
4123 +#define ICU0_IM3_ISR_ASC0_TB 0x00000008
4124 +/* Nothing
4125 +#define ICU0_IM3_ISR_ASC0_TB_NULL 0x00000000 */
4126 +/** Write: Acknowledge the interrupt. */
4127 +#define ICU0_IM3_ISR_ASC0_TB_INTACK 0x00000008
4128 +/** Read: Interrupt occurred. */
4129 +#define ICU0_IM3_ISR_ASC0_TB_INTOCC 0x00000008
4130 +/** ASC0 Error Interrupt
4131 +    This bit is a direct interrupt. */
4132 +#define ICU0_IM3_ISR_ASC0_E 0x00000004
4133 +/* Nothing
4134 +#define ICU0_IM3_ISR_ASC0_E_NULL 0x00000000 */
4135 +/** Write: Acknowledge the interrupt. */
4136 +#define ICU0_IM3_ISR_ASC0_E_INTACK 0x00000004
4137 +/** Read: Interrupt occurred. */
4138 +#define ICU0_IM3_ISR_ASC0_E_INTOCC 0x00000004
4139 +/** ASC0 Receive Interrupt
4140 +    This bit is a direct interrupt. */
4141 +#define ICU0_IM3_ISR_ASC0_R 0x00000002
4142 +/* Nothing
4143 +#define ICU0_IM3_ISR_ASC0_R_NULL 0x00000000 */
4144 +/** Write: Acknowledge the interrupt. */
4145 +#define ICU0_IM3_ISR_ASC0_R_INTACK 0x00000002
4146 +/** Read: Interrupt occurred. */
4147 +#define ICU0_IM3_ISR_ASC0_R_INTOCC 0x00000002
4148 +/** ASC0 Transmit Interrupt
4149 +    This bit is a direct interrupt. */
4150 +#define ICU0_IM3_ISR_ASC0_T 0x00000001
4151 +/* Nothing
4152 +#define ICU0_IM3_ISR_ASC0_T_NULL 0x00000000 */
4153 +/** Write: Acknowledge the interrupt. */
4154 +#define ICU0_IM3_ISR_ASC0_T_INTACK 0x00000001
4155 +/** Read: Interrupt occurred. */
4156 +#define ICU0_IM3_ISR_ASC0_T_INTOCC 0x00000001
4157 +
4158 +/* Fields of "IM3 Interrupt Enable Register" */
4159 +/** DFEV0, Channel 0 General Purpose Interrupt
4160 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4161 +#define ICU0_IM3_IER_DFEV0_1GP 0x80000000
4162 +/* Disable
4163 +#define ICU0_IM3_IER_DFEV0_1GP_DIS 0x00000000 */
4164 +/** Enable */
4165 +#define ICU0_IM3_IER_DFEV0_1GP_EN 0x80000000
4166 +/** DFEV0, Channel 0 Receive Interrupt
4167 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4168 +#define ICU0_IM3_IER_DFEV0_1RX 0x40000000
4169 +/* Disable
4170 +#define ICU0_IM3_IER_DFEV0_1RX_DIS 0x00000000 */
4171 +/** Enable */
4172 +#define ICU0_IM3_IER_DFEV0_1RX_EN 0x40000000
4173 +/** DFEV0, Channel 0 Transmit Interrupt
4174 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4175 +#define ICU0_IM3_IER_DFEV0_1TX 0x20000000
4176 +/* Disable
4177 +#define ICU0_IM3_IER_DFEV0_1TX_DIS 0x00000000 */
4178 +/** Enable */
4179 +#define ICU0_IM3_IER_DFEV0_1TX_EN 0x20000000
4180 +/** DFEV0, Channel 1 General Purpose Interrupt
4181 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4182 +#define ICU0_IM3_IER_DFEV0_2GP 0x10000000
4183 +/* Disable
4184 +#define ICU0_IM3_IER_DFEV0_2GP_DIS 0x00000000 */
4185 +/** Enable */
4186 +#define ICU0_IM3_IER_DFEV0_2GP_EN 0x10000000
4187 +/** DFEV0, Channel 1 Receive Interrupt
4188 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4189 +#define ICU0_IM3_IER_DFEV0_2RX 0x08000000
4190 +/* Disable
4191 +#define ICU0_IM3_IER_DFEV0_2RX_DIS 0x00000000 */
4192 +/** Enable */
4193 +#define ICU0_IM3_IER_DFEV0_2RX_EN 0x08000000
4194 +/** DFEV0, Channel 1 Transmit Interrupt
4195 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4196 +#define ICU0_IM3_IER_DFEV0_2TX 0x04000000
4197 +/* Disable
4198 +#define ICU0_IM3_IER_DFEV0_2TX_DIS 0x00000000 */
4199 +/** Enable */
4200 +#define ICU0_IM3_IER_DFEV0_2TX_EN 0x04000000
4201 +/** GPTC Timer/Counter 3B Interrupt
4202 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4203 +#define ICU0_IM3_IER_GPTC_TC3B 0x00200000
4204 +/* Disable
4205 +#define ICU0_IM3_IER_GPTC_TC3B_DIS 0x00000000 */
4206 +/** Enable */
4207 +#define ICU0_IM3_IER_GPTC_TC3B_EN 0x00200000
4208 +/** GPTC Timer/Counter 3A Interrupt
4209 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4210 +#define ICU0_IM3_IER_GPTC_TC3A 0x00100000
4211 +/* Disable
4212 +#define ICU0_IM3_IER_GPTC_TC3A_DIS 0x00000000 */
4213 +/** Enable */
4214 +#define ICU0_IM3_IER_GPTC_TC3A_EN 0x00100000
4215 +/** GPTC Timer/Counter 2B Interrupt
4216 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4217 +#define ICU0_IM3_IER_GPTC_TC2B 0x00080000
4218 +/* Disable
4219 +#define ICU0_IM3_IER_GPTC_TC2B_DIS 0x00000000 */
4220 +/** Enable */
4221 +#define ICU0_IM3_IER_GPTC_TC2B_EN 0x00080000
4222 +/** GPTC Timer/Counter 2A Interrupt
4223 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4224 +#define ICU0_IM3_IER_GPTC_TC2A 0x00040000
4225 +/* Disable
4226 +#define ICU0_IM3_IER_GPTC_TC2A_DIS 0x00000000 */
4227 +/** Enable */
4228 +#define ICU0_IM3_IER_GPTC_TC2A_EN 0x00040000
4229 +/** GPTC Timer/Counter 1B Interrupt
4230 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4231 +#define ICU0_IM3_IER_GPTC_TC1B 0x00020000
4232 +/* Disable
4233 +#define ICU0_IM3_IER_GPTC_TC1B_DIS 0x00000000 */
4234 +/** Enable */
4235 +#define ICU0_IM3_IER_GPTC_TC1B_EN 0x00020000
4236 +/** GPTC Timer/Counter 1A Interrupt
4237 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4238 +#define ICU0_IM3_IER_GPTC_TC1A 0x00010000
4239 +/* Disable
4240 +#define ICU0_IM3_IER_GPTC_TC1A_DIS 0x00000000 */
4241 +/** Enable */
4242 +#define ICU0_IM3_IER_GPTC_TC1A_EN 0x00010000
4243 +/** ASC1 Soft Flow Control Interrupt
4244 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4245 +#define ICU0_IM3_IER_ASC1_SFC 0x00008000
4246 +/* Disable
4247 +#define ICU0_IM3_IER_ASC1_SFC_DIS 0x00000000 */
4248 +/** Enable */
4249 +#define ICU0_IM3_IER_ASC1_SFC_EN 0x00008000
4250 +/** ASC1 Modem Status Interrupt
4251 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4252 +#define ICU0_IM3_IER_ASC1_MS 0x00004000
4253 +/* Disable
4254 +#define ICU0_IM3_IER_ASC1_MS_DIS 0x00000000 */
4255 +/** Enable */
4256 +#define ICU0_IM3_IER_ASC1_MS_EN 0x00004000
4257 +/** ASC1 Autobaud Detection Interrupt
4258 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4259 +#define ICU0_IM3_IER_ASC1_ABDET 0x00002000
4260 +/* Disable
4261 +#define ICU0_IM3_IER_ASC1_ABDET_DIS 0x00000000 */
4262 +/** Enable */
4263 +#define ICU0_IM3_IER_ASC1_ABDET_EN 0x00002000
4264 +/** ASC1 Autobaud Start Interrupt
4265 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4266 +#define ICU0_IM3_IER_ASC1_ABST 0x00001000
4267 +/* Disable
4268 +#define ICU0_IM3_IER_ASC1_ABST_DIS 0x00000000 */
4269 +/** Enable */
4270 +#define ICU0_IM3_IER_ASC1_ABST_EN 0x00001000
4271 +/** ASC1 Transmit Buffer Interrupt
4272 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4273 +#define ICU0_IM3_IER_ASC1_TB 0x00000800
4274 +/* Disable
4275 +#define ICU0_IM3_IER_ASC1_TB_DIS 0x00000000 */
4276 +/** Enable */
4277 +#define ICU0_IM3_IER_ASC1_TB_EN 0x00000800
4278 +/** ASC1 Error Interrupt
4279 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4280 +#define ICU0_IM3_IER_ASC1_E 0x00000400
4281 +/* Disable
4282 +#define ICU0_IM3_IER_ASC1_E_DIS 0x00000000 */
4283 +/** Enable */
4284 +#define ICU0_IM3_IER_ASC1_E_EN 0x00000400
4285 +/** ASC1 Receive Interrupt
4286 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4287 +#define ICU0_IM3_IER_ASC1_R 0x00000200
4288 +/* Disable
4289 +#define ICU0_IM3_IER_ASC1_R_DIS 0x00000000 */
4290 +/** Enable */
4291 +#define ICU0_IM3_IER_ASC1_R_EN 0x00000200
4292 +/** ASC1 Transmit Interrupt
4293 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4294 +#define ICU0_IM3_IER_ASC1_T 0x00000100
4295 +/* Disable
4296 +#define ICU0_IM3_IER_ASC1_T_DIS 0x00000000 */
4297 +/** Enable */
4298 +#define ICU0_IM3_IER_ASC1_T_EN 0x00000100
4299 +/** ASC0 Soft Flow Control Interrupt
4300 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4301 +#define ICU0_IM3_IER_ASC0_SFC 0x00000080
4302 +/* Disable
4303 +#define ICU0_IM3_IER_ASC0_SFC_DIS 0x00000000 */
4304 +/** Enable */
4305 +#define ICU0_IM3_IER_ASC0_SFC_EN 0x00000080
4306 +/** ASC1 Modem Status Interrupt
4307 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4308 +#define ICU0_IM3_IER_ASC0_MS 0x00000040
4309 +/* Disable
4310 +#define ICU0_IM3_IER_ASC0_MS_DIS 0x00000000 */
4311 +/** Enable */
4312 +#define ICU0_IM3_IER_ASC0_MS_EN 0x00000040
4313 +/** ASC0 Autobaud Detection Interrupt
4314 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4315 +#define ICU0_IM3_IER_ASC0_ABDET 0x00000020
4316 +/* Disable
4317 +#define ICU0_IM3_IER_ASC0_ABDET_DIS 0x00000000 */
4318 +/** Enable */
4319 +#define ICU0_IM3_IER_ASC0_ABDET_EN 0x00000020
4320 +/** ASC0 Autobaud Start Interrupt
4321 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4322 +#define ICU0_IM3_IER_ASC0_ABST 0x00000010
4323 +/* Disable
4324 +#define ICU0_IM3_IER_ASC0_ABST_DIS 0x00000000 */
4325 +/** Enable */
4326 +#define ICU0_IM3_IER_ASC0_ABST_EN 0x00000010
4327 +/** ASC0 Transmit Buffer Interrupt
4328 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4329 +#define ICU0_IM3_IER_ASC0_TB 0x00000008
4330 +/* Disable
4331 +#define ICU0_IM3_IER_ASC0_TB_DIS 0x00000000 */
4332 +/** Enable */
4333 +#define ICU0_IM3_IER_ASC0_TB_EN 0x00000008
4334 +/** ASC0 Error Interrupt
4335 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4336 +#define ICU0_IM3_IER_ASC0_E 0x00000004
4337 +/* Disable
4338 +#define ICU0_IM3_IER_ASC0_E_DIS 0x00000000 */
4339 +/** Enable */
4340 +#define ICU0_IM3_IER_ASC0_E_EN 0x00000004
4341 +/** ASC0 Receive Interrupt
4342 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4343 +#define ICU0_IM3_IER_ASC0_R 0x00000002
4344 +/* Disable
4345 +#define ICU0_IM3_IER_ASC0_R_DIS 0x00000000 */
4346 +/** Enable */
4347 +#define ICU0_IM3_IER_ASC0_R_EN 0x00000002
4348 +/** ASC0 Transmit Interrupt
4349 +    Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
4350 +#define ICU0_IM3_IER_ASC0_T 0x00000001
4351 +/* Disable
4352 +#define ICU0_IM3_IER_ASC0_T_DIS 0x00000000 */
4353 +/** Enable */
4354 +#define ICU0_IM3_IER_ASC0_T_EN 0x00000001
4355 +
4356 +/* Fields of "IM3 Interrupt Output Status Register" */
4357 +/** DFEV0, Channel 0 General Purpose Interrupt
4358 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4359 +#define ICU0_IM3_IOSR_DFEV0_1GP 0x80000000
4360 +/* Nothing
4361 +#define ICU0_IM3_IOSR_DFEV0_1GP_NULL 0x00000000 */
4362 +/** Read: Interrupt occurred. */
4363 +#define ICU0_IM3_IOSR_DFEV0_1GP_INTOCC 0x80000000
4364 +/** DFEV0, Channel 0 Receive Interrupt
4365 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4366 +#define ICU0_IM3_IOSR_DFEV0_1RX 0x40000000
4367 +/* Nothing
4368 +#define ICU0_IM3_IOSR_DFEV0_1RX_NULL 0x00000000 */
4369 +/** Read: Interrupt occurred. */
4370 +#define ICU0_IM3_IOSR_DFEV0_1RX_INTOCC 0x40000000
4371 +/** DFEV0, Channel 0 Transmit Interrupt
4372 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4373 +#define ICU0_IM3_IOSR_DFEV0_1TX 0x20000000
4374 +/* Nothing
4375 +#define ICU0_IM3_IOSR_DFEV0_1TX_NULL 0x00000000 */
4376 +/** Read: Interrupt occurred. */
4377 +#define ICU0_IM3_IOSR_DFEV0_1TX_INTOCC 0x20000000
4378 +/** DFEV0, Channel 1 General Purpose Interrupt
4379 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4380 +#define ICU0_IM3_IOSR_DFEV0_2GP 0x10000000
4381 +/* Nothing
4382 +#define ICU0_IM3_IOSR_DFEV0_2GP_NULL 0x00000000 */
4383 +/** Read: Interrupt occurred. */
4384 +#define ICU0_IM3_IOSR_DFEV0_2GP_INTOCC 0x10000000
4385 +/** DFEV0, Channel 1 Receive Interrupt
4386 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4387 +#define ICU0_IM3_IOSR_DFEV0_2RX 0x08000000
4388 +/* Nothing
4389 +#define ICU0_IM3_IOSR_DFEV0_2RX_NULL 0x00000000 */
4390 +/** Read: Interrupt occurred. */
4391 +#define ICU0_IM3_IOSR_DFEV0_2RX_INTOCC 0x08000000
4392 +/** DFEV0, Channel 1 Transmit Interrupt
4393 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4394 +#define ICU0_IM3_IOSR_DFEV0_2TX 0x04000000
4395 +/* Nothing
4396 +#define ICU0_IM3_IOSR_DFEV0_2TX_NULL 0x00000000 */
4397 +/** Read: Interrupt occurred. */
4398 +#define ICU0_IM3_IOSR_DFEV0_2TX_INTOCC 0x04000000
4399 +/** GPTC Timer/Counter 3B Interrupt
4400 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4401 +#define ICU0_IM3_IOSR_GPTC_TC3B 0x00200000
4402 +/* Nothing
4403 +#define ICU0_IM3_IOSR_GPTC_TC3B_NULL 0x00000000 */
4404 +/** Read: Interrupt occurred. */
4405 +#define ICU0_IM3_IOSR_GPTC_TC3B_INTOCC 0x00200000
4406 +/** GPTC Timer/Counter 3A Interrupt
4407 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4408 +#define ICU0_IM3_IOSR_GPTC_TC3A 0x00100000
4409 +/* Nothing
4410 +#define ICU0_IM3_IOSR_GPTC_TC3A_NULL 0x00000000 */
4411 +/** Read: Interrupt occurred. */
4412 +#define ICU0_IM3_IOSR_GPTC_TC3A_INTOCC 0x00100000
4413 +/** GPTC Timer/Counter 2B Interrupt
4414 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4415 +#define ICU0_IM3_IOSR_GPTC_TC2B 0x00080000
4416 +/* Nothing
4417 +#define ICU0_IM3_IOSR_GPTC_TC2B_NULL 0x00000000 */
4418 +/** Read: Interrupt occurred. */
4419 +#define ICU0_IM3_IOSR_GPTC_TC2B_INTOCC 0x00080000
4420 +/** GPTC Timer/Counter 2A Interrupt
4421 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4422 +#define ICU0_IM3_IOSR_GPTC_TC2A 0x00040000
4423 +/* Nothing
4424 +#define ICU0_IM3_IOSR_GPTC_TC2A_NULL 0x00000000 */
4425 +/** Read: Interrupt occurred. */
4426 +#define ICU0_IM3_IOSR_GPTC_TC2A_INTOCC 0x00040000
4427 +/** GPTC Timer/Counter 1B Interrupt
4428 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4429 +#define ICU0_IM3_IOSR_GPTC_TC1B 0x00020000
4430 +/* Nothing
4431 +#define ICU0_IM3_IOSR_GPTC_TC1B_NULL 0x00000000 */
4432 +/** Read: Interrupt occurred. */
4433 +#define ICU0_IM3_IOSR_GPTC_TC1B_INTOCC 0x00020000
4434 +/** GPTC Timer/Counter 1A Interrupt
4435 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4436 +#define ICU0_IM3_IOSR_GPTC_TC1A 0x00010000
4437 +/* Nothing
4438 +#define ICU0_IM3_IOSR_GPTC_TC1A_NULL 0x00000000 */
4439 +/** Read: Interrupt occurred. */
4440 +#define ICU0_IM3_IOSR_GPTC_TC1A_INTOCC 0x00010000
4441 +/** ASC1 Soft Flow Control Interrupt
4442 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4443 +#define ICU0_IM3_IOSR_ASC1_SFC 0x00008000
4444 +/* Nothing
4445 +#define ICU0_IM3_IOSR_ASC1_SFC_NULL 0x00000000 */
4446 +/** Read: Interrupt occurred. */
4447 +#define ICU0_IM3_IOSR_ASC1_SFC_INTOCC 0x00008000
4448 +/** ASC1 Modem Status Interrupt
4449 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4450 +#define ICU0_IM3_IOSR_ASC1_MS 0x00004000
4451 +/* Nothing
4452 +#define ICU0_IM3_IOSR_ASC1_MS_NULL 0x00000000 */
4453 +/** Read: Interrupt occurred. */
4454 +#define ICU0_IM3_IOSR_ASC1_MS_INTOCC 0x00004000
4455 +/** ASC1 Autobaud Detection Interrupt
4456 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4457 +#define ICU0_IM3_IOSR_ASC1_ABDET 0x00002000
4458 +/* Nothing
4459 +#define ICU0_IM3_IOSR_ASC1_ABDET_NULL 0x00000000 */
4460 +/** Read: Interrupt occurred. */
4461 +#define ICU0_IM3_IOSR_ASC1_ABDET_INTOCC 0x00002000
4462 +/** ASC1 Autobaud Start Interrupt
4463 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4464 +#define ICU0_IM3_IOSR_ASC1_ABST 0x00001000
4465 +/* Nothing
4466 +#define ICU0_IM3_IOSR_ASC1_ABST_NULL 0x00000000 */
4467 +/** Read: Interrupt occurred. */
4468 +#define ICU0_IM3_IOSR_ASC1_ABST_INTOCC 0x00001000
4469 +/** ASC1 Transmit Buffer Interrupt
4470 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4471 +#define ICU0_IM3_IOSR_ASC1_TB 0x00000800
4472 +/* Nothing
4473 +#define ICU0_IM3_IOSR_ASC1_TB_NULL 0x00000000 */
4474 +/** Read: Interrupt occurred. */
4475 +#define ICU0_IM3_IOSR_ASC1_TB_INTOCC 0x00000800
4476 +/** ASC1 Error Interrupt
4477 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4478 +#define ICU0_IM3_IOSR_ASC1_E 0x00000400
4479 +/* Nothing
4480 +#define ICU0_IM3_IOSR_ASC1_E_NULL 0x00000000 */
4481 +/** Read: Interrupt occurred. */
4482 +#define ICU0_IM3_IOSR_ASC1_E_INTOCC 0x00000400
4483 +/** ASC1 Receive Interrupt
4484 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4485 +#define ICU0_IM3_IOSR_ASC1_R 0x00000200
4486 +/* Nothing
4487 +#define ICU0_IM3_IOSR_ASC1_R_NULL 0x00000000 */
4488 +/** Read: Interrupt occurred. */
4489 +#define ICU0_IM3_IOSR_ASC1_R_INTOCC 0x00000200
4490 +/** ASC1 Transmit Interrupt
4491 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4492 +#define ICU0_IM3_IOSR_ASC1_T 0x00000100
4493 +/* Nothing
4494 +#define ICU0_IM3_IOSR_ASC1_T_NULL 0x00000000 */
4495 +/** Read: Interrupt occurred. */
4496 +#define ICU0_IM3_IOSR_ASC1_T_INTOCC 0x00000100
4497 +/** ASC0 Soft Flow Control Interrupt
4498 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4499 +#define ICU0_IM3_IOSR_ASC0_SFC 0x00000080
4500 +/* Nothing
4501 +#define ICU0_IM3_IOSR_ASC0_SFC_NULL 0x00000000 */
4502 +/** Read: Interrupt occurred. */
4503 +#define ICU0_IM3_IOSR_ASC0_SFC_INTOCC 0x00000080
4504 +/** ASC1 Modem Status Interrupt
4505 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4506 +#define ICU0_IM3_IOSR_ASC0_MS 0x00000040
4507 +/* Nothing
4508 +#define ICU0_IM3_IOSR_ASC0_MS_NULL 0x00000000 */
4509 +/** Read: Interrupt occurred. */
4510 +#define ICU0_IM3_IOSR_ASC0_MS_INTOCC 0x00000040
4511 +/** ASC0 Autobaud Detection Interrupt
4512 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4513 +#define ICU0_IM3_IOSR_ASC0_ABDET 0x00000020
4514 +/* Nothing
4515 +#define ICU0_IM3_IOSR_ASC0_ABDET_NULL 0x00000000 */
4516 +/** Read: Interrupt occurred. */
4517 +#define ICU0_IM3_IOSR_ASC0_ABDET_INTOCC 0x00000020
4518 +/** ASC0 Autobaud Start Interrupt
4519 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4520 +#define ICU0_IM3_IOSR_ASC0_ABST 0x00000010
4521 +/* Nothing
4522 +#define ICU0_IM3_IOSR_ASC0_ABST_NULL 0x00000000 */
4523 +/** Read: Interrupt occurred. */
4524 +#define ICU0_IM3_IOSR_ASC0_ABST_INTOCC 0x00000010
4525 +/** ASC0 Transmit Buffer Interrupt
4526 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4527 +#define ICU0_IM3_IOSR_ASC0_TB 0x00000008
4528 +/* Nothing
4529 +#define ICU0_IM3_IOSR_ASC0_TB_NULL 0x00000000 */
4530 +/** Read: Interrupt occurred. */
4531 +#define ICU0_IM3_IOSR_ASC0_TB_INTOCC 0x00000008
4532 +/** ASC0 Error Interrupt
4533 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4534 +#define ICU0_IM3_IOSR_ASC0_E 0x00000004
4535 +/* Nothing
4536 +#define ICU0_IM3_IOSR_ASC0_E_NULL 0x00000000 */
4537 +/** Read: Interrupt occurred. */
4538 +#define ICU0_IM3_IOSR_ASC0_E_INTOCC 0x00000004
4539 +/** ASC0 Receive Interrupt
4540 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4541 +#define ICU0_IM3_IOSR_ASC0_R 0x00000002
4542 +/* Nothing
4543 +#define ICU0_IM3_IOSR_ASC0_R_NULL 0x00000000 */
4544 +/** Read: Interrupt occurred. */
4545 +#define ICU0_IM3_IOSR_ASC0_R_INTOCC 0x00000002
4546 +/** ASC0 Transmit Interrupt
4547 +    Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
4548 +#define ICU0_IM3_IOSR_ASC0_T 0x00000001
4549 +/* Nothing
4550 +#define ICU0_IM3_IOSR_ASC0_T_NULL 0x00000000 */
4551 +/** Read: Interrupt occurred. */
4552 +#define ICU0_IM3_IOSR_ASC0_T_INTOCC 0x00000001
4553 +
4554 +/* Fields of "IM3 Interrupt Request Set Register" */
4555 +/** DFEV0, Channel 0 General Purpose Interrupt
4556 +    Software control for the corresponding bit in the IM3_ISR register. */
4557 +#define ICU0_IM3_IRSR_DFEV0_1GP 0x80000000
4558 +/** DFEV0, Channel 0 Receive Interrupt
4559 +    Software control for the corresponding bit in the IM3_ISR register. */
4560 +#define ICU0_IM3_IRSR_DFEV0_1RX 0x40000000
4561 +/** DFEV0, Channel 0 Transmit Interrupt
4562 +    Software control for the corresponding bit in the IM3_ISR register. */
4563 +#define ICU0_IM3_IRSR_DFEV0_1TX 0x20000000
4564 +/** DFEV0, Channel 1 General Purpose Interrupt
4565 +    Software control for the corresponding bit in the IM3_ISR register. */
4566 +#define ICU0_IM3_IRSR_DFEV0_2GP 0x10000000
4567 +/** DFEV0, Channel 1 Receive Interrupt
4568 +    Software control for the corresponding bit in the IM3_ISR register. */
4569 +#define ICU0_IM3_IRSR_DFEV0_2RX 0x08000000
4570 +/** DFEV0, Channel 1 Transmit Interrupt
4571 +    Software control for the corresponding bit in the IM3_ISR register. */
4572 +#define ICU0_IM3_IRSR_DFEV0_2TX 0x04000000
4573 +/** GPTC Timer/Counter 3B Interrupt
4574 +    Software control for the corresponding bit in the IM3_ISR register. */
4575 +#define ICU0_IM3_IRSR_GPTC_TC3B 0x00200000
4576 +/** GPTC Timer/Counter 3A Interrupt
4577 +    Software control for the corresponding bit in the IM3_ISR register. */
4578 +#define ICU0_IM3_IRSR_GPTC_TC3A 0x00100000
4579 +/** GPTC Timer/Counter 2B Interrupt
4580 +    Software control for the corresponding bit in the IM3_ISR register. */
4581 +#define ICU0_IM3_IRSR_GPTC_TC2B 0x00080000
4582 +/** GPTC Timer/Counter 2A Interrupt
4583 +    Software control for the corresponding bit in the IM3_ISR register. */
4584 +#define ICU0_IM3_IRSR_GPTC_TC2A 0x00040000
4585 +/** GPTC Timer/Counter 1B Interrupt
4586 +    Software control for the corresponding bit in the IM3_ISR register. */
4587 +#define ICU0_IM3_IRSR_GPTC_TC1B 0x00020000
4588 +/** GPTC Timer/Counter 1A Interrupt
4589 +    Software control for the corresponding bit in the IM3_ISR register. */
4590 +#define ICU0_IM3_IRSR_GPTC_TC1A 0x00010000
4591 +/** ASC1 Soft Flow Control Interrupt
4592 +    Software control for the corresponding bit in the IM3_ISR register. */
4593 +#define ICU0_IM3_IRSR_ASC1_SFC 0x00008000
4594 +/** ASC1 Modem Status Interrupt
4595 +    Software control for the corresponding bit in the IM3_ISR register. */
4596 +#define ICU0_IM3_IRSR_ASC1_MS 0x00004000
4597 +/** ASC1 Autobaud Detection Interrupt
4598 +    Software control for the corresponding bit in the IM3_ISR register. */
4599 +#define ICU0_IM3_IRSR_ASC1_ABDET 0x00002000
4600 +/** ASC1 Autobaud Start Interrupt
4601 +    Software control for the corresponding bit in the IM3_ISR register. */
4602 +#define ICU0_IM3_IRSR_ASC1_ABST 0x00001000
4603 +/** ASC1 Transmit Buffer Interrupt
4604 +    Software control for the corresponding bit in the IM3_ISR register. */
4605 +#define ICU0_IM3_IRSR_ASC1_TB 0x00000800
4606 +/** ASC1 Error Interrupt
4607 +    Software control for the corresponding bit in the IM3_ISR register. */
4608 +#define ICU0_IM3_IRSR_ASC1_E 0x00000400
4609 +/** ASC1 Receive Interrupt
4610 +    Software control for the corresponding bit in the IM3_ISR register. */
4611 +#define ICU0_IM3_IRSR_ASC1_R 0x00000200
4612 +/** ASC1 Transmit Interrupt
4613 +    Software control for the corresponding bit in the IM3_ISR register. */
4614 +#define ICU0_IM3_IRSR_ASC1_T 0x00000100
4615 +/** ASC0 Soft Flow Control Interrupt
4616 +    Software control for the corresponding bit in the IM3_ISR register. */
4617 +#define ICU0_IM3_IRSR_ASC0_SFC 0x00000080
4618 +/** ASC1 Modem Status Interrupt
4619 +    Software control for the corresponding bit in the IM3_ISR register. */
4620 +#define ICU0_IM3_IRSR_ASC0_MS 0x00000040
4621 +/** ASC0 Autobaud Detection Interrupt
4622 +    Software control for the corresponding bit in the IM3_ISR register. */
4623 +#define ICU0_IM3_IRSR_ASC0_ABDET 0x00000020
4624 +/** ASC0 Autobaud Start Interrupt
4625 +    Software control for the corresponding bit in the IM3_ISR register. */
4626 +#define ICU0_IM3_IRSR_ASC0_ABST 0x00000010
4627 +/** ASC0 Transmit Buffer Interrupt
4628 +    Software control for the corresponding bit in the IM3_ISR register. */
4629 +#define ICU0_IM3_IRSR_ASC0_TB 0x00000008
4630 +/** ASC0 Error Interrupt
4631 +    Software control for the corresponding bit in the IM3_ISR register. */
4632 +#define ICU0_IM3_IRSR_ASC0_E 0x00000004
4633 +/** ASC0 Receive Interrupt
4634 +    Software control for the corresponding bit in the IM3_ISR register. */
4635 +#define ICU0_IM3_IRSR_ASC0_R 0x00000002
4636 +/** ASC0 Transmit Interrupt
4637 +    Software control for the corresponding bit in the IM3_ISR register. */
4638 +#define ICU0_IM3_IRSR_ASC0_T 0x00000001
4639 +
4640 +/* Fields of "IM3 Interrupt Mode Register" */
4641 +/** DFEV0, Channel 0 General Purpose Interrupt
4642 +    Type of interrupt. */
4643 +#define ICU0_IM3_IMR_DFEV0_1GP 0x80000000
4644 +/* Indirect Interrupt.
4645 +#define ICU0_IM3_IMR_DFEV0_1GP_IND 0x00000000 */
4646 +/** Direct Interrupt. */
4647 +#define ICU0_IM3_IMR_DFEV0_1GP_DIR 0x80000000
4648 +/** DFEV0, Channel 0 Receive Interrupt
4649 +    Type of interrupt. */
4650 +#define ICU0_IM3_IMR_DFEV0_1RX 0x40000000
4651 +/* Indirect Interrupt.
4652 +#define ICU0_IM3_IMR_DFEV0_1RX_IND 0x00000000 */
4653 +/** Direct Interrupt. */
4654 +#define ICU0_IM3_IMR_DFEV0_1RX_DIR 0x40000000
4655 +/** DFEV0, Channel 0 Transmit Interrupt
4656 +    Type of interrupt. */
4657 +#define ICU0_IM3_IMR_DFEV0_1TX 0x20000000
4658 +/* Indirect Interrupt.
4659 +#define ICU0_IM3_IMR_DFEV0_1TX_IND 0x00000000 */
4660 +/** Direct Interrupt. */
4661 +#define ICU0_IM3_IMR_DFEV0_1TX_DIR 0x20000000
4662 +/** DFEV0, Channel 1 General Purpose Interrupt
4663 +    Type of interrupt. */
4664 +#define ICU0_IM3_IMR_DFEV0_2GP 0x10000000
4665 +/* Indirect Interrupt.
4666 +#define ICU0_IM3_IMR_DFEV0_2GP_IND 0x00000000 */
4667 +/** Direct Interrupt. */
4668 +#define ICU0_IM3_IMR_DFEV0_2GP_DIR 0x10000000
4669 +/** DFEV0, Channel 1 Receive Interrupt
4670 +    Type of interrupt. */
4671 +#define ICU0_IM3_IMR_DFEV0_2RX 0x08000000
4672 +/* Indirect Interrupt.
4673 +#define ICU0_IM3_IMR_DFEV0_2RX_IND 0x00000000 */
4674 +/** Direct Interrupt. */
4675 +#define ICU0_IM3_IMR_DFEV0_2RX_DIR 0x08000000
4676 +/** DFEV0, Channel 1 Transmit Interrupt
4677 +    Type of interrupt. */
4678 +#define ICU0_IM3_IMR_DFEV0_2TX 0x04000000
4679 +/* Indirect Interrupt.
4680 +#define ICU0_IM3_IMR_DFEV0_2TX_IND 0x00000000 */
4681 +/** Direct Interrupt. */
4682 +#define ICU0_IM3_IMR_DFEV0_2TX_DIR 0x04000000
4683 +/** GPTC Timer/Counter 3B Interrupt
4684 +    Type of interrupt. */
4685 +#define ICU0_IM3_IMR_GPTC_TC3B 0x00200000
4686 +/* Indirect Interrupt.
4687 +#define ICU0_IM3_IMR_GPTC_TC3B_IND 0x00000000 */
4688 +/** Direct Interrupt. */
4689 +#define ICU0_IM3_IMR_GPTC_TC3B_DIR 0x00200000
4690 +/** GPTC Timer/Counter 3A Interrupt
4691 +    Type of interrupt. */
4692 +#define ICU0_IM3_IMR_GPTC_TC3A 0x00100000
4693 +/* Indirect Interrupt.
4694 +#define ICU0_IM3_IMR_GPTC_TC3A_IND 0x00000000 */
4695 +/** Direct Interrupt. */
4696 +#define ICU0_IM3_IMR_GPTC_TC3A_DIR 0x00100000
4697 +/** GPTC Timer/Counter 2B Interrupt
4698 +    Type of interrupt. */
4699 +#define ICU0_IM3_IMR_GPTC_TC2B 0x00080000
4700 +/* Indirect Interrupt.
4701 +#define ICU0_IM3_IMR_GPTC_TC2B_IND 0x00000000 */
4702 +/** Direct Interrupt. */
4703 +#define ICU0_IM3_IMR_GPTC_TC2B_DIR 0x00080000
4704 +/** GPTC Timer/Counter 2A Interrupt
4705 +    Type of interrupt. */
4706 +#define ICU0_IM3_IMR_GPTC_TC2A 0x00040000
4707 +/* Indirect Interrupt.
4708 +#define ICU0_IM3_IMR_GPTC_TC2A_IND 0x00000000 */
4709 +/** Direct Interrupt. */
4710 +#define ICU0_IM3_IMR_GPTC_TC2A_DIR 0x00040000
4711 +/** GPTC Timer/Counter 1B Interrupt
4712 +    Type of interrupt. */
4713 +#define ICU0_IM3_IMR_GPTC_TC1B 0x00020000
4714 +/* Indirect Interrupt.
4715 +#define ICU0_IM3_IMR_GPTC_TC1B_IND 0x00000000 */
4716 +/** Direct Interrupt. */
4717 +#define ICU0_IM3_IMR_GPTC_TC1B_DIR 0x00020000
4718 +/** GPTC Timer/Counter 1A Interrupt
4719 +    Type of interrupt. */
4720 +#define ICU0_IM3_IMR_GPTC_TC1A 0x00010000
4721 +/* Indirect Interrupt.
4722 +#define ICU0_IM3_IMR_GPTC_TC1A_IND 0x00000000 */
4723 +/** Direct Interrupt. */
4724 +#define ICU0_IM3_IMR_GPTC_TC1A_DIR 0x00010000
4725 +/** ASC1 Soft Flow Control Interrupt
4726 +    Type of interrupt. */
4727 +#define ICU0_IM3_IMR_ASC1_SFC 0x00008000
4728 +/* Indirect Interrupt.
4729 +#define ICU0_IM3_IMR_ASC1_SFC_IND 0x00000000 */
4730 +/** Direct Interrupt. */
4731 +#define ICU0_IM3_IMR_ASC1_SFC_DIR 0x00008000
4732 +/** ASC1 Modem Status Interrupt
4733 +    Type of interrupt. */
4734 +#define ICU0_IM3_IMR_ASC1_MS 0x00004000
4735 +/* Indirect Interrupt.
4736 +#define ICU0_IM3_IMR_ASC1_MS_IND 0x00000000 */
4737 +/** Direct Interrupt. */
4738 +#define ICU0_IM3_IMR_ASC1_MS_DIR 0x00004000
4739 +/** ASC1 Autobaud Detection Interrupt
4740 +    Type of interrupt. */
4741 +#define ICU0_IM3_IMR_ASC1_ABDET 0x00002000
4742 +/* Indirect Interrupt.
4743 +#define ICU0_IM3_IMR_ASC1_ABDET_IND 0x00000000 */
4744 +/** Direct Interrupt. */
4745 +#define ICU0_IM3_IMR_ASC1_ABDET_DIR 0x00002000
4746 +/** ASC1 Autobaud Start Interrupt
4747 +    Type of interrupt. */
4748 +#define ICU0_IM3_IMR_ASC1_ABST 0x00001000
4749 +/* Indirect Interrupt.
4750 +#define ICU0_IM3_IMR_ASC1_ABST_IND 0x00000000 */
4751 +/** Direct Interrupt. */
4752 +#define ICU0_IM3_IMR_ASC1_ABST_DIR 0x00001000
4753 +/** ASC1 Transmit Buffer Interrupt
4754 +    Type of interrupt. */
4755 +#define ICU0_IM3_IMR_ASC1_TB 0x00000800
4756 +/* Indirect Interrupt.
4757 +#define ICU0_IM3_IMR_ASC1_TB_IND 0x00000000 */
4758 +/** Direct Interrupt. */
4759 +#define ICU0_IM3_IMR_ASC1_TB_DIR 0x00000800
4760 +/** ASC1 Error Interrupt
4761 +    Type of interrupt. */
4762 +#define ICU0_IM3_IMR_ASC1_E 0x00000400
4763 +/* Indirect Interrupt.
4764 +#define ICU0_IM3_IMR_ASC1_E_IND 0x00000000 */
4765 +/** Direct Interrupt. */
4766 +#define ICU0_IM3_IMR_ASC1_E_DIR 0x00000400
4767 +/** ASC1 Receive Interrupt
4768 +    Type of interrupt. */
4769 +#define ICU0_IM3_IMR_ASC1_R 0x00000200
4770 +/* Indirect Interrupt.
4771 +#define ICU0_IM3_IMR_ASC1_R_IND 0x00000000 */
4772 +/** Direct Interrupt. */
4773 +#define ICU0_IM3_IMR_ASC1_R_DIR 0x00000200
4774 +/** ASC1 Transmit Interrupt
4775 +    Type of interrupt. */
4776 +#define ICU0_IM3_IMR_ASC1_T 0x00000100
4777 +/* Indirect Interrupt.
4778 +#define ICU0_IM3_IMR_ASC1_T_IND 0x00000000 */
4779 +/** Direct Interrupt. */
4780 +#define ICU0_IM3_IMR_ASC1_T_DIR 0x00000100
4781 +/** ASC0 Soft Flow Control Interrupt
4782 +    Type of interrupt. */
4783 +#define ICU0_IM3_IMR_ASC0_SFC 0x00000080
4784 +/* Indirect Interrupt.
4785 +#define ICU0_IM3_IMR_ASC0_SFC_IND 0x00000000 */
4786 +/** Direct Interrupt. */
4787 +#define ICU0_IM3_IMR_ASC0_SFC_DIR 0x00000080
4788 +/** ASC1 Modem Status Interrupt
4789 +    Type of interrupt. */
4790 +#define ICU0_IM3_IMR_ASC0_MS 0x00000040
4791 +/* Indirect Interrupt.
4792 +#define ICU0_IM3_IMR_ASC0_MS_IND 0x00000000 */
4793 +/** Direct Interrupt. */
4794 +#define ICU0_IM3_IMR_ASC0_MS_DIR 0x00000040
4795 +/** ASC0 Autobaud Detection Interrupt
4796 +    Type of interrupt. */
4797 +#define ICU0_IM3_IMR_ASC0_ABDET 0x00000020
4798 +/* Indirect Interrupt.
4799 +#define ICU0_IM3_IMR_ASC0_ABDET_IND 0x00000000 */
4800 +/** Direct Interrupt. */
4801 +#define ICU0_IM3_IMR_ASC0_ABDET_DIR 0x00000020
4802 +/** ASC0 Autobaud Start Interrupt
4803 +    Type of interrupt. */
4804 +#define ICU0_IM3_IMR_ASC0_ABST 0x00000010
4805 +/* Indirect Interrupt.
4806 +#define ICU0_IM3_IMR_ASC0_ABST_IND 0x00000000 */
4807 +/** Direct Interrupt. */
4808 +#define ICU0_IM3_IMR_ASC0_ABST_DIR 0x00000010
4809 +/** ASC0 Transmit Buffer Interrupt
4810 +    Type of interrupt. */
4811 +#define ICU0_IM3_IMR_ASC0_TB 0x00000008
4812 +/* Indirect Interrupt.
4813 +#define ICU0_IM3_IMR_ASC0_TB_IND 0x00000000 */
4814 +/** Direct Interrupt. */
4815 +#define ICU0_IM3_IMR_ASC0_TB_DIR 0x00000008
4816 +/** ASC0 Error Interrupt
4817 +    Type of interrupt. */
4818 +#define ICU0_IM3_IMR_ASC0_E 0x00000004
4819 +/* Indirect Interrupt.
4820 +#define ICU0_IM3_IMR_ASC0_E_IND 0x00000000 */
4821 +/** Direct Interrupt. */
4822 +#define ICU0_IM3_IMR_ASC0_E_DIR 0x00000004
4823 +/** ASC0 Receive Interrupt
4824 +    Type of interrupt. */
4825 +#define ICU0_IM3_IMR_ASC0_R 0x00000002
4826 +/* Indirect Interrupt.
4827 +#define ICU0_IM3_IMR_ASC0_R_IND 0x00000000 */
4828 +/** Direct Interrupt. */
4829 +#define ICU0_IM3_IMR_ASC0_R_DIR 0x00000002
4830 +/** ASC0 Transmit Interrupt
4831 +    Type of interrupt. */
4832 +#define ICU0_IM3_IMR_ASC0_T 0x00000001
4833 +/* Indirect Interrupt.
4834 +#define ICU0_IM3_IMR_ASC0_T_IND 0x00000000 */
4835 +/** Direct Interrupt. */
4836 +#define ICU0_IM3_IMR_ASC0_T_DIR 0x00000001
4837 +
4838 +/* Fields of "IM4 Interrupt Status Register" */
4839 +/** VPE0 Performance Monitoring Counter Interrupt
4840 +    This bit is an indirect interrupt. */
4841 +#define ICU0_IM4_ISR_VPE0_PMCIR 0x80000000
4842 +/* Nothing
4843 +#define ICU0_IM4_ISR_VPE0_PMCIR_NULL 0x00000000 */
4844 +/** Write: Acknowledge the interrupt. */
4845 +#define ICU0_IM4_ISR_VPE0_PMCIR_INTACK 0x80000000
4846 +/** Read: Interrupt occurred. */
4847 +#define ICU0_IM4_ISR_VPE0_PMCIR_INTOCC 0x80000000
4848 +/** VPE0 Error Level Flag Interrupt
4849 +    This bit is an indirect interrupt. */
4850 +#define ICU0_IM4_ISR_VPE0_ERL 0x40000000
4851 +/* Nothing
4852 +#define ICU0_IM4_ISR_VPE0_ERL_NULL 0x00000000 */
4853 +/** Write: Acknowledge the interrupt. */
4854 +#define ICU0_IM4_ISR_VPE0_ERL_INTACK 0x40000000
4855 +/** Read: Interrupt occurred. */
4856 +#define ICU0_IM4_ISR_VPE0_ERL_INTOCC 0x40000000
4857 +/** VPE0 Exception Level Flag Interrupt
4858 +    This bit is an indirect interrupt. */
4859 +#define ICU0_IM4_ISR_VPE0_EXL 0x20000000
4860 +/* Nothing
4861 +#define ICU0_IM4_ISR_VPE0_EXL_NULL 0x00000000 */
4862 +/** Write: Acknowledge the interrupt. */
4863 +#define ICU0_IM4_ISR_VPE0_EXL_INTACK 0x20000000
4864 +/** Read: Interrupt occurred. */
4865 +#define ICU0_IM4_ISR_VPE0_EXL_INTOCC 0x20000000
4866 +/** MPS Bin. Sem Interrupt to VPE0
4867 +    This bit is an indirect interrupt. */
4868 +#define ICU0_IM4_ISR_MPS_IR8 0x00400000
4869 +/* Nothing
4870 +#define ICU0_IM4_ISR_MPS_IR8_NULL 0x00000000 */
4871 +/** Write: Acknowledge the interrupt. */
4872 +#define ICU0_IM4_ISR_MPS_IR8_INTACK 0x00400000
4873 +/** Read: Interrupt occurred. */
4874 +#define ICU0_IM4_ISR_MPS_IR8_INTOCC 0x00400000
4875 +/** MPS Global Interrupt to VPE0
4876 +    This bit is an indirect interrupt. */
4877 +#define ICU0_IM4_ISR_MPS_IR7 0x00200000
4878 +/* Nothing
4879 +#define ICU0_IM4_ISR_MPS_IR7_NULL 0x00000000 */
4880 +/** Write: Acknowledge the interrupt. */
4881 +#define ICU0_IM4_ISR_MPS_IR7_INTACK 0x00200000
4882 +/** Read: Interrupt occurred. */
4883 +#define ICU0_IM4_ISR_MPS_IR7_INTOCC 0x00200000
4884 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
4885 +    This bit is an indirect interrupt. */
4886 +#define ICU0_IM4_ISR_MPS_IR6 0x00100000
4887 +/* Nothing
4888 +#define ICU0_IM4_ISR_MPS_IR6_NULL 0x00000000 */
4889 +/** Write: Acknowledge the interrupt. */
4890 +#define ICU0_IM4_ISR_MPS_IR6_INTACK 0x00100000
4891 +/** Read: Interrupt occurred. */
4892 +#define ICU0_IM4_ISR_MPS_IR6_INTOCC 0x00100000
4893 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
4894 +    This bit is an indirect interrupt. */
4895 +#define ICU0_IM4_ISR_MPS_IR5 0x00080000
4896 +/* Nothing
4897 +#define ICU0_IM4_ISR_MPS_IR5_NULL 0x00000000 */
4898 +/** Write: Acknowledge the interrupt. */
4899 +#define ICU0_IM4_ISR_MPS_IR5_INTACK 0x00080000
4900 +/** Read: Interrupt occurred. */
4901 +#define ICU0_IM4_ISR_MPS_IR5_INTOCC 0x00080000
4902 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
4903 +    This bit is an indirect interrupt. */
4904 +#define ICU0_IM4_ISR_MPS_IR4 0x00040000
4905 +/* Nothing
4906 +#define ICU0_IM4_ISR_MPS_IR4_NULL 0x00000000 */
4907 +/** Write: Acknowledge the interrupt. */
4908 +#define ICU0_IM4_ISR_MPS_IR4_INTACK 0x00040000
4909 +/** Read: Interrupt occurred. */
4910 +#define ICU0_IM4_ISR_MPS_IR4_INTOCC 0x00040000
4911 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
4912 +    This bit is an indirect interrupt. */
4913 +#define ICU0_IM4_ISR_MPS_IR3 0x00020000
4914 +/* Nothing
4915 +#define ICU0_IM4_ISR_MPS_IR3_NULL 0x00000000 */
4916 +/** Write: Acknowledge the interrupt. */
4917 +#define ICU0_IM4_ISR_MPS_IR3_INTACK 0x00020000
4918 +/** Read: Interrupt occurred. */
4919 +#define ICU0_IM4_ISR_MPS_IR3_INTOCC 0x00020000
4920 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
4921 +    This bit is an indirect interrupt. */
4922 +#define ICU0_IM4_ISR_MPS_IR2 0x00010000
4923 +/* Nothing
4924 +#define ICU0_IM4_ISR_MPS_IR2_NULL 0x00000000 */
4925 +/** Write: Acknowledge the interrupt. */
4926 +#define ICU0_IM4_ISR_MPS_IR2_INTACK 0x00010000
4927 +/** Read: Interrupt occurred. */
4928 +#define ICU0_IM4_ISR_MPS_IR2_INTOCC 0x00010000
4929 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
4930 +    This bit is an indirect interrupt. */
4931 +#define ICU0_IM4_ISR_MPS_IR1 0x00008000
4932 +/* Nothing
4933 +#define ICU0_IM4_ISR_MPS_IR1_NULL 0x00000000 */
4934 +/** Write: Acknowledge the interrupt. */
4935 +#define ICU0_IM4_ISR_MPS_IR1_INTACK 0x00008000
4936 +/** Read: Interrupt occurred. */
4937 +#define ICU0_IM4_ISR_MPS_IR1_INTOCC 0x00008000
4938 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
4939 +    This bit is an indirect interrupt. */
4940 +#define ICU0_IM4_ISR_MPS_IR0 0x00004000
4941 +/* Nothing
4942 +#define ICU0_IM4_ISR_MPS_IR0_NULL 0x00000000 */
4943 +/** Write: Acknowledge the interrupt. */
4944 +#define ICU0_IM4_ISR_MPS_IR0_INTACK 0x00004000
4945 +/** Read: Interrupt occurred. */
4946 +#define ICU0_IM4_ISR_MPS_IR0_INTOCC 0x00004000
4947 +/** TMU Error
4948 +    This bit is an indirect interrupt. */
4949 +#define ICU0_IM4_ISR_TMU_ERR 0x00001000
4950 +/* Nothing
4951 +#define ICU0_IM4_ISR_TMU_ERR_NULL 0x00000000 */
4952 +/** Write: Acknowledge the interrupt. */
4953 +#define ICU0_IM4_ISR_TMU_ERR_INTACK 0x00001000
4954 +/** Read: Interrupt occurred. */
4955 +#define ICU0_IM4_ISR_TMU_ERR_INTOCC 0x00001000
4956 +/** FSQM Error
4957 +    This bit is an indirect interrupt. */
4958 +#define ICU0_IM4_ISR_FSQM_ERR 0x00000800
4959 +/* Nothing
4960 +#define ICU0_IM4_ISR_FSQM_ERR_NULL 0x00000000 */
4961 +/** Write: Acknowledge the interrupt. */
4962 +#define ICU0_IM4_ISR_FSQM_ERR_INTACK 0x00000800
4963 +/** Read: Interrupt occurred. */
4964 +#define ICU0_IM4_ISR_FSQM_ERR_INTOCC 0x00000800
4965 +/** IQM Error
4966 +    This bit is an indirect interrupt. */
4967 +#define ICU0_IM4_ISR_IQM_ERR 0x00000400
4968 +/* Nothing
4969 +#define ICU0_IM4_ISR_IQM_ERR_NULL 0x00000000 */
4970 +/** Write: Acknowledge the interrupt. */
4971 +#define ICU0_IM4_ISR_IQM_ERR_INTACK 0x00000400
4972 +/** Read: Interrupt occurred. */
4973 +#define ICU0_IM4_ISR_IQM_ERR_INTOCC 0x00000400
4974 +/** OCTRLG Error
4975 +    This bit is an indirect interrupt. */
4976 +#define ICU0_IM4_ISR_OCTRLG_ERR 0x00000200
4977 +/* Nothing
4978 +#define ICU0_IM4_ISR_OCTRLG_ERR_NULL 0x00000000 */
4979 +/** Write: Acknowledge the interrupt. */
4980 +#define ICU0_IM4_ISR_OCTRLG_ERR_INTACK 0x00000200
4981 +/** Read: Interrupt occurred. */
4982 +#define ICU0_IM4_ISR_OCTRLG_ERR_INTOCC 0x00000200
4983 +/** ICTRLG Error
4984 +    This bit is an indirect interrupt. */
4985 +#define ICU0_IM4_ISR_ICTRLG_ERR 0x00000100
4986 +/* Nothing
4987 +#define ICU0_IM4_ISR_ICTRLG_ERR_NULL 0x00000000 */
4988 +/** Write: Acknowledge the interrupt. */
4989 +#define ICU0_IM4_ISR_ICTRLG_ERR_INTACK 0x00000100
4990 +/** Read: Interrupt occurred. */
4991 +#define ICU0_IM4_ISR_ICTRLG_ERR_INTOCC 0x00000100
4992 +/** OCTRLL 3 Error
4993 +    This bit is an indirect interrupt. */
4994 +#define ICU0_IM4_ISR_OCTRLL3_ERR 0x00000080
4995 +/* Nothing
4996 +#define ICU0_IM4_ISR_OCTRLL3_ERR_NULL 0x00000000 */
4997 +/** Write: Acknowledge the interrupt. */
4998 +#define ICU0_IM4_ISR_OCTRLL3_ERR_INTACK 0x00000080
4999 +/** Read: Interrupt occurred. */
5000 +#define ICU0_IM4_ISR_OCTRLL3_ERR_INTOCC 0x00000080
5001 +/** OCTRLL 2 Error
5002 +    This bit is an indirect interrupt. */
5003 +#define ICU0_IM4_ISR_OCTRLL2_ERR 0x00000040
5004 +/* Nothing
5005 +#define ICU0_IM4_ISR_OCTRLL2_ERR_NULL 0x00000000 */
5006 +/** Write: Acknowledge the interrupt. */
5007 +#define ICU0_IM4_ISR_OCTRLL2_ERR_INTACK 0x00000040
5008 +/** Read: Interrupt occurred. */
5009 +#define ICU0_IM4_ISR_OCTRLL2_ERR_INTOCC 0x00000040
5010 +/** OCTRLL 1 Error
5011 +    This bit is an indirect interrupt. */
5012 +#define ICU0_IM4_ISR_OCTRLL1_ERR 0x00000020
5013 +/* Nothing
5014 +#define ICU0_IM4_ISR_OCTRLL1_ERR_NULL 0x00000000 */
5015 +/** Write: Acknowledge the interrupt. */
5016 +#define ICU0_IM4_ISR_OCTRLL1_ERR_INTACK 0x00000020
5017 +/** Read: Interrupt occurred. */
5018 +#define ICU0_IM4_ISR_OCTRLL1_ERR_INTOCC 0x00000020
5019 +/** OCTRLL 0 Error
5020 +    This bit is an indirect interrupt. */
5021 +#define ICU0_IM4_ISR_OCTRLL0_ERR 0x00000010
5022 +/* Nothing
5023 +#define ICU0_IM4_ISR_OCTRLL0_ERR_NULL 0x00000000 */
5024 +/** Write: Acknowledge the interrupt. */
5025 +#define ICU0_IM4_ISR_OCTRLL0_ERR_INTACK 0x00000010
5026 +/** Read: Interrupt occurred. */
5027 +#define ICU0_IM4_ISR_OCTRLL0_ERR_INTOCC 0x00000010
5028 +/** ICTRLL 3 Error
5029 +    This bit is an indirect interrupt. */
5030 +#define ICU0_IM4_ISR_ICTRLL3_ERR 0x00000008
5031 +/* Nothing
5032 +#define ICU0_IM4_ISR_ICTRLL3_ERR_NULL 0x00000000 */
5033 +/** Write: Acknowledge the interrupt. */
5034 +#define ICU0_IM4_ISR_ICTRLL3_ERR_INTACK 0x00000008
5035 +/** Read: Interrupt occurred. */
5036 +#define ICU0_IM4_ISR_ICTRLL3_ERR_INTOCC 0x00000008
5037 +/** ICTRLL 2 Error
5038 +    This bit is an indirect interrupt. */
5039 +#define ICU0_IM4_ISR_ICTRLL2_ERR 0x00000004
5040 +/* Nothing
5041 +#define ICU0_IM4_ISR_ICTRLL2_ERR_NULL 0x00000000 */
5042 +/** Write: Acknowledge the interrupt. */
5043 +#define ICU0_IM4_ISR_ICTRLL2_ERR_INTACK 0x00000004
5044 +/** Read: Interrupt occurred. */
5045 +#define ICU0_IM4_ISR_ICTRLL2_ERR_INTOCC 0x00000004
5046 +/** ICTRLL 1 Error
5047 +    This bit is an indirect interrupt. */
5048 +#define ICU0_IM4_ISR_ICTRLL1_ERR 0x00000002
5049 +/* Nothing
5050 +#define ICU0_IM4_ISR_ICTRLL1_ERR_NULL 0x00000000 */
5051 +/** Write: Acknowledge the interrupt. */
5052 +#define ICU0_IM4_ISR_ICTRLL1_ERR_INTACK 0x00000002
5053 +/** Read: Interrupt occurred. */
5054 +#define ICU0_IM4_ISR_ICTRLL1_ERR_INTOCC 0x00000002
5055 +/** ICTRLL 0 Error
5056 +    This bit is an indirect interrupt. */
5057 +#define ICU0_IM4_ISR_ICTRLL0_ERR 0x00000001
5058 +/* Nothing
5059 +#define ICU0_IM4_ISR_ICTRLL0_ERR_NULL 0x00000000 */
5060 +/** Write: Acknowledge the interrupt. */
5061 +#define ICU0_IM4_ISR_ICTRLL0_ERR_INTACK 0x00000001
5062 +/** Read: Interrupt occurred. */
5063 +#define ICU0_IM4_ISR_ICTRLL0_ERR_INTOCC 0x00000001
5064 +
5065 +/* Fields of "IM4 Interrupt Enable Register" */
5066 +/** VPE0 Performance Monitoring Counter Interrupt
5067 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5068 +#define ICU0_IM4_IER_VPE0_PMCIR 0x80000000
5069 +/* Disable
5070 +#define ICU0_IM4_IER_VPE0_PMCIR_DIS 0x00000000 */
5071 +/** Enable */
5072 +#define ICU0_IM4_IER_VPE0_PMCIR_EN 0x80000000
5073 +/** VPE0 Error Level Flag Interrupt
5074 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5075 +#define ICU0_IM4_IER_VPE0_ERL 0x40000000
5076 +/* Disable
5077 +#define ICU0_IM4_IER_VPE0_ERL_DIS 0x00000000 */
5078 +/** Enable */
5079 +#define ICU0_IM4_IER_VPE0_ERL_EN 0x40000000
5080 +/** VPE0 Exception Level Flag Interrupt
5081 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5082 +#define ICU0_IM4_IER_VPE0_EXL 0x20000000
5083 +/* Disable
5084 +#define ICU0_IM4_IER_VPE0_EXL_DIS 0x00000000 */
5085 +/** Enable */
5086 +#define ICU0_IM4_IER_VPE0_EXL_EN 0x20000000
5087 +/** MPS Bin. Sem Interrupt to VPE0
5088 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5089 +#define ICU0_IM4_IER_MPS_IR8 0x00400000
5090 +/* Disable
5091 +#define ICU0_IM4_IER_MPS_IR8_DIS 0x00000000 */
5092 +/** Enable */
5093 +#define ICU0_IM4_IER_MPS_IR8_EN 0x00400000
5094 +/** MPS Global Interrupt to VPE0
5095 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5096 +#define ICU0_IM4_IER_MPS_IR7 0x00200000
5097 +/* Disable
5098 +#define ICU0_IM4_IER_MPS_IR7_DIS 0x00000000 */
5099 +/** Enable */
5100 +#define ICU0_IM4_IER_MPS_IR7_EN 0x00200000
5101 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
5102 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5103 +#define ICU0_IM4_IER_MPS_IR6 0x00100000
5104 +/* Disable
5105 +#define ICU0_IM4_IER_MPS_IR6_DIS 0x00000000 */
5106 +/** Enable */
5107 +#define ICU0_IM4_IER_MPS_IR6_EN 0x00100000
5108 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
5109 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5110 +#define ICU0_IM4_IER_MPS_IR5 0x00080000
5111 +/* Disable
5112 +#define ICU0_IM4_IER_MPS_IR5_DIS 0x00000000 */
5113 +/** Enable */
5114 +#define ICU0_IM4_IER_MPS_IR5_EN 0x00080000
5115 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
5116 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5117 +#define ICU0_IM4_IER_MPS_IR4 0x00040000
5118 +/* Disable
5119 +#define ICU0_IM4_IER_MPS_IR4_DIS 0x00000000 */
5120 +/** Enable */
5121 +#define ICU0_IM4_IER_MPS_IR4_EN 0x00040000
5122 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
5123 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5124 +#define ICU0_IM4_IER_MPS_IR3 0x00020000
5125 +/* Disable
5126 +#define ICU0_IM4_IER_MPS_IR3_DIS 0x00000000 */
5127 +/** Enable */
5128 +#define ICU0_IM4_IER_MPS_IR3_EN 0x00020000
5129 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
5130 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5131 +#define ICU0_IM4_IER_MPS_IR2 0x00010000
5132 +/* Disable
5133 +#define ICU0_IM4_IER_MPS_IR2_DIS 0x00000000 */
5134 +/** Enable */
5135 +#define ICU0_IM4_IER_MPS_IR2_EN 0x00010000
5136 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
5137 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5138 +#define ICU0_IM4_IER_MPS_IR1 0x00008000
5139 +/* Disable
5140 +#define ICU0_IM4_IER_MPS_IR1_DIS 0x00000000 */
5141 +/** Enable */
5142 +#define ICU0_IM4_IER_MPS_IR1_EN 0x00008000
5143 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
5144 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5145 +#define ICU0_IM4_IER_MPS_IR0 0x00004000
5146 +/* Disable
5147 +#define ICU0_IM4_IER_MPS_IR0_DIS 0x00000000 */
5148 +/** Enable */
5149 +#define ICU0_IM4_IER_MPS_IR0_EN 0x00004000
5150 +/** TMU Error
5151 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5152 +#define ICU0_IM4_IER_TMU_ERR 0x00001000
5153 +/* Disable
5154 +#define ICU0_IM4_IER_TMU_ERR_DIS 0x00000000 */
5155 +/** Enable */
5156 +#define ICU0_IM4_IER_TMU_ERR_EN 0x00001000
5157 +/** FSQM Error
5158 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5159 +#define ICU0_IM4_IER_FSQM_ERR 0x00000800
5160 +/* Disable
5161 +#define ICU0_IM4_IER_FSQM_ERR_DIS 0x00000000 */
5162 +/** Enable */
5163 +#define ICU0_IM4_IER_FSQM_ERR_EN 0x00000800
5164 +/** IQM Error
5165 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5166 +#define ICU0_IM4_IER_IQM_ERR 0x00000400
5167 +/* Disable
5168 +#define ICU0_IM4_IER_IQM_ERR_DIS 0x00000000 */
5169 +/** Enable */
5170 +#define ICU0_IM4_IER_IQM_ERR_EN 0x00000400
5171 +/** OCTRLG Error
5172 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5173 +#define ICU0_IM4_IER_OCTRLG_ERR 0x00000200
5174 +/* Disable
5175 +#define ICU0_IM4_IER_OCTRLG_ERR_DIS 0x00000000 */
5176 +/** Enable */
5177 +#define ICU0_IM4_IER_OCTRLG_ERR_EN 0x00000200
5178 +/** ICTRLG Error
5179 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5180 +#define ICU0_IM4_IER_ICTRLG_ERR 0x00000100
5181 +/* Disable
5182 +#define ICU0_IM4_IER_ICTRLG_ERR_DIS 0x00000000 */
5183 +/** Enable */
5184 +#define ICU0_IM4_IER_ICTRLG_ERR_EN 0x00000100
5185 +/** OCTRLL 3 Error
5186 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5187 +#define ICU0_IM4_IER_OCTRLL3_ERR 0x00000080
5188 +/* Disable
5189 +#define ICU0_IM4_IER_OCTRLL3_ERR_DIS 0x00000000 */
5190 +/** Enable */
5191 +#define ICU0_IM4_IER_OCTRLL3_ERR_EN 0x00000080
5192 +/** OCTRLL 2 Error
5193 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5194 +#define ICU0_IM4_IER_OCTRLL2_ERR 0x00000040
5195 +/* Disable
5196 +#define ICU0_IM4_IER_OCTRLL2_ERR_DIS 0x00000000 */
5197 +/** Enable */
5198 +#define ICU0_IM4_IER_OCTRLL2_ERR_EN 0x00000040
5199 +/** OCTRLL 1 Error
5200 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5201 +#define ICU0_IM4_IER_OCTRLL1_ERR 0x00000020
5202 +/* Disable
5203 +#define ICU0_IM4_IER_OCTRLL1_ERR_DIS 0x00000000 */
5204 +/** Enable */
5205 +#define ICU0_IM4_IER_OCTRLL1_ERR_EN 0x00000020
5206 +/** OCTRLL 0 Error
5207 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5208 +#define ICU0_IM4_IER_OCTRLL0_ERR 0x00000010
5209 +/* Disable
5210 +#define ICU0_IM4_IER_OCTRLL0_ERR_DIS 0x00000000 */
5211 +/** Enable */
5212 +#define ICU0_IM4_IER_OCTRLL0_ERR_EN 0x00000010
5213 +/** ICTRLL 3 Error
5214 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5215 +#define ICU0_IM4_IER_ICTRLL3_ERR 0x00000008
5216 +/* Disable
5217 +#define ICU0_IM4_IER_ICTRLL3_ERR_DIS 0x00000000 */
5218 +/** Enable */
5219 +#define ICU0_IM4_IER_ICTRLL3_ERR_EN 0x00000008
5220 +/** ICTRLL 2 Error
5221 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5222 +#define ICU0_IM4_IER_ICTRLL2_ERR 0x00000004
5223 +/* Disable
5224 +#define ICU0_IM4_IER_ICTRLL2_ERR_DIS 0x00000000 */
5225 +/** Enable */
5226 +#define ICU0_IM4_IER_ICTRLL2_ERR_EN 0x00000004
5227 +/** ICTRLL 1 Error
5228 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5229 +#define ICU0_IM4_IER_ICTRLL1_ERR 0x00000002
5230 +/* Disable
5231 +#define ICU0_IM4_IER_ICTRLL1_ERR_DIS 0x00000000 */
5232 +/** Enable */
5233 +#define ICU0_IM4_IER_ICTRLL1_ERR_EN 0x00000002
5234 +/** ICTRLL 0 Error
5235 +    Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
5236 +#define ICU0_IM4_IER_ICTRLL0_ERR 0x00000001
5237 +/* Disable
5238 +#define ICU0_IM4_IER_ICTRLL0_ERR_DIS 0x00000000 */
5239 +/** Enable */
5240 +#define ICU0_IM4_IER_ICTRLL0_ERR_EN 0x00000001
5241 +
5242 +/* Fields of "IM4 Interrupt Output Status Register" */
5243 +/** VPE0 Performance Monitoring Counter Interrupt
5244 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5245 +#define ICU0_IM4_IOSR_VPE0_PMCIR 0x80000000
5246 +/* Nothing
5247 +#define ICU0_IM4_IOSR_VPE0_PMCIR_NULL 0x00000000 */
5248 +/** Read: Interrupt occurred. */
5249 +#define ICU0_IM4_IOSR_VPE0_PMCIR_INTOCC 0x80000000
5250 +/** VPE0 Error Level Flag Interrupt
5251 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5252 +#define ICU0_IM4_IOSR_VPE0_ERL 0x40000000
5253 +/* Nothing
5254 +#define ICU0_IM4_IOSR_VPE0_ERL_NULL 0x00000000 */
5255 +/** Read: Interrupt occurred. */
5256 +#define ICU0_IM4_IOSR_VPE0_ERL_INTOCC 0x40000000
5257 +/** VPE0 Exception Level Flag Interrupt
5258 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5259 +#define ICU0_IM4_IOSR_VPE0_EXL 0x20000000
5260 +/* Nothing
5261 +#define ICU0_IM4_IOSR_VPE0_EXL_NULL 0x00000000 */
5262 +/** Read: Interrupt occurred. */
5263 +#define ICU0_IM4_IOSR_VPE0_EXL_INTOCC 0x20000000
5264 +/** MPS Bin. Sem Interrupt to VPE0
5265 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5266 +#define ICU0_IM4_IOSR_MPS_IR8 0x00400000
5267 +/* Nothing
5268 +#define ICU0_IM4_IOSR_MPS_IR8_NULL 0x00000000 */
5269 +/** Read: Interrupt occurred. */
5270 +#define ICU0_IM4_IOSR_MPS_IR8_INTOCC 0x00400000
5271 +/** MPS Global Interrupt to VPE0
5272 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5273 +#define ICU0_IM4_IOSR_MPS_IR7 0x00200000
5274 +/* Nothing
5275 +#define ICU0_IM4_IOSR_MPS_IR7_NULL 0x00000000 */
5276 +/** Read: Interrupt occurred. */
5277 +#define ICU0_IM4_IOSR_MPS_IR7_INTOCC 0x00200000
5278 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
5279 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5280 +#define ICU0_IM4_IOSR_MPS_IR6 0x00100000
5281 +/* Nothing
5282 +#define ICU0_IM4_IOSR_MPS_IR6_NULL 0x00000000 */
5283 +/** Read: Interrupt occurred. */
5284 +#define ICU0_IM4_IOSR_MPS_IR6_INTOCC 0x00100000
5285 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
5286 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5287 +#define ICU0_IM4_IOSR_MPS_IR5 0x00080000
5288 +/* Nothing
5289 +#define ICU0_IM4_IOSR_MPS_IR5_NULL 0x00000000 */
5290 +/** Read: Interrupt occurred. */
5291 +#define ICU0_IM4_IOSR_MPS_IR5_INTOCC 0x00080000
5292 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
5293 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5294 +#define ICU0_IM4_IOSR_MPS_IR4 0x00040000
5295 +/* Nothing
5296 +#define ICU0_IM4_IOSR_MPS_IR4_NULL 0x00000000 */
5297 +/** Read: Interrupt occurred. */
5298 +#define ICU0_IM4_IOSR_MPS_IR4_INTOCC 0x00040000
5299 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
5300 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5301 +#define ICU0_IM4_IOSR_MPS_IR3 0x00020000
5302 +/* Nothing
5303 +#define ICU0_IM4_IOSR_MPS_IR3_NULL 0x00000000 */
5304 +/** Read: Interrupt occurred. */
5305 +#define ICU0_IM4_IOSR_MPS_IR3_INTOCC 0x00020000
5306 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
5307 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5308 +#define ICU0_IM4_IOSR_MPS_IR2 0x00010000
5309 +/* Nothing
5310 +#define ICU0_IM4_IOSR_MPS_IR2_NULL 0x00000000 */
5311 +/** Read: Interrupt occurred. */
5312 +#define ICU0_IM4_IOSR_MPS_IR2_INTOCC 0x00010000
5313 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
5314 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5315 +#define ICU0_IM4_IOSR_MPS_IR1 0x00008000
5316 +/* Nothing
5317 +#define ICU0_IM4_IOSR_MPS_IR1_NULL 0x00000000 */
5318 +/** Read: Interrupt occurred. */
5319 +#define ICU0_IM4_IOSR_MPS_IR1_INTOCC 0x00008000
5320 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
5321 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5322 +#define ICU0_IM4_IOSR_MPS_IR0 0x00004000
5323 +/* Nothing
5324 +#define ICU0_IM4_IOSR_MPS_IR0_NULL 0x00000000 */
5325 +/** Read: Interrupt occurred. */
5326 +#define ICU0_IM4_IOSR_MPS_IR0_INTOCC 0x00004000
5327 +/** TMU Error
5328 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5329 +#define ICU0_IM4_IOSR_TMU_ERR 0x00001000
5330 +/* Nothing
5331 +#define ICU0_IM4_IOSR_TMU_ERR_NULL 0x00000000 */
5332 +/** Read: Interrupt occurred. */
5333 +#define ICU0_IM4_IOSR_TMU_ERR_INTOCC 0x00001000
5334 +/** FSQM Error
5335 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5336 +#define ICU0_IM4_IOSR_FSQM_ERR 0x00000800
5337 +/* Nothing
5338 +#define ICU0_IM4_IOSR_FSQM_ERR_NULL 0x00000000 */
5339 +/** Read: Interrupt occurred. */
5340 +#define ICU0_IM4_IOSR_FSQM_ERR_INTOCC 0x00000800
5341 +/** IQM Error
5342 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5343 +#define ICU0_IM4_IOSR_IQM_ERR 0x00000400
5344 +/* Nothing
5345 +#define ICU0_IM4_IOSR_IQM_ERR_NULL 0x00000000 */
5346 +/** Read: Interrupt occurred. */
5347 +#define ICU0_IM4_IOSR_IQM_ERR_INTOCC 0x00000400
5348 +/** OCTRLG Error
5349 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5350 +#define ICU0_IM4_IOSR_OCTRLG_ERR 0x00000200
5351 +/* Nothing
5352 +#define ICU0_IM4_IOSR_OCTRLG_ERR_NULL 0x00000000 */
5353 +/** Read: Interrupt occurred. */
5354 +#define ICU0_IM4_IOSR_OCTRLG_ERR_INTOCC 0x00000200
5355 +/** ICTRLG Error
5356 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5357 +#define ICU0_IM4_IOSR_ICTRLG_ERR 0x00000100
5358 +/* Nothing
5359 +#define ICU0_IM4_IOSR_ICTRLG_ERR_NULL 0x00000000 */
5360 +/** Read: Interrupt occurred. */
5361 +#define ICU0_IM4_IOSR_ICTRLG_ERR_INTOCC 0x00000100
5362 +/** OCTRLL 3 Error
5363 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5364 +#define ICU0_IM4_IOSR_OCTRLL3_ERR 0x00000080
5365 +/* Nothing
5366 +#define ICU0_IM4_IOSR_OCTRLL3_ERR_NULL 0x00000000 */
5367 +/** Read: Interrupt occurred. */
5368 +#define ICU0_IM4_IOSR_OCTRLL3_ERR_INTOCC 0x00000080
5369 +/** OCTRLL 2 Error
5370 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5371 +#define ICU0_IM4_IOSR_OCTRLL2_ERR 0x00000040
5372 +/* Nothing
5373 +#define ICU0_IM4_IOSR_OCTRLL2_ERR_NULL 0x00000000 */
5374 +/** Read: Interrupt occurred. */
5375 +#define ICU0_IM4_IOSR_OCTRLL2_ERR_INTOCC 0x00000040
5376 +/** OCTRLL 1 Error
5377 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5378 +#define ICU0_IM4_IOSR_OCTRLL1_ERR 0x00000020
5379 +/* Nothing
5380 +#define ICU0_IM4_IOSR_OCTRLL1_ERR_NULL 0x00000000 */
5381 +/** Read: Interrupt occurred. */
5382 +#define ICU0_IM4_IOSR_OCTRLL1_ERR_INTOCC 0x00000020
5383 +/** OCTRLL 0 Error
5384 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5385 +#define ICU0_IM4_IOSR_OCTRLL0_ERR 0x00000010
5386 +/* Nothing
5387 +#define ICU0_IM4_IOSR_OCTRLL0_ERR_NULL 0x00000000 */
5388 +/** Read: Interrupt occurred. */
5389 +#define ICU0_IM4_IOSR_OCTRLL0_ERR_INTOCC 0x00000010
5390 +/** ICTRLL 3 Error
5391 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5392 +#define ICU0_IM4_IOSR_ICTRLL3_ERR 0x00000008
5393 +/* Nothing
5394 +#define ICU0_IM4_IOSR_ICTRLL3_ERR_NULL 0x00000000 */
5395 +/** Read: Interrupt occurred. */
5396 +#define ICU0_IM4_IOSR_ICTRLL3_ERR_INTOCC 0x00000008
5397 +/** ICTRLL 2 Error
5398 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5399 +#define ICU0_IM4_IOSR_ICTRLL2_ERR 0x00000004
5400 +/* Nothing
5401 +#define ICU0_IM4_IOSR_ICTRLL2_ERR_NULL 0x00000000 */
5402 +/** Read: Interrupt occurred. */
5403 +#define ICU0_IM4_IOSR_ICTRLL2_ERR_INTOCC 0x00000004
5404 +/** ICTRLL 1 Error
5405 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5406 +#define ICU0_IM4_IOSR_ICTRLL1_ERR 0x00000002
5407 +/* Nothing
5408 +#define ICU0_IM4_IOSR_ICTRLL1_ERR_NULL 0x00000000 */
5409 +/** Read: Interrupt occurred. */
5410 +#define ICU0_IM4_IOSR_ICTRLL1_ERR_INTOCC 0x00000002
5411 +/** ICTRLL 0 Error
5412 +    Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
5413 +#define ICU0_IM4_IOSR_ICTRLL0_ERR 0x00000001
5414 +/* Nothing
5415 +#define ICU0_IM4_IOSR_ICTRLL0_ERR_NULL 0x00000000 */
5416 +/** Read: Interrupt occurred. */
5417 +#define ICU0_IM4_IOSR_ICTRLL0_ERR_INTOCC 0x00000001
5418 +
5419 +/* Fields of "IM4 Interrupt Request Set Register" */
5420 +/** VPE0 Performance Monitoring Counter Interrupt
5421 +    Software control for the corresponding bit in the IM4_ISR register. */
5422 +#define ICU0_IM4_IRSR_VPE0_PMCIR 0x80000000
5423 +/** VPE0 Error Level Flag Interrupt
5424 +    Software control for the corresponding bit in the IM4_ISR register. */
5425 +#define ICU0_IM4_IRSR_VPE0_ERL 0x40000000
5426 +/** VPE0 Exception Level Flag Interrupt
5427 +    Software control for the corresponding bit in the IM4_ISR register. */
5428 +#define ICU0_IM4_IRSR_VPE0_EXL 0x20000000
5429 +/** MPS Bin. Sem Interrupt to VPE0
5430 +    Software control for the corresponding bit in the IM4_ISR register. */
5431 +#define ICU0_IM4_IRSR_MPS_IR8 0x00400000
5432 +/** MPS Global Interrupt to VPE0
5433 +    Software control for the corresponding bit in the IM4_ISR register. */
5434 +#define ICU0_IM4_IRSR_MPS_IR7 0x00200000
5435 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
5436 +    Software control for the corresponding bit in the IM4_ISR register. */
5437 +#define ICU0_IM4_IRSR_MPS_IR6 0x00100000
5438 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
5439 +    Software control for the corresponding bit in the IM4_ISR register. */
5440 +#define ICU0_IM4_IRSR_MPS_IR5 0x00080000
5441 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
5442 +    Software control for the corresponding bit in the IM4_ISR register. */
5443 +#define ICU0_IM4_IRSR_MPS_IR4 0x00040000
5444 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
5445 +    Software control for the corresponding bit in the IM4_ISR register. */
5446 +#define ICU0_IM4_IRSR_MPS_IR3 0x00020000
5447 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
5448 +    Software control for the corresponding bit in the IM4_ISR register. */
5449 +#define ICU0_IM4_IRSR_MPS_IR2 0x00010000
5450 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
5451 +    Software control for the corresponding bit in the IM4_ISR register. */
5452 +#define ICU0_IM4_IRSR_MPS_IR1 0x00008000
5453 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
5454 +    Software control for the corresponding bit in the IM4_ISR register. */
5455 +#define ICU0_IM4_IRSR_MPS_IR0 0x00004000
5456 +/** TMU Error
5457 +    Software control for the corresponding bit in the IM4_ISR register. */
5458 +#define ICU0_IM4_IRSR_TMU_ERR 0x00001000
5459 +/** FSQM Error
5460 +    Software control for the corresponding bit in the IM4_ISR register. */
5461 +#define ICU0_IM4_IRSR_FSQM_ERR 0x00000800
5462 +/** IQM Error
5463 +    Software control for the corresponding bit in the IM4_ISR register. */
5464 +#define ICU0_IM4_IRSR_IQM_ERR 0x00000400
5465 +/** OCTRLG Error
5466 +    Software control for the corresponding bit in the IM4_ISR register. */
5467 +#define ICU0_IM4_IRSR_OCTRLG_ERR 0x00000200
5468 +/** ICTRLG Error
5469 +    Software control for the corresponding bit in the IM4_ISR register. */
5470 +#define ICU0_IM4_IRSR_ICTRLG_ERR 0x00000100
5471 +/** OCTRLL 3 Error
5472 +    Software control for the corresponding bit in the IM4_ISR register. */
5473 +#define ICU0_IM4_IRSR_OCTRLL3_ERR 0x00000080
5474 +/** OCTRLL 2 Error
5475 +    Software control for the corresponding bit in the IM4_ISR register. */
5476 +#define ICU0_IM4_IRSR_OCTRLL2_ERR 0x00000040
5477 +/** OCTRLL 1 Error
5478 +    Software control for the corresponding bit in the IM4_ISR register. */
5479 +#define ICU0_IM4_IRSR_OCTRLL1_ERR 0x00000020
5480 +/** OCTRLL 0 Error
5481 +    Software control for the corresponding bit in the IM4_ISR register. */
5482 +#define ICU0_IM4_IRSR_OCTRLL0_ERR 0x00000010
5483 +/** ICTRLL 3 Error
5484 +    Software control for the corresponding bit in the IM4_ISR register. */
5485 +#define ICU0_IM4_IRSR_ICTRLL3_ERR 0x00000008
5486 +/** ICTRLL 2 Error
5487 +    Software control for the corresponding bit in the IM4_ISR register. */
5488 +#define ICU0_IM4_IRSR_ICTRLL2_ERR 0x00000004
5489 +/** ICTRLL 1 Error
5490 +    Software control for the corresponding bit in the IM4_ISR register. */
5491 +#define ICU0_IM4_IRSR_ICTRLL1_ERR 0x00000002
5492 +/** ICTRLL 0 Error
5493 +    Software control for the corresponding bit in the IM4_ISR register. */
5494 +#define ICU0_IM4_IRSR_ICTRLL0_ERR 0x00000001
5495 +
5496 +/* Fields of "IM4 Interrupt Mode Register" */
5497 +/** VPE0 Performance Monitoring Counter Interrupt
5498 +    Type of interrupt. */
5499 +#define ICU0_IM4_IMR_VPE0_PMCIR 0x80000000
5500 +/* Indirect Interrupt.
5501 +#define ICU0_IM4_IMR_VPE0_PMCIR_IND 0x00000000 */
5502 +/** Direct Interrupt. */
5503 +#define ICU0_IM4_IMR_VPE0_PMCIR_DIR 0x80000000
5504 +/** VPE0 Error Level Flag Interrupt
5505 +    Type of interrupt. */
5506 +#define ICU0_IM4_IMR_VPE0_ERL 0x40000000
5507 +/* Indirect Interrupt.
5508 +#define ICU0_IM4_IMR_VPE0_ERL_IND 0x00000000 */
5509 +/** Direct Interrupt. */
5510 +#define ICU0_IM4_IMR_VPE0_ERL_DIR 0x40000000
5511 +/** VPE0 Exception Level Flag Interrupt
5512 +    Type of interrupt. */
5513 +#define ICU0_IM4_IMR_VPE0_EXL 0x20000000
5514 +/* Indirect Interrupt.
5515 +#define ICU0_IM4_IMR_VPE0_EXL_IND 0x00000000 */
5516 +/** Direct Interrupt. */
5517 +#define ICU0_IM4_IMR_VPE0_EXL_DIR 0x20000000
5518 +/** MPS Bin. Sem Interrupt to VPE0
5519 +    Type of interrupt. */
5520 +#define ICU0_IM4_IMR_MPS_IR8 0x00400000
5521 +/* Indirect Interrupt.
5522 +#define ICU0_IM4_IMR_MPS_IR8_IND 0x00000000 */
5523 +/** Direct Interrupt. */
5524 +#define ICU0_IM4_IMR_MPS_IR8_DIR 0x00400000
5525 +/** MPS Global Interrupt to VPE0
5526 +    Type of interrupt. */
5527 +#define ICU0_IM4_IMR_MPS_IR7 0x00200000
5528 +/* Indirect Interrupt.
5529 +#define ICU0_IM4_IMR_MPS_IR7_IND 0x00000000 */
5530 +/** Direct Interrupt. */
5531 +#define ICU0_IM4_IMR_MPS_IR7_DIR 0x00200000
5532 +/** MPS Status Interrupt #6 (VPE1 to VPE0)
5533 +    Type of interrupt. */
5534 +#define ICU0_IM4_IMR_MPS_IR6 0x00100000
5535 +/* Indirect Interrupt.
5536 +#define ICU0_IM4_IMR_MPS_IR6_IND 0x00000000 */
5537 +/** Direct Interrupt. */
5538 +#define ICU0_IM4_IMR_MPS_IR6_DIR 0x00100000
5539 +/** MPS Status Interrupt #5 (VPE1 to VPE0)
5540 +    Type of interrupt. */
5541 +#define ICU0_IM4_IMR_MPS_IR5 0x00080000
5542 +/* Indirect Interrupt.
5543 +#define ICU0_IM4_IMR_MPS_IR5_IND 0x00000000 */
5544 +/** Direct Interrupt. */
5545 +#define ICU0_IM4_IMR_MPS_IR5_DIR 0x00080000
5546 +/** MPS Status Interrupt #4 (VPE1 to VPE0)
5547 +    Type of interrupt. */
5548 +#define ICU0_IM4_IMR_MPS_IR4 0x00040000
5549 +/* Indirect Interrupt.
5550 +#define ICU0_IM4_IMR_MPS_IR4_IND 0x00000000 */
5551 +/** Direct Interrupt. */
5552 +#define ICU0_IM4_IMR_MPS_IR4_DIR 0x00040000
5553 +/** MPS Status Interrupt #3 (VPE1 to VPE0)
5554 +    Type of interrupt. */
5555 +#define ICU0_IM4_IMR_MPS_IR3 0x00020000
5556 +/* Indirect Interrupt.
5557 +#define ICU0_IM4_IMR_MPS_IR3_IND 0x00000000 */
5558 +/** Direct Interrupt. */
5559 +#define ICU0_IM4_IMR_MPS_IR3_DIR 0x00020000
5560 +/** MPS Status Interrupt #2 (VPE1 to VPE0)
5561 +    Type of interrupt. */
5562 +#define ICU0_IM4_IMR_MPS_IR2 0x00010000
5563 +/* Indirect Interrupt.
5564 +#define ICU0_IM4_IMR_MPS_IR2_IND 0x00000000 */
5565 +/** Direct Interrupt. */
5566 +#define ICU0_IM4_IMR_MPS_IR2_DIR 0x00010000
5567 +/** MPS Status Interrupt #1 (VPE1 to VPE0)
5568 +    Type of interrupt. */
5569 +#define ICU0_IM4_IMR_MPS_IR1 0x00008000
5570 +/* Indirect Interrupt.
5571 +#define ICU0_IM4_IMR_MPS_IR1_IND 0x00000000 */
5572 +/** Direct Interrupt. */
5573 +#define ICU0_IM4_IMR_MPS_IR1_DIR 0x00008000
5574 +/** MPS Status Interrupt #0 (VPE1 to VPE0)
5575 +    Type of interrupt. */
5576 +#define ICU0_IM4_IMR_MPS_IR0 0x00004000
5577 +/* Indirect Interrupt.
5578 +#define ICU0_IM4_IMR_MPS_IR0_IND 0x00000000 */
5579 +/** Direct Interrupt. */
5580 +#define ICU0_IM4_IMR_MPS_IR0_DIR 0x00004000
5581 +/** TMU Error
5582 +    Type of interrupt. */
5583 +#define ICU0_IM4_IMR_TMU_ERR 0x00001000
5584 +/* Indirect Interrupt.
5585 +#define ICU0_IM4_IMR_TMU_ERR_IND 0x00000000 */
5586 +/** Direct Interrupt. */
5587 +#define ICU0_IM4_IMR_TMU_ERR_DIR 0x00001000
5588 +/** FSQM Error
5589 +    Type of interrupt. */
5590 +#define ICU0_IM4_IMR_FSQM_ERR 0x00000800
5591 +/* Indirect Interrupt.
5592 +#define ICU0_IM4_IMR_FSQM_ERR_IND 0x00000000 */
5593 +/** Direct Interrupt. */
5594 +#define ICU0_IM4_IMR_FSQM_ERR_DIR 0x00000800
5595 +/** IQM Error
5596 +    Type of interrupt. */
5597 +#define ICU0_IM4_IMR_IQM_ERR 0x00000400
5598 +/* Indirect Interrupt.
5599 +#define ICU0_IM4_IMR_IQM_ERR_IND 0x00000000 */
5600 +/** Direct Interrupt. */
5601 +#define ICU0_IM4_IMR_IQM_ERR_DIR 0x00000400
5602 +/** OCTRLG Error
5603 +    Type of interrupt. */
5604 +#define ICU0_IM4_IMR_OCTRLG_ERR 0x00000200
5605 +/* Indirect Interrupt.
5606 +#define ICU0_IM4_IMR_OCTRLG_ERR_IND 0x00000000 */
5607 +/** Direct Interrupt. */
5608 +#define ICU0_IM4_IMR_OCTRLG_ERR_DIR 0x00000200
5609 +/** ICTRLG Error
5610 +    Type of interrupt. */
5611 +#define ICU0_IM4_IMR_ICTRLG_ERR 0x00000100
5612 +/* Indirect Interrupt.
5613 +#define ICU0_IM4_IMR_ICTRLG_ERR_IND 0x00000000 */
5614 +/** Direct Interrupt. */
5615 +#define ICU0_IM4_IMR_ICTRLG_ERR_DIR 0x00000100
5616 +/** OCTRLL 3 Error
5617 +    Type of interrupt. */
5618 +#define ICU0_IM4_IMR_OCTRLL3_ERR 0x00000080
5619 +/* Indirect Interrupt.
5620 +#define ICU0_IM4_IMR_OCTRLL3_ERR_IND 0x00000000 */
5621 +/** Direct Interrupt. */
5622 +#define ICU0_IM4_IMR_OCTRLL3_ERR_DIR 0x00000080
5623 +/** OCTRLL 2 Error
5624 +    Type of interrupt. */
5625 +#define ICU0_IM4_IMR_OCTRLL2_ERR 0x00000040
5626 +/* Indirect Interrupt.
5627 +#define ICU0_IM4_IMR_OCTRLL2_ERR_IND 0x00000000 */
5628 +/** Direct Interrupt. */
5629 +#define ICU0_IM4_IMR_OCTRLL2_ERR_DIR 0x00000040
5630 +/** OCTRLL 1 Error
5631 +    Type of interrupt. */
5632 +#define ICU0_IM4_IMR_OCTRLL1_ERR 0x00000020
5633 +/* Indirect Interrupt.
5634 +#define ICU0_IM4_IMR_OCTRLL1_ERR_IND 0x00000000 */
5635 +/** Direct Interrupt. */
5636 +#define ICU0_IM4_IMR_OCTRLL1_ERR_DIR 0x00000020
5637 +/** OCTRLL 0 Error
5638 +    Type of interrupt. */
5639 +#define ICU0_IM4_IMR_OCTRLL0_ERR 0x00000010
5640 +/* Indirect Interrupt.
5641 +#define ICU0_IM4_IMR_OCTRLL0_ERR_IND 0x00000000 */
5642 +/** Direct Interrupt. */
5643 +#define ICU0_IM4_IMR_OCTRLL0_ERR_DIR 0x00000010
5644 +/** ICTRLL 3 Error
5645 +    Type of interrupt. */
5646 +#define ICU0_IM4_IMR_ICTRLL3_ERR 0x00000008
5647 +/* Indirect Interrupt.
5648 +#define ICU0_IM4_IMR_ICTRLL3_ERR_IND 0x00000000 */
5649 +/** Direct Interrupt. */
5650 +#define ICU0_IM4_IMR_ICTRLL3_ERR_DIR 0x00000008
5651 +/** ICTRLL 2 Error
5652 +    Type of interrupt. */
5653 +#define ICU0_IM4_IMR_ICTRLL2_ERR 0x00000004
5654 +/* Indirect Interrupt.
5655 +#define ICU0_IM4_IMR_ICTRLL2_ERR_IND 0x00000000 */
5656 +/** Direct Interrupt. */
5657 +#define ICU0_IM4_IMR_ICTRLL2_ERR_DIR 0x00000004
5658 +/** ICTRLL 1 Error
5659 +    Type of interrupt. */
5660 +#define ICU0_IM4_IMR_ICTRLL1_ERR 0x00000002
5661 +/* Indirect Interrupt.
5662 +#define ICU0_IM4_IMR_ICTRLL1_ERR_IND 0x00000000 */
5663 +/** Direct Interrupt. */
5664 +#define ICU0_IM4_IMR_ICTRLL1_ERR_DIR 0x00000002
5665 +/** ICTRLL 0 Error
5666 +    Type of interrupt. */
5667 +#define ICU0_IM4_IMR_ICTRLL0_ERR 0x00000001
5668 +/* Indirect Interrupt.
5669 +#define ICU0_IM4_IMR_ICTRLL0_ERR_IND 0x00000000 */
5670 +/** Direct Interrupt. */
5671 +#define ICU0_IM4_IMR_ICTRLL0_ERR_DIR 0x00000001
5672 +
5673 +/* Fields of "ICU Interrupt Vector Register (5 bit variant)" */
5674 +/** IM4 Interrupt Vector Value
5675 +    Returns the highest priority pending interrupt vector. */
5676 +#define ICU0_ICU_IVEC_IM4_vec_MASK 0x01F00000
5677 +/** field offset */
5678 +#define ICU0_ICU_IVEC_IM4_vec_OFFSET 20
5679 +/** Interrupt pending at bit 31 or no pending interrupt */
5680 +#define ICU0_ICU_IVEC_IM4_vec_NOINTorBit31 0x00000000
5681 +/** Interrupt pending at bit 0. */
5682 +#define ICU0_ICU_IVEC_IM4_vec_BIT0 0x00100000
5683 +/** Interrupt pending at bit 1. */
5684 +#define ICU0_ICU_IVEC_IM4_vec_BIT1 0x00200000
5685 +/** Interrupt pending at bit 30. */
5686 +#define ICU0_ICU_IVEC_IM4_vec_BIT30 0x01F00000
5687 +/** IM3 Interrupt Vector Value
5688 +    Returns the highest priority pending interrupt vector. */
5689 +#define ICU0_ICU_IVEC_IM3_vec_MASK 0x000F8000
5690 +/** field offset */
5691 +#define ICU0_ICU_IVEC_IM3_vec_OFFSET 15
5692 +/** Interrupt pending at bit 31 or no pending interrupt */
5693 +#define ICU0_ICU_IVEC_IM3_vec_NOINTorBit31 0x00000000
5694 +/** Interrupt pending at bit 0. */
5695 +#define ICU0_ICU_IVEC_IM3_vec_BIT0 0x00008000
5696 +/** Interrupt pending at bit 1. */
5697 +#define ICU0_ICU_IVEC_IM3_vec_BIT1 0x00010000
5698 +/** Interrupt pending at bit 30. */
5699 +#define ICU0_ICU_IVEC_IM3_vec_BIT30 0x000F8000
5700 +/** IM2 Interrupt Vector Value
5701 +    Returns the highest priority pending interrupt vector. */
5702 +#define ICU0_ICU_IVEC_IM2_vec_MASK 0x00007C00
5703 +/** field offset */
5704 +#define ICU0_ICU_IVEC_IM2_vec_OFFSET 10
5705 +/** Interrupt pending at bit 31 or no pending interrupt */
5706 +#define ICU0_ICU_IVEC_IM2_vec_NOINTorBit31 0x00000000
5707 +/** Interrupt pending at bit 0. */
5708 +#define ICU0_ICU_IVEC_IM2_vec_BIT0 0x00000400
5709 +/** Interrupt pending at bit 1. */
5710 +#define ICU0_ICU_IVEC_IM2_vec_BIT1 0x00000800
5711 +/** Interrupt pending at bit 30. */
5712 +#define ICU0_ICU_IVEC_IM2_vec_BIT30 0x00007C00
5713 +/** IM1 Interrupt Vector Value
5714 +    Returns the highest priority pending interrupt vector. */
5715 +#define ICU0_ICU_IVEC_IM1_vec_MASK 0x000003E0
5716 +/** field offset */
5717 +#define ICU0_ICU_IVEC_IM1_vec_OFFSET 5
5718 +/** Interrupt pending at bit 31 or no pending interrupt */
5719 +#define ICU0_ICU_IVEC_IM1_vec_NOINTorBit31 0x00000000
5720 +/** Interrupt pending at bit 0. */
5721 +#define ICU0_ICU_IVEC_IM1_vec_BIT0 0x00000020
5722 +/** Interrupt pending at bit 1. */
5723 +#define ICU0_ICU_IVEC_IM1_vec_BIT1 0x00000040
5724 +/** Interrupt pending at bit 30. */
5725 +#define ICU0_ICU_IVEC_IM1_vec_BIT30 0x000003E0
5726 +/** IM0 Interrupt Vector Value
5727 +    Returns the highest priority pending interrupt vector. */
5728 +#define ICU0_ICU_IVEC_IM0_vec_MASK 0x0000001F
5729 +/** field offset */
5730 +#define ICU0_ICU_IVEC_IM0_vec_OFFSET 0
5731 +/** Interrupt pending at bit 31 or no pending interrupt */
5732 +#define ICU0_ICU_IVEC_IM0_vec_NOINTorBit31 0x00000000
5733 +/** Interrupt pending at bit 0. */
5734 +#define ICU0_ICU_IVEC_IM0_vec_BIT0 0x00000001
5735 +/** Interrupt pending at bit 1. */
5736 +#define ICU0_ICU_IVEC_IM0_vec_BIT1 0x00000002
5737 +/** Interrupt pending at bit 30. */
5738 +#define ICU0_ICU_IVEC_IM0_vec_BIT30 0x0000001F
5739 +
5740 +/* Fields of "ICU Interrupt Vector Register (6 bit variant)" */
5741 +/** IM4 Interrupt Vector Value
5742 +    Returns the highest priority pending interrupt vector. */
5743 +#define ICU0_ICU_IVEC_6_IM4_vec_MASK 0x3F000000
5744 +/** field offset */
5745 +#define ICU0_ICU_IVEC_6_IM4_vec_OFFSET 24
5746 +/** No pending interrupt */
5747 +#define ICU0_ICU_IVEC_6_IM4_vec_NOINT 0x00000000
5748 +/** Interrupt pending at bit 0. */
5749 +#define ICU0_ICU_IVEC_6_IM4_vec_BIT0 0x01000000
5750 +/** Interrupt pending at bit 1. */
5751 +#define ICU0_ICU_IVEC_6_IM4_vec_BIT1 0x02000000
5752 +/** Interrupt pending at bit 30. */
5753 +#define ICU0_ICU_IVEC_6_IM4_vec_BIT30 0x1F000000
5754 +/** Interrupt pending at bit 31. */
5755 +#define ICU0_ICU_IVEC_6_IM4_vec_BIT31 0x20000000
5756 +/** IM3 Interrupt Vector Value
5757 +    Returns the highest priority pending interrupt vector. */
5758 +#define ICU0_ICU_IVEC_6_IM3_vec_MASK 0x00FC0000
5759 +/** field offset */
5760 +#define ICU0_ICU_IVEC_6_IM3_vec_OFFSET 18
5761 +/** No pending interrupt */
5762 +#define ICU0_ICU_IVEC_6_IM3_vec_NOINT 0x00000000
5763 +/** Interrupt pending at bit 0. */
5764 +#define ICU0_ICU_IVEC_6_IM3_vec_BIT0 0x00040000
5765 +/** Interrupt pending at bit 1. */
5766 +#define ICU0_ICU_IVEC_6_IM3_vec_BIT1 0x00080000
5767 +/** Interrupt pending at bit 30. */
5768 +#define ICU0_ICU_IVEC_6_IM3_vec_BIT30 0x007C0000
5769 +/** Interrupt pending at bit 31. */
5770 +#define ICU0_ICU_IVEC_6_IM3_vec_BIT31 0x00800000
5771 +/** IM2 Interrupt Vector Value
5772 +    Returns the highest priority pending interrupt vector. */
5773 +#define ICU0_ICU_IVEC_6_IM2_vec_MASK 0x0003F000
5774 +/** field offset */
5775 +#define ICU0_ICU_IVEC_6_IM2_vec_OFFSET 12
5776 +/** No pending interrupt */
5777 +#define ICU0_ICU_IVEC_6_IM2_vec_NOINT 0x00000000
5778 +/** Interrupt pending at bit 0. */
5779 +#define ICU0_ICU_IVEC_6_IM2_vec_BIT0 0x00001000
5780 +/** Interrupt pending at bit 1. */
5781 +#define ICU0_ICU_IVEC_6_IM2_vec_BIT1 0x00002000
5782 +/** Interrupt pending at bit 30. */
5783 +#define ICU0_ICU_IVEC_6_IM2_vec_BIT30 0x0001F000
5784 +/** Interrupt pending at bit 31. */
5785 +#define ICU0_ICU_IVEC_6_IM2_vec_BIT31 0x00020000
5786 +/** IM1 Interrupt Vector Value
5787 +    Returns the highest priority pending interrupt vector. */
5788 +#define ICU0_ICU_IVEC_6_IM1_vec_MASK 0x00000FC0
5789 +/** field offset */
5790 +#define ICU0_ICU_IVEC_6_IM1_vec_OFFSET 6
5791 +/** No pending interrupt */
5792 +#define ICU0_ICU_IVEC_6_IM1_vec_NOINT 0x00000000
5793 +/** Interrupt pending at bit 0. */
5794 +#define ICU0_ICU_IVEC_6_IM1_vec_BIT0 0x00000040
5795 +/** Interrupt pending at bit 1. */
5796 +#define ICU0_ICU_IVEC_6_IM1_vec_BIT1 0x00000080
5797 +/** Interrupt pending at bit 30. */
5798 +#define ICU0_ICU_IVEC_6_IM1_vec_BIT30 0x000007C0
5799 +/** Interrupt pending at bit 31. */
5800 +#define ICU0_ICU_IVEC_6_IM1_vec_BIT31 0x00000800
5801 +/** IM0 Interrupt Vector Value
5802 +    Returns the highest priority pending interrupt vector. */
5803 +#define ICU0_ICU_IVEC_6_IM0_vec_MASK 0x0000003F
5804 +/** field offset */
5805 +#define ICU0_ICU_IVEC_6_IM0_vec_OFFSET 0
5806 +/** No pending interrupt */
5807 +#define ICU0_ICU_IVEC_6_IM0_vec_NOINT 0x00000000
5808 +/** Interrupt pending at bit 0. */
5809 +#define ICU0_ICU_IVEC_6_IM0_vec_BIT0 0x00000001
5810 +/** Interrupt pending at bit 1. */
5811 +#define ICU0_ICU_IVEC_6_IM0_vec_BIT1 0x00000002
5812 +/** Interrupt pending at bit 30. */
5813 +#define ICU0_ICU_IVEC_6_IM0_vec_BIT30 0x0000001F
5814 +/** Interrupt pending at bit 31. */
5815 +#define ICU0_ICU_IVEC_6_IM0_vec_BIT31 0x00000020
5816 +
5817 +/*! @} */ /* ICU0_REGISTER */
5818 +
5819 +#endif /* _icu0_reg_h */
5820 --- /dev/null
5821 +++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
5822 @@ -0,0 +1,31 @@
5823 +/*
5824 + *   arch/mips/include/asm/mach-ifxmips/falcon/irq.h
5825 + *
5826 + *   This program is free software; you can redistribute it and/or modify
5827 + *   it under the terms of the GNU General Public License as published by
5828 + *   the Free Software Foundation; either version 2 of the License, or
5829 + *   (at your option) any later version.
5830 + *
5831 + *   This program is distributed in the hope that it will be useful,
5832 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
5833 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5834 + *   GNU General Public License for more details.
5835 + *
5836 + *   You should have received a copy of the GNU General Public License
5837 + *   along with this program; if not, write to the Free Software
5838 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5839 + *
5840 + *   Copyright (C) 2010 Lantiq
5841 + *
5842 + */
5843 +
5844 +#ifndef __FALCON_IRQ_H
5845 +#define __FALCON_IRQ_H
5846 +
5847 +#include <falcon_irq.h>
5848 +
5849 +#define NR_IRQS 264
5850 +
5851 +#include_next <irq.h>
5852 +
5853 +#endif
5854 --- /dev/null
5855 +++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h
5856 @@ -0,0 +1,529 @@
5857 +/******************************************************************************
5858 +
5859 +                               Copyright (c) 2010
5860 +                            Lantiq Deutschland GmbH
5861 +
5862 +  For licensing information, see the file 'LICENSE' in the root folder of
5863 +  this software module.
5864 +
5865 +******************************************************************************/
5866 +
5867 +#ifndef _status_reg_h
5868 +#define _status_reg_h
5869 +
5870 +/** \addtogroup STATUS_REGISTER
5871 +   @{
5872 +*/
5873 +/* access macros */
5874 +#define status_r32(reg) reg_r32(&status->reg)
5875 +#define status_w32(val, reg) reg_w32(val, &status->reg)
5876 +#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg)
5877 +#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx)
5878 +#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx)
5879 +#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx)
5880 +#define status_adr_table(reg, idx) adr_table(status->reg, idx)
5881 +
5882 +
5883 +/** STATUS register structure */
5884 +struct gpon_reg_status
5885 +{
5886 +   /** Reserved */
5887 +   unsigned int res_0[3]; /* 0x00000000 */
5888 +   /** Chip Identification Register */
5889 +   unsigned int chipid; /* 0x0000000C */
5890 +   /** Chip Location Register
5891 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5892 +   unsigned int chiploc; /* 0x00000010 */
5893 +   /** Redundancy register
5894 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5895 +   unsigned int red0; /* 0x00000014 */
5896 +   /** Redundancy register
5897 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5898 +   unsigned int red1; /* 0x00000018 */
5899 +   /** Redundancy register
5900 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5901 +   unsigned int red2; /* 0x0000001C */
5902 +   /** Redundancy register
5903 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5904 +   unsigned int red3; /* 0x00000020 */
5905 +   /** Redundancy register
5906 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5907 +   unsigned int red4; /* 0x00000024 */
5908 +   /** Redundancy register
5909 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5910 +   unsigned int red5; /* 0x00000028 */
5911 +   /** Redundancy register
5912 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5913 +   unsigned int red6; /* 0x0000002C */
5914 +   /** Redundancy register
5915 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5916 +   unsigned int red7; /* 0x00000030 */
5917 +   /** Redundancy register
5918 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5919 +   unsigned int red8; /* 0x00000034 */
5920 +   /** SPARE fuse register 0
5921 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5922 +   unsigned int fuse0; /* 0x00000038 */
5923 +   /** Fuses for Analog modules
5924 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5925 +   unsigned int analog; /* 0x0000003C */
5926 +   /** Configuration fuses for drivers and pll
5927 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5928 +   unsigned int config; /* 0x00000040 */
5929 +   /** SPARE fuse register 1
5930 +       Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
5931 +   unsigned int fuse1; /* 0x00000044 */
5932 +   /** Configuration for sbs0 rambist */
5933 +   unsigned int mbcfg; /* 0x00000048 */
5934 +   /** sbs0 bist result and debug data */
5935 +   unsigned int mbdata; /* 0x0000004C */
5936 +   /** Reserved */
5937 +   unsigned int res_1[12]; /* 0x00000050 */
5938 +};
5939 +
5940 +
5941 +/* Fields of "Chip Identification Register" */
5942 +/** Chip Version Number
5943 +    Version number */
5944 +#define STATUS_CHIPID_VERSION_MASK 0xF0000000
5945 +/** field offset */
5946 +#define STATUS_CHIPID_VERSION_OFFSET 28
5947 +/** Part Number, Constant Part
5948 +    The Part Number is fixed to 016Bhex. */
5949 +#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000
5950 +/** field offset */
5951 +#define STATUS_CHIPID_PARTNR_OFFSET 12
5952 +/** Manufacturer ID
5953 +    The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */
5954 +#define STATUS_CHIPID_MANID_MASK 0x00000FFE
5955 +/** field offset */
5956 +#define STATUS_CHIPID_MANID_OFFSET 1
5957 +/** Constant bit
5958 +    The value of bit field CONST1 is fixed to 1hex */
5959 +#define STATUS_CHIPID_CONST1 0x00000001
5960 +
5961 +/* Fields of "Chip Location Register" */
5962 +/** Chip Lot ID */
5963 +#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000
5964 +/** field offset */
5965 +#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16
5966 +/** Chip X Coordinate */
5967 +#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00
5968 +/** field offset */
5969 +#define STATUS_CHIPLOC_CHIPX_OFFSET 8
5970 +/** Chip Y Coordinate */
5971 +#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF
5972 +/** field offset */
5973 +#define STATUS_CHIPLOC_CHIPY_OFFSET 0
5974 +
5975 +/* Fields of "Redundancy register" */
5976 +/** Redundancy
5977 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5978 +#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF
5979 +/** field offset */
5980 +#define STATUS_RED0_REDUNDANCY_OFFSET 0
5981 +
5982 +/* Fields of "Redundancy register" */
5983 +/** Redundancy
5984 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5985 +#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF
5986 +/** field offset */
5987 +#define STATUS_RED1_REDUNDANCY_OFFSET 0
5988 +
5989 +/* Fields of "Redundancy register" */
5990 +/** Redundancy
5991 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5992 +#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF
5993 +/** field offset */
5994 +#define STATUS_RED2_REDUNDANCY_OFFSET 0
5995 +
5996 +/* Fields of "Redundancy register" */
5997 +/** Redundancy
5998 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
5999 +#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF
6000 +/** field offset */
6001 +#define STATUS_RED3_REDUNDANCY_OFFSET 0
6002 +
6003 +/* Fields of "Redundancy register" */
6004 +/** Redundancy
6005 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
6006 +#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF
6007 +/** field offset */
6008 +#define STATUS_RED4_REDUNDANCY_OFFSET 0
6009 +
6010 +/* Fields of "Redundancy register" */
6011 +/** Redundancy
6012 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
6013 +#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF
6014 +/** field offset */
6015 +#define STATUS_RED5_REDUNDANCY_OFFSET 0
6016 +
6017 +/* Fields of "Redundancy register" */
6018 +/** Redundancy
6019 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
6020 +#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF
6021 +/** field offset */
6022 +#define STATUS_RED6_REDUNDANCY_OFFSET 0
6023 +
6024 +/* Fields of "Redundancy register" */
6025 +/** Redundancy
6026 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
6027 +#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF
6028 +/** field offset */
6029 +#define STATUS_RED7_REDUNDANCY_OFFSET 0
6030 +
6031 +/* Fields of "Redundancy register" */
6032 +/** Redundancy
6033 +    redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
6034 +#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF
6035 +/** field offset */
6036 +#define STATUS_RED8_REDUNDANCY_OFFSET 0
6037 +
6038 +/* Fields of "SPARE fuse register 0" */
6039 +/** Soft fuse control
6040 +    Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */
6041 +#define STATUS_FUSE0_SFC 0x80000000
6042 +/* Not selected
6043 +#define STATUS_FUSE0_SFC_NSEL 0x00000000 */
6044 +/** Selected */
6045 +#define STATUS_FUSE0_SFC_SEL 0x80000000
6046 +/** Soft control MBCFG
6047 +    Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */
6048 +#define STATUS_FUSE0_SC_MBCFG 0x40000000
6049 +/* Not selected
6050 +#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */
6051 +/** Selected */
6052 +#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000
6053 +/** spare fuse0
6054 +    eFuses not assigned to hw/sw, can be used for future applications */
6055 +#define STATUS_FUSE0_F0_MASK 0x3C000000
6056 +/** field offset */
6057 +#define STATUS_FUSE0_F0_OFFSET 26
6058 +/** VCALMM20 Voltage Reference
6059 +    Voltage Reference for calibration via R and constant current (20 uA) */
6060 +#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000
6061 +/** field offset */
6062 +#define STATUS_FUSE0_VCALMM20_OFFSET 20
6063 +/** VCALMM100 Voltage Reference
6064 +    Voltage Reference for calibration via R and constant current (100 uA) */
6065 +#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000
6066 +/** field offset */
6067 +#define STATUS_FUSE0_VCALMM100_OFFSET 14
6068 +/** VCALMM400 Voltage Reference
6069 +    Voltage Reference for calibration via R and constant current (400 uA) */
6070 +#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00
6071 +/** field offset */
6072 +#define STATUS_FUSE0_VCALMM400_OFFSET 8
6073 +/** RCALMM R error correction
6074 +    The resistance deviation from ideal R (1000 Ohm) */
6075 +#define STATUS_FUSE0_RCALMM_MASK 0x000000FF
6076 +/** field offset */
6077 +#define STATUS_FUSE0_RCALMM_OFFSET 0
6078 +
6079 +/* Fields of "Fuses for Analog modules" */
6080 +/** reserved Analog eFuses
6081 +    Reserved Register contains information stored in eFuses needed for the analog modules */
6082 +#define STATUS_ANALOG_A0_MASK 0xFF000000
6083 +/** field offset */
6084 +#define STATUS_ANALOG_A0_OFFSET 24
6085 +/** Absolut Temperature
6086 +    Temperature ERROR */
6087 +#define STATUS_ANALOG_TEMPMM_MASK 0x00FC0000
6088 +/** field offset */
6089 +#define STATUS_ANALOG_TEMPMM_OFFSET 18
6090 +/** Bias Voltage Generation
6091 +    temperature dependency */
6092 +#define STATUS_ANALOG_TBGP_MASK 0x00038000
6093 +/** field offset */
6094 +#define STATUS_ANALOG_TBGP_OFFSET 15
6095 +/** Bias Voltage Generation
6096 +    voltage dependency */
6097 +#define STATUS_ANALOG_VBGP_MASK 0x00007000
6098 +/** field offset */
6099 +#define STATUS_ANALOG_VBGP_OFFSET 12
6100 +/** Bias Current Generation */
6101 +#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00
6102 +/** field offset */
6103 +#define STATUS_ANALOG_IREFBGP_OFFSET 8
6104 +/** Drive DAC Gain */
6105 +#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000000F0
6106 +/** field offset */
6107 +#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 4
6108 +/** BIAS DAC Gain */
6109 +#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000000F
6110 +/** field offset */
6111 +#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0
6112 +
6113 +/* Fields of "Configuration fuses for drivers and pll" */
6114 +/** ddr PU driver
6115 +    ddr pullup driver strength adjustment */
6116 +#define STATUS_CONFIG_DDRPU_MASK 0xC0000000
6117 +/** field offset */
6118 +#define STATUS_CONFIG_DDRPU_OFFSET 30
6119 +/** ddr PD driver
6120 +    ddr pulldown driver strength adjustment */
6121 +#define STATUS_CONFIG_DDRPD_MASK 0x30000000
6122 +/** field offset */
6123 +#define STATUS_CONFIG_DDRPD_OFFSET 28
6124 +/** Authentification Unit enable
6125 +    This bit can only be set via eFuse and enables the authentification unit. */
6126 +#define STATUS_CONFIG_SHA1EN 0x08000000
6127 +/* Not selected
6128 +#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */
6129 +/** Selected */
6130 +#define STATUS_CONFIG_SHA1EN_SEL 0x08000000
6131 +/** Encryption Unit enable
6132 +    This bit can only be set via eFuse and enables the encryption unit. */
6133 +#define STATUS_CONFIG_AESEN 0x04000000
6134 +/* Not selected
6135 +#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */
6136 +/** Selected */
6137 +#define STATUS_CONFIG_AESEN_SEL 0x04000000
6138 +/** Subversion Number
6139 +    The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. In this way different product packages consisting of GPON_MODEM and software can be defined for example */
6140 +#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000
6141 +/** field offset */
6142 +#define STATUS_CONFIG_SUBVERS_OFFSET 22
6143 +/** PLL settings
6144 +    PLL settings for infrastructure block */
6145 +#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000
6146 +/** field offset */
6147 +#define STATUS_CONFIG_PLLINFRA_OFFSET 12
6148 +/** GPE frequency selection
6149 +    Scaling down the GPE frequency for debugging purpose */
6150 +#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00
6151 +/** field offset */
6152 +#define STATUS_CONFIG_GPEFREQ_OFFSET 10
6153 +/** RM enable
6154 +    Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */
6155 +#define STATUS_CONFIG_RME 0x00000200
6156 +/* Not selected
6157 +#define STATUS_CONFIG_RME_NSEL 0x00000000 */
6158 +/** Selected */
6159 +#define STATUS_CONFIG_RME_SEL 0x00000200
6160 +/** RM settings
6161 +    Read Marging Settings for all VIRAGE Memories except GPE */
6162 +#define STATUS_CONFIG_RM_MASK 0x000001E0
6163 +/** field offset */
6164 +#define STATUS_CONFIG_RM_OFFSET 5
6165 +/** RM enable for GPE Memories
6166 +    Activates the Read Margin Settings defined in the RM Field */
6167 +#define STATUS_CONFIG_RMEGPE 0x00000010
6168 +/* Not selected
6169 +#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */
6170 +/** Selected */
6171 +#define STATUS_CONFIG_RMEGPE_SEL 0x00000010
6172 +/** RM settings for GPE Memories
6173 +    Read Marging Settings for VIRAGE Memories in GPE module */
6174 +#define STATUS_CONFIG_RMGPE_MASK 0x0000000F
6175 +/** field offset */
6176 +#define STATUS_CONFIG_RMGPE_OFFSET 0
6177 +
6178 +/* Fields of "SPARE fuse register 1" */
6179 +/** spare fuse1
6180 +    eFuses not assigned to hw/sw, can be used for future applications */
6181 +#define STATUS_FUSE1_F1_MASK 0xFFF00000
6182 +/** field offset */
6183 +#define STATUS_FUSE1_F1_OFFSET 20
6184 +/** DCDC DDR OFFSET
6185 +    offset error sense path */
6186 +#define STATUS_FUSE1_OFFSETDDRDCDC_MASK 0x000F0000
6187 +/** field offset */
6188 +#define STATUS_FUSE1_OFFSETDDRDCDC_OFFSET 16
6189 +/** DCDC DDR GAIN
6190 +    gain error sense path */
6191 +#define STATUS_FUSE1_GAINDDRDCDC_MASK 0x0000FC00
6192 +/** field offset */
6193 +#define STATUS_FUSE1_GAINDDRDCDC_OFFSET 10
6194 +/** DCDC APD OFFSET
6195 +    offset error sense path */
6196 +#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000003C0
6197 +/** field offset */
6198 +#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6
6199 +/** DCDC APD GAIN
6200 +    gain error sense path */
6201 +#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F
6202 +/** field offset */
6203 +#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0
6204 +
6205 +/* Fields of "Configuration for sbs0 rambist" */
6206 +/** Disable asc monitoring during boot-up
6207 +    Bit is used to avoid asc output for reducing pattern count on testsystem */
6208 +#define STATUS_MBCFG_ASC_DBGDIS 0x01000000
6209 +/* Disable
6210 +#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */
6211 +/** Enable */
6212 +#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000
6213 +/** Descrambling Enable/Disable
6214 +    Enables Address and Data Descrambling for internal Memory Test */
6215 +#define STATUS_MBCFG_DSC 0x00800000
6216 +/* Disable
6217 +#define STATUS_MBCFG_DSC_DIS 0x00000000 */
6218 +/** Enable */
6219 +#define STATUS_MBCFG_DSC_EN 0x00800000
6220 +/** Enable repair mode
6221 +    When bit is set redundancy repair mode is activated */
6222 +#define STATUS_MBCFG_REPAIR 0x00400000
6223 +/* Disable
6224 +#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */
6225 +/** Enable */
6226 +#define STATUS_MBCFG_REPAIR_EN 0x00400000
6227 +/** DEBUG Mode */
6228 +#define STATUS_MBCFG_DBG 0x00200000
6229 +/* Disable
6230 +#define STATUS_MBCFG_DBG_DIS 0x00000000 */
6231 +/** Enable */
6232 +#define STATUS_MBCFG_DBG_EN 0x00200000
6233 +/** Retention Time
6234 +    Length oft the Retention Time */
6235 +#define STATUS_MBCFG_RTIME_MASK 0x001C0000
6236 +/** field offset */
6237 +#define STATUS_MBCFG_RTIME_OFFSET 18
6238 +/** retention mode is switched off */
6239 +#define STATUS_MBCFG_RTIME_RET0 0x00000000
6240 +/** Retention time 50 ms */
6241 +#define STATUS_MBCFG_RTIME_RET50 0x00040000
6242 +/** Retention time 60 ms */
6243 +#define STATUS_MBCFG_RTIME_RET60 0x00080000
6244 +/** Retention time 70 ms */
6245 +#define STATUS_MBCFG_RTIME_RET70 0x000C0000
6246 +/** Retention time 80 ms */
6247 +#define STATUS_MBCFG_RTIME_RET80 0x00100000
6248 +/** Retention time 90 ms */
6249 +#define STATUS_MBCFG_RTIME_RET90 0x00140000
6250 +/** Retention time 1000 ms */
6251 +#define STATUS_MBCFG_RTIME_RET1000 0x00180000
6252 +/** Test ID
6253 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
6254 +#define STATUS_MBCFG_TID_5_MASK 0x00038000
6255 +/** field offset */
6256 +#define STATUS_MBCFG_TID_5_OFFSET 15
6257 +/** No test is performed */
6258 +#define STATUS_MBCFG_TID_5_NONE 0x00000000
6259 +/** March test */
6260 +#define STATUS_MBCFG_TID_5_MARCH 0x00008000
6261 +/** Checkerboard test */
6262 +#define STATUS_MBCFG_TID_5_CHCK 0x00010000
6263 +/** Hammer test */
6264 +#define STATUS_MBCFG_TID_5_HAM 0x00018000
6265 +/** Address decoder test */
6266 +#define STATUS_MBCFG_TID_5_ADEC 0x00020000
6267 +/** Write mask byte test */
6268 +#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000
6269 +/** Reserved */
6270 +#define STATUS_MBCFG_TID_5_RES 0x00030000
6271 +/** Test ID
6272 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
6273 +#define STATUS_MBCFG_TID_4_MASK 0x00007000
6274 +/** field offset */
6275 +#define STATUS_MBCFG_TID_4_OFFSET 12
6276 +/** No test is performed */
6277 +#define STATUS_MBCFG_TID_4_NONE 0x00000000
6278 +/** March test */
6279 +#define STATUS_MBCFG_TID_4_MARCH 0x00001000
6280 +/** Checkerboard test */
6281 +#define STATUS_MBCFG_TID_4_CHCK 0x00002000
6282 +/** Hammer test */
6283 +#define STATUS_MBCFG_TID_4_HAM 0x00003000
6284 +/** Address decoder test */
6285 +#define STATUS_MBCFG_TID_4_ADEC 0x00004000
6286 +/** Write mask byte test */
6287 +#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000
6288 +/** Reserved */
6289 +#define STATUS_MBCFG_TID_4_RES 0x00006000
6290 +/** Test ID
6291 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
6292 +#define STATUS_MBCFG_TID_3_MASK 0x00000E00
6293 +/** field offset */
6294 +#define STATUS_MBCFG_TID_3_OFFSET 9
6295 +/** No test is performed */
6296 +#define STATUS_MBCFG_TID_3_NONE 0x00000000
6297 +/** March test */
6298 +#define STATUS_MBCFG_TID_3_MARCH 0x00000200
6299 +/** Checkerboard test */
6300 +#define STATUS_MBCFG_TID_3_CHCK 0x00000400
6301 +/** Hammer test */
6302 +#define STATUS_MBCFG_TID_3_HAM 0x00000600
6303 +/** Address decoder test */
6304 +#define STATUS_MBCFG_TID_3_ADEC 0x00000800
6305 +/** Write mask byte test */
6306 +#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00
6307 +/** Reserved */
6308 +#define STATUS_MBCFG_TID_3_RES 0x00000C00
6309 +/** Test ID
6310 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
6311 +#define STATUS_MBCFG_TID_2_MASK 0x000001C0
6312 +/** field offset */
6313 +#define STATUS_MBCFG_TID_2_OFFSET 6
6314 +/** No test is performed */
6315 +#define STATUS_MBCFG_TID_2_NONE 0x00000000
6316 +/** March test */
6317 +#define STATUS_MBCFG_TID_2_MARCH 0x00000040
6318 +/** Checkerboard test */
6319 +#define STATUS_MBCFG_TID_2_CHCK 0x00000080
6320 +/** Hammer test */
6321 +#define STATUS_MBCFG_TID_2_HAM 0x000000C0
6322 +/** Address decoder test */
6323 +#define STATUS_MBCFG_TID_2_ADEC 0x00000100
6324 +/** Write mask byte test */
6325 +#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140
6326 +/** Reserved */
6327 +#define STATUS_MBCFG_TID_2_RES 0x00000180
6328 +/** Test ID
6329 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
6330 +#define STATUS_MBCFG_TID_1_MASK 0x00000038
6331 +/** field offset */
6332 +#define STATUS_MBCFG_TID_1_OFFSET 3
6333 +/** No test is performed */
6334 +#define STATUS_MBCFG_TID_1_NONE 0x00000000
6335 +/** March test */
6336 +#define STATUS_MBCFG_TID_1_MARCH 0x00000008
6337 +/** Checkerboard test */
6338 +#define STATUS_MBCFG_TID_1_CHCK 0x00000010
6339 +/** Hammer test */
6340 +#define STATUS_MBCFG_TID_1_HAM 0x00000018
6341 +/** Address decoder test */
6342 +#define STATUS_MBCFG_TID_1_ADEC 0x00000020
6343 +/** Write mask byte test */
6344 +#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028
6345 +/** Reserved */
6346 +#define STATUS_MBCFG_TID_1_RES 0x00000030
6347 +/** Test ID
6348 +    Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
6349 +#define STATUS_MBCFG_TID_0_MASK 0x00000007
6350 +/** field offset */
6351 +#define STATUS_MBCFG_TID_0_OFFSET 0
6352 +/** No test is performed */
6353 +#define STATUS_MBCFG_TID_0_NONE 0x00000000
6354 +/** March test */
6355 +#define STATUS_MBCFG_TID_0_MARCH 0x00000001
6356 +/** Checkerboard test */
6357 +#define STATUS_MBCFG_TID_0_CHCK 0x00000002
6358 +/** Hammer test */
6359 +#define STATUS_MBCFG_TID_0_HAM 0x00000003
6360 +/** Address decoder test */
6361 +#define STATUS_MBCFG_TID_0_ADEC 0x00000004
6362 +/** Write mask byte test */
6363 +#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005
6364 +/** Reserved */
6365 +#define STATUS_MBCFG_TID_0_RES 0x00000006
6366 +
6367 +/* Fields of "sbs0 bist result and debug data" */
6368 +/** BIST result and debug data
6369 +    Stores additional debug information */
6370 +#define STATUS_MBDATA_DATA_MASK 0xFFFFFFF8
6371 +/** field offset */
6372 +#define STATUS_MBDATA_DATA_OFFSET 3
6373 +/** MBIST NOGO
6374 +    The BIST failed and cannot be repaired due to many failure locations */
6375 +#define STATUS_MBDATA_MBNOGO 0x00000004
6376 +/** MBIST FAILED
6377 +    The BIST failed but can be repaired */
6378 +#define STATUS_MBDATA_MBFAIL 0x00000002
6379 +/** MBIST PASSED
6380 +    The BIST passed without any Failures */
6381 +#define STATUS_MBDATA_MBPASS 0x00000001
6382 +
6383 +/*! @} */ /* STATUS_REGISTER */
6384 +
6385 +#endif /* _status_reg_h */
6386 --- /dev/null
6387 +++ b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h
6388 @@ -0,0 +1,2008 @@
6389 +/******************************************************************************
6390 +
6391 +                               Copyright (c) 2010
6392 +                            Lantiq Deutschland GmbH
6393 +
6394 +  For licensing information, see the file 'LICENSE' in the root folder of
6395 +  this software module.
6396 +
6397 +******************************************************************************/
6398 +
6399 +#ifndef _sys1_reg_h
6400 +#define _sys1_reg_h
6401 +
6402 +/** \addtogroup SYS1_REGISTER
6403 +   @{
6404 +*/
6405 +/* access macros */
6406 +#define sys1_r32(reg) reg_r32(&sys1->reg)
6407 +#define sys1_w32(val, reg) reg_w32(val, &sys1->reg)
6408 +#define sys1_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys1->reg)
6409 +#define sys1_r32_table(reg, idx) reg_r32_table(sys1->reg, idx)
6410 +#define sys1_w32_table(val, reg, idx) reg_w32_table(val, sys1->reg, idx)
6411 +#define sys1_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys1->reg, idx)
6412 +#define sys1_adr_table(reg, idx) adr_table(sys1->reg, idx)
6413 +
6414 +
6415 +/** SYS1 register structure */
6416 +struct gpon_reg_sys1
6417 +{
6418 +   /** Clock Status Register */
6419 +   unsigned int clks; /* 0x00000000 */
6420 +   /** Clock Enable Register
6421 +       Via this register the clocks for the domains can be enabled. */
6422 +   unsigned int clken; /* 0x00000004 */
6423 +   /** Clock Clear Register
6424 +       Via this register the clocks for the domains can be disabled. */
6425 +   unsigned int clkclr; /* 0x00000008 */
6426 +   /** Reserved */
6427 +   unsigned int res_0[5]; /* 0x0000000C */
6428 +   /** Activation Status Register */
6429 +   unsigned int acts; /* 0x00000020 */
6430 +   /** Activation Register
6431 +       Via this register the domains can be activated. */
6432 +   unsigned int act; /* 0x00000024 */
6433 +   /** Deactivation Register
6434 +       Via this register the domains can be deactivated. */
6435 +   unsigned int deact; /* 0x00000028 */
6436 +   /** Reboot Trigger Register
6437 +       Via this register the domains can be rebooted (sent through reset). */
6438 +   unsigned int rbt; /* 0x0000002C */
6439 +   /** Reserved */
6440 +   unsigned int res_1[4]; /* 0x00000030 */
6441 +   /** CPU0 Clock Control Register
6442 +       Clock control register for CPU0 */
6443 +   unsigned int cpu0cc; /* 0x00000040 */
6444 +   /** Reserved */
6445 +   unsigned int res_2[7]; /* 0x00000044 */
6446 +   /** CPU0 Reset Source Register
6447 +       Via this register the CPU can find the the root cause for the boot it currently goes through, and take the appropriate measures. */
6448 +   unsigned int cpu0rs; /* 0x00000060 */
6449 +   /** Reserved */
6450 +   unsigned int res_3[7]; /* 0x00000064 */
6451 +   /** CPU0 Wakeup Configuration Register
6452 +       Controls the wakeup condition for CPU0. Note: The upper 16 bit of this register have to be set to the same value as the mask bits within the yield-resume interface block. If the yield-resume interface is not used at all, set the upper 16 bit to 0. */
6453 +   unsigned int cpu0wcfg; /* 0x00000080 */
6454 +   /** Reserved */
6455 +   unsigned int res_4[7]; /* 0x00000084 */
6456 +   /** Bootmode Control Register
6457 +       Reflects the bootmode for the CPU and provides means to manipulate it. */
6458 +   unsigned int bmc; /* 0x000000A0 */
6459 +   /** Reserved */
6460 +   unsigned int res_5[3]; /* 0x000000A4 */
6461 +   /** Sleep Configuration Register */
6462 +   unsigned int scfg; /* 0x000000B0 */
6463 +   /** Power Down Configuration Register
6464 +       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be switched off. */
6465 +   unsigned int pdcfg; /* 0x000000B4 */
6466 +   /** CLKO Pad Control Register
6467 +       Controls the behaviour of the CLKO pad/ball. */
6468 +   unsigned int clkoc; /* 0x000000B8 */
6469 +   /** Infrastructure Control Register
6470 +       Controls the behaviour of the components of the infrastructure block. */
6471 +   unsigned int infrac; /* 0x000000BC */
6472 +   /** HRST_OUT_N Control Register
6473 +       Controls the behaviour of the HRST_OUT_N pin. */
6474 +   unsigned int hrstoutc; /* 0x000000C0 */
6475 +   /** EBU Clock Control Register
6476 +       Clock control register for the EBU. */
6477 +   unsigned int ebucc; /* 0x000000C4 */
6478 +   /** Reserved */
6479 +   unsigned int res_6[2]; /* 0x000000C8 */
6480 +   /** NMI Status Register
6481 +       The Test NMI source is the GPTC counter 1A overflow bit. */
6482 +   unsigned int nmis; /* 0x000000D0 */
6483 +   /** NMI Set Register */
6484 +   unsigned int nmiset; /* 0x000000D4 */
6485 +   /** NMI Clear Register */
6486 +   unsigned int nmiclr; /* 0x000000D8 */
6487 +   /** NMI Test Configuration Register */
6488 +   unsigned int nmitcfg; /* 0x000000DC */
6489 +   /** NMI VPE1 Control Register */
6490 +   unsigned int nmivpe1c; /* 0x000000E0 */
6491 +   /** Reserved */
6492 +   unsigned int res_7[3]; /* 0x000000E4 */
6493 +   /** IRN Capture Register
6494 +       This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
6495 +   unsigned int irncr; /* 0x000000F0 */
6496 +   /** IRN Interrupt Control Register
6497 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
6498 +   unsigned int irnicr; /* 0x000000F4 */
6499 +   /** IRN Interrupt Enable Register
6500 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
6501 +   unsigned int irnen; /* 0x000000F8 */
6502 +   /** Reserved */
6503 +   unsigned int res_8; /* 0x000000FC */
6504 +};
6505 +
6506 +
6507 +/* Fields of "Clock Status Register" */
6508 +/** STATUS Clock Enable
6509 +    Shows the clock enable bit for the STATUS domain. This domain contains the STATUS block. */
6510 +#define CLKS_STATUS 0x80000000
6511 +/* Disable
6512 +#define CLKS_STATUS_DIS 0x00000000 */
6513 +/** Enable */
6514 +#define CLKS_STATUS_EN 0x80000000
6515 +/** SHA1 Clock Enable
6516 +    Shows the clock enable bit for the SHA1 domain. This domain contains the SHA1 block. */
6517 +#define CLKS_SHA1 0x40000000
6518 +/* Disable
6519 +#define CLKS_SHA1_DIS 0x00000000 */
6520 +/** Enable */
6521 +#define CLKS_SHA1_EN 0x40000000
6522 +/** AES Clock Enable
6523 +    Shows the clock enable bit for the AES domain. This domain contains the AES block. */
6524 +#define CLKS_AES 0x20000000
6525 +/* Disable
6526 +#define CLKS_AES_DIS 0x00000000 */
6527 +/** Enable */
6528 +#define CLKS_AES_EN 0x20000000
6529 +/** PCM Clock Enable
6530 +    Shows the clock enable bit for the PCM domain. This domain contains the PCM interface block. */
6531 +#define CLKS_PCM 0x10000000
6532 +/* Disable
6533 +#define CLKS_PCM_DIS 0x00000000 */
6534 +/** Enable */
6535 +#define CLKS_PCM_EN 0x10000000
6536 +/** FSCT Clock Enable
6537 +    Shows the clock enable bit for the FSCT domain. This domain contains the FSCT block. */
6538 +#define CLKS_FSCT 0x08000000
6539 +/* Disable
6540 +#define CLKS_FSCT_DIS 0x00000000 */
6541 +/** Enable */
6542 +#define CLKS_FSCT_EN 0x08000000
6543 +/** GPTC Clock Enable
6544 +    Shows the clock enable bit for the GPTC domain. This domain contains the GPTC block. */
6545 +#define CLKS_GPTC 0x04000000
6546 +/* Disable
6547 +#define CLKS_GPTC_DIS 0x00000000 */
6548 +/** Enable */
6549 +#define CLKS_GPTC_EN 0x04000000
6550 +/** MPS Clock Enable
6551 +    Shows the clock enable bit for the MPS domain. This domain contains the MPS block. */
6552 +#define CLKS_MPS 0x02000000
6553 +/* Disable
6554 +#define CLKS_MPS_DIS 0x00000000 */
6555 +/** Enable */
6556 +#define CLKS_MPS_EN 0x02000000
6557 +/** DFEV0 Clock Enable
6558 +    Shows the clock enable bit for the DFEV0 domain. This domain contains the DFEV0 block. */
6559 +#define CLKS_DFEV0 0x01000000
6560 +/* Disable
6561 +#define CLKS_DFEV0_DIS 0x00000000 */
6562 +/** Enable */
6563 +#define CLKS_DFEV0_EN 0x01000000
6564 +/** PADCTRL4 Clock Enable
6565 +    Shows the clock enable bit for the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
6566 +#define CLKS_PADCTRL4 0x00400000
6567 +/* Disable
6568 +#define CLKS_PADCTRL4_DIS 0x00000000 */
6569 +/** Enable */
6570 +#define CLKS_PADCTRL4_EN 0x00400000
6571 +/** PADCTRL3 Clock Enable
6572 +    Shows the clock enable bit for the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
6573 +#define CLKS_PADCTRL3 0x00200000
6574 +/* Disable
6575 +#define CLKS_PADCTRL3_DIS 0x00000000 */
6576 +/** Enable */
6577 +#define CLKS_PADCTRL3_EN 0x00200000
6578 +/** PADCTRL1 Clock Enable
6579 +    Shows the clock enable bit for the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
6580 +#define CLKS_PADCTRL1 0x00100000
6581 +/* Disable
6582 +#define CLKS_PADCTRL1_DIS 0x00000000 */
6583 +/** Enable */
6584 +#define CLKS_PADCTRL1_EN 0x00100000
6585 +/** P4 Clock Enable
6586 +    Shows the clock enable bit for the P4 domain. This domain contains the P4 instance of the GPIO block. */
6587 +#define CLKS_P4 0x00040000
6588 +/* Disable
6589 +#define CLKS_P4_DIS 0x00000000 */
6590 +/** Enable */
6591 +#define CLKS_P4_EN 0x00040000
6592 +/** P3 Clock Enable
6593 +    Shows the clock enable bit for the P3 domain. This domain contains the P3 instance of the GPIO block. */
6594 +#define CLKS_P3 0x00020000
6595 +/* Disable
6596 +#define CLKS_P3_DIS 0x00000000 */
6597 +/** Enable */
6598 +#define CLKS_P3_EN 0x00020000
6599 +/** P1 Clock Enable
6600 +    Shows the clock enable bit for the P1 domain. This domain contains the P1 instance of the GPIO block. */
6601 +#define CLKS_P1 0x00010000
6602 +/* Disable
6603 +#define CLKS_P1_DIS 0x00000000 */
6604 +/** Enable */
6605 +#define CLKS_P1_EN 0x00010000
6606 +/** HOST Clock Enable
6607 +    Shows the clock enable bit for the HOST domain. This domain contains the HOST interface block. */
6608 +#define CLKS_HOST 0x00008000
6609 +/* Disable
6610 +#define CLKS_HOST_DIS 0x00000000 */
6611 +/** Enable */
6612 +#define CLKS_HOST_EN 0x00008000
6613 +/** I2C Clock Enable
6614 +    Shows the clock enable bit for the I2C domain. This domain contains the I2C interface block. */
6615 +#define CLKS_I2C 0x00004000
6616 +/* Disable
6617 +#define CLKS_I2C_DIS 0x00000000 */
6618 +/** Enable */
6619 +#define CLKS_I2C_EN 0x00004000
6620 +/** SSC0 Clock Enable
6621 +    Shows the clock enable bit for the SSC0 domain. This domain contains the SSC0 interface block. */
6622 +#define CLKS_SSC0 0x00002000
6623 +/* Disable
6624 +#define CLKS_SSC0_DIS 0x00000000 */
6625 +/** Enable */
6626 +#define CLKS_SSC0_EN 0x00002000
6627 +/** ASC0 Clock Enable
6628 +    Shows the clock enable bit for the ASC0 domain. This domain contains the ASC0 interface block. */
6629 +#define CLKS_ASC0 0x00001000
6630 +/* Disable
6631 +#define CLKS_ASC0_DIS 0x00000000 */
6632 +/** Enable */
6633 +#define CLKS_ASC0_EN 0x00001000
6634 +/** ASC1 Clock Enable
6635 +    Shows the clock enable bit for the ASC1 domain. This domain contains the ASC1 block. */
6636 +#define CLKS_ASC1 0x00000800
6637 +/* Disable
6638 +#define CLKS_ASC1_DIS 0x00000000 */
6639 +/** Enable */
6640 +#define CLKS_ASC1_EN 0x00000800
6641 +/** DCDCAPD Clock Enable
6642 +    Shows the clock enable bit for the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
6643 +#define CLKS_DCDCAPD 0x00000400
6644 +/* Disable
6645 +#define CLKS_DCDCAPD_DIS 0x00000000 */
6646 +/** Enable */
6647 +#define CLKS_DCDCAPD_EN 0x00000400
6648 +/** DCDCDDR Clock Enable
6649 +    Shows the clock enable bit for the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
6650 +#define CLKS_DCDCDDR 0x00000200
6651 +/* Disable
6652 +#define CLKS_DCDCDDR_DIS 0x00000000 */
6653 +/** Enable */
6654 +#define CLKS_DCDCDDR_EN 0x00000200
6655 +/** DCDC1V0 Clock Enable
6656 +    Shows the clock enable bit for the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
6657 +#define CLKS_DCDC1V0 0x00000100
6658 +/* Disable
6659 +#define CLKS_DCDC1V0_DIS 0x00000000 */
6660 +/** Enable */
6661 +#define CLKS_DCDC1V0_EN 0x00000100
6662 +/** TRC2MEM Clock Enable
6663 +    Shows the clock enable bit for the TRC2MEM domain. This domain contains the TRC2MEM block. */
6664 +#define CLKS_TRC2MEM 0x00000040
6665 +/* Disable
6666 +#define CLKS_TRC2MEM_DIS 0x00000000 */
6667 +/** Enable */
6668 +#define CLKS_TRC2MEM_EN 0x00000040
6669 +/** DDR Clock Enable
6670 +    Shows the clock enable bit for the DDR domain. This domain contains the DDR interface block. */
6671 +#define CLKS_DDR 0x00000020
6672 +/* Disable
6673 +#define CLKS_DDR_DIS 0x00000000 */
6674 +/** Enable */
6675 +#define CLKS_DDR_EN 0x00000020
6676 +/** EBU Clock Enable
6677 +    Shows the clock enable bit for the EBU domain. This domain contains the EBU interface block. */
6678 +#define CLKS_EBU 0x00000010
6679 +/* Disable
6680 +#define CLKS_EBU_DIS 0x00000000 */
6681 +/** Enable */
6682 +#define CLKS_EBU_EN 0x00000010
6683 +
6684 +/* Fields of "Clock Enable Register" */
6685 +/** Set Clock Enable STATUS
6686 +    Sets the clock enable bit of the STATUS domain. This domain contains the STATUS block. */
6687 +#define CLKEN_STATUS 0x80000000
6688 +/* No-Operation
6689 +#define CLKEN_STATUS_NOP 0x00000000 */
6690 +/** Set */
6691 +#define CLKEN_STATUS_SET 0x80000000
6692 +/** Set Clock Enable SHA1
6693 +    Sets the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */
6694 +#define CLKEN_SHA1 0x40000000
6695 +/* No-Operation
6696 +#define CLKEN_SHA1_NOP 0x00000000 */
6697 +/** Set */
6698 +#define CLKEN_SHA1_SET 0x40000000
6699 +/** Set Clock Enable AES
6700 +    Sets the clock enable bit of the AES domain. This domain contains the AES block. */
6701 +#define CLKEN_AES 0x20000000
6702 +/* No-Operation
6703 +#define CLKEN_AES_NOP 0x00000000 */
6704 +/** Set */
6705 +#define CLKEN_AES_SET 0x20000000
6706 +/** Set Clock Enable PCM
6707 +    Sets the clock enable bit of the PCM domain. This domain contains the PCM interface block. */
6708 +#define CLKEN_PCM 0x10000000
6709 +/* No-Operation
6710 +#define CLKEN_PCM_NOP 0x00000000 */
6711 +/** Set */
6712 +#define CLKEN_PCM_SET 0x10000000
6713 +/** Set Clock Enable FSCT
6714 +    Sets the clock enable bit of the FSCT domain. This domain contains the FSCT block. */
6715 +#define CLKEN_FSCT 0x08000000
6716 +/* No-Operation
6717 +#define CLKEN_FSCT_NOP 0x00000000 */
6718 +/** Set */
6719 +#define CLKEN_FSCT_SET 0x08000000
6720 +/** Set Clock Enable GPTC
6721 +    Sets the clock enable bit of the GPTC domain. This domain contains the GPTC block. */
6722 +#define CLKEN_GPTC 0x04000000
6723 +/* No-Operation
6724 +#define CLKEN_GPTC_NOP 0x00000000 */
6725 +/** Set */
6726 +#define CLKEN_GPTC_SET 0x04000000
6727 +/** Set Clock Enable MPS
6728 +    Sets the clock enable bit of the MPS domain. This domain contains the MPS block. */
6729 +#define CLKEN_MPS 0x02000000
6730 +/* No-Operation
6731 +#define CLKEN_MPS_NOP 0x00000000 */
6732 +/** Set */
6733 +#define CLKEN_MPS_SET 0x02000000
6734 +/** Set Clock Enable DFEV0
6735 +    Sets the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */
6736 +#define CLKEN_DFEV0 0x01000000
6737 +/* No-Operation
6738 +#define CLKEN_DFEV0_NOP 0x00000000 */
6739 +/** Set */
6740 +#define CLKEN_DFEV0_SET 0x01000000
6741 +/** Set Clock Enable PADCTRL4
6742 +    Sets the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
6743 +#define CLKEN_PADCTRL4 0x00400000
6744 +/* No-Operation
6745 +#define CLKEN_PADCTRL4_NOP 0x00000000 */
6746 +/** Set */
6747 +#define CLKEN_PADCTRL4_SET 0x00400000
6748 +/** Set Clock Enable PADCTRL3
6749 +    Sets the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
6750 +#define CLKEN_PADCTRL3 0x00200000
6751 +/* No-Operation
6752 +#define CLKEN_PADCTRL3_NOP 0x00000000 */
6753 +/** Set */
6754 +#define CLKEN_PADCTRL3_SET 0x00200000
6755 +/** Set Clock Enable PADCTRL1
6756 +    Sets the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
6757 +#define CLKEN_PADCTRL1 0x00100000
6758 +/* No-Operation
6759 +#define CLKEN_PADCTRL1_NOP 0x00000000 */
6760 +/** Set */
6761 +#define CLKEN_PADCTRL1_SET 0x00100000
6762 +/** Set Clock Enable P4
6763 +    Sets the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */
6764 +#define CLKEN_P4 0x00040000
6765 +/* No-Operation
6766 +#define CLKEN_P4_NOP 0x00000000 */
6767 +/** Set */
6768 +#define CLKEN_P4_SET 0x00040000
6769 +/** Set Clock Enable P3
6770 +    Sets the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */
6771 +#define CLKEN_P3 0x00020000
6772 +/* No-Operation
6773 +#define CLKEN_P3_NOP 0x00000000 */
6774 +/** Set */
6775 +#define CLKEN_P3_SET 0x00020000
6776 +/** Set Clock Enable P1
6777 +    Sets the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */
6778 +#define CLKEN_P1 0x00010000
6779 +/* No-Operation
6780 +#define CLKEN_P1_NOP 0x00000000 */
6781 +/** Set */
6782 +#define CLKEN_P1_SET 0x00010000
6783 +/** Set Clock Enable HOST
6784 +    Sets the clock enable bit of the HOST domain. This domain contains the HOST interface block. */
6785 +#define CLKEN_HOST 0x00008000
6786 +/* No-Operation
6787 +#define CLKEN_HOST_NOP 0x00000000 */
6788 +/** Set */
6789 +#define CLKEN_HOST_SET 0x00008000
6790 +/** Set Clock Enable I2C
6791 +    Sets the clock enable bit of the I2C domain. This domain contains the I2C interface block. */
6792 +#define CLKEN_I2C 0x00004000
6793 +/* No-Operation
6794 +#define CLKEN_I2C_NOP 0x00000000 */
6795 +/** Set */
6796 +#define CLKEN_I2C_SET 0x00004000
6797 +/** Set Clock Enable SSC0
6798 +    Sets the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */
6799 +#define CLKEN_SSC0 0x00002000
6800 +/* No-Operation
6801 +#define CLKEN_SSC0_NOP 0x00000000 */
6802 +/** Set */
6803 +#define CLKEN_SSC0_SET 0x00002000
6804 +/** Set Clock Enable ASC0
6805 +    Sets the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */
6806 +#define CLKEN_ASC0 0x00001000
6807 +/* No-Operation
6808 +#define CLKEN_ASC0_NOP 0x00000000 */
6809 +/** Set */
6810 +#define CLKEN_ASC0_SET 0x00001000
6811 +/** Set Clock Enable ASC1
6812 +    Sets the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */
6813 +#define CLKEN_ASC1 0x00000800
6814 +/* No-Operation
6815 +#define CLKEN_ASC1_NOP 0x00000000 */
6816 +/** Set */
6817 +#define CLKEN_ASC1_SET 0x00000800
6818 +/** Set Clock Enable DCDCAPD
6819 +    Sets the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
6820 +#define CLKEN_DCDCAPD 0x00000400
6821 +/* No-Operation
6822 +#define CLKEN_DCDCAPD_NOP 0x00000000 */
6823 +/** Set */
6824 +#define CLKEN_DCDCAPD_SET 0x00000400
6825 +/** Set Clock Enable DCDCDDR
6826 +    Sets the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
6827 +#define CLKEN_DCDCDDR 0x00000200
6828 +/* No-Operation
6829 +#define CLKEN_DCDCDDR_NOP 0x00000000 */
6830 +/** Set */
6831 +#define CLKEN_DCDCDDR_SET 0x00000200
6832 +/** Set Clock Enable DCDC1V0
6833 +    Sets the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
6834 +#define CLKEN_DCDC1V0 0x00000100
6835 +/* No-Operation
6836 +#define CLKEN_DCDC1V0_NOP 0x00000000 */
6837 +/** Set */
6838 +#define CLKEN_DCDC1V0_SET 0x00000100
6839 +/** Set Clock Enable TRC2MEM
6840 +    Sets the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */
6841 +#define CLKEN_TRC2MEM 0x00000040
6842 +/* No-Operation
6843 +#define CLKEN_TRC2MEM_NOP 0x00000000 */
6844 +/** Set */
6845 +#define CLKEN_TRC2MEM_SET 0x00000040
6846 +/** Set Clock Enable DDR
6847 +    Sets the clock enable bit of the DDR domain. This domain contains the DDR interface block. */
6848 +#define CLKEN_DDR 0x00000020
6849 +/* No-Operation
6850 +#define CLKEN_DDR_NOP 0x00000000 */
6851 +/** Set */
6852 +#define CLKEN_DDR_SET 0x00000020
6853 +/** Set Clock Enable EBU
6854 +    Sets the clock enable bit of the EBU domain. This domain contains the EBU interface block. */
6855 +#define CLKEN_EBU 0x00000010
6856 +/* No-Operation
6857 +#define CLKEN_EBU_NOP 0x00000000 */
6858 +/** Set */
6859 +#define CLKEN_EBU_SET 0x00000010
6860 +
6861 +/* Fields of "Clock Clear Register" */
6862 +/** Clear Clock Enable STATUS
6863 +    Clears the clock enable bit of the STATUS domain. This domain contains the STATUS block. */
6864 +#define CLKCLR_STATUS 0x80000000
6865 +/* No-Operation
6866 +#define CLKCLR_STATUS_NOP 0x00000000 */
6867 +/** Clear */
6868 +#define CLKCLR_STATUS_CLR 0x80000000
6869 +/** Clear Clock Enable SHA1
6870 +    Clears the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */
6871 +#define CLKCLR_SHA1 0x40000000
6872 +/* No-Operation
6873 +#define CLKCLR_SHA1_NOP 0x00000000 */
6874 +/** Clear */
6875 +#define CLKCLR_SHA1_CLR 0x40000000
6876 +/** Clear Clock Enable AES
6877 +    Clears the clock enable bit of the AES domain. This domain contains the AES block. */
6878 +#define CLKCLR_AES 0x20000000
6879 +/* No-Operation
6880 +#define CLKCLR_AES_NOP 0x00000000 */
6881 +/** Clear */
6882 +#define CLKCLR_AES_CLR 0x20000000
6883 +/** Clear Clock Enable PCM
6884 +    Clears the clock enable bit of the PCM domain. This domain contains the PCM interface block. */
6885 +#define CLKCLR_PCM 0x10000000
6886 +/* No-Operation
6887 +#define CLKCLR_PCM_NOP 0x00000000 */
6888 +/** Clear */
6889 +#define CLKCLR_PCM_CLR 0x10000000
6890 +/** Clear Clock Enable FSCT
6891 +    Clears the clock enable bit of the FSCT domain. This domain contains the FSCT block. */
6892 +#define CLKCLR_FSCT 0x08000000
6893 +/* No-Operation
6894 +#define CLKCLR_FSCT_NOP 0x00000000 */
6895 +/** Clear */
6896 +#define CLKCLR_FSCT_CLR 0x08000000
6897 +/** Clear Clock Enable GPTC
6898 +    Clears the clock enable bit of the GPTC domain. This domain contains the GPTC block. */
6899 +#define CLKCLR_GPTC 0x04000000
6900 +/* No-Operation
6901 +#define CLKCLR_GPTC_NOP 0x00000000 */
6902 +/** Clear */
6903 +#define CLKCLR_GPTC_CLR 0x04000000
6904 +/** Clear Clock Enable MPS
6905 +    Clears the clock enable bit of the MPS domain. This domain contains the MPS block. */
6906 +#define CLKCLR_MPS 0x02000000
6907 +/* No-Operation
6908 +#define CLKCLR_MPS_NOP 0x00000000 */
6909 +/** Clear */
6910 +#define CLKCLR_MPS_CLR 0x02000000
6911 +/** Clear Clock Enable DFEV0
6912 +    Clears the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */
6913 +#define CLKCLR_DFEV0 0x01000000
6914 +/* No-Operation
6915 +#define CLKCLR_DFEV0_NOP 0x00000000 */
6916 +/** Clear */
6917 +#define CLKCLR_DFEV0_CLR 0x01000000
6918 +/** Clear Clock Enable PADCTRL4
6919 +    Clears the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
6920 +#define CLKCLR_PADCTRL4 0x00400000
6921 +/* No-Operation
6922 +#define CLKCLR_PADCTRL4_NOP 0x00000000 */
6923 +/** Clear */
6924 +#define CLKCLR_PADCTRL4_CLR 0x00400000
6925 +/** Clear Clock Enable PADCTRL3
6926 +    Clears the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
6927 +#define CLKCLR_PADCTRL3 0x00200000
6928 +/* No-Operation
6929 +#define CLKCLR_PADCTRL3_NOP 0x00000000 */
6930 +/** Clear */
6931 +#define CLKCLR_PADCTRL3_CLR 0x00200000
6932 +/** Clear Clock Enable PADCTRL1
6933 +    Clears the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
6934 +#define CLKCLR_PADCTRL1 0x00100000
6935 +/* No-Operation
6936 +#define CLKCLR_PADCTRL1_NOP 0x00000000 */
6937 +/** Clear */
6938 +#define CLKCLR_PADCTRL1_CLR 0x00100000
6939 +/** Clear Clock Enable P4
6940 +    Clears the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */
6941 +#define CLKCLR_P4 0x00040000
6942 +/* No-Operation
6943 +#define CLKCLR_P4_NOP 0x00000000 */
6944 +/** Clear */
6945 +#define CLKCLR_P4_CLR 0x00040000
6946 +/** Clear Clock Enable P3
6947 +    Clears the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */
6948 +#define CLKCLR_P3 0x00020000
6949 +/* No-Operation
6950 +#define CLKCLR_P3_NOP 0x00000000 */
6951 +/** Clear */
6952 +#define CLKCLR_P3_CLR 0x00020000
6953 +/** Clear Clock Enable P1
6954 +    Clears the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */
6955 +#define CLKCLR_P1 0x00010000
6956 +/* No-Operation
6957 +#define CLKCLR_P1_NOP 0x00000000 */
6958 +/** Clear */
6959 +#define CLKCLR_P1_CLR 0x00010000
6960 +/** Clear Clock Enable HOST
6961 +    Clears the clock enable bit of the HOST domain. This domain contains the HOST interface block. */
6962 +#define CLKCLR_HOST 0x00008000
6963 +/* No-Operation
6964 +#define CLKCLR_HOST_NOP 0x00000000 */
6965 +/** Clear */
6966 +#define CLKCLR_HOST_CLR 0x00008000
6967 +/** Clear Clock Enable I2C
6968 +    Clears the clock enable bit of the I2C domain. This domain contains the I2C interface block. */
6969 +#define CLKCLR_I2C 0x00004000
6970 +/* No-Operation
6971 +#define CLKCLR_I2C_NOP 0x00000000 */
6972 +/** Clear */
6973 +#define CLKCLR_I2C_CLR 0x00004000
6974 +/** Clear Clock Enable SSC0
6975 +    Clears the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */
6976 +#define CLKCLR_SSC0 0x00002000
6977 +/* No-Operation
6978 +#define CLKCLR_SSC0_NOP 0x00000000 */
6979 +/** Clear */
6980 +#define CLKCLR_SSC0_CLR 0x00002000
6981 +/** Clear Clock Enable ASC0
6982 +    Clears the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */
6983 +#define CLKCLR_ASC0 0x00001000
6984 +/* No-Operation
6985 +#define CLKCLR_ASC0_NOP 0x00000000 */
6986 +/** Clear */
6987 +#define CLKCLR_ASC0_CLR 0x00001000
6988 +/** Clear Clock Enable ASC1
6989 +    Clears the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */
6990 +#define CLKCLR_ASC1 0x00000800
6991 +/* No-Operation
6992 +#define CLKCLR_ASC1_NOP 0x00000000 */
6993 +/** Clear */
6994 +#define CLKCLR_ASC1_CLR 0x00000800
6995 +/** Clear Clock Enable DCDCAPD
6996 +    Clears the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
6997 +#define CLKCLR_DCDCAPD 0x00000400
6998 +/* No-Operation
6999 +#define CLKCLR_DCDCAPD_NOP 0x00000000 */
7000 +/** Clear */
7001 +#define CLKCLR_DCDCAPD_CLR 0x00000400
7002 +/** Clear Clock Enable DCDCDDR
7003 +    Clears the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
7004 +#define CLKCLR_DCDCDDR 0x00000200
7005 +/* No-Operation
7006 +#define CLKCLR_DCDCDDR_NOP 0x00000000 */
7007 +/** Clear */
7008 +#define CLKCLR_DCDCDDR_CLR 0x00000200
7009 +/** Clear Clock Enable DCDC1V0
7010 +    Clears the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
7011 +#define CLKCLR_DCDC1V0 0x00000100
7012 +/* No-Operation
7013 +#define CLKCLR_DCDC1V0_NOP 0x00000000 */
7014 +/** Clear */
7015 +#define CLKCLR_DCDC1V0_CLR 0x00000100
7016 +/** Clear Clock Enable TRC2MEM
7017 +    Clears the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */
7018 +#define CLKCLR_TRC2MEM 0x00000040
7019 +/* No-Operation
7020 +#define CLKCLR_TRC2MEM_NOP 0x00000000 */
7021 +/** Clear */
7022 +#define CLKCLR_TRC2MEM_CLR 0x00000040
7023 +/** Clear Clock Enable DDR
7024 +    Clears the clock enable bit of the DDR domain. This domain contains the DDR interface block. */
7025 +#define CLKCLR_DDR 0x00000020
7026 +/* No-Operation
7027 +#define CLKCLR_DDR_NOP 0x00000000 */
7028 +/** Clear */
7029 +#define CLKCLR_DDR_CLR 0x00000020
7030 +/** Clear Clock Enable EBU
7031 +    Clears the clock enable bit of the EBU domain. This domain contains the EBU interface block. */
7032 +#define CLKCLR_EBU 0x00000010
7033 +/* No-Operation
7034 +#define CLKCLR_EBU_NOP 0x00000000 */
7035 +/** Clear */
7036 +#define CLKCLR_EBU_CLR 0x00000010
7037 +
7038 +/* Fields of "Activation Status Register" */
7039 +/** STATUS Status
7040 +    Shows the activation status of the STATUS domain. This domain contains the STATUS block. */
7041 +#define ACTS_STATUS 0x80000000
7042 +/* The block is inactive.
7043 +#define ACTS_STATUS_INACT 0x00000000 */
7044 +/** The block is active. */
7045 +#define ACTS_STATUS_ACT 0x80000000
7046 +/** SHA1 Status
7047 +    Shows the activation status of the SHA1 domain. This domain contains the SHA1 block. */
7048 +#define ACTS_SHA1 0x40000000
7049 +/* The block is inactive.
7050 +#define ACTS_SHA1_INACT 0x00000000 */
7051 +/** The block is active. */
7052 +#define ACTS_SHA1_ACT 0x40000000
7053 +/** AES Status
7054 +    Shows the activation status of the AES domain. This domain contains the AES block. */
7055 +#define ACTS_AES 0x20000000
7056 +/* The block is inactive.
7057 +#define ACTS_AES_INACT 0x00000000 */
7058 +/** The block is active. */
7059 +#define ACTS_AES_ACT 0x20000000
7060 +/** PCM Status
7061 +    Shows the activation status of the PCM domain. This domain contains the PCM interface block. */
7062 +#define ACTS_PCM 0x10000000
7063 +/* The block is inactive.
7064 +#define ACTS_PCM_INACT 0x00000000 */
7065 +/** The block is active. */
7066 +#define ACTS_PCM_ACT 0x10000000
7067 +/** FSCT Status
7068 +    Shows the activation status of the FSCT domain. This domain contains the FSCT block. */
7069 +#define ACTS_FSCT 0x08000000
7070 +/* The block is inactive.
7071 +#define ACTS_FSCT_INACT 0x00000000 */
7072 +/** The block is active. */
7073 +#define ACTS_FSCT_ACT 0x08000000
7074 +/** GPTC Status
7075 +    Shows the activation status of the GPTC domain. This domain contains the GPTC block. */
7076 +#define ACTS_GPTC 0x04000000
7077 +/* The block is inactive.
7078 +#define ACTS_GPTC_INACT 0x00000000 */
7079 +/** The block is active. */
7080 +#define ACTS_GPTC_ACT 0x04000000
7081 +/** MPS Status
7082 +    Shows the activation status of the MPS domain. This domain contains the MPS block. */
7083 +#define ACTS_MPS 0x02000000
7084 +/* The block is inactive.
7085 +#define ACTS_MPS_INACT 0x00000000 */
7086 +/** The block is active. */
7087 +#define ACTS_MPS_ACT 0x02000000
7088 +/** DFEV0 Status
7089 +    Shows the activation status of the DFEV0 domain. This domain contains the DFEV0 block. */
7090 +#define ACTS_DFEV0 0x01000000
7091 +/* The block is inactive.
7092 +#define ACTS_DFEV0_INACT 0x00000000 */
7093 +/** The block is active. */
7094 +#define ACTS_DFEV0_ACT 0x01000000
7095 +/** PADCTRL4 Status
7096 +    Shows the activation status of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
7097 +#define ACTS_PADCTRL4 0x00400000
7098 +/* The block is inactive.
7099 +#define ACTS_PADCTRL4_INACT 0x00000000 */
7100 +/** The block is active. */
7101 +#define ACTS_PADCTRL4_ACT 0x00400000
7102 +/** PADCTRL3 Status
7103 +    Shows the activation status of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
7104 +#define ACTS_PADCTRL3 0x00200000
7105 +/* The block is inactive.
7106 +#define ACTS_PADCTRL3_INACT 0x00000000 */
7107 +/** The block is active. */
7108 +#define ACTS_PADCTRL3_ACT 0x00200000
7109 +/** PADCTRL1 Status
7110 +    Shows the activation status of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
7111 +#define ACTS_PADCTRL1 0x00100000
7112 +/* The block is inactive.
7113 +#define ACTS_PADCTRL1_INACT 0x00000000 */
7114 +/** The block is active. */
7115 +#define ACTS_PADCTRL1_ACT 0x00100000
7116 +/** P4 Status
7117 +    Shows the activation status of the P4 domain. This domain contains the P4 instance of the GPIO block. */
7118 +#define ACTS_P4 0x00040000
7119 +/* The block is inactive.
7120 +#define ACTS_P4_INACT 0x00000000 */
7121 +/** The block is active. */
7122 +#define ACTS_P4_ACT 0x00040000
7123 +/** P3 Status
7124 +    Shows the activation status of the P3 domain. This domain contains the P3 instance of the GPIO block. */
7125 +#define ACTS_P3 0x00020000
7126 +/* The block is inactive.
7127 +#define ACTS_P3_INACT 0x00000000 */
7128 +/** The block is active. */
7129 +#define ACTS_P3_ACT 0x00020000
7130 +/** P1 Status
7131 +    Shows the activation status of the P1 domain. This domain contains the P1 instance of the GPIO block. */
7132 +#define ACTS_P1 0x00010000
7133 +/* The block is inactive.
7134 +#define ACTS_P1_INACT 0x00000000 */
7135 +/** The block is active. */
7136 +#define ACTS_P1_ACT 0x00010000
7137 +/** HOST Status
7138 +    Shows the activation status of the HOST domain. This domain contains the HOST interface block. */
7139 +#define ACTS_HOST 0x00008000
7140 +/* The block is inactive.
7141 +#define ACTS_HOST_INACT 0x00000000 */
7142 +/** The block is active. */
7143 +#define ACTS_HOST_ACT 0x00008000
7144 +/** I2C Status
7145 +    Shows the activation status of the I2C domain. This domain contains the I2C interface block. */
7146 +#define ACTS_I2C 0x00004000
7147 +/* The block is inactive.
7148 +#define ACTS_I2C_INACT 0x00000000 */
7149 +/** The block is active. */
7150 +#define ACTS_I2C_ACT 0x00004000
7151 +/** SSC0 Status
7152 +    Shows the activation status of the SSC0 domain. This domain contains the SSC0 interface block. */
7153 +#define ACTS_SSC0 0x00002000
7154 +/* The block is inactive.
7155 +#define ACTS_SSC0_INACT 0x00000000 */
7156 +/** The block is active. */
7157 +#define ACTS_SSC0_ACT 0x00002000
7158 +/** ASC0 Status
7159 +    Shows the activation status of the ASC0 domain. This domain contains the ASC0 interface block. */
7160 +#define ACTS_ASC0 0x00001000
7161 +/* The block is inactive.
7162 +#define ACTS_ASC0_INACT 0x00000000 */
7163 +/** The block is active. */
7164 +#define ACTS_ASC0_ACT 0x00001000
7165 +/** ASC1 Status
7166 +    Shows the activation status of the ASC1 domain. This domain contains the ASC1 block. */
7167 +#define ACTS_ASC1 0x00000800
7168 +/* The block is inactive.
7169 +#define ACTS_ASC1_INACT 0x00000000 */
7170 +/** The block is active. */
7171 +#define ACTS_ASC1_ACT 0x00000800
7172 +/** DCDCAPD Status
7173 +    Shows the activation status of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
7174 +#define ACTS_DCDCAPD 0x00000400
7175 +/* The block is inactive.
7176 +#define ACTS_DCDCAPD_INACT 0x00000000 */
7177 +/** The block is active. */
7178 +#define ACTS_DCDCAPD_ACT 0x00000400
7179 +/** DCDCDDR Status
7180 +    Shows the activation status of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
7181 +#define ACTS_DCDCDDR 0x00000200
7182 +/* The block is inactive.
7183 +#define ACTS_DCDCDDR_INACT 0x00000000 */
7184 +/** The block is active. */
7185 +#define ACTS_DCDCDDR_ACT 0x00000200
7186 +/** DCDC1V0 Status
7187 +    Shows the activation status of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
7188 +#define ACTS_DCDC1V0 0x00000100
7189 +/* The block is inactive.
7190 +#define ACTS_DCDC1V0_INACT 0x00000000 */
7191 +/** The block is active. */
7192 +#define ACTS_DCDC1V0_ACT 0x00000100
7193 +/** TRC2MEM Status
7194 +    Shows the activation status of the TRC2MEM domain. This domain contains the TRC2MEM block. */
7195 +#define ACTS_TRC2MEM 0x00000040
7196 +/* The block is inactive.
7197 +#define ACTS_TRC2MEM_INACT 0x00000000 */
7198 +/** The block is active. */
7199 +#define ACTS_TRC2MEM_ACT 0x00000040
7200 +/** DDR Status
7201 +    Shows the activation status of the DDR domain. This domain contains the DDR interface block. */
7202 +#define ACTS_DDR 0x00000020
7203 +/* The block is inactive.
7204 +#define ACTS_DDR_INACT 0x00000000 */
7205 +/** The block is active. */
7206 +#define ACTS_DDR_ACT 0x00000020
7207 +/** EBU Status
7208 +    Shows the activation status of the EBU domain. This domain contains the EBU interface block. */
7209 +#define ACTS_EBU 0x00000010
7210 +/* The block is inactive.
7211 +#define ACTS_EBU_INACT 0x00000000 */
7212 +/** The block is active. */
7213 +#define ACTS_EBU_ACT 0x00000010
7214 +
7215 +/* Fields of "Activation Register" */
7216 +/** Activate STATUS
7217 +    Sets the activation flag of the STATUS domain. This domain contains the STATUS block. */
7218 +#define ACT_STATUS 0x80000000
7219 +/* No-Operation
7220 +#define ACT_STATUS_NOP 0x00000000 */
7221 +/** Set */
7222 +#define ACT_STATUS_SET 0x80000000
7223 +/** Activate SHA1
7224 +    Sets the activation flag of the SHA1 domain. This domain contains the SHA1 block. */
7225 +#define ACT_SHA1 0x40000000
7226 +/* No-Operation
7227 +#define ACT_SHA1_NOP 0x00000000 */
7228 +/** Set */
7229 +#define ACT_SHA1_SET 0x40000000
7230 +/** Activate AES
7231 +    Sets the activation flag of the AES domain. This domain contains the AES block. */
7232 +#define ACT_AES 0x20000000
7233 +/* No-Operation
7234 +#define ACT_AES_NOP 0x00000000 */
7235 +/** Set */
7236 +#define ACT_AES_SET 0x20000000
7237 +/** Activate PCM
7238 +    Sets the activation flag of the PCM domain. This domain contains the PCM interface block. */
7239 +#define ACT_PCM 0x10000000
7240 +/* No-Operation
7241 +#define ACT_PCM_NOP 0x00000000 */
7242 +/** Set */
7243 +#define ACT_PCM_SET 0x10000000
7244 +/** Activate FSCT
7245 +    Sets the activation flag of the FSCT domain. This domain contains the FSCT block. */
7246 +#define ACT_FSCT 0x08000000
7247 +/* No-Operation
7248 +#define ACT_FSCT_NOP 0x00000000 */
7249 +/** Set */
7250 +#define ACT_FSCT_SET 0x08000000
7251 +/** Activate GPTC
7252 +    Sets the activation flag of the GPTC domain. This domain contains the GPTC block. */
7253 +#define ACT_GPTC 0x04000000
7254 +/* No-Operation
7255 +#define ACT_GPTC_NOP 0x00000000 */
7256 +/** Set */
7257 +#define ACT_GPTC_SET 0x04000000
7258 +/** Activate MPS
7259 +    Sets the activation flag of the MPS domain. This domain contains the MPS block. */
7260 +#define ACT_MPS 0x02000000
7261 +/* No-Operation
7262 +#define ACT_MPS_NOP 0x00000000 */
7263 +/** Set */
7264 +#define ACT_MPS_SET 0x02000000
7265 +/** Activate DFEV0
7266 +    Sets the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */
7267 +#define ACT_DFEV0 0x01000000
7268 +/* No-Operation
7269 +#define ACT_DFEV0_NOP 0x00000000 */
7270 +/** Set */
7271 +#define ACT_DFEV0_SET 0x01000000
7272 +/** Activate PADCTRL4
7273 +    Sets the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
7274 +#define ACT_PADCTRL4 0x00400000
7275 +/* No-Operation
7276 +#define ACT_PADCTRL4_NOP 0x00000000 */
7277 +/** Set */
7278 +#define ACT_PADCTRL4_SET 0x00400000
7279 +/** Activate PADCTRL3
7280 +    Sets the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
7281 +#define ACT_PADCTRL3 0x00200000
7282 +/* No-Operation
7283 +#define ACT_PADCTRL3_NOP 0x00000000 */
7284 +/** Set */
7285 +#define ACT_PADCTRL3_SET 0x00200000
7286 +/** Activate PADCTRL1
7287 +    Sets the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
7288 +#define ACT_PADCTRL1 0x00100000
7289 +/* No-Operation
7290 +#define ACT_PADCTRL1_NOP 0x00000000 */
7291 +/** Set */
7292 +#define ACT_PADCTRL1_SET 0x00100000
7293 +/** Activate P4
7294 +    Sets the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */
7295 +#define ACT_P4 0x00040000
7296 +/* No-Operation
7297 +#define ACT_P4_NOP 0x00000000 */
7298 +/** Set */
7299 +#define ACT_P4_SET 0x00040000
7300 +/** Activate P3
7301 +    Sets the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */
7302 +#define ACT_P3 0x00020000
7303 +/* No-Operation
7304 +#define ACT_P3_NOP 0x00000000 */
7305 +/** Set */
7306 +#define ACT_P3_SET 0x00020000
7307 +/** Activate P1
7308 +    Sets the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */
7309 +#define ACT_P1 0x00010000
7310 +/* No-Operation
7311 +#define ACT_P1_NOP 0x00000000 */
7312 +/** Set */
7313 +#define ACT_P1_SET 0x00010000
7314 +/** Activate HOST
7315 +    Sets the activation flag of the HOST domain. This domain contains the HOST interface block. */
7316 +#define ACT_HOST 0x00008000
7317 +/* No-Operation
7318 +#define ACT_HOST_NOP 0x00000000 */
7319 +/** Set */
7320 +#define ACT_HOST_SET 0x00008000
7321 +/** Activate I2C
7322 +    Sets the activation flag of the I2C domain. This domain contains the I2C interface block. */
7323 +#define ACT_I2C 0x00004000
7324 +/* No-Operation
7325 +#define ACT_I2C_NOP 0x00000000 */
7326 +/** Set */
7327 +#define ACT_I2C_SET 0x00004000
7328 +/** Activate SSC0
7329 +    Sets the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */
7330 +#define ACT_SSC0 0x00002000
7331 +/* No-Operation
7332 +#define ACT_SSC0_NOP 0x00000000 */
7333 +/** Set */
7334 +#define ACT_SSC0_SET 0x00002000
7335 +/** Activate ASC0
7336 +    Sets the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */
7337 +#define ACT_ASC0 0x00001000
7338 +/* No-Operation
7339 +#define ACT_ASC0_NOP 0x00000000 */
7340 +/** Set */
7341 +#define ACT_ASC0_SET 0x00001000
7342 +/** Activate ASC1
7343 +    Sets the activation flag of the ASC1 domain. This domain contains the ASC1 block. */
7344 +#define ACT_ASC1 0x00000800
7345 +/* No-Operation
7346 +#define ACT_ASC1_NOP 0x00000000 */
7347 +/** Set */
7348 +#define ACT_ASC1_SET 0x00000800
7349 +/** Activate DCDCAPD
7350 +    Sets the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
7351 +#define ACT_DCDCAPD 0x00000400
7352 +/* No-Operation
7353 +#define ACT_DCDCAPD_NOP 0x00000000 */
7354 +/** Set */
7355 +#define ACT_DCDCAPD_SET 0x00000400
7356 +/** Activate DCDCDDR
7357 +    Sets the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
7358 +#define ACT_DCDCDDR 0x00000200
7359 +/* No-Operation
7360 +#define ACT_DCDCDDR_NOP 0x00000000 */
7361 +/** Set */
7362 +#define ACT_DCDCDDR_SET 0x00000200
7363 +/** Activate DCDC1V0
7364 +    Sets the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
7365 +#define ACT_DCDC1V0 0x00000100
7366 +/* No-Operation
7367 +#define ACT_DCDC1V0_NOP 0x00000000 */
7368 +/** Set */
7369 +#define ACT_DCDC1V0_SET 0x00000100
7370 +/** Activate TRC2MEM
7371 +    Sets the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */
7372 +#define ACT_TRC2MEM 0x00000040
7373 +/* No-Operation
7374 +#define ACT_TRC2MEM_NOP 0x00000000 */
7375 +/** Set */
7376 +#define ACT_TRC2MEM_SET 0x00000040
7377 +/** Activate DDR
7378 +    Sets the activation flag of the DDR domain. This domain contains the DDR interface block. */
7379 +#define ACT_DDR 0x00000020
7380 +/* No-Operation
7381 +#define ACT_DDR_NOP 0x00000000 */
7382 +/** Set */
7383 +#define ACT_DDR_SET 0x00000020
7384 +/** Activate EBU
7385 +    Sets the activation flag of the EBU domain. This domain contains the EBU interface block. */
7386 +#define ACT_EBU 0x00000010
7387 +/* No-Operation
7388 +#define ACT_EBU_NOP 0x00000000 */
7389 +/** Set */
7390 +#define ACT_EBU_SET 0x00000010
7391 +
7392 +/* Fields of "Deactivation Register" */
7393 +/** Deactivate STATUS
7394 +    Clears the activation flag of the STATUS domain. This domain contains the STATUS block. */
7395 +#define DEACT_STATUS 0x80000000
7396 +/* No-Operation
7397 +#define DEACT_STATUS_NOP 0x00000000 */
7398 +/** Clear */
7399 +#define DEACT_STATUS_CLR 0x80000000
7400 +/** Deactivate SHA1
7401 +    Clears the activation flag of the SHA1 domain. This domain contains the SHA1 block. */
7402 +#define DEACT_SHA1 0x40000000
7403 +/* No-Operation
7404 +#define DEACT_SHA1_NOP 0x00000000 */
7405 +/** Clear */
7406 +#define DEACT_SHA1_CLR 0x40000000
7407 +/** Deactivate AES
7408 +    Clears the activation flag of the AES domain. This domain contains the AES block. */
7409 +#define DEACT_AES 0x20000000
7410 +/* No-Operation
7411 +#define DEACT_AES_NOP 0x00000000 */
7412 +/** Clear */
7413 +#define DEACT_AES_CLR 0x20000000
7414 +/** Deactivate PCM
7415 +    Clears the activation flag of the PCM domain. This domain contains the PCM interface block. */
7416 +#define DEACT_PCM 0x10000000
7417 +/* No-Operation
7418 +#define DEACT_PCM_NOP 0x00000000 */
7419 +/** Clear */
7420 +#define DEACT_PCM_CLR 0x10000000
7421 +/** Deactivate FSCT
7422 +    Clears the activation flag of the FSCT domain. This domain contains the FSCT block. */
7423 +#define DEACT_FSCT 0x08000000
7424 +/* No-Operation
7425 +#define DEACT_FSCT_NOP 0x00000000 */
7426 +/** Clear */
7427 +#define DEACT_FSCT_CLR 0x08000000
7428 +/** Deactivate GPTC
7429 +    Clears the activation flag of the GPTC domain. This domain contains the GPTC block. */
7430 +#define DEACT_GPTC 0x04000000
7431 +/* No-Operation
7432 +#define DEACT_GPTC_NOP 0x00000000 */
7433 +/** Clear */
7434 +#define DEACT_GPTC_CLR 0x04000000
7435 +/** Deactivate MPS
7436 +    Clears the activation flag of the MPS domain. This domain contains the MPS block. */
7437 +#define DEACT_MPS 0x02000000
7438 +/* No-Operation
7439 +#define DEACT_MPS_NOP 0x00000000 */
7440 +/** Clear */
7441 +#define DEACT_MPS_CLR 0x02000000
7442 +/** Deactivate DFEV0
7443 +    Clears the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */
7444 +#define DEACT_DFEV0 0x01000000
7445 +/* No-Operation
7446 +#define DEACT_DFEV0_NOP 0x00000000 */
7447 +/** Clear */
7448 +#define DEACT_DFEV0_CLR 0x01000000
7449 +/** Deactivate PADCTRL4
7450 +    Clears the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
7451 +#define DEACT_PADCTRL4 0x00400000
7452 +/* No-Operation
7453 +#define DEACT_PADCTRL4_NOP 0x00000000 */
7454 +/** Clear */
7455 +#define DEACT_PADCTRL4_CLR 0x00400000
7456 +/** Deactivate PADCTRL3
7457 +    Clears the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
7458 +#define DEACT_PADCTRL3 0x00200000
7459 +/* No-Operation
7460 +#define DEACT_PADCTRL3_NOP 0x00000000 */
7461 +/** Clear */
7462 +#define DEACT_PADCTRL3_CLR 0x00200000
7463 +/** Deactivate PADCTRL1
7464 +    Clears the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
7465 +#define DEACT_PADCTRL1 0x00100000
7466 +/* No-Operation
7467 +#define DEACT_PADCTRL1_NOP 0x00000000 */
7468 +/** Clear */
7469 +#define DEACT_PADCTRL1_CLR 0x00100000
7470 +/** Deactivate P4
7471 +    Clears the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */
7472 +#define DEACT_P4 0x00040000
7473 +/* No-Operation
7474 +#define DEACT_P4_NOP 0x00000000 */
7475 +/** Clear */
7476 +#define DEACT_P4_CLR 0x00040000
7477 +/** Deactivate P3
7478 +    Clears the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */
7479 +#define DEACT_P3 0x00020000
7480 +/* No-Operation
7481 +#define DEACT_P3_NOP 0x00000000 */
7482 +/** Clear */
7483 +#define DEACT_P3_CLR 0x00020000
7484 +/** Deactivate P1
7485 +    Clears the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */
7486 +#define DEACT_P1 0x00010000
7487 +/* No-Operation
7488 +#define DEACT_P1_NOP 0x00000000 */
7489 +/** Clear */
7490 +#define DEACT_P1_CLR 0x00010000
7491 +/** Deactivate HOST
7492 +    Clears the activation flag of the HOST domain. This domain contains the HOST interface block. */
7493 +#define DEACT_HOST 0x00008000
7494 +/* No-Operation
7495 +#define DEACT_HOST_NOP 0x00000000 */
7496 +/** Clear */
7497 +#define DEACT_HOST_CLR 0x00008000
7498 +/** Deactivate I2C
7499 +    Clears the activation flag of the I2C domain. This domain contains the I2C interface block. */
7500 +#define DEACT_I2C 0x00004000
7501 +/* No-Operation
7502 +#define DEACT_I2C_NOP 0x00000000 */
7503 +/** Clear */
7504 +#define DEACT_I2C_CLR 0x00004000
7505 +/** Deactivate SSC0
7506 +    Clears the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */
7507 +#define DEACT_SSC0 0x00002000
7508 +/* No-Operation
7509 +#define DEACT_SSC0_NOP 0x00000000 */
7510 +/** Clear */
7511 +#define DEACT_SSC0_CLR 0x00002000
7512 +/** Deactivate ASC0
7513 +    Clears the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */
7514 +#define DEACT_ASC0 0x00001000
7515 +/* No-Operation
7516 +#define DEACT_ASC0_NOP 0x00000000 */
7517 +/** Clear */
7518 +#define DEACT_ASC0_CLR 0x00001000
7519 +/** Deactivate ASC1
7520 +    Clears the activation flag of the ASC1 domain. This domain contains the ASC1 block. */
7521 +#define DEACT_ASC1 0x00000800
7522 +/* No-Operation
7523 +#define DEACT_ASC1_NOP 0x00000000 */
7524 +/** Clear */
7525 +#define DEACT_ASC1_CLR 0x00000800
7526 +/** Deactivate DCDCAPD
7527 +    Clears the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
7528 +#define DEACT_DCDCAPD 0x00000400
7529 +/* No-Operation
7530 +#define DEACT_DCDCAPD_NOP 0x00000000 */
7531 +/** Clear */
7532 +#define DEACT_DCDCAPD_CLR 0x00000400
7533 +/** Deactivate DCDCDDR
7534 +    Clears the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
7535 +#define DEACT_DCDCDDR 0x00000200
7536 +/* No-Operation
7537 +#define DEACT_DCDCDDR_NOP 0x00000000 */
7538 +/** Clear */
7539 +#define DEACT_DCDCDDR_CLR 0x00000200
7540 +/** Deactivate DCDC1V0
7541 +    Clears the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
7542 +#define DEACT_DCDC1V0 0x00000100
7543 +/* No-Operation
7544 +#define DEACT_DCDC1V0_NOP 0x00000000 */
7545 +/** Clear */
7546 +#define DEACT_DCDC1V0_CLR 0x00000100
7547 +/** Deactivate TRC2MEM
7548 +    Clears the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */
7549 +#define DEACT_TRC2MEM 0x00000040
7550 +/* No-Operation
7551 +#define DEACT_TRC2MEM_NOP 0x00000000 */
7552 +/** Clear */
7553 +#define DEACT_TRC2MEM_CLR 0x00000040
7554 +/** Deactivate DDR
7555 +    Clears the activation flag of the DDR domain. This domain contains the DDR interface block. */
7556 +#define DEACT_DDR 0x00000020
7557 +/* No-Operation
7558 +#define DEACT_DDR_NOP 0x00000000 */
7559 +/** Clear */
7560 +#define DEACT_DDR_CLR 0x00000020
7561 +/** Deactivate EBU
7562 +    Clears the activation flag of the EBU domain. This domain contains the EBU interface block. */
7563 +#define DEACT_EBU 0x00000010
7564 +/* No-Operation
7565 +#define DEACT_EBU_NOP 0x00000000 */
7566 +/** Clear */
7567 +#define DEACT_EBU_CLR 0x00000010
7568 +
7569 +/* Fields of "Reboot Trigger Register" */
7570 +/** Reboot STATUS
7571 +    Triggers a reboot of the STATUS domain. This domain contains the STATUS block. */
7572 +#define RBT_STATUS 0x80000000
7573 +/* No-Operation
7574 +#define RBT_STATUS_NOP 0x00000000 */
7575 +/** Trigger */
7576 +#define RBT_STATUS_TRIG 0x80000000
7577 +/** Reboot SHA1
7578 +    Triggers a reboot of the SHA1 domain. This domain contains the SHA1 block. */
7579 +#define RBT_SHA1 0x40000000
7580 +/* No-Operation
7581 +#define RBT_SHA1_NOP 0x00000000 */
7582 +/** Trigger */
7583 +#define RBT_SHA1_TRIG 0x40000000
7584 +/** Reboot AES
7585 +    Triggers a reboot of the AES domain. This domain contains the AES block. */
7586 +#define RBT_AES 0x20000000
7587 +/* No-Operation
7588 +#define RBT_AES_NOP 0x00000000 */
7589 +/** Trigger */
7590 +#define RBT_AES_TRIG 0x20000000
7591 +/** Reboot PCM
7592 +    Triggers a reboot of the PCM domain. This domain contains the PCM interface block. */
7593 +#define RBT_PCM 0x10000000
7594 +/* No-Operation
7595 +#define RBT_PCM_NOP 0x00000000 */
7596 +/** Trigger */
7597 +#define RBT_PCM_TRIG 0x10000000
7598 +/** Reboot FSCT
7599 +    Triggers a reboot of the FSCT domain. This domain contains the FSCT block. */
7600 +#define RBT_FSCT 0x08000000
7601 +/* No-Operation
7602 +#define RBT_FSCT_NOP 0x00000000 */
7603 +/** Trigger */
7604 +#define RBT_FSCT_TRIG 0x08000000
7605 +/** Reboot GPTC
7606 +    Triggers a reboot of the GPTC domain. This domain contains the GPTC block. */
7607 +#define RBT_GPTC 0x04000000
7608 +/* No-Operation
7609 +#define RBT_GPTC_NOP 0x00000000 */
7610 +/** Trigger */
7611 +#define RBT_GPTC_TRIG 0x04000000
7612 +/** Reboot MPS
7613 +    Triggers a reboot of the MPS domain. This domain contains the MPS block. */
7614 +#define RBT_MPS 0x02000000
7615 +/* No-Operation
7616 +#define RBT_MPS_NOP 0x00000000 */
7617 +/** Trigger */
7618 +#define RBT_MPS_TRIG 0x02000000
7619 +/** Reboot DFEV0
7620 +    Triggers a reboot of the DFEV0 domain. This domain contains the DFEV0 block. */
7621 +#define RBT_DFEV0 0x01000000
7622 +/* No-Operation
7623 +#define RBT_DFEV0_NOP 0x00000000 */
7624 +/** Trigger */
7625 +#define RBT_DFEV0_TRIG 0x01000000
7626 +/** Reboot PADCTRL4
7627 +    Triggers a reboot of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
7628 +#define RBT_PADCTRL4 0x00400000
7629 +/* No-Operation
7630 +#define RBT_PADCTRL4_NOP 0x00000000 */
7631 +/** Trigger */
7632 +#define RBT_PADCTRL4_TRIG 0x00400000
7633 +/** Reboot PADCTRL3
7634 +    Triggers a reboot of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
7635 +#define RBT_PADCTRL3 0x00200000
7636 +/* No-Operation
7637 +#define RBT_PADCTRL3_NOP 0x00000000 */
7638 +/** Trigger */
7639 +#define RBT_PADCTRL3_TRIG 0x00200000
7640 +/** Reboot PADCTRL1
7641 +    Triggers a reboot of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
7642 +#define RBT_PADCTRL1 0x00100000
7643 +/* No-Operation
7644 +#define RBT_PADCTRL1_NOP 0x00000000 */
7645 +/** Trigger */
7646 +#define RBT_PADCTRL1_TRIG 0x00100000
7647 +/** Reboot P4
7648 +    Triggers a reboot of the P4 domain. This domain contains the P4 instance of the GPIO block. */
7649 +#define RBT_P4 0x00040000
7650 +/* No-Operation
7651 +#define RBT_P4_NOP 0x00000000 */
7652 +/** Trigger */
7653 +#define RBT_P4_TRIG 0x00040000
7654 +/** Reboot P3
7655 +    Triggers a reboot of the P3 domain. This domain contains the P3 instance of the GPIO block. */
7656 +#define RBT_P3 0x00020000
7657 +/* No-Operation
7658 +#define RBT_P3_NOP 0x00000000 */
7659 +/** Trigger */
7660 +#define RBT_P3_TRIG 0x00020000
7661 +/** Reboot P1
7662 +    Triggers a reboot of the P1 domain. This domain contains the P1 instance of the GPIO block. */
7663 +#define RBT_P1 0x00010000
7664 +/* No-Operation
7665 +#define RBT_P1_NOP 0x00000000 */
7666 +/** Trigger */
7667 +#define RBT_P1_TRIG 0x00010000
7668 +/** Reboot HOST
7669 +    Triggers a reboot of the HOST domain. This domain contains the HOST interface block. */
7670 +#define RBT_HOST 0x00008000
7671 +/* No-Operation
7672 +#define RBT_HOST_NOP 0x00000000 */
7673 +/** Trigger */
7674 +#define RBT_HOST_TRIG 0x00008000
7675 +/** Reboot I2C
7676 +    Triggers a reboot of the I2C domain. This domain contains the I2C interface block. */
7677 +#define RBT_I2C 0x00004000
7678 +/* No-Operation
7679 +#define RBT_I2C_NOP 0x00000000 */
7680 +/** Trigger */
7681 +#define RBT_I2C_TRIG 0x00004000
7682 +/** Reboot SSC0
7683 +    Triggers a reboot of the SSC0 domain. This domain contains the SSC0 interface block. */
7684 +#define RBT_SSC0 0x00002000
7685 +/* No-Operation
7686 +#define RBT_SSC0_NOP 0x00000000 */
7687 +/** Trigger */
7688 +#define RBT_SSC0_TRIG 0x00002000
7689 +/** Reboot ASC0
7690 +    Triggers a reboot of the ASC0 domain. This domain contains the ASC0 interface block. */
7691 +#define RBT_ASC0 0x00001000
7692 +/* No-Operation
7693 +#define RBT_ASC0_NOP 0x00000000 */
7694 +/** Trigger */
7695 +#define RBT_ASC0_TRIG 0x00001000
7696 +/** Reboot ASC1
7697 +    Triggers a reboot of the ASC1 domain. This domain contains the ASC1 block. */
7698 +#define RBT_ASC1 0x00000800
7699 +/* No-Operation
7700 +#define RBT_ASC1_NOP 0x00000000 */
7701 +/** Trigger */
7702 +#define RBT_ASC1_TRIG 0x00000800
7703 +/** Reboot DCDCAPD
7704 +    Triggers a reboot of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
7705 +#define RBT_DCDCAPD 0x00000400
7706 +/* No-Operation
7707 +#define RBT_DCDCAPD_NOP 0x00000000 */
7708 +/** Trigger */
7709 +#define RBT_DCDCAPD_TRIG 0x00000400
7710 +/** Reboot DCDCDDR
7711 +    Triggers a reboot of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
7712 +#define RBT_DCDCDDR 0x00000200
7713 +/* No-Operation
7714 +#define RBT_DCDCDDR_NOP 0x00000000 */
7715 +/** Trigger */
7716 +#define RBT_DCDCDDR_TRIG 0x00000200
7717 +/** Reboot DCDC1V0
7718 +    Triggers a reboot of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
7719 +#define RBT_DCDC1V0 0x00000100
7720 +/* No-Operation
7721 +#define RBT_DCDC1V0_NOP 0x00000000 */
7722 +/** Trigger */
7723 +#define RBT_DCDC1V0_TRIG 0x00000100
7724 +/** Reboot TRC2MEM
7725 +    Triggers a reboot of the TRC2MEM domain. This domain contains the TRC2MEM block. */
7726 +#define RBT_TRC2MEM 0x00000040
7727 +/* No-Operation
7728 +#define RBT_TRC2MEM_NOP 0x00000000 */
7729 +/** Trigger */
7730 +#define RBT_TRC2MEM_TRIG 0x00000040
7731 +/** Reboot DDR
7732 +    Triggers a reboot of the DDR domain. This domain contains the DDR interface block. */
7733 +#define RBT_DDR 0x00000020
7734 +/* No-Operation
7735 +#define RBT_DDR_NOP 0x00000000 */
7736 +/** Trigger */
7737 +#define RBT_DDR_TRIG 0x00000020
7738 +/** Reboot EBU
7739 +    Triggers a reboot of the EBU domain. This domain contains the EBU interface block. */
7740 +#define RBT_EBU 0x00000010
7741 +/* No-Operation
7742 +#define RBT_EBU_NOP 0x00000000 */
7743 +/** Trigger */
7744 +#define RBT_EBU_TRIG 0x00000010
7745 +/** Reboot XBAR
7746 +    Triggers a reboot of the XBAR. */
7747 +#define RBT_XBAR 0x00000002
7748 +/* No-Operation
7749 +#define RBT_XBAR_NOP 0x00000000 */
7750 +/** Trigger */
7751 +#define RBT_XBAR_TRIG 0x00000002
7752 +/** Reboot CPU
7753 +    Triggers a reboot of the CPU. */
7754 +#define RBT_CPU 0x00000001
7755 +/* No-Operation
7756 +#define RBT_CPU_NOP 0x00000000 */
7757 +/** Trigger */
7758 +#define RBT_CPU_TRIG 0x00000001
7759 +
7760 +/* Fields of "CPU0 Clock Control Register" */
7761 +/** CPU Clock Divider
7762 +    Via this bit the divider and therefore the frequency of the clock of CPU0 can be selected. */
7763 +#define CPU0CC_CPUDIV 0x00000001
7764 +/* Frequency set to the nominal value.
7765 +#define CPU0CC_CPUDIV_SELFNOM 0x00000000 */
7766 +/** Frequency set to half of its nominal value. */
7767 +#define CPU0CC_CPUDIV_SELFHALF 0x00000001
7768 +
7769 +/* Fields of "CPU0 Reset Source Register" */
7770 +/** Software Reboot Request Occurred
7771 +    This bit can be acknowledged by a write operation. */
7772 +#define CPU0RS_SWRRO 0x00000004
7773 +/* Nothing
7774 +#define CPU0RS_SWRRO_NULL 0x00000000 */
7775 +/** Write: Acknowledge the event. */
7776 +#define CPU0RS_SWRRO_EVACK 0x00000004
7777 +/** Read: Event occurred. */
7778 +#define CPU0RS_SWRRO_EVOCC 0x00000004
7779 +/** Hardware Reset Source
7780 +    Reflects the root cause for the last hardware reset. The infrastructure-block is only reset in case of POR. For all other blocks there is no difference between the three HW-reset sources. */
7781 +#define CPU0RS_HWRS_MASK 0x00000003
7782 +/** field offset */
7783 +#define CPU0RS_HWRS_OFFSET 0
7784 +/** Power-on reset. */
7785 +#define CPU0RS_HWRS_POR 0x00000000
7786 +/** RST pin. */
7787 +#define CPU0RS_HWRS_RST 0x00000001
7788 +/** Watchdog reset request. */
7789 +#define CPU0RS_HWRS_WDT 0x00000002
7790 +
7791 +/* Fields of "CPU0 Wakeup Configuration Register" */
7792 +/** Wakeup Request Source Yield Resume 15
7793 +    Select the signal connected to the yield/resume interface pin 15 as source for wakeup from sleep state. */
7794 +#define CPU0WCFG_WRSYR15 0x80000000
7795 +/* Not selected
7796 +#define CPU0WCFG_WRSYR15_NSEL 0x00000000 */
7797 +/** Selected */
7798 +#define CPU0WCFG_WRSYR15_SEL 0x80000000
7799 +/** Wakeup Request Source Yield Resume 14
7800 +    Select the signal connected to the yield/resume interface pin 14 as source for wakeup from sleep state. */
7801 +#define CPU0WCFG_WRSYR14 0x40000000
7802 +/* Not selected
7803 +#define CPU0WCFG_WRSYR14_NSEL 0x00000000 */
7804 +/** Selected */
7805 +#define CPU0WCFG_WRSYR14_SEL 0x40000000
7806 +/** Wakeup Request Source Yield Resume 13
7807 +    Select the signal connected to the yield/resume interface pin 13 as source for wakeup from sleep state. */
7808 +#define CPU0WCFG_WRSYR13 0x20000000
7809 +/* Not selected
7810 +#define CPU0WCFG_WRSYR13_NSEL 0x00000000 */
7811 +/** Selected */
7812 +#define CPU0WCFG_WRSYR13_SEL 0x20000000
7813 +/** Wakeup Request Source Yield Resume 12
7814 +    Select the signal connected to the yield/resume interface pin 12 as source for wakeup from sleep state. */
7815 +#define CPU0WCFG_WRSYR12 0x10000000
7816 +/* Not selected
7817 +#define CPU0WCFG_WRSYR12_NSEL 0x00000000 */
7818 +/** Selected */
7819 +#define CPU0WCFG_WRSYR12_SEL 0x10000000
7820 +/** Wakeup Request Source Yield Resume 11
7821 +    Select the signal connected to the yield/resume interface pin 11 as source for wakeup from sleep state. */
7822 +#define CPU0WCFG_WRSYR11 0x08000000
7823 +/* Not selected
7824 +#define CPU0WCFG_WRSYR11_NSEL 0x00000000 */
7825 +/** Selected */
7826 +#define CPU0WCFG_WRSYR11_SEL 0x08000000
7827 +/** Wakeup Request Source Yield Resume 10
7828 +    Select the signal connected to the yield/resume interface pin 10 as source for wakeup from sleep state. */
7829 +#define CPU0WCFG_WRSYR10 0x04000000
7830 +/* Not selected
7831 +#define CPU0WCFG_WRSYR10_NSEL 0x00000000 */
7832 +/** Selected */
7833 +#define CPU0WCFG_WRSYR10_SEL 0x04000000
7834 +/** Wakeup Request Source Yield Resume 9
7835 +    Select the signal connected to the yield/resume interface pin 9 as source for wakeup from sleep state. */
7836 +#define CPU0WCFG_WRSYR9 0x02000000
7837 +/* Not selected
7838 +#define CPU0WCFG_WRSYR9_NSEL 0x00000000 */
7839 +/** Selected */
7840 +#define CPU0WCFG_WRSYR9_SEL 0x02000000
7841 +/** Wakeup Request Source Yield Resume 8
7842 +    Select the signal connected to the yield/resume interface pin 8 as source for wakeup from sleep state. */
7843 +#define CPU0WCFG_WRSYR8 0x01000000
7844 +/* Not selected
7845 +#define CPU0WCFG_WRSYR8_NSEL 0x00000000 */
7846 +/** Selected */
7847 +#define CPU0WCFG_WRSYR8_SEL 0x01000000
7848 +/** Wakeup Request Source Yield Resume 7
7849 +    Select the signal connected to the yield/resume interface pin 7 as source for wakeup from sleep state. */
7850 +#define CPU0WCFG_WRSYR7 0x00800000
7851 +/* Not selected
7852 +#define CPU0WCFG_WRSYR7_NSEL 0x00000000 */
7853 +/** Selected */
7854 +#define CPU0WCFG_WRSYR7_SEL 0x00800000
7855 +/** Wakeup Request Source Yield Resume 6
7856 +    Select the signal connected to the yield/resume interface pin 6 as source for wakeup from sleep state. */
7857 +#define CPU0WCFG_WRSYR6 0x00400000
7858 +/* Not selected
7859 +#define CPU0WCFG_WRSYR6_NSEL 0x00000000 */
7860 +/** Selected */
7861 +#define CPU0WCFG_WRSYR6_SEL 0x00400000
7862 +/** Wakeup Request Source Yield Resume 5
7863 +    Select the signal connected to the yield/resume interface pin 5 as source for wakeup from sleep state. */
7864 +#define CPU0WCFG_WRSYR5 0x00200000
7865 +/* Not selected
7866 +#define CPU0WCFG_WRSYR5_NSEL 0x00000000 */
7867 +/** Selected */
7868 +#define CPU0WCFG_WRSYR5_SEL 0x00200000
7869 +/** Wakeup Request Source Yield Resume 4
7870 +    Select the signal connected to the yield/resume interface pin 4 as source for wakeup from sleep state. */
7871 +#define CPU0WCFG_WRSYR4 0x00100000
7872 +/* Not selected
7873 +#define CPU0WCFG_WRSYR4_NSEL 0x00000000 */
7874 +/** Selected */
7875 +#define CPU0WCFG_WRSYR4_SEL 0x00100000
7876 +/** Wakeup Request Source Yield Resume 3
7877 +    Select the signal connected to the yield/resume interface pin 3 as source for wakeup from sleep state. */
7878 +#define CPU0WCFG_WRSYR3 0x00080000
7879 +/* Not selected
7880 +#define CPU0WCFG_WRSYR3_NSEL 0x00000000 */
7881 +/** Selected */
7882 +#define CPU0WCFG_WRSYR3_SEL 0x00080000
7883 +/** Wakeup Request Source Yield Resume 2
7884 +    Select the signal connected to the yield/resume interface pin 2 as source for wakeup from sleep state. */
7885 +#define CPU0WCFG_WRSYR2 0x00040000
7886 +/* Not selected
7887 +#define CPU0WCFG_WRSYR2_NSEL 0x00000000 */
7888 +/** Selected */
7889 +#define CPU0WCFG_WRSYR2_SEL 0x00040000
7890 +/** Wakeup Request Source Yield Resume 1
7891 +    Select the signal connected to the yield/resume interface pin 1 as source for wakeup from sleep state. */
7892 +#define CPU0WCFG_WRSYR1 0x00020000
7893 +/* Not selected
7894 +#define CPU0WCFG_WRSYR1_NSEL 0x00000000 */
7895 +/** Selected */
7896 +#define CPU0WCFG_WRSYR1_SEL 0x00020000
7897 +/** Wakeup Request Source Yield Resume 0
7898 +    Select the signal connected to the yield/resume interface pin 0 as source for wakeup from sleep state. */
7899 +#define CPU0WCFG_WRSYR0 0x00010000
7900 +/* Not selected
7901 +#define CPU0WCFG_WRSYR0_NSEL 0x00000000 */
7902 +/** Selected */
7903 +#define CPU0WCFG_WRSYR0_SEL 0x00010000
7904 +/** Wakeup Request Source Debug
7905 +    Select signal EJ_DINT as source for wakeup from sleep state. */
7906 +#define CPU0WCFG_WRSDBG 0x00000100
7907 +/* Not selected
7908 +#define CPU0WCFG_WRSDBG_NSEL 0x00000000 */
7909 +/** Selected */
7910 +#define CPU0WCFG_WRSDBG_SEL 0x00000100
7911 +/** Wakeup Request Source ICU of VPE1
7912 +    Select signal ICU_IRQ of VPE1 as source for wakeup from sleep state. */
7913 +#define CPU0WCFG_WRSICUVPE1 0x00000002
7914 +/* Not selected
7915 +#define CPU0WCFG_WRSICUVPE1_NSEL 0x00000000 */
7916 +/** Selected */
7917 +#define CPU0WCFG_WRSICUVPE1_SEL 0x00000002
7918 +/** Wakeup Request Source ICU of VPE0
7919 +    Select signal ICU_IRQ of VPE0 as source for wakeup from sleep state. */
7920 +#define CPU0WCFG_WRSICUVPE0 0x00000001
7921 +/* Not selected
7922 +#define CPU0WCFG_WRSICUVPE0_NSEL 0x00000000 */
7923 +/** Selected */
7924 +#define CPU0WCFG_WRSICUVPE0_SEL 0x00000001
7925 +
7926 +/* Fields of "Bootmode Control Register" */
7927 +/** Software Bootmode Select
7928 +    Enables SW writing of Bootmode and shows whether or not the SW-programmed bootmode is reflected in field Bootmode instead of the hardware given value. */
7929 +#define BMC_BMSW 0x80000000
7930 +/* Disable
7931 +#define BMC_BMSW_DIS 0x00000000 */
7932 +/** Enable */
7933 +#define BMC_BMSW_EN 0x80000000
7934 +/** Bootmode
7935 +    Initially this field holds the value of the pinstraps LED_BMODEx on positions 5:0, and the value of the corresponding JTAG register bit on position 6. Writing is enabled by setting Software Bootmode Select to 1 during the write cycle. */
7936 +#define BMC_BM_MASK 0x0000007F
7937 +/** field offset */
7938 +#define BMC_BM_OFFSET 0
7939 +
7940 +/* Fields of "Sleep Configuration Register" */
7941 +/** Enable XBAR Clockoff When All XBAR masters Clockoff
7942 +    Enable XBAR clock shutdown in case all XBAR masters are in clockoff mode. This bit has no effect if bit CPU0 is not enabled. */
7943 +#define SCFG_XBAR 0x00010000
7944 +/* Disable
7945 +#define SCFG_XBAR_DIS 0x00000000 */
7946 +/** Enable */
7947 +#define SCFG_XBAR_EN 0x00010000
7948 +/** CPU0 Clockoff On Sleep
7949 +    Enable CPU0 clock shutdown in case its SI_SLEEP signal becomes active. */
7950 +#define SCFG_CPU0 0x00000001
7951 +/* Disable
7952 +#define SCFG_CPU0_DIS 0x00000000 */
7953 +/** Enable */
7954 +#define SCFG_CPU0_EN 0x00000001
7955 +
7956 +/* Fields of "Power Down Configuration Register" */
7957 +/** Enable Power Down STATUS
7958 +    Ignore this bit as power-gating is not supported for this chip. */
7959 +#define PDCFG_STATUS 0x80000000
7960 +/* Disable
7961 +#define PDCFG_STATUS_DIS 0x00000000 */
7962 +/** Enable */
7963 +#define PDCFG_STATUS_EN 0x80000000
7964 +/** Enable Power Down SHA1
7965 +    Ignore this bit as power-gating is not supported for this chip. */
7966 +#define PDCFG_SHA1 0x40000000
7967 +/* Disable
7968 +#define PDCFG_SHA1_DIS 0x00000000 */
7969 +/** Enable */
7970 +#define PDCFG_SHA1_EN 0x40000000
7971 +/** Enable Power Down AES
7972 +    Ignore this bit as power-gating is not supported for this chip. */
7973 +#define PDCFG_AES 0x20000000
7974 +/* Disable
7975 +#define PDCFG_AES_DIS 0x00000000 */
7976 +/** Enable */
7977 +#define PDCFG_AES_EN 0x20000000
7978 +/** Enable Power Down PCM
7979 +    Ignore this bit as power-gating is not supported for this chip. */
7980 +#define PDCFG_PCM 0x10000000
7981 +/* Disable
7982 +#define PDCFG_PCM_DIS 0x00000000 */
7983 +/** Enable */
7984 +#define PDCFG_PCM_EN 0x10000000
7985 +/** Enable Power Down FSCT
7986 +    Ignore this bit as power-gating is not supported for this chip. */
7987 +#define PDCFG_FSCT 0x08000000
7988 +/* Disable
7989 +#define PDCFG_FSCT_DIS 0x00000000 */
7990 +/** Enable */
7991 +#define PDCFG_FSCT_EN 0x08000000
7992 +/** Enable Power Down GPTC
7993 +    Ignore this bit as power-gating is not supported for this chip. */
7994 +#define PDCFG_GPTC 0x04000000
7995 +/* Disable
7996 +#define PDCFG_GPTC_DIS 0x00000000 */
7997 +/** Enable */
7998 +#define PDCFG_GPTC_EN 0x04000000
7999 +/** Enable Power Down MPS
8000 +    Ignore this bit as power-gating is not supported for this chip. */
8001 +#define PDCFG_MPS 0x02000000
8002 +/* Disable
8003 +#define PDCFG_MPS_DIS 0x00000000 */
8004 +/** Enable */
8005 +#define PDCFG_MPS_EN 0x02000000
8006 +/** Enable Power Down DFEV0
8007 +    Ignore this bit as power-gating is not supported for this chip. */
8008 +#define PDCFG_DFEV0 0x01000000
8009 +/* Disable
8010 +#define PDCFG_DFEV0_DIS 0x00000000 */
8011 +/** Enable */
8012 +#define PDCFG_DFEV0_EN 0x01000000
8013 +/** Enable Power Down PADCTRL4
8014 +    Ignore this bit as power-gating is not supported for this chip. */
8015 +#define PDCFG_PADCTRL4 0x00400000
8016 +/* Disable
8017 +#define PDCFG_PADCTRL4_DIS 0x00000000 */
8018 +/** Enable */
8019 +#define PDCFG_PADCTRL4_EN 0x00400000
8020 +/** Enable Power Down PADCTRL3
8021 +    Ignore this bit as power-gating is not supported for this chip. */
8022 +#define PDCFG_PADCTRL3 0x00200000
8023 +/* Disable
8024 +#define PDCFG_PADCTRL3_DIS 0x00000000 */
8025 +/** Enable */
8026 +#define PDCFG_PADCTRL3_EN 0x00200000
8027 +/** Enable Power Down PADCTRL1
8028 +    Ignore this bit as power-gating is not supported for this chip. */
8029 +#define PDCFG_PADCTRL1 0x00100000
8030 +/* Disable
8031 +#define PDCFG_PADCTRL1_DIS 0x00000000 */
8032 +/** Enable */
8033 +#define PDCFG_PADCTRL1_EN 0x00100000
8034 +/** Enable Power Down P4
8035 +    Ignore this bit as power-gating is not supported for this chip. */
8036 +#define PDCFG_P4 0x00040000
8037 +/* Disable
8038 +#define PDCFG_P4_DIS 0x00000000 */
8039 +/** Enable */
8040 +#define PDCFG_P4_EN 0x00040000
8041 +/** Enable Power Down P3
8042 +    Ignore this bit as power-gating is not supported for this chip. */
8043 +#define PDCFG_P3 0x00020000
8044 +/* Disable
8045 +#define PDCFG_P3_DIS 0x00000000 */
8046 +/** Enable */
8047 +#define PDCFG_P3_EN 0x00020000
8048 +/** Enable Power Down P1
8049 +    Ignore this bit as power-gating is not supported for this chip. */
8050 +#define PDCFG_P1 0x00010000
8051 +/* Disable
8052 +#define PDCFG_P1_DIS 0x00000000 */
8053 +/** Enable */
8054 +#define PDCFG_P1_EN 0x00010000
8055 +/** Enable Power Down HOST
8056 +    Ignore this bit as power-gating is not supported for this chip. */
8057 +#define PDCFG_HOST 0x00008000
8058 +/* Disable
8059 +#define PDCFG_HOST_DIS 0x00000000 */
8060 +/** Enable */
8061 +#define PDCFG_HOST_EN 0x00008000
8062 +/** Enable Power Down I2C
8063 +    Ignore this bit as power-gating is not supported for this chip. */
8064 +#define PDCFG_I2C 0x00004000
8065 +/* Disable
8066 +#define PDCFG_I2C_DIS 0x00000000 */
8067 +/** Enable */
8068 +#define PDCFG_I2C_EN 0x00004000
8069 +/** Enable Power Down SSC0
8070 +    Ignore this bit as power-gating is not supported for this chip. */
8071 +#define PDCFG_SSC0 0x00002000
8072 +/* Disable
8073 +#define PDCFG_SSC0_DIS 0x00000000 */
8074 +/** Enable */
8075 +#define PDCFG_SSC0_EN 0x00002000
8076 +/** Enable Power Down ASC0
8077 +    Ignore this bit as power-gating is not supported for this chip. */
8078 +#define PDCFG_ASC0 0x00001000
8079 +/* Disable
8080 +#define PDCFG_ASC0_DIS 0x00000000 */
8081 +/** Enable */
8082 +#define PDCFG_ASC0_EN 0x00001000
8083 +/** Enable Power Down ASC1
8084 +    Ignore this bit as power-gating is not supported for this chip. */
8085 +#define PDCFG_ASC1 0x00000800
8086 +/* Disable
8087 +#define PDCFG_ASC1_DIS 0x00000000 */
8088 +/** Enable */
8089 +#define PDCFG_ASC1_EN 0x00000800
8090 +/** Enable Power Down DCDCAPD
8091 +    Ignore this bit as power-gating is not supported for this chip. */
8092 +#define PDCFG_DCDCAPD 0x00000400
8093 +/* Disable
8094 +#define PDCFG_DCDCAPD_DIS 0x00000000 */
8095 +/** Enable */
8096 +#define PDCFG_DCDCAPD_EN 0x00000400
8097 +/** Enable Power Down DCDCDDR
8098 +    Ignore this bit as power-gating is not supported for this chip. */
8099 +#define PDCFG_DCDCDDR 0x00000200
8100 +/* Disable
8101 +#define PDCFG_DCDCDDR_DIS 0x00000000 */
8102 +/** Enable */
8103 +#define PDCFG_DCDCDDR_EN 0x00000200
8104 +/** Enable Power Down DCDC1V0
8105 +    Ignore this bit as power-gating is not supported for this chip. */
8106 +#define PDCFG_DCDC1V0 0x00000100
8107 +/* Disable
8108 +#define PDCFG_DCDC1V0_DIS 0x00000000 */
8109 +/** Enable */
8110 +#define PDCFG_DCDC1V0_EN 0x00000100
8111 +/** Enable Power Down TRC2MEM
8112 +    Ignore this bit as power-gating is not supported for this chip. */
8113 +#define PDCFG_TRC2MEM 0x00000040
8114 +/* Disable
8115 +#define PDCFG_TRC2MEM_DIS 0x00000000 */
8116 +/** Enable */
8117 +#define PDCFG_TRC2MEM_EN 0x00000040
8118 +/** Enable Power Down DDR
8119 +    Ignore this bit as power-gating is not supported for this chip. */
8120 +#define PDCFG_DDR 0x00000020
8121 +/* Disable
8122 +#define PDCFG_DDR_DIS 0x00000000 */
8123 +/** Enable */
8124 +#define PDCFG_DDR_EN 0x00000020
8125 +/** Enable Power Down EBU
8126 +    Ignore this bit as power-gating is not supported for this chip. */
8127 +#define PDCFG_EBU 0x00000010
8128 +/* Disable
8129 +#define PDCFG_EBU_DIS 0x00000000 */
8130 +/** Enable */
8131 +#define PDCFG_EBU_EN 0x00000010
8132 +
8133 +/* Fields of "CLKO Pad Control Register" */
8134 +/** Ethernet Reference Clock CLKO Select
8135 +    Selects the CLKO pad's input as source for the GPHY, SGMII PLLs. */
8136 +#define CLKOC_ETHREF 0x00000002
8137 +/* Not selected
8138 +#define CLKOC_ETHREF_NSEL 0x00000000 */
8139 +/** Selected */
8140 +#define CLKOC_ETHREF_SEL 0x00000002
8141 +/** Output Enable
8142 +    Enables the output driver of the CLKO pad. */
8143 +#define CLKOC_OEN 0x00000001
8144 +/* Disable
8145 +#define CLKOC_OEN_DIS 0x00000000 */
8146 +/** Enable */
8147 +#define CLKOC_OEN_EN 0x00000001
8148 +
8149 +/* Fields of "Infrastructure Control Register" */
8150 +/** General Purpose Control
8151 +    Backup bits. Currently they are connected as: bit 0 : connected to the configmode_on pin of the pinstrapping block. bit 1 : clock enable of the GPE primary clock. bits 3:2 : frequency select of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz All other bits are unconnected. */
8152 +#define INFRAC_GP_MASK 0x1F000000
8153 +/** field offset */
8154 +#define INFRAC_GP_OFFSET 24
8155 +/** CMOS2CML Ethernet Control
8156 +    CMOS2CML Ethernet Control. */
8157 +#define INFRAC_CMOS2CML_GPON_MASK 0x0000F000
8158 +/** field offset */
8159 +#define INFRAC_CMOS2CML_GPON_OFFSET 12
8160 +/** CMOS2CML Ethernet Control
8161 +    CMOS2CML Ethernet Control. */
8162 +#define INFRAC_CMOS2CML_ETH_MASK 0x00000F00
8163 +/** field offset */
8164 +#define INFRAC_CMOS2CML_ETH_OFFSET 8
8165 +/** Dying Gasp Enable
8166 +    Enables the dying gasp detector. */
8167 +#define INFRAC_DGASPEN 0x00000040
8168 +/* Disable
8169 +#define INFRAC_DGASPEN_DIS 0x00000000 */
8170 +/** Enable */
8171 +#define INFRAC_DGASPEN_EN 0x00000040
8172 +/** Dying Gasp Hysteresis Control
8173 +    Dying Gasp Hysteresis Control. */
8174 +#define INFRAC_DGASPHYS_MASK 0x00000030
8175 +/** field offset */
8176 +#define INFRAC_DGASPHYS_OFFSET 4
8177 +/** Linear Regulator 1.5V Enable
8178 +    Enables 1.5V linear regulator. */
8179 +#define INFRAC_LIN1V5EN 0x00000008
8180 +/* Disable
8181 +#define INFRAC_LIN1V5EN_DIS 0x00000000 */
8182 +/** Enable */
8183 +#define INFRAC_LIN1V5EN_EN 0x00000008
8184 +/** Linear Regulator 1.5V Control
8185 +    Linear regulator 1.5V control. */
8186 +#define INFRAC_LIN1V5C_MASK 0x00000007
8187 +/** field offset */
8188 +#define INFRAC_LIN1V5C_OFFSET 0
8189 +
8190 +/* Fields of "HRST_OUT_N Control Register" */
8191 +/** HRST_OUT_N Pin Value
8192 +    Controls the value of the HRST_OUT_N pin. */
8193 +#define HRSTOUTC_VALUE 0x00000001
8194 +
8195 +/* Fields of "EBU Clock Control Register" */
8196 +/** EBU Clock Divider
8197 +    Via this bit the frequency of the clock of the EBU can be selected. */
8198 +#define EBUCC_EBUDIV 0x00000001
8199 +/* Frequency set to 50MHz.
8200 +#define EBUCC_EBUDIV_SELF50 0x00000000 */
8201 +/** Frequency set to 100MHz. */
8202 +#define EBUCC_EBUDIV_SELF100 0x00000001
8203 +
8204 +/* Fields of "NMI Status Register" */
8205 +/** NMI Status Flag TEST
8206 +    Shows whether the event NMI TEST occurred. */
8207 +#define NMIS_TEST 0x00000100
8208 +/* Nothing
8209 +#define NMIS_TEST_NULL 0x00000000 */
8210 +/** Read: Event occurred. */
8211 +#define NMIS_TEST_EVOCC 0x00000100
8212 +/** NMI Status Flag DGASP
8213 +    Shows whether the event NMI DGASP occurred. */
8214 +#define NMIS_DGASP 0x00000004
8215 +/* Nothing
8216 +#define NMIS_DGASP_NULL 0x00000000 */
8217 +/** Read: Event occurred. */
8218 +#define NMIS_DGASP_EVOCC 0x00000004
8219 +/** NMI Status Flag HOST
8220 +    Shows whether the event NMI HOST occurred. */
8221 +#define NMIS_HOST 0x00000002
8222 +/* Nothing
8223 +#define NMIS_HOST_NULL 0x00000000 */
8224 +/** Read: Event occurred. */
8225 +#define NMIS_HOST_EVOCC 0x00000002
8226 +/** NMI Status Flag PIN
8227 +    Shows whether the event NMI PIN occurred. */
8228 +#define NMIS_PIN 0x00000001
8229 +/* Nothing
8230 +#define NMIS_PIN_NULL 0x00000000 */
8231 +/** Read: Event occurred. */
8232 +#define NMIS_PIN_EVOCC 0x00000001
8233 +
8234 +/* Fields of "NMI Set Register" */
8235 +/** Set NMI Status Flag TEST
8236 +    Sets the corresponding NMI status flag. */
8237 +#define NMISET_TEST 0x00000100
8238 +/* Nothing
8239 +#define NMISET_TEST_NULL 0x00000000 */
8240 +/** Set */
8241 +#define NMISET_TEST_SET 0x00000100
8242 +/** Set NMI Status Flag DGASP
8243 +    Sets the corresponding NMI status flag. */
8244 +#define NMISET_DGASP 0x00000004
8245 +/* Nothing
8246 +#define NMISET_DGASP_NULL 0x00000000 */
8247 +/** Set */
8248 +#define NMISET_DGASP_SET 0x00000004
8249 +/** Set NMI Status Flag HOST
8250 +    Sets the corresponding NMI status flag. */
8251 +#define NMISET_HOST 0x00000002
8252 +/* Nothing
8253 +#define NMISET_HOST_NULL 0x00000000 */
8254 +/** Set */
8255 +#define NMISET_HOST_SET 0x00000002
8256 +/** Set NMI Status Flag PIN
8257 +    Sets the corresponding NMI status flag. */
8258 +#define NMISET_PIN 0x00000001
8259 +/* Nothing
8260 +#define NMISET_PIN_NULL 0x00000000 */
8261 +/** Set */
8262 +#define NMISET_PIN_SET 0x00000001
8263 +
8264 +/* Fields of "NMI Clear Register" */
8265 +/** Clear NMI Status Flag TEST
8266 +    Clears the corresponding NMI status flag. */
8267 +#define NMICLR_TEST 0x00000100
8268 +/* Nothing
8269 +#define NMICLR_TEST_NULL 0x00000000 */
8270 +/** Clear */
8271 +#define NMICLR_TEST_CLR 0x00000100
8272 +/** Clear NMI Status Flag DGASP
8273 +    Clears the corresponding NMI status flag. */
8274 +#define NMICLR_DGASP 0x00000004
8275 +/* Nothing
8276 +#define NMICLR_DGASP_NULL 0x00000000 */
8277 +/** Clear */
8278 +#define NMICLR_DGASP_CLR 0x00000004
8279 +/** Clear NMI Status Flag HOST
8280 +    Clears the corresponding NMI status flag. */
8281 +#define NMICLR_HOST 0x00000002
8282 +/* Nothing
8283 +#define NMICLR_HOST_NULL 0x00000000 */
8284 +/** Clear */
8285 +#define NMICLR_HOST_CLR 0x00000002
8286 +/** Clear NMI Status Flag PIN
8287 +    Clears the corresponding NMI status flag. */
8288 +#define NMICLR_PIN 0x00000001
8289 +/* Nothing
8290 +#define NMICLR_PIN_NULL 0x00000000 */
8291 +/** Clear */
8292 +#define NMICLR_PIN_CLR 0x00000001
8293 +
8294 +/* Fields of "NMI Test Configuration Register" */
8295 +/** Enable NMI Test Feature
8296 +    Enables the operation of the NMI TEST flag. This is the mask for the Non-Maskable-Interrupt dedicated to SW tests. All others cannot be masked. */
8297 +#define NMITCFG_TEN 0x00000100
8298 +/* Disable
8299 +#define NMITCFG_TEN_DIS 0x00000000 */
8300 +/** Enable */
8301 +#define NMITCFG_TEN_EN 0x00000100
8302 +
8303 +/* Fields of "NMI VPE1 Control Register" */
8304 +/** NMI VPE1 State
8305 +    Reflects the state of the NMI signal towards VPE1. This bit is controlled by software only, there is no hardware NMI source dedicated to VPE1. So VPE0 could trigger an NMI at VPE1 using this bit in its own NMI-routine. */
8306 +#define NMIVPE1C_NMI 0x00000001
8307 +/* False
8308 +#define NMIVPE1C_NMI_FALSE 0x00000000 */
8309 +/** True */
8310 +#define NMIVPE1C_NMI_TRUE 0x00000001
8311 +
8312 +/* Fields of "IRN Capture Register" */
8313 +/** DCDCAPD Alarm
8314 +    The DCDC Converter for the APD Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
8315 +#define IRNCR_DCDCAPD 0x00400000
8316 +/* Nothing
8317 +#define IRNCR_DCDCAPD_NULL 0x00000000 */
8318 +/** Write: Acknowledge the interrupt. */
8319 +#define IRNCR_DCDCAPD_INTACK 0x00400000
8320 +/** Read: Interrupt occurred. */
8321 +#define IRNCR_DCDCAPD_INTOCC 0x00400000
8322 +/** DCDCDDR Alarm
8323 +    The DCDC Converter for the DDR Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
8324 +#define IRNCR_DCDCDDR 0x00200000
8325 +/* Nothing
8326 +#define IRNCR_DCDCDDR_NULL 0x00000000 */
8327 +/** Write: Acknowledge the interrupt. */
8328 +#define IRNCR_DCDCDDR_INTACK 0x00200000
8329 +/** Read: Interrupt occurred. */
8330 +#define IRNCR_DCDCDDR_INTOCC 0x00200000
8331 +/** DCDC1V0 Alarm
8332 +    The DCDC Converter for the 1.0 Volts submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
8333 +#define IRNCR_DCDC1V0 0x00100000
8334 +/* Nothing
8335 +#define IRNCR_DCDC1V0_NULL 0x00000000 */
8336 +/** Write: Acknowledge the interrupt. */
8337 +#define IRNCR_DCDC1V0_INTACK 0x00100000
8338 +/** Read: Interrupt occurred. */
8339 +#define IRNCR_DCDC1V0_INTOCC 0x00100000
8340 +/** SIF0 wakeup request
8341 +    SmartSlic Interface 0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
8342 +#define IRNCR_SIF0 0x00010000
8343 +/* Nothing
8344 +#define IRNCR_SIF0_NULL 0x00000000 */
8345 +/** Write: Acknowledge the interrupt. */
8346 +#define IRNCR_SIF0_INTACK 0x00010000
8347 +/** Read: Interrupt occurred. */
8348 +#define IRNCR_SIF0_INTOCC 0x00010000
8349 +
8350 +/* Fields of "IRN Interrupt Control Register" */
8351 +/** DCDCAPD Alarm
8352 +    Interrupt control bit for the corresponding bit in the IRNCR register. */
8353 +#define IRNICR_DCDCAPD 0x00400000
8354 +/** DCDCDDR Alarm
8355 +    Interrupt control bit for the corresponding bit in the IRNCR register. */
8356 +#define IRNICR_DCDCDDR 0x00200000
8357 +/** DCDC1V0 Alarm
8358 +    Interrupt control bit for the corresponding bit in the IRNCR register. */
8359 +#define IRNICR_DCDC1V0 0x00100000
8360 +/** SIF0 wakeup request
8361 +    Interrupt control bit for the corresponding bit in the IRNCR register. */
8362 +#define IRNICR_SIF0 0x00010000
8363 +
8364 +/* Fields of "IRN Interrupt Enable Register" */
8365 +/** DCDCAPD Alarm
8366 +    Interrupt enable bit for the corresponding bit in the IRNCR register. */
8367 +#define IRNEN_DCDCAPD 0x00400000
8368 +/* Disable
8369 +#define IRNEN_DCDCAPD_DIS 0x00000000 */
8370 +/** Enable */
8371 +#define IRNEN_DCDCAPD_EN 0x00400000
8372 +/** DCDCDDR Alarm
8373 +    Interrupt enable bit for the corresponding bit in the IRNCR register. */
8374 +#define IRNEN_DCDCDDR 0x00200000
8375 +/* Disable
8376 +#define IRNEN_DCDCDDR_DIS 0x00000000 */
8377 +/** Enable */
8378 +#define IRNEN_DCDCDDR_EN 0x00200000
8379 +/** DCDC1V0 Alarm
8380 +    Interrupt enable bit for the corresponding bit in the IRNCR register. */
8381 +#define IRNEN_DCDC1V0 0x00100000
8382 +/* Disable
8383 +#define IRNEN_DCDC1V0_DIS 0x00000000 */
8384 +/** Enable */
8385 +#define IRNEN_DCDC1V0_EN 0x00100000
8386 +/** SIF0 wakeup request
8387 +    Interrupt enable bit for the corresponding bit in the IRNCR register. */
8388 +#define IRNEN_SIF0 0x00010000
8389 +/* Disable
8390 +#define IRNEN_SIF0_DIS 0x00000000 */
8391 +/** Enable */
8392 +#define IRNEN_SIF0_EN 0x00010000
8393 +
8394 +/*! @} */ /* SYS1_REGISTER */
8395 +
8396 +#endif /* _sys1_reg_h */
8397 --- /dev/null
8398 +++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h
8399 @@ -0,0 +1,1132 @@
8400 +/******************************************************************************
8401 +
8402 +                               Copyright (c) 2010
8403 +                            Lantiq Deutschland GmbH
8404 +
8405 +  For licensing information, see the file 'LICENSE' in the root folder of
8406 +  this software module.
8407 +
8408 +******************************************************************************/
8409 +
8410 +#ifndef _sys_eth_reg_h
8411 +#define _sys_eth_reg_h
8412 +
8413 +/** \addtogroup SYS_ETH_REGISTER
8414 +   @{
8415 +*/
8416 +/* access macros */
8417 +#define sys_eth_r32(reg) reg_r32(&sys_eth->reg)
8418 +#define sys_eth_w32(val, reg) reg_w32(val, &sys_eth->reg)
8419 +#define sys_eth_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_eth->reg)
8420 +#define sys_eth_r32_table(reg, idx) reg_r32_table(sys_eth->reg, idx)
8421 +#define sys_eth_w32_table(val, reg, idx) reg_w32_table(val, sys_eth->reg, idx)
8422 +#define sys_eth_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_eth->reg, idx)
8423 +#define sys_eth_adr_table(reg, idx) adr_table(sys_eth->reg, idx)
8424 +
8425 +
8426 +/** SYS_ETH register structure */
8427 +struct gpon_reg_sys_eth
8428 +{
8429 +   /** Clock Status Register */
8430 +   unsigned int clks; /* 0x00000000 */
8431 +   /** Clock Enable Register
8432 +       Via this register the clocks for the domains can be enabled. */
8433 +   unsigned int clken; /* 0x00000004 */
8434 +   /** Clock Clear Register
8435 +       Via this register the clocks for the domains can be disabled. */
8436 +   unsigned int clkclr; /* 0x00000008 */
8437 +   /** Reserved */
8438 +   unsigned int res_0[5]; /* 0x0000000C */
8439 +   /** Activation Status Register */
8440 +   unsigned int acts; /* 0x00000020 */
8441 +   /** Activation Register
8442 +       Via this register the domains can be activated. */
8443 +   unsigned int act; /* 0x00000024 */
8444 +   /** Deactivation Register
8445 +       Via this register the domains can be deactivated. */
8446 +   unsigned int deact; /* 0x00000028 */
8447 +   /** Reboot Trigger Register
8448 +       Via this register the domains can be rebooted (sent through reset). */
8449 +   unsigned int rbt; /* 0x0000002C */
8450 +   /** Reserved */
8451 +   unsigned int res_1[32]; /* 0x00000030 */
8452 +   /** External PHY Control Register */
8453 +   unsigned int extphyc; /* 0x000000B0 */
8454 +   /** Power Down Configuration Register
8455 +       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */
8456 +   unsigned int pdcfg; /* 0x000000B4 */
8457 +   /** Datarate Control Register
8458 +       Controls the datarate of the various physical layers. The contents of the writeable fields of this register shall not be changed during operation. */
8459 +   unsigned int drc; /* 0x000000B8 */
8460 +   /** GMAC Multiplexer Control Register
8461 +       Controls the interconnect between GMACs and the various physical layers. All fields need to have a different content. If two GMACs are muxed to the same PHY unpredictable results may occur. The contents of this register shall not be changed during operation. */
8462 +   unsigned int gmuxc; /* 0x000000BC */
8463 +   /** Datarate Status Register
8464 +       Shows the datarate of the GMACs. The datarate of a GMAC is derived from the datarate of the physical layer it is multiplexed to. This register is for debugging only. */
8465 +   unsigned int drs; /* 0x000000C0 */
8466 +   /** SGMII Control Register */
8467 +   unsigned int sgmiic; /* 0x000000C4 */
8468 +   /** Reserved */
8469 +   unsigned int res_2[14]; /* 0x000000C8 */
8470 +};
8471 +
8472 +
8473 +/* Fields of "Clock Status Register" */
8474 +/** GPHY1MII2 Clock Enable
8475 +    Shows the clock enable bit for GPHY1MII2. */
8476 +#define SYS_ETH_CLKS_GPHY1MII2 0x02000000
8477 +/* Disable
8478 +#define SYS_ETH_CLKS_GPHY1MII2_DIS 0x00000000 */
8479 +/** Enable */
8480 +#define SYS_ETH_CLKS_GPHY1MII2_EN 0x02000000
8481 +/** GPHY0MII2 Clock Enable
8482 +    Shows the clock enable bit for GPHY0MII2. */
8483 +#define SYS_ETH_CLKS_GPHY0MII2 0x01000000
8484 +/* Disable
8485 +#define SYS_ETH_CLKS_GPHY0MII2_DIS 0x00000000 */
8486 +/** Enable */
8487 +#define SYS_ETH_CLKS_GPHY0MII2_EN 0x01000000
8488 +/** PADCTRL2 Clock Enable
8489 +    Shows the clock enable bit for the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8490 +#define SYS_ETH_CLKS_PADCTRL2 0x00200000
8491 +/* Disable
8492 +#define SYS_ETH_CLKS_PADCTRL2_DIS 0x00000000 */
8493 +/** Enable */
8494 +#define SYS_ETH_CLKS_PADCTRL2_EN 0x00200000
8495 +/** PADCTRL0 Clock Enable
8496 +    Shows the clock enable bit for the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8497 +#define SYS_ETH_CLKS_PADCTRL0 0x00100000
8498 +/* Disable
8499 +#define SYS_ETH_CLKS_PADCTRL0_DIS 0x00000000 */
8500 +/** Enable */
8501 +#define SYS_ETH_CLKS_PADCTRL0_EN 0x00100000
8502 +/** P2 Clock Enable
8503 +    Shows the clock enable bit for the P2 domain. This domain contains the P2 instance of the GPIO block. */
8504 +#define SYS_ETH_CLKS_P2 0x00020000
8505 +/* Disable
8506 +#define SYS_ETH_CLKS_P2_DIS 0x00000000 */
8507 +/** Enable */
8508 +#define SYS_ETH_CLKS_P2_EN 0x00020000
8509 +/** P0 Clock Enable
8510 +    Shows the clock enable bit for the P0 domain. This domain contains the P0 instance of the GPIO block. */
8511 +#define SYS_ETH_CLKS_P0 0x00010000
8512 +/* Disable
8513 +#define SYS_ETH_CLKS_P0_DIS 0x00000000 */
8514 +/** Enable */
8515 +#define SYS_ETH_CLKS_P0_EN 0x00010000
8516 +/** xMII Clock Enable
8517 +    Shows the clock enable bit for the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8518 +#define SYS_ETH_CLKS_xMII 0x00000800
8519 +/* Disable
8520 +#define SYS_ETH_CLKS_xMII_DIS 0x00000000 */
8521 +/** Enable */
8522 +#define SYS_ETH_CLKS_xMII_EN 0x00000800
8523 +/** SGMII Clock Enable
8524 +    Shows the clock enable bit for the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8525 +#define SYS_ETH_CLKS_SGMII 0x00000400
8526 +/* Disable
8527 +#define SYS_ETH_CLKS_SGMII_DIS 0x00000000 */
8528 +/** Enable */
8529 +#define SYS_ETH_CLKS_SGMII_EN 0x00000400
8530 +/** GPHY1 Clock Enable
8531 +    Shows the clock enable bit for the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8532 +#define SYS_ETH_CLKS_GPHY1 0x00000200
8533 +/* Disable
8534 +#define SYS_ETH_CLKS_GPHY1_DIS 0x00000000 */
8535 +/** Enable */
8536 +#define SYS_ETH_CLKS_GPHY1_EN 0x00000200
8537 +/** GPHY0 Clock Enable
8538 +    Shows the clock enable bit for the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8539 +#define SYS_ETH_CLKS_GPHY0 0x00000100
8540 +/* Disable
8541 +#define SYS_ETH_CLKS_GPHY0_DIS 0x00000000 */
8542 +/** Enable */
8543 +#define SYS_ETH_CLKS_GPHY0_EN 0x00000100
8544 +/** MDIO Clock Enable
8545 +    Shows the clock enable bit for the MDIO domain. This domain contains the MDIO block. */
8546 +#define SYS_ETH_CLKS_MDIO 0x00000080
8547 +/* Disable
8548 +#define SYS_ETH_CLKS_MDIO_DIS 0x00000000 */
8549 +/** Enable */
8550 +#define SYS_ETH_CLKS_MDIO_EN 0x00000080
8551 +/** GMAC3 Clock Enable
8552 +    Shows the clock enable bit for the GMAC3 domain. This domain contains the GMAC3 block. */
8553 +#define SYS_ETH_CLKS_GMAC3 0x00000008
8554 +/* Disable
8555 +#define SYS_ETH_CLKS_GMAC3_DIS 0x00000000 */
8556 +/** Enable */
8557 +#define SYS_ETH_CLKS_GMAC3_EN 0x00000008
8558 +/** GMAC2 Clock Enable
8559 +    Shows the clock enable bit for the GMAC2 domain. This domain contains the GMAC2 block. */
8560 +#define SYS_ETH_CLKS_GMAC2 0x00000004
8561 +/* Disable
8562 +#define SYS_ETH_CLKS_GMAC2_DIS 0x00000000 */
8563 +/** Enable */
8564 +#define SYS_ETH_CLKS_GMAC2_EN 0x00000004
8565 +/** GMAC1 Clock Enable
8566 +    Shows the clock enable bit for the GMAC1 domain. This domain contains the GMAC1 block. */
8567 +#define SYS_ETH_CLKS_GMAC1 0x00000002
8568 +/* Disable
8569 +#define SYS_ETH_CLKS_GMAC1_DIS 0x00000000 */
8570 +/** Enable */
8571 +#define SYS_ETH_CLKS_GMAC1_EN 0x00000002
8572 +/** GMAC0 Clock Enable
8573 +    Shows the clock enable bit for the GMAC0 domain. This domain contains the GMAC0 block. */
8574 +#define SYS_ETH_CLKS_GMAC0 0x00000001
8575 +/* Disable
8576 +#define SYS_ETH_CLKS_GMAC0_DIS 0x00000000 */
8577 +/** Enable */
8578 +#define SYS_ETH_CLKS_GMAC0_EN 0x00000001
8579 +
8580 +/* Fields of "Clock Enable Register" */
8581 +/** Set Clock Enable GPHY1MII2
8582 +    Sets the clock enable bit of the GPHY1MII2. */
8583 +#define SYS_ETH_CLKEN_GPHY1MII2 0x02000000
8584 +/* No-Operation
8585 +#define SYS_ETH_CLKEN_GPHY1MII2_NOP 0x00000000 */
8586 +/** Set */
8587 +#define SYS_ETH_CLKEN_GPHY1MII2_SET 0x02000000
8588 +/** Set Clock Enable GPHY0MII2
8589 +    Sets the clock enable bit of the GPHY0MII2. */
8590 +#define SYS_ETH_CLKEN_GPHY0MII2 0x01000000
8591 +/* No-Operation
8592 +#define SYS_ETH_CLKEN_GPHY0MII2_NOP 0x00000000 */
8593 +/** Set */
8594 +#define SYS_ETH_CLKEN_GPHY0MII2_SET 0x01000000
8595 +/** Set Clock Enable PADCTRL2
8596 +    Sets the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8597 +#define SYS_ETH_CLKEN_PADCTRL2 0x00200000
8598 +/* No-Operation
8599 +#define SYS_ETH_CLKEN_PADCTRL2_NOP 0x00000000 */
8600 +/** Set */
8601 +#define SYS_ETH_CLKEN_PADCTRL2_SET 0x00200000
8602 +/** Set Clock Enable PADCTRL0
8603 +    Sets the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8604 +#define SYS_ETH_CLKEN_PADCTRL0 0x00100000
8605 +/* No-Operation
8606 +#define SYS_ETH_CLKEN_PADCTRL0_NOP 0x00000000 */
8607 +/** Set */
8608 +#define SYS_ETH_CLKEN_PADCTRL0_SET 0x00100000
8609 +/** Set Clock Enable P2
8610 +    Sets the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8611 +#define SYS_ETH_CLKEN_P2 0x00020000
8612 +/* No-Operation
8613 +#define SYS_ETH_CLKEN_P2_NOP 0x00000000 */
8614 +/** Set */
8615 +#define SYS_ETH_CLKEN_P2_SET 0x00020000
8616 +/** Set Clock Enable P0
8617 +    Sets the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8618 +#define SYS_ETH_CLKEN_P0 0x00010000
8619 +/* No-Operation
8620 +#define SYS_ETH_CLKEN_P0_NOP 0x00000000 */
8621 +/** Set */
8622 +#define SYS_ETH_CLKEN_P0_SET 0x00010000
8623 +/** Set Clock Enable xMII
8624 +    Sets the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8625 +#define SYS_ETH_CLKEN_xMII 0x00000800
8626 +/* No-Operation
8627 +#define SYS_ETH_CLKEN_xMII_NOP 0x00000000 */
8628 +/** Set */
8629 +#define SYS_ETH_CLKEN_xMII_SET 0x00000800
8630 +/** Set Clock Enable SGMII
8631 +    Sets the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8632 +#define SYS_ETH_CLKEN_SGMII 0x00000400
8633 +/* No-Operation
8634 +#define SYS_ETH_CLKEN_SGMII_NOP 0x00000000 */
8635 +/** Set */
8636 +#define SYS_ETH_CLKEN_SGMII_SET 0x00000400
8637 +/** Set Clock Enable GPHY1
8638 +    Sets the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8639 +#define SYS_ETH_CLKEN_GPHY1 0x00000200
8640 +/* No-Operation
8641 +#define SYS_ETH_CLKEN_GPHY1_NOP 0x00000000 */
8642 +/** Set */
8643 +#define SYS_ETH_CLKEN_GPHY1_SET 0x00000200
8644 +/** Set Clock Enable GPHY0
8645 +    Sets the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8646 +#define SYS_ETH_CLKEN_GPHY0 0x00000100
8647 +/* No-Operation
8648 +#define SYS_ETH_CLKEN_GPHY0_NOP 0x00000000 */
8649 +/** Set */
8650 +#define SYS_ETH_CLKEN_GPHY0_SET 0x00000100
8651 +/** Set Clock Enable MDIO
8652 +    Sets the clock enable bit of the MDIO domain. This domain contains the MDIO block. */
8653 +#define SYS_ETH_CLKEN_MDIO 0x00000080
8654 +/* No-Operation
8655 +#define SYS_ETH_CLKEN_MDIO_NOP 0x00000000 */
8656 +/** Set */
8657 +#define SYS_ETH_CLKEN_MDIO_SET 0x00000080
8658 +/** Set Clock Enable GMAC3
8659 +    Sets the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */
8660 +#define SYS_ETH_CLKEN_GMAC3 0x00000008
8661 +/* No-Operation
8662 +#define SYS_ETH_CLKEN_GMAC3_NOP 0x00000000 */
8663 +/** Set */
8664 +#define SYS_ETH_CLKEN_GMAC3_SET 0x00000008
8665 +/** Set Clock Enable GMAC2
8666 +    Sets the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */
8667 +#define SYS_ETH_CLKEN_GMAC2 0x00000004
8668 +/* No-Operation
8669 +#define SYS_ETH_CLKEN_GMAC2_NOP 0x00000000 */
8670 +/** Set */
8671 +#define SYS_ETH_CLKEN_GMAC2_SET 0x00000004
8672 +/** Set Clock Enable GMAC1
8673 +    Sets the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */
8674 +#define SYS_ETH_CLKEN_GMAC1 0x00000002
8675 +/* No-Operation
8676 +#define SYS_ETH_CLKEN_GMAC1_NOP 0x00000000 */
8677 +/** Set */
8678 +#define SYS_ETH_CLKEN_GMAC1_SET 0x00000002
8679 +/** Set Clock Enable GMAC0
8680 +    Sets the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */
8681 +#define SYS_ETH_CLKEN_GMAC0 0x00000001
8682 +/* No-Operation
8683 +#define SYS_ETH_CLKEN_GMAC0_NOP 0x00000000 */
8684 +/** Set */
8685 +#define SYS_ETH_CLKEN_GMAC0_SET 0x00000001
8686 +
8687 +/* Fields of "Clock Clear Register" */
8688 +/** Clear Clock Enable GPHY1MII2
8689 +    Clears the clock enable bit of the GPHY1MII2. */
8690 +#define SYS_ETH_CLKCLR_GPHY1MII2 0x02000000
8691 +/* No-Operation
8692 +#define SYS_ETH_CLKCLR_GPHY1MII2_NOP 0x00000000 */
8693 +/** Clear */
8694 +#define SYS_ETH_CLKCLR_GPHY1MII2_CLR 0x02000000
8695 +/** Clear Clock Enable GPHY0MII2
8696 +    Clears the clock enable bit of the GPHY0MII2. */
8697 +#define SYS_ETH_CLKCLR_GPHY0MII2 0x01000000
8698 +/* No-Operation
8699 +#define SYS_ETH_CLKCLR_GPHY0MII2_NOP 0x00000000 */
8700 +/** Clear */
8701 +#define SYS_ETH_CLKCLR_GPHY0MII2_CLR 0x01000000
8702 +/** Clear Clock Enable PADCTRL2
8703 +    Clears the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8704 +#define SYS_ETH_CLKCLR_PADCTRL2 0x00200000
8705 +/* No-Operation
8706 +#define SYS_ETH_CLKCLR_PADCTRL2_NOP 0x00000000 */
8707 +/** Clear */
8708 +#define SYS_ETH_CLKCLR_PADCTRL2_CLR 0x00200000
8709 +/** Clear Clock Enable PADCTRL0
8710 +    Clears the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8711 +#define SYS_ETH_CLKCLR_PADCTRL0 0x00100000
8712 +/* No-Operation
8713 +#define SYS_ETH_CLKCLR_PADCTRL0_NOP 0x00000000 */
8714 +/** Clear */
8715 +#define SYS_ETH_CLKCLR_PADCTRL0_CLR 0x00100000
8716 +/** Clear Clock Enable P2
8717 +    Clears the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8718 +#define SYS_ETH_CLKCLR_P2 0x00020000
8719 +/* No-Operation
8720 +#define SYS_ETH_CLKCLR_P2_NOP 0x00000000 */
8721 +/** Clear */
8722 +#define SYS_ETH_CLKCLR_P2_CLR 0x00020000
8723 +/** Clear Clock Enable P0
8724 +    Clears the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8725 +#define SYS_ETH_CLKCLR_P0 0x00010000
8726 +/* No-Operation
8727 +#define SYS_ETH_CLKCLR_P0_NOP 0x00000000 */
8728 +/** Clear */
8729 +#define SYS_ETH_CLKCLR_P0_CLR 0x00010000
8730 +/** Clear Clock Enable xMII
8731 +    Clears the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8732 +#define SYS_ETH_CLKCLR_xMII 0x00000800
8733 +/* No-Operation
8734 +#define SYS_ETH_CLKCLR_xMII_NOP 0x00000000 */
8735 +/** Clear */
8736 +#define SYS_ETH_CLKCLR_xMII_CLR 0x00000800
8737 +/** Clear Clock Enable SGMII
8738 +    Clears the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8739 +#define SYS_ETH_CLKCLR_SGMII 0x00000400
8740 +/* No-Operation
8741 +#define SYS_ETH_CLKCLR_SGMII_NOP 0x00000000 */
8742 +/** Clear */
8743 +#define SYS_ETH_CLKCLR_SGMII_CLR 0x00000400
8744 +/** Clear Clock Enable GPHY1
8745 +    Clears the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8746 +#define SYS_ETH_CLKCLR_GPHY1 0x00000200
8747 +/* No-Operation
8748 +#define SYS_ETH_CLKCLR_GPHY1_NOP 0x00000000 */
8749 +/** Clear */
8750 +#define SYS_ETH_CLKCLR_GPHY1_CLR 0x00000200
8751 +/** Clear Clock Enable GPHY0
8752 +    Clears the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8753 +#define SYS_ETH_CLKCLR_GPHY0 0x00000100
8754 +/* No-Operation
8755 +#define SYS_ETH_CLKCLR_GPHY0_NOP 0x00000000 */
8756 +/** Clear */
8757 +#define SYS_ETH_CLKCLR_GPHY0_CLR 0x00000100
8758 +/** Clear Clock Enable MDIO
8759 +    Clears the clock enable bit of the MDIO domain. This domain contains the MDIO block. */
8760 +#define SYS_ETH_CLKCLR_MDIO 0x00000080
8761 +/* No-Operation
8762 +#define SYS_ETH_CLKCLR_MDIO_NOP 0x00000000 */
8763 +/** Clear */
8764 +#define SYS_ETH_CLKCLR_MDIO_CLR 0x00000080
8765 +/** Clear Clock Enable GMAC3
8766 +    Clears the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */
8767 +#define SYS_ETH_CLKCLR_GMAC3 0x00000008
8768 +/* No-Operation
8769 +#define SYS_ETH_CLKCLR_GMAC3_NOP 0x00000000 */
8770 +/** Clear */
8771 +#define SYS_ETH_CLKCLR_GMAC3_CLR 0x00000008
8772 +/** Clear Clock Enable GMAC2
8773 +    Clears the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */
8774 +#define SYS_ETH_CLKCLR_GMAC2 0x00000004
8775 +/* No-Operation
8776 +#define SYS_ETH_CLKCLR_GMAC2_NOP 0x00000000 */
8777 +/** Clear */
8778 +#define SYS_ETH_CLKCLR_GMAC2_CLR 0x00000004
8779 +/** Clear Clock Enable GMAC1
8780 +    Clears the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */
8781 +#define SYS_ETH_CLKCLR_GMAC1 0x00000002
8782 +/* No-Operation
8783 +#define SYS_ETH_CLKCLR_GMAC1_NOP 0x00000000 */
8784 +/** Clear */
8785 +#define SYS_ETH_CLKCLR_GMAC1_CLR 0x00000002
8786 +/** Clear Clock Enable GMAC0
8787 +    Clears the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */
8788 +#define SYS_ETH_CLKCLR_GMAC0 0x00000001
8789 +/* No-Operation
8790 +#define SYS_ETH_CLKCLR_GMAC0_NOP 0x00000000 */
8791 +/** Clear */
8792 +#define SYS_ETH_CLKCLR_GMAC0_CLR 0x00000001
8793 +
8794 +/* Fields of "Activation Status Register" */
8795 +/** PADCTRL2 Status
8796 +    Shows the activation status of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8797 +#define SYS_ETH_ACTS_PADCTRL2 0x00200000
8798 +/* The block is inactive.
8799 +#define SYS_ETH_ACTS_PADCTRL2_INACT 0x00000000 */
8800 +/** The block is active. */
8801 +#define SYS_ETH_ACTS_PADCTRL2_ACT 0x00200000
8802 +/** PADCTRL0 Status
8803 +    Shows the activation status of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8804 +#define SYS_ETH_ACTS_PADCTRL0 0x00100000
8805 +/* The block is inactive.
8806 +#define SYS_ETH_ACTS_PADCTRL0_INACT 0x00000000 */
8807 +/** The block is active. */
8808 +#define SYS_ETH_ACTS_PADCTRL0_ACT 0x00100000
8809 +/** P2 Status
8810 +    Shows the activation status of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8811 +#define SYS_ETH_ACTS_P2 0x00020000
8812 +/* The block is inactive.
8813 +#define SYS_ETH_ACTS_P2_INACT 0x00000000 */
8814 +/** The block is active. */
8815 +#define SYS_ETH_ACTS_P2_ACT 0x00020000
8816 +/** P0 Status
8817 +    Shows the activation status of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8818 +#define SYS_ETH_ACTS_P0 0x00010000
8819 +/* The block is inactive.
8820 +#define SYS_ETH_ACTS_P0_INACT 0x00000000 */
8821 +/** The block is active. */
8822 +#define SYS_ETH_ACTS_P0_ACT 0x00010000
8823 +/** xMII Status
8824 +    Shows the activation status of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8825 +#define SYS_ETH_ACTS_xMII 0x00000800
8826 +/* The block is inactive.
8827 +#define SYS_ETH_ACTS_xMII_INACT 0x00000000 */
8828 +/** The block is active. */
8829 +#define SYS_ETH_ACTS_xMII_ACT 0x00000800
8830 +/** SGMII Status
8831 +    Shows the activation status of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8832 +#define SYS_ETH_ACTS_SGMII 0x00000400
8833 +/* The block is inactive.
8834 +#define SYS_ETH_ACTS_SGMII_INACT 0x00000000 */
8835 +/** The block is active. */
8836 +#define SYS_ETH_ACTS_SGMII_ACT 0x00000400
8837 +/** GPHY1 Status
8838 +    Shows the activation status of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8839 +#define SYS_ETH_ACTS_GPHY1 0x00000200
8840 +/* The block is inactive.
8841 +#define SYS_ETH_ACTS_GPHY1_INACT 0x00000000 */
8842 +/** The block is active. */
8843 +#define SYS_ETH_ACTS_GPHY1_ACT 0x00000200
8844 +/** GPHY0 Status
8845 +    Shows the activation status of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8846 +#define SYS_ETH_ACTS_GPHY0 0x00000100
8847 +/* The block is inactive.
8848 +#define SYS_ETH_ACTS_GPHY0_INACT 0x00000000 */
8849 +/** The block is active. */
8850 +#define SYS_ETH_ACTS_GPHY0_ACT 0x00000100
8851 +/** MDIO Status
8852 +    Shows the activation status of the MDIO domain. This domain contains the MDIO block. */
8853 +#define SYS_ETH_ACTS_MDIO 0x00000080
8854 +/* The block is inactive.
8855 +#define SYS_ETH_ACTS_MDIO_INACT 0x00000000 */
8856 +/** The block is active. */
8857 +#define SYS_ETH_ACTS_MDIO_ACT 0x00000080
8858 +/** GMAC3 Status
8859 +    Shows the activation status of the GMAC3 domain. This domain contains the GMAC3 block. */
8860 +#define SYS_ETH_ACTS_GMAC3 0x00000008
8861 +/* The block is inactive.
8862 +#define SYS_ETH_ACTS_GMAC3_INACT 0x00000000 */
8863 +/** The block is active. */
8864 +#define SYS_ETH_ACTS_GMAC3_ACT 0x00000008
8865 +/** GMAC2 Status
8866 +    Shows the activation status of the GMAC2 domain. This domain contains the GMAC2 block. */
8867 +#define SYS_ETH_ACTS_GMAC2 0x00000004
8868 +/* The block is inactive.
8869 +#define SYS_ETH_ACTS_GMAC2_INACT 0x00000000 */
8870 +/** The block is active. */
8871 +#define SYS_ETH_ACTS_GMAC2_ACT 0x00000004
8872 +/** GMAC1 Status
8873 +    Shows the activation status of the GMAC1 domain. This domain contains the GMAC1 block. */
8874 +#define SYS_ETH_ACTS_GMAC1 0x00000002
8875 +/* The block is inactive.
8876 +#define SYS_ETH_ACTS_GMAC1_INACT 0x00000000 */
8877 +/** The block is active. */
8878 +#define SYS_ETH_ACTS_GMAC1_ACT 0x00000002
8879 +/** GMAC0 Status
8880 +    Shows the activation status of the GMAC0 domain. This domain contains the GMAC0 block. */
8881 +#define SYS_ETH_ACTS_GMAC0 0x00000001
8882 +/* The block is inactive.
8883 +#define SYS_ETH_ACTS_GMAC0_INACT 0x00000000 */
8884 +/** The block is active. */
8885 +#define SYS_ETH_ACTS_GMAC0_ACT 0x00000001
8886 +
8887 +/* Fields of "Activation Register" */
8888 +/** Activate PADCTRL2
8889 +    Sets the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8890 +#define SYS_ETH_ACT_PADCTRL2 0x00200000
8891 +/* No-Operation
8892 +#define SYS_ETH_ACT_PADCTRL2_NOP 0x00000000 */
8893 +/** Set */
8894 +#define SYS_ETH_ACT_PADCTRL2_SET 0x00200000
8895 +/** Activate PADCTRL0
8896 +    Sets the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8897 +#define SYS_ETH_ACT_PADCTRL0 0x00100000
8898 +/* No-Operation
8899 +#define SYS_ETH_ACT_PADCTRL0_NOP 0x00000000 */
8900 +/** Set */
8901 +#define SYS_ETH_ACT_PADCTRL0_SET 0x00100000
8902 +/** Activate P2
8903 +    Sets the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8904 +#define SYS_ETH_ACT_P2 0x00020000
8905 +/* No-Operation
8906 +#define SYS_ETH_ACT_P2_NOP 0x00000000 */
8907 +/** Set */
8908 +#define SYS_ETH_ACT_P2_SET 0x00020000
8909 +/** Activate P0
8910 +    Sets the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */
8911 +#define SYS_ETH_ACT_P0 0x00010000
8912 +/* No-Operation
8913 +#define SYS_ETH_ACT_P0_NOP 0x00000000 */
8914 +/** Set */
8915 +#define SYS_ETH_ACT_P0_SET 0x00010000
8916 +/** Activate xMII
8917 +    Sets the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
8918 +#define SYS_ETH_ACT_xMII 0x00000800
8919 +/* No-Operation
8920 +#define SYS_ETH_ACT_xMII_NOP 0x00000000 */
8921 +/** Set */
8922 +#define SYS_ETH_ACT_xMII_SET 0x00000800
8923 +/** Activate SGMII
8924 +    Sets the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
8925 +#define SYS_ETH_ACT_SGMII 0x00000400
8926 +/* No-Operation
8927 +#define SYS_ETH_ACT_SGMII_NOP 0x00000000 */
8928 +/** Set */
8929 +#define SYS_ETH_ACT_SGMII_SET 0x00000400
8930 +/** Activate GPHY1
8931 +    Sets the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
8932 +#define SYS_ETH_ACT_GPHY1 0x00000200
8933 +/* No-Operation
8934 +#define SYS_ETH_ACT_GPHY1_NOP 0x00000000 */
8935 +/** Set */
8936 +#define SYS_ETH_ACT_GPHY1_SET 0x00000200
8937 +/** Activate GPHY0
8938 +    Sets the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
8939 +#define SYS_ETH_ACT_GPHY0 0x00000100
8940 +/* No-Operation
8941 +#define SYS_ETH_ACT_GPHY0_NOP 0x00000000 */
8942 +/** Set */
8943 +#define SYS_ETH_ACT_GPHY0_SET 0x00000100
8944 +/** Activate MDIO
8945 +    Sets the activation flag of the MDIO domain. This domain contains the MDIO block. */
8946 +#define SYS_ETH_ACT_MDIO 0x00000080
8947 +/* No-Operation
8948 +#define SYS_ETH_ACT_MDIO_NOP 0x00000000 */
8949 +/** Set */
8950 +#define SYS_ETH_ACT_MDIO_SET 0x00000080
8951 +/** Activate GMAC3
8952 +    Sets the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */
8953 +#define SYS_ETH_ACT_GMAC3 0x00000008
8954 +/* No-Operation
8955 +#define SYS_ETH_ACT_GMAC3_NOP 0x00000000 */
8956 +/** Set */
8957 +#define SYS_ETH_ACT_GMAC3_SET 0x00000008
8958 +/** Activate GMAC2
8959 +    Sets the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */
8960 +#define SYS_ETH_ACT_GMAC2 0x00000004
8961 +/* No-Operation
8962 +#define SYS_ETH_ACT_GMAC2_NOP 0x00000000 */
8963 +/** Set */
8964 +#define SYS_ETH_ACT_GMAC2_SET 0x00000004
8965 +/** Activate GMAC1
8966 +    Sets the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */
8967 +#define SYS_ETH_ACT_GMAC1 0x00000002
8968 +/* No-Operation
8969 +#define SYS_ETH_ACT_GMAC1_NOP 0x00000000 */
8970 +/** Set */
8971 +#define SYS_ETH_ACT_GMAC1_SET 0x00000002
8972 +/** Activate GMAC0
8973 +    Sets the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */
8974 +#define SYS_ETH_ACT_GMAC0 0x00000001
8975 +/* No-Operation
8976 +#define SYS_ETH_ACT_GMAC0_NOP 0x00000000 */
8977 +/** Set */
8978 +#define SYS_ETH_ACT_GMAC0_SET 0x00000001
8979 +
8980 +/* Fields of "Deactivation Register" */
8981 +/** Deactivate PADCTRL2
8982 +    Clears the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
8983 +#define SYS_ETH_DEACT_PADCTRL2 0x00200000
8984 +/* No-Operation
8985 +#define SYS_ETH_DEACT_PADCTRL2_NOP 0x00000000 */
8986 +/** Clear */
8987 +#define SYS_ETH_DEACT_PADCTRL2_CLR 0x00200000
8988 +/** Deactivate PADCTRL0
8989 +    Clears the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
8990 +#define SYS_ETH_DEACT_PADCTRL0 0x00100000
8991 +/* No-Operation
8992 +#define SYS_ETH_DEACT_PADCTRL0_NOP 0x00000000 */
8993 +/** Clear */
8994 +#define SYS_ETH_DEACT_PADCTRL0_CLR 0x00100000
8995 +/** Deactivate P2
8996 +    Clears the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */
8997 +#define SYS_ETH_DEACT_P2 0x00020000
8998 +/* No-Operation
8999 +#define SYS_ETH_DEACT_P2_NOP 0x00000000 */
9000 +/** Clear */
9001 +#define SYS_ETH_DEACT_P2_CLR 0x00020000
9002 +/** Deactivate P0
9003 +    Clears the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */
9004 +#define SYS_ETH_DEACT_P0 0x00010000
9005 +/* No-Operation
9006 +#define SYS_ETH_DEACT_P0_NOP 0x00000000 */
9007 +/** Clear */
9008 +#define SYS_ETH_DEACT_P0_CLR 0x00010000
9009 +/** Deactivate xMII
9010 +    Clears the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
9011 +#define SYS_ETH_DEACT_xMII 0x00000800
9012 +/* No-Operation
9013 +#define SYS_ETH_DEACT_xMII_NOP 0x00000000 */
9014 +/** Clear */
9015 +#define SYS_ETH_DEACT_xMII_CLR 0x00000800
9016 +/** Deactivate SGMII
9017 +    Clears the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
9018 +#define SYS_ETH_DEACT_SGMII 0x00000400
9019 +/* No-Operation
9020 +#define SYS_ETH_DEACT_SGMII_NOP 0x00000000 */
9021 +/** Clear */
9022 +#define SYS_ETH_DEACT_SGMII_CLR 0x00000400
9023 +/** Deactivate GPHY1
9024 +    Clears the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
9025 +#define SYS_ETH_DEACT_GPHY1 0x00000200
9026 +/* No-Operation
9027 +#define SYS_ETH_DEACT_GPHY1_NOP 0x00000000 */
9028 +/** Clear */
9029 +#define SYS_ETH_DEACT_GPHY1_CLR 0x00000200
9030 +/** Deactivate GPHY0
9031 +    Clears the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
9032 +#define SYS_ETH_DEACT_GPHY0 0x00000100
9033 +/* No-Operation
9034 +#define SYS_ETH_DEACT_GPHY0_NOP 0x00000000 */
9035 +/** Clear */
9036 +#define SYS_ETH_DEACT_GPHY0_CLR 0x00000100
9037 +/** Deactivate MDIO
9038 +    Clears the activation flag of the MDIO domain. This domain contains the MDIO block. */
9039 +#define SYS_ETH_DEACT_MDIO 0x00000080
9040 +/* No-Operation
9041 +#define SYS_ETH_DEACT_MDIO_NOP 0x00000000 */
9042 +/** Clear */
9043 +#define SYS_ETH_DEACT_MDIO_CLR 0x00000080
9044 +/** Deactivate GMAC3
9045 +    Clears the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */
9046 +#define SYS_ETH_DEACT_GMAC3 0x00000008
9047 +/* No-Operation
9048 +#define SYS_ETH_DEACT_GMAC3_NOP 0x00000000 */
9049 +/** Clear */
9050 +#define SYS_ETH_DEACT_GMAC3_CLR 0x00000008
9051 +/** Deactivate GMAC2
9052 +    Clears the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */
9053 +#define SYS_ETH_DEACT_GMAC2 0x00000004
9054 +/* No-Operation
9055 +#define SYS_ETH_DEACT_GMAC2_NOP 0x00000000 */
9056 +/** Clear */
9057 +#define SYS_ETH_DEACT_GMAC2_CLR 0x00000004
9058 +/** Deactivate GMAC1
9059 +    Clears the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */
9060 +#define SYS_ETH_DEACT_GMAC1 0x00000002
9061 +/* No-Operation
9062 +#define SYS_ETH_DEACT_GMAC1_NOP 0x00000000 */
9063 +/** Clear */
9064 +#define SYS_ETH_DEACT_GMAC1_CLR 0x00000002
9065 +/** Deactivate GMAC0
9066 +    Clears the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */
9067 +#define SYS_ETH_DEACT_GMAC0 0x00000001
9068 +/* No-Operation
9069 +#define SYS_ETH_DEACT_GMAC0_NOP 0x00000000 */
9070 +/** Clear */
9071 +#define SYS_ETH_DEACT_GMAC0_CLR 0x00000001
9072 +
9073 +/* Fields of "Reboot Trigger Register" */
9074 +/** Reboot PADCTRL2
9075 +    Triggers a reboot of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
9076 +#define SYS_ETH_RBT_PADCTRL2 0x00200000
9077 +/* No-Operation
9078 +#define SYS_ETH_RBT_PADCTRL2_NOP 0x00000000 */
9079 +/** Trigger */
9080 +#define SYS_ETH_RBT_PADCTRL2_TRIG 0x00200000
9081 +/** Reboot PADCTRL0
9082 +    Triggers a reboot of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
9083 +#define SYS_ETH_RBT_PADCTRL0 0x00100000
9084 +/* No-Operation
9085 +#define SYS_ETH_RBT_PADCTRL0_NOP 0x00000000 */
9086 +/** Trigger */
9087 +#define SYS_ETH_RBT_PADCTRL0_TRIG 0x00100000
9088 +/** Reboot P2
9089 +    Triggers a reboot of the P2 domain. This domain contains the P2 instance of the GPIO block. */
9090 +#define SYS_ETH_RBT_P2 0x00020000
9091 +/* No-Operation
9092 +#define SYS_ETH_RBT_P2_NOP 0x00000000 */
9093 +/** Trigger */
9094 +#define SYS_ETH_RBT_P2_TRIG 0x00020000
9095 +/** Reboot P0
9096 +    Triggers a reboot of the P0 domain. This domain contains the P0 instance of the GPIO block. */
9097 +#define SYS_ETH_RBT_P0 0x00010000
9098 +/* No-Operation
9099 +#define SYS_ETH_RBT_P0_NOP 0x00000000 */
9100 +/** Trigger */
9101 +#define SYS_ETH_RBT_P0_TRIG 0x00010000
9102 +/** Reboot xMII
9103 +    Triggers a reboot of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
9104 +#define SYS_ETH_RBT_xMII 0x00000800
9105 +/* No-Operation
9106 +#define SYS_ETH_RBT_xMII_NOP 0x00000000 */
9107 +/** Trigger */
9108 +#define SYS_ETH_RBT_xMII_TRIG 0x00000800
9109 +/** Reboot SGMII
9110 +    Triggers a reboot of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
9111 +#define SYS_ETH_RBT_SGMII 0x00000400
9112 +/* No-Operation
9113 +#define SYS_ETH_RBT_SGMII_NOP 0x00000000 */
9114 +/** Trigger */
9115 +#define SYS_ETH_RBT_SGMII_TRIG 0x00000400
9116 +/** Reboot GPHY1
9117 +    Triggers a reboot of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
9118 +#define SYS_ETH_RBT_GPHY1 0x00000200
9119 +/* No-Operation
9120 +#define SYS_ETH_RBT_GPHY1_NOP 0x00000000 */
9121 +/** Trigger */
9122 +#define SYS_ETH_RBT_GPHY1_TRIG 0x00000200
9123 +/** Reboot GPHY0
9124 +    Triggers a reboot of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
9125 +#define SYS_ETH_RBT_GPHY0 0x00000100
9126 +/* No-Operation
9127 +#define SYS_ETH_RBT_GPHY0_NOP 0x00000000 */
9128 +/** Trigger */
9129 +#define SYS_ETH_RBT_GPHY0_TRIG 0x00000100
9130 +/** Reboot MDIO
9131 +    Triggers a reboot of the MDIO domain. This domain contains the MDIO block. */
9132 +#define SYS_ETH_RBT_MDIO 0x00000080
9133 +/* No-Operation
9134 +#define SYS_ETH_RBT_MDIO_NOP 0x00000000 */
9135 +/** Trigger */
9136 +#define SYS_ETH_RBT_MDIO_TRIG 0x00000080
9137 +/** Reboot GMAC3
9138 +    Triggers a reboot of the GMAC3 domain. This domain contains the GMAC3 block. */
9139 +#define SYS_ETH_RBT_GMAC3 0x00000008
9140 +/* No-Operation
9141 +#define SYS_ETH_RBT_GMAC3_NOP 0x00000000 */
9142 +/** Trigger */
9143 +#define SYS_ETH_RBT_GMAC3_TRIG 0x00000008
9144 +/** Reboot GMAC2
9145 +    Triggers a reboot of the GMAC2 domain. This domain contains the GMAC2 block. */
9146 +#define SYS_ETH_RBT_GMAC2 0x00000004
9147 +/* No-Operation
9148 +#define SYS_ETH_RBT_GMAC2_NOP 0x00000000 */
9149 +/** Trigger */
9150 +#define SYS_ETH_RBT_GMAC2_TRIG 0x00000004
9151 +/** Reboot GMAC1
9152 +    Triggers a reboot of the GMAC1 domain. This domain contains the GMAC1 block. */
9153 +#define SYS_ETH_RBT_GMAC1 0x00000002
9154 +/* No-Operation
9155 +#define SYS_ETH_RBT_GMAC1_NOP 0x00000000 */
9156 +/** Trigger */
9157 +#define SYS_ETH_RBT_GMAC1_TRIG 0x00000002
9158 +/** Reboot GMAC0
9159 +    Triggers a reboot of the GMAC0 domain. This domain contains the GMAC0 block. */
9160 +#define SYS_ETH_RBT_GMAC0 0x00000001
9161 +/* No-Operation
9162 +#define SYS_ETH_RBT_GMAC0_NOP 0x00000000 */
9163 +/** Trigger */
9164 +#define SYS_ETH_RBT_GMAC0_TRIG 0x00000001
9165 +
9166 +/* Fields of "External PHY Control Register" */
9167 +/** PHY_CLKO Output Enable
9168 +    Enables the output driver of the PHY_CLKO pin. */
9169 +#define SYS_ETH_EXTPHYC_CLKEN 0x80000000
9170 +/* Disable
9171 +#define SYS_ETH_EXTPHYC_CLKEN_DIS 0x00000000 */
9172 +/** Enable */
9173 +#define SYS_ETH_EXTPHYC_CLKEN_EN 0x80000000
9174 +/** PHY_CLKO Frequency Select
9175 +    Selects the frequency of the PHY_CLKO pin. */
9176 +#define SYS_ETH_EXTPHYC_CLKSEL_MASK 0x00000007
9177 +/** field offset */
9178 +#define SYS_ETH_EXTPHYC_CLKSEL_OFFSET 0
9179 +/** 25 MHz. */
9180 +#define SYS_ETH_EXTPHYC_CLKSEL_F25 0x00000001
9181 +/** 125 MHz. */
9182 +#define SYS_ETH_EXTPHYC_CLKSEL_F125 0x00000002
9183 +/** 50 MHz. */
9184 +#define SYS_ETH_EXTPHYC_CLKSEL_F50 0x00000005
9185 +
9186 +/* Fields of "Power Down Configuration Register" */
9187 +/** Enable Power Down PADCTRL2
9188 +    Ignore this bit as power-gating is not supported for this chip. */
9189 +#define SYS_ETH_PDCFG_PADCTRL2 0x00200000
9190 +/* Disable
9191 +#define SYS_ETH_PDCFG_PADCTRL2_DIS 0x00000000 */
9192 +/** Enable */
9193 +#define SYS_ETH_PDCFG_PADCTRL2_EN 0x00200000
9194 +/** Enable Power Down PADCTRL0
9195 +    Ignore this bit as power-gating is not supported for this chip. */
9196 +#define SYS_ETH_PDCFG_PADCTRL0 0x00100000
9197 +/* Disable
9198 +#define SYS_ETH_PDCFG_PADCTRL0_DIS 0x00000000 */
9199 +/** Enable */
9200 +#define SYS_ETH_PDCFG_PADCTRL0_EN 0x00100000
9201 +/** Enable Power Down P2
9202 +    Ignore this bit as power-gating is not supported for this chip. */
9203 +#define SYS_ETH_PDCFG_P2 0x00020000
9204 +/* Disable
9205 +#define SYS_ETH_PDCFG_P2_DIS 0x00000000 */
9206 +/** Enable */
9207 +#define SYS_ETH_PDCFG_P2_EN 0x00020000
9208 +/** Enable Power Down P0
9209 +    Ignore this bit as power-gating is not supported for this chip. */
9210 +#define SYS_ETH_PDCFG_P0 0x00010000
9211 +/* Disable
9212 +#define SYS_ETH_PDCFG_P0_DIS 0x00000000 */
9213 +/** Enable */
9214 +#define SYS_ETH_PDCFG_P0_EN 0x00010000
9215 +/** Enable Power Down xMII
9216 +    Ignore this bit as power-gating is not supported for this chip. */
9217 +#define SYS_ETH_PDCFG_xMII 0x00000800
9218 +/* Disable
9219 +#define SYS_ETH_PDCFG_xMII_DIS 0x00000000 */
9220 +/** Enable */
9221 +#define SYS_ETH_PDCFG_xMII_EN 0x00000800
9222 +/** Enable Power Down SGMII
9223 +    Ignore this bit as power-gating is not supported for this chip. */
9224 +#define SYS_ETH_PDCFG_SGMII 0x00000400
9225 +/* Disable
9226 +#define SYS_ETH_PDCFG_SGMII_DIS 0x00000000 */
9227 +/** Enable */
9228 +#define SYS_ETH_PDCFG_SGMII_EN 0x00000400
9229 +/** Enable Power Down GPHY1
9230 +    Ignore this bit as power-gating is not supported for this chip. */
9231 +#define SYS_ETH_PDCFG_GPHY1 0x00000200
9232 +/* Disable
9233 +#define SYS_ETH_PDCFG_GPHY1_DIS 0x00000000 */
9234 +/** Enable */
9235 +#define SYS_ETH_PDCFG_GPHY1_EN 0x00000200
9236 +/** Enable Power Down GPHY0
9237 +    Ignore this bit as power-gating is not supported for this chip. */
9238 +#define SYS_ETH_PDCFG_GPHY0 0x00000100
9239 +/* Disable
9240 +#define SYS_ETH_PDCFG_GPHY0_DIS 0x00000000 */
9241 +/** Enable */
9242 +#define SYS_ETH_PDCFG_GPHY0_EN 0x00000100
9243 +/** Enable Power Down MDIO
9244 +    Ignore this bit as power-gating is not supported for this chip. */
9245 +#define SYS_ETH_PDCFG_MDIO 0x00000080
9246 +/* Disable
9247 +#define SYS_ETH_PDCFG_MDIO_DIS 0x00000000 */
9248 +/** Enable */
9249 +#define SYS_ETH_PDCFG_MDIO_EN 0x00000080
9250 +/** Enable Power Down GMAC3
9251 +    Ignore this bit as power-gating is not supported for this chip. */
9252 +#define SYS_ETH_PDCFG_GMAC3 0x00000008
9253 +/* Disable
9254 +#define SYS_ETH_PDCFG_GMAC3_DIS 0x00000000 */
9255 +/** Enable */
9256 +#define SYS_ETH_PDCFG_GMAC3_EN 0x00000008
9257 +/** Enable Power Down GMAC2
9258 +    Ignore this bit as power-gating is not supported for this chip. */
9259 +#define SYS_ETH_PDCFG_GMAC2 0x00000004
9260 +/* Disable
9261 +#define SYS_ETH_PDCFG_GMAC2_DIS 0x00000000 */
9262 +/** Enable */
9263 +#define SYS_ETH_PDCFG_GMAC2_EN 0x00000004
9264 +/** Enable Power Down GMAC1
9265 +    Ignore this bit as power-gating is not supported for this chip. */
9266 +#define SYS_ETH_PDCFG_GMAC1 0x00000002
9267 +/* Disable
9268 +#define SYS_ETH_PDCFG_GMAC1_DIS 0x00000000 */
9269 +/** Enable */
9270 +#define SYS_ETH_PDCFG_GMAC1_EN 0x00000002
9271 +/** Enable Power Down GMAC0
9272 +    Ignore this bit as power-gating is not supported for this chip. */
9273 +#define SYS_ETH_PDCFG_GMAC0 0x00000001
9274 +/* Disable
9275 +#define SYS_ETH_PDCFG_GMAC0_DIS 0x00000000 */
9276 +/** Enable */
9277 +#define SYS_ETH_PDCFG_GMAC0_EN 0x00000001
9278 +
9279 +/* Fields of "Datarate Control Register" */
9280 +/** MDC Clockrate
9281 +    Selects the clockrate of the MDIO interface. */
9282 +#define SYS_ETH_DRC_MDC_MASK 0x30000000
9283 +/** field offset */
9284 +#define SYS_ETH_DRC_MDC_OFFSET 28
9285 +/** 312.5/128 = appr. 2.44 MHz. */
9286 +#define SYS_ETH_DRC_MDC_F2M44 0x00000000
9287 +/** 312.5/64 = appr. 4.88 MHz. */
9288 +#define SYS_ETH_DRC_MDC_F4M88 0x10000000
9289 +/** 312.5/32 = appr. 9.77 MHz. */
9290 +#define SYS_ETH_DRC_MDC_F9M77 0x20000000
9291 +/** 312.5/16 = appr. 19.5 MHz. */
9292 +#define SYS_ETH_DRC_MDC_F19M5 0x30000000
9293 +/** xMII1 Datarate
9294 +    Selects the datarate of the xMII1 interface. */
9295 +#define SYS_ETH_DRC_xMII1_MASK 0x07000000
9296 +/** field offset */
9297 +#define SYS_ETH_DRC_xMII1_OFFSET 24
9298 +/** 10 MBit/s. */
9299 +#define SYS_ETH_DRC_xMII1_DR10 0x00000000
9300 +/** 100 MBit/s. */
9301 +#define SYS_ETH_DRC_xMII1_DR100 0x01000000
9302 +/** 1000 MBit/s. */
9303 +#define SYS_ETH_DRC_xMII1_DR1000 0x02000000
9304 +/** 200 MBit/s. */
9305 +#define SYS_ETH_DRC_xMII1_DR200 0x05000000
9306 +/** xMII0 Datarate
9307 +    Selects the datarate of the xMII0 interface. */
9308 +#define SYS_ETH_DRC_xMII0_MASK 0x00700000
9309 +/** field offset */
9310 +#define SYS_ETH_DRC_xMII0_OFFSET 20
9311 +/** 10 MBit/s. */
9312 +#define SYS_ETH_DRC_xMII0_DR10 0x00000000
9313 +/** 100 MBit/s. */
9314 +#define SYS_ETH_DRC_xMII0_DR100 0x00100000
9315 +/** 1000 MBit/s. */
9316 +#define SYS_ETH_DRC_xMII0_DR1000 0x00200000
9317 +/** 200 MBit/s. */
9318 +#define SYS_ETH_DRC_xMII0_DR200 0x00500000
9319 +/** SGMII Datarate
9320 +    Selects the datarate of the SGMII interface. */
9321 +#define SYS_ETH_DRC_SGMII_MASK 0x00070000
9322 +/** field offset */
9323 +#define SYS_ETH_DRC_SGMII_OFFSET 16
9324 +/** 10 MBit/s. */
9325 +#define SYS_ETH_DRC_SGMII_DR10 0x00000000
9326 +/** 100 MBit/s. */
9327 +#define SYS_ETH_DRC_SGMII_DR100 0x00010000
9328 +/** 1000 MBit/s. */
9329 +#define SYS_ETH_DRC_SGMII_DR1000 0x00020000
9330 +/** 2500 MBit/s. */
9331 +#define SYS_ETH_DRC_SGMII_DR2500 0x00040000
9332 +/** GPHY1_MII2 Datarate
9333 +    Shows the datarate of the GPHY1_MII2 interface. */
9334 +#define SYS_ETH_DRC_GPHY1_MII2_MASK 0x00007000
9335 +/** field offset */
9336 +#define SYS_ETH_DRC_GPHY1_MII2_OFFSET 12
9337 +/** 10 MBit/s. */
9338 +#define SYS_ETH_DRC_GPHY1_MII2_DR10 0x00000000
9339 +/** 100 MBit/s. */
9340 +#define SYS_ETH_DRC_GPHY1_MII2_DR100 0x00001000
9341 +/** GPHY1_GMII Datarate
9342 +    Shows the datarate of the GPHY1_GMII interface. */
9343 +#define SYS_ETH_DRC_GPHY1_GMII_MASK 0x00000700
9344 +/** field offset */
9345 +#define SYS_ETH_DRC_GPHY1_GMII_OFFSET 8
9346 +/** 10 MBit/s. */
9347 +#define SYS_ETH_DRC_GPHY1_GMII_DR10 0x00000000
9348 +/** 100 MBit/s. */
9349 +#define SYS_ETH_DRC_GPHY1_GMII_DR100 0x00000100
9350 +/** 1000 MBit/s. */
9351 +#define SYS_ETH_DRC_GPHY1_GMII_DR1000 0x00000200
9352 +/** GPHY0_MII2 Datarate
9353 +    Shows the datarate of the GPHY0_MII2 interface. */
9354 +#define SYS_ETH_DRC_GPHY0_MII2_MASK 0x00000070
9355 +/** field offset */
9356 +#define SYS_ETH_DRC_GPHY0_MII2_OFFSET 4
9357 +/** 10 MBit/s. */
9358 +#define SYS_ETH_DRC_GPHY0_MII2_DR10 0x00000000
9359 +/** 100 MBit/s. */
9360 +#define SYS_ETH_DRC_GPHY0_MII2_DR100 0x00000010
9361 +/** GPHY0_GMII Datarate
9362 +    Shows the datarate of the GPHY0_GMII interface. */
9363 +#define SYS_ETH_DRC_GPHY0_GMII_MASK 0x00000007
9364 +/** field offset */
9365 +#define SYS_ETH_DRC_GPHY0_GMII_OFFSET 0
9366 +/** 10 MBit/s. */
9367 +#define SYS_ETH_DRC_GPHY0_GMII_DR10 0x00000000
9368 +/** 100 MBit/s. */
9369 +#define SYS_ETH_DRC_GPHY0_GMII_DR100 0x00000001
9370 +/** 1000 MBit/s. */
9371 +#define SYS_ETH_DRC_GPHY0_GMII_DR1000 0x00000002
9372 +
9373 +/* Fields of "GMAC Multiplexer Control Register" */
9374 +/** GMAC 3 MUX setting
9375 +    Selects the physical layer to be connected to GMAC3 */
9376 +#define SYS_ETH_GMUXC_GMAC3_MASK 0x00007000
9377 +/** field offset */
9378 +#define SYS_ETH_GMUXC_GMAC3_OFFSET 12
9379 +/** GMAC connects to GPHY0_GMII interface */
9380 +#define SYS_ETH_GMUXC_GMAC3_GPHY0_GMII 0x00000000
9381 +/** GMAC connects to GPHY0_MII2 interface */
9382 +#define SYS_ETH_GMUXC_GMAC3_GPHY0_MII2 0x00001000
9383 +/** GMAC connects to GPHY1_GMII interface */
9384 +#define SYS_ETH_GMUXC_GMAC3_GPHY1_GMII 0x00002000
9385 +/** GMAC connects to GPHY1_MII2 interface */
9386 +#define SYS_ETH_GMUXC_GMAC3_GPHY1_MII2 0x00003000
9387 +/** GMAC connects to SGMII interface */
9388 +#define SYS_ETH_GMUXC_GMAC3_SGMII 0x00004000
9389 +/** GMAC connects to xMII0 interface */
9390 +#define SYS_ETH_GMUXC_GMAC3_xMII0 0x00005000
9391 +/** GMAC connects to xMII1 interface */
9392 +#define SYS_ETH_GMUXC_GMAC3_xMII1 0x00006000
9393 +/** GMAC 2 MUX setting
9394 +    Selects the physical layer to be connected to GMAC2 */
9395 +#define SYS_ETH_GMUXC_GMAC2_MASK 0x00000700
9396 +/** field offset */
9397 +#define SYS_ETH_GMUXC_GMAC2_OFFSET 8
9398 +/** GMAC connects to GPHY0_GMII interface */
9399 +#define SYS_ETH_GMUXC_GMAC2_GPHY0_GMII 0x00000000
9400 +/** GMAC connects to GPHY0_MII2 interface */
9401 +#define SYS_ETH_GMUXC_GMAC2_GPHY0_MII2 0x00000100
9402 +/** GMAC connects to GPHY1_GMII interface */
9403 +#define SYS_ETH_GMUXC_GMAC2_GPHY1_GMII 0x00000200
9404 +/** GMAC connects to GPHY1_MII2 interface */
9405 +#define SYS_ETH_GMUXC_GMAC2_GPHY1_MII2 0x00000300
9406 +/** GMAC connects to SGMII interface */
9407 +#define SYS_ETH_GMUXC_GMAC2_SGMII 0x00000400
9408 +/** GMAC connects to xMII0 interface */
9409 +#define SYS_ETH_GMUXC_GMAC2_xMII0 0x00000500
9410 +/** GMAC connects to xMII1 interface */
9411 +#define SYS_ETH_GMUXC_GMAC2_xMII1 0x00000600
9412 +/** GMAC 1 MUX setting
9413 +    Selects the physical layer to be connected to GMAC1 */
9414 +#define SYS_ETH_GMUXC_GMAC1_MASK 0x00000070
9415 +/** field offset */
9416 +#define SYS_ETH_GMUXC_GMAC1_OFFSET 4
9417 +/** GMAC connects to GPHY0_GMII interface */
9418 +#define SYS_ETH_GMUXC_GMAC1_GPHY0_GMII 0x00000000
9419 +/** GMAC connects to GPHY0_MII2 interface */
9420 +#define SYS_ETH_GMUXC_GMAC1_GPHY0_MII2 0x00000010
9421 +/** GMAC connects to GPHY1_GMII interface */
9422 +#define SYS_ETH_GMUXC_GMAC1_GPHY1_GMII 0x00000020
9423 +/** GMAC connects to GPHY1_MII2 interface */
9424 +#define SYS_ETH_GMUXC_GMAC1_GPHY1_MII2 0x00000030
9425 +/** GMAC connects to SGMII interface */
9426 +#define SYS_ETH_GMUXC_GMAC1_SGMII 0x00000040
9427 +/** GMAC connects to xMII0 interface */
9428 +#define SYS_ETH_GMUXC_GMAC1_xMII0 0x00000050
9429 +/** GMAC connects to xMII1 interface */
9430 +#define SYS_ETH_GMUXC_GMAC1_xMII1 0x00000060
9431 +/** GMAC 0 MUX setting
9432 +    Selects the physical layer to be connected to GMAC0 */
9433 +#define SYS_ETH_GMUXC_GMAC0_MASK 0x00000007
9434 +/** field offset */
9435 +#define SYS_ETH_GMUXC_GMAC0_OFFSET 0
9436 +/** GMAC connects to GPHY0_GMII interface */
9437 +#define SYS_ETH_GMUXC_GMAC0_GPHY0_GMII 0x00000000
9438 +/** GMAC connects to GPHY0_MII2 interface */
9439 +#define SYS_ETH_GMUXC_GMAC0_GPHY0_MII2 0x00000001
9440 +/** GMAC connects to GPHY1_GMII interface */
9441 +#define SYS_ETH_GMUXC_GMAC0_GPHY1_GMII 0x00000002
9442 +/** GMAC connects to GPHY1_MII2 interface */
9443 +#define SYS_ETH_GMUXC_GMAC0_GPHY1_MII2 0x00000003
9444 +/** GMAC connects to SGMII interface */
9445 +#define SYS_ETH_GMUXC_GMAC0_SGMII 0x00000004
9446 +/** GMAC connects to xMII0 interface */
9447 +#define SYS_ETH_GMUXC_GMAC0_xMII0 0x00000005
9448 +/** GMAC connects to xMII1 interface */
9449 +#define SYS_ETH_GMUXC_GMAC0_xMII1 0x00000006
9450 +
9451 +/* Fields of "Datarate Status Register" */
9452 +/** GMAC 3 datarate
9453 +    Shows the datarate of GMAC3 */
9454 +#define SYS_ETH_DRS_GMAC3_MASK 0x00007000
9455 +/** field offset */
9456 +#define SYS_ETH_DRS_GMAC3_OFFSET 12
9457 +/** 10 MBit/s. */
9458 +#define SYS_ETH_DRS_GMAC3_DR10 0x00000000
9459 +/** 100 MBit/s. */
9460 +#define SYS_ETH_DRS_GMAC3_DR100 0x00001000
9461 +/** 1000 MBit/s. */
9462 +#define SYS_ETH_DRS_GMAC3_DR1000 0x00002000
9463 +/** 2500 MBit/s. */
9464 +#define SYS_ETH_DRS_GMAC3_DR2500 0x00004000
9465 +/** 200 MBit/s. */
9466 +#define SYS_ETH_DRS_GMAC3_DR200 0x00005000
9467 +/** GMAC 2 datarate
9468 +    Shows the datarate of GMAC2 */
9469 +#define SYS_ETH_DRS_GMAC2_MASK 0x00000700
9470 +/** field offset */
9471 +#define SYS_ETH_DRS_GMAC2_OFFSET 8
9472 +/** 10 MBit/s. */
9473 +#define SYS_ETH_DRS_GMAC2_DR10 0x00000000
9474 +/** 100 MBit/s. */
9475 +#define SYS_ETH_DRS_GMAC2_DR100 0x00000100
9476 +/** 1000 MBit/s. */
9477 +#define SYS_ETH_DRS_GMAC2_DR1000 0x00000200
9478 +/** 2500 MBit/s. */
9479 +#define SYS_ETH_DRS_GMAC2_DR2500 0x00000400
9480 +/** 200 MBit/s. */
9481 +#define SYS_ETH_DRS_GMAC2_DR200 0x00000500
9482 +/** GMAC 1 datarate
9483 +    Shows the datarate of GMAC1 */
9484 +#define SYS_ETH_DRS_GMAC1_MASK 0x00000070
9485 +/** field offset */
9486 +#define SYS_ETH_DRS_GMAC1_OFFSET 4
9487 +/** 10 MBit/s. */
9488 +#define SYS_ETH_DRS_GMAC1_DR10 0x00000000
9489 +/** 100 MBit/s. */
9490 +#define SYS_ETH_DRS_GMAC1_DR100 0x00000010
9491 +/** 1000 MBit/s. */
9492 +#define SYS_ETH_DRS_GMAC1_DR1000 0x00000020
9493 +/** 2500 MBit/s. */
9494 +#define SYS_ETH_DRS_GMAC1_DR2500 0x00000040
9495 +/** 200 MBit/s. */
9496 +#define SYS_ETH_DRS_GMAC1_DR200 0x00000050
9497 +/** GMAC 0 datarate
9498 +    Shows the datarate of GMAC0 */
9499 +#define SYS_ETH_DRS_GMAC0_MASK 0x00000007
9500 +/** field offset */
9501 +#define SYS_ETH_DRS_GMAC0_OFFSET 0
9502 +/** 10 MBit/s. */
9503 +#define SYS_ETH_DRS_GMAC0_DR10 0x00000000
9504 +/** 100 MBit/s. */
9505 +#define SYS_ETH_DRS_GMAC0_DR100 0x00000001
9506 +/** 1000 MBit/s. */
9507 +#define SYS_ETH_DRS_GMAC0_DR1000 0x00000002
9508 +/** 2500 MBit/s. */
9509 +#define SYS_ETH_DRS_GMAC0_DR2500 0x00000004
9510 +/** 200 MBit/s. */
9511 +#define SYS_ETH_DRS_GMAC0_DR200 0x00000005
9512 +
9513 +/* Fields of "SGMII Control Register" */
9514 +/** Auto Negotiation Protocol
9515 +    Selects the TBX/SGMII mode for the autonegotiation of the SGMII interface. */
9516 +#define SYS_ETH_SGMIIC_ANP 0x00000002
9517 +/* TBX Mode (IEEE 802.3 Clause 37 ANEG)
9518 +#define SYS_ETH_SGMIIC_ANP_TBXM 0x00000000 */
9519 +/** SGMII Mode (Cisco Aneg) */
9520 +#define SYS_ETH_SGMIIC_ANP_SGMIIM 0x00000002
9521 +/** Auto Negotiation MAC/PHY
9522 +    Selects the MAC/PHY mode for the autonegotiation of the SGMII interface. */
9523 +#define SYS_ETH_SGMIIC_ANMP 0x00000001
9524 +/* MAC Mode
9525 +#define SYS_ETH_SGMIIC_ANMP_MAC 0x00000000 */
9526 +/** PHY Mode */
9527 +#define SYS_ETH_SGMIIC_ANMP_PHY 0x00000001
9528 +
9529 +/*! @} */ /* SYS_ETH_REGISTER */
9530 +
9531 +#endif /* _sys_eth_reg_h */
9532 --- /dev/null
9533 +++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h
9534 @@ -0,0 +1,2829 @@
9535 +/******************************************************************************
9536 +
9537 +                               Copyright (c) 2010
9538 +                            Lantiq Deutschland GmbH
9539 +
9540 +  For licensing information, see the file 'LICENSE' in the root folder of
9541 +  this software module.
9542 +
9543 +******************************************************************************/
9544 +
9545 +#ifndef _sys_gpe_reg_h
9546 +#define _sys_gpe_reg_h
9547 +
9548 +/** \addtogroup SYS_GPE_REGISTER
9549 +   @{
9550 +*/
9551 +/* access macros */
9552 +#define sys_gpe_r32(reg) reg_r32(&sys_gpe->reg)
9553 +#define sys_gpe_w32(val, reg) reg_w32(val, &sys_gpe->reg)
9554 +#define sys_gpe_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_gpe->reg)
9555 +#define sys_gpe_r32_table(reg, idx) reg_r32_table(sys_gpe->reg, idx)
9556 +#define sys_gpe_w32_table(val, reg, idx) reg_w32_table(val, sys_gpe->reg, idx)
9557 +#define sys_gpe_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_gpe->reg, idx)
9558 +#define sys_gpe_adr_table(reg, idx) adr_table(sys_gpe->reg, idx)
9559 +
9560 +
9561 +/** SYS_GPE register structure */
9562 +struct gpon_reg_sys_gpe
9563 +{
9564 +   /** Clock Status Register
9565 +       The clock status reflects the actual clocking mode as a function of the SW settings and the hardware sleep mode. */
9566 +   unsigned int clks; /* 0x00000000 */
9567 +   /** Clock Enable Register
9568 +       Via this register the clocks for the domains can be enabled. */
9569 +   unsigned int clken; /* 0x00000004 */
9570 +   /** Clock Clear Register
9571 +       Via this register the clocks for the domains can be disabled. */
9572 +   unsigned int clkclr; /* 0x00000008 */
9573 +   /** Reserved */
9574 +   unsigned int res_0[5]; /* 0x0000000C */
9575 +   /** Activation Status Register */
9576 +   unsigned int acts; /* 0x00000020 */
9577 +   /** Activation Register
9578 +       Via this register the domains can be activated. */
9579 +   unsigned int act; /* 0x00000024 */
9580 +   /** Deactivation Register
9581 +       Via this register the domains can be deactivated. */
9582 +   unsigned int deact; /* 0x00000028 */
9583 +   /** Reboot Trigger Register
9584 +       Via this register the domains can be rebooted (sent through reset). */
9585 +   unsigned int rbt; /* 0x0000002C */
9586 +   /** Reserved */
9587 +   unsigned int res_1[33]; /* 0x00000030 */
9588 +   /** Power Down Configuration Register
9589 +       Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */
9590 +   unsigned int pdcfg; /* 0x000000B4 */
9591 +   /** Sleep Source Configuration Register
9592 +       All sleep/wakeup conditions selected in this register contribute to the generation of the hardware sleep/wakeup request. Unselected conditions are ignored for sleep and wakeup. If no bit is selected, HW sleep is disabled. */
9593 +   unsigned int sscfg; /* 0x000000B8 */
9594 +   /** Sleep Source Timer Register */
9595 +   unsigned int sst; /* 0x000000BC */
9596 +   /** Sleep Destination Status Register
9597 +       Shows the status of the sleep destination vector. All clock domains selected in this register will be shutoff in case of a hardware sleep request. These clocks will be automatically reenabled in case of a hardware wakeup request. */
9598 +   unsigned int sds; /* 0x000000C0 */
9599 +   /** Sleep Destination Set Register
9600 +       Via this register the the domains to be shutoff in case of a hardware sleep request can be selected. */
9601 +   unsigned int sdset; /* 0x000000C4 */
9602 +   /** Sleep Destination Clear Register
9603 +       Via this register the the domains to be shutoff in case of a hardware sleep request can be deselected. */
9604 +   unsigned int sdclr; /* 0x000000C8 */
9605 +   /** Reserved */
9606 +   unsigned int res_2[9]; /* 0x000000CC */
9607 +   /** IRNCS Capture Register
9608 +       This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNCSEN register. The interrupts can be acknowledged by a write operation. */
9609 +   unsigned int irncscr; /* 0x000000F0 */
9610 +   /** IRNCS Interrupt Control Register
9611 +       A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
9612 +   unsigned int irncsicr; /* 0x000000F4 */
9613 +   /** IRNCS Interrupt Enable Register
9614 +       This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCSCR register and are not signalled via the interrupt line towards the controller. */
9615 +   unsigned int irncsen; /* 0x000000F8 */
9616 +   /** Reserved */
9617 +   unsigned int res_3; /* 0x000000FC */
9618 +};
9619 +
9620 +
9621 +/* Fields of "Clock Status Register" */
9622 +/** COP7 Clock Enable
9623 +    Shows the clock enable bit for the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
9624 +#define SYS_GPE_CLKS_COP7 0x80000000
9625 +/* Disable
9626 +#define SYS_GPE_CLKS_COP7_DIS 0x00000000 */
9627 +/** Enable */
9628 +#define SYS_GPE_CLKS_COP7_EN 0x80000000
9629 +/** COP6 Clock Enable
9630 +    Shows the clock enable bit for the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
9631 +#define SYS_GPE_CLKS_COP6 0x40000000
9632 +/* Disable
9633 +#define SYS_GPE_CLKS_COP6_DIS 0x00000000 */
9634 +/** Enable */
9635 +#define SYS_GPE_CLKS_COP6_EN 0x40000000
9636 +/** COP5 Clock Enable
9637 +    Shows the clock enable bit for the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
9638 +#define SYS_GPE_CLKS_COP5 0x20000000
9639 +/* Disable
9640 +#define SYS_GPE_CLKS_COP5_DIS 0x00000000 */
9641 +/** Enable */
9642 +#define SYS_GPE_CLKS_COP5_EN 0x20000000
9643 +/** COP4 Clock Enable
9644 +    Shows the clock enable bit for the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
9645 +#define SYS_GPE_CLKS_COP4 0x10000000
9646 +/* Disable
9647 +#define SYS_GPE_CLKS_COP4_DIS 0x00000000 */
9648 +/** Enable */
9649 +#define SYS_GPE_CLKS_COP4_EN 0x10000000
9650 +/** COP3 Clock Enable
9651 +    Shows the clock enable bit for the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
9652 +#define SYS_GPE_CLKS_COP3 0x08000000
9653 +/* Disable
9654 +#define SYS_GPE_CLKS_COP3_DIS 0x00000000 */
9655 +/** Enable */
9656 +#define SYS_GPE_CLKS_COP3_EN 0x08000000
9657 +/** COP2 Clock Enable
9658 +    Shows the clock enable bit for the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
9659 +#define SYS_GPE_CLKS_COP2 0x04000000
9660 +/* Disable
9661 +#define SYS_GPE_CLKS_COP2_DIS 0x00000000 */
9662 +/** Enable */
9663 +#define SYS_GPE_CLKS_COP2_EN 0x04000000
9664 +/** COP1 Clock Enable
9665 +    Shows the clock enable bit for the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
9666 +#define SYS_GPE_CLKS_COP1 0x02000000
9667 +/* Disable
9668 +#define SYS_GPE_CLKS_COP1_DIS 0x00000000 */
9669 +/** Enable */
9670 +#define SYS_GPE_CLKS_COP1_EN 0x02000000
9671 +/** COP0 Clock Enable
9672 +    Shows the clock enable bit for the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
9673 +#define SYS_GPE_CLKS_COP0 0x01000000
9674 +/* Disable
9675 +#define SYS_GPE_CLKS_COP0_DIS 0x00000000 */
9676 +/** Enable */
9677 +#define SYS_GPE_CLKS_COP0_EN 0x01000000
9678 +/** PE5 Clock Enable
9679 +    Shows the clock enable bit for the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
9680 +#define SYS_GPE_CLKS_PE5 0x00200000
9681 +/* Disable
9682 +#define SYS_GPE_CLKS_PE5_DIS 0x00000000 */
9683 +/** Enable */
9684 +#define SYS_GPE_CLKS_PE5_EN 0x00200000
9685 +/** PE4 Clock Enable
9686 +    Shows the clock enable bit for the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
9687 +#define SYS_GPE_CLKS_PE4 0x00100000
9688 +/* Disable
9689 +#define SYS_GPE_CLKS_PE4_DIS 0x00000000 */
9690 +/** Enable */
9691 +#define SYS_GPE_CLKS_PE4_EN 0x00100000
9692 +/** PE3 Clock Enable
9693 +    Shows the clock enable bit for the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
9694 +#define SYS_GPE_CLKS_PE3 0x00080000
9695 +/* Disable
9696 +#define SYS_GPE_CLKS_PE3_DIS 0x00000000 */
9697 +/** Enable */
9698 +#define SYS_GPE_CLKS_PE3_EN 0x00080000
9699 +/** PE2 Clock Enable
9700 +    Shows the clock enable bit for the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
9701 +#define SYS_GPE_CLKS_PE2 0x00040000
9702 +/* Disable
9703 +#define SYS_GPE_CLKS_PE2_DIS 0x00000000 */
9704 +/** Enable */
9705 +#define SYS_GPE_CLKS_PE2_EN 0x00040000
9706 +/** PE1 Clock Enable
9707 +    Shows the clock enable bit for the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
9708 +#define SYS_GPE_CLKS_PE1 0x00020000
9709 +/* Disable
9710 +#define SYS_GPE_CLKS_PE1_DIS 0x00000000 */
9711 +/** Enable */
9712 +#define SYS_GPE_CLKS_PE1_EN 0x00020000
9713 +/** PE0 Clock Enable
9714 +    Shows the clock enable bit for the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
9715 +#define SYS_GPE_CLKS_PE0 0x00010000
9716 +/* Disable
9717 +#define SYS_GPE_CLKS_PE0_DIS 0x00000000 */
9718 +/** Enable */
9719 +#define SYS_GPE_CLKS_PE0_EN 0x00010000
9720 +/** ARB Clock Enable
9721 +    Shows the clock enable bit for the ARB domain. This domain contains the Arbiter. */
9722 +#define SYS_GPE_CLKS_ARB 0x00002000
9723 +/* Disable
9724 +#define SYS_GPE_CLKS_ARB_DIS 0x00000000 */
9725 +/** Enable */
9726 +#define SYS_GPE_CLKS_ARB_EN 0x00002000
9727 +/** FSQM Clock Enable
9728 +    Shows the clock enable bit for the FSQM domain. This domain contains the FSQM. */
9729 +#define SYS_GPE_CLKS_FSQM 0x00001000
9730 +/* Disable
9731 +#define SYS_GPE_CLKS_FSQM_DIS 0x00000000 */
9732 +/** Enable */
9733 +#define SYS_GPE_CLKS_FSQM_EN 0x00001000
9734 +/** TMU Clock Enable
9735 +    Shows the clock enable bit for the TMU domain. This domain contains the TMU. */
9736 +#define SYS_GPE_CLKS_TMU 0x00000800
9737 +/* Disable
9738 +#define SYS_GPE_CLKS_TMU_DIS 0x00000000 */
9739 +/** Enable */
9740 +#define SYS_GPE_CLKS_TMU_EN 0x00000800
9741 +/** MRG Clock Enable
9742 +    Shows the clock enable bit for the MRG domain. This domain contains the Merger. */
9743 +#define SYS_GPE_CLKS_MRG 0x00000400
9744 +/* Disable
9745 +#define SYS_GPE_CLKS_MRG_DIS 0x00000000 */
9746 +/** Enable */
9747 +#define SYS_GPE_CLKS_MRG_EN 0x00000400
9748 +/** DISP Clock Enable
9749 +    Shows the clock enable bit for the DISP domain. This domain contains the Dispatcher. */
9750 +#define SYS_GPE_CLKS_DISP 0x00000200
9751 +/* Disable
9752 +#define SYS_GPE_CLKS_DISP_DIS 0x00000000 */
9753 +/** Enable */
9754 +#define SYS_GPE_CLKS_DISP_EN 0x00000200
9755 +/** IQM Clock Enable
9756 +    Shows the clock enable bit for the IQM domain. This domain contains the IQM. */
9757 +#define SYS_GPE_CLKS_IQM 0x00000100
9758 +/* Disable
9759 +#define SYS_GPE_CLKS_IQM_DIS 0x00000000 */
9760 +/** Enable */
9761 +#define SYS_GPE_CLKS_IQM_EN 0x00000100
9762 +/** CPUE Clock Enable
9763 +    Shows the clock enable bit for the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
9764 +#define SYS_GPE_CLKS_CPUE 0x00000080
9765 +/* Disable
9766 +#define SYS_GPE_CLKS_CPUE_DIS 0x00000000 */
9767 +/** Enable */
9768 +#define SYS_GPE_CLKS_CPUE_EN 0x00000080
9769 +/** CPUI Clock Enable
9770 +    Shows the clock enable bit for the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
9771 +#define SYS_GPE_CLKS_CPUI 0x00000040
9772 +/* Disable
9773 +#define SYS_GPE_CLKS_CPUI_DIS 0x00000000 */
9774 +/** Enable */
9775 +#define SYS_GPE_CLKS_CPUI_EN 0x00000040
9776 +/** GPONE Clock Enable
9777 +    Shows the clock enable bit for the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
9778 +#define SYS_GPE_CLKS_GPONE 0x00000020
9779 +/* Disable
9780 +#define SYS_GPE_CLKS_GPONE_DIS 0x00000000 */
9781 +/** Enable */
9782 +#define SYS_GPE_CLKS_GPONE_EN 0x00000020
9783 +/** GPONI Clock Enable
9784 +    Shows the clock enable bit for the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
9785 +#define SYS_GPE_CLKS_GPONI 0x00000010
9786 +/* Disable
9787 +#define SYS_GPE_CLKS_GPONI_DIS 0x00000000 */
9788 +/** Enable */
9789 +#define SYS_GPE_CLKS_GPONI_EN 0x00000010
9790 +/** LAN3 Clock Enable
9791 +    Shows the clock enable bit for the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
9792 +#define SYS_GPE_CLKS_LAN3 0x00000008
9793 +/* Disable
9794 +#define SYS_GPE_CLKS_LAN3_DIS 0x00000000 */
9795 +/** Enable */
9796 +#define SYS_GPE_CLKS_LAN3_EN 0x00000008
9797 +/** LAN2 Clock Enable
9798 +    Shows the clock enable bit for the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
9799 +#define SYS_GPE_CLKS_LAN2 0x00000004
9800 +/* Disable
9801 +#define SYS_GPE_CLKS_LAN2_DIS 0x00000000 */
9802 +/** Enable */
9803 +#define SYS_GPE_CLKS_LAN2_EN 0x00000004
9804 +/** LAN1 Clock Enable
9805 +    Shows the clock enable bit for the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
9806 +#define SYS_GPE_CLKS_LAN1 0x00000002
9807 +/* Disable
9808 +#define SYS_GPE_CLKS_LAN1_DIS 0x00000000 */
9809 +/** Enable */
9810 +#define SYS_GPE_CLKS_LAN1_EN 0x00000002
9811 +/** LAN0 Clock Enable
9812 +    Shows the clock enable bit for the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
9813 +#define SYS_GPE_CLKS_LAN0 0x00000001
9814 +/* Disable
9815 +#define SYS_GPE_CLKS_LAN0_DIS 0x00000000 */
9816 +/** Enable */
9817 +#define SYS_GPE_CLKS_LAN0_EN 0x00000001
9818 +
9819 +/* Fields of "Clock Enable Register" */
9820 +/** Set Clock Enable COP7
9821 +    Sets the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
9822 +#define SYS_GPE_CLKEN_COP7 0x80000000
9823 +/* No-Operation
9824 +#define SYS_GPE_CLKEN_COP7_NOP 0x00000000 */
9825 +/** Set */
9826 +#define SYS_GPE_CLKEN_COP7_SET 0x80000000
9827 +/** Set Clock Enable COP6
9828 +    Sets the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
9829 +#define SYS_GPE_CLKEN_COP6 0x40000000
9830 +/* No-Operation
9831 +#define SYS_GPE_CLKEN_COP6_NOP 0x00000000 */
9832 +/** Set */
9833 +#define SYS_GPE_CLKEN_COP6_SET 0x40000000
9834 +/** Set Clock Enable COP5
9835 +    Sets the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
9836 +#define SYS_GPE_CLKEN_COP5 0x20000000
9837 +/* No-Operation
9838 +#define SYS_GPE_CLKEN_COP5_NOP 0x00000000 */
9839 +/** Set */
9840 +#define SYS_GPE_CLKEN_COP5_SET 0x20000000
9841 +/** Set Clock Enable COP4
9842 +    Sets the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
9843 +#define SYS_GPE_CLKEN_COP4 0x10000000
9844 +/* No-Operation
9845 +#define SYS_GPE_CLKEN_COP4_NOP 0x00000000 */
9846 +/** Set */
9847 +#define SYS_GPE_CLKEN_COP4_SET 0x10000000
9848 +/** Set Clock Enable COP3
9849 +    Sets the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
9850 +#define SYS_GPE_CLKEN_COP3 0x08000000
9851 +/* No-Operation
9852 +#define SYS_GPE_CLKEN_COP3_NOP 0x00000000 */
9853 +/** Set */
9854 +#define SYS_GPE_CLKEN_COP3_SET 0x08000000
9855 +/** Set Clock Enable COP2
9856 +    Sets the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
9857 +#define SYS_GPE_CLKEN_COP2 0x04000000
9858 +/* No-Operation
9859 +#define SYS_GPE_CLKEN_COP2_NOP 0x00000000 */
9860 +/** Set */
9861 +#define SYS_GPE_CLKEN_COP2_SET 0x04000000
9862 +/** Set Clock Enable COP1
9863 +    Sets the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
9864 +#define SYS_GPE_CLKEN_COP1 0x02000000
9865 +/* No-Operation
9866 +#define SYS_GPE_CLKEN_COP1_NOP 0x00000000 */
9867 +/** Set */
9868 +#define SYS_GPE_CLKEN_COP1_SET 0x02000000
9869 +/** Set Clock Enable COP0
9870 +    Sets the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
9871 +#define SYS_GPE_CLKEN_COP0 0x01000000
9872 +/* No-Operation
9873 +#define SYS_GPE_CLKEN_COP0_NOP 0x00000000 */
9874 +/** Set */
9875 +#define SYS_GPE_CLKEN_COP0_SET 0x01000000
9876 +/** Set Clock Enable PE5
9877 +    Sets the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
9878 +#define SYS_GPE_CLKEN_PE5 0x00200000
9879 +/* No-Operation
9880 +#define SYS_GPE_CLKEN_PE5_NOP 0x00000000 */
9881 +/** Set */
9882 +#define SYS_GPE_CLKEN_PE5_SET 0x00200000
9883 +/** Set Clock Enable PE4
9884 +    Sets the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
9885 +#define SYS_GPE_CLKEN_PE4 0x00100000
9886 +/* No-Operation
9887 +#define SYS_GPE_CLKEN_PE4_NOP 0x00000000 */
9888 +/** Set */
9889 +#define SYS_GPE_CLKEN_PE4_SET 0x00100000
9890 +/** Set Clock Enable PE3
9891 +    Sets the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
9892 +#define SYS_GPE_CLKEN_PE3 0x00080000
9893 +/* No-Operation
9894 +#define SYS_GPE_CLKEN_PE3_NOP 0x00000000 */
9895 +/** Set */
9896 +#define SYS_GPE_CLKEN_PE3_SET 0x00080000
9897 +/** Set Clock Enable PE2
9898 +    Sets the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
9899 +#define SYS_GPE_CLKEN_PE2 0x00040000
9900 +/* No-Operation
9901 +#define SYS_GPE_CLKEN_PE2_NOP 0x00000000 */
9902 +/** Set */
9903 +#define SYS_GPE_CLKEN_PE2_SET 0x00040000
9904 +/** Set Clock Enable PE1
9905 +    Sets the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
9906 +#define SYS_GPE_CLKEN_PE1 0x00020000
9907 +/* No-Operation
9908 +#define SYS_GPE_CLKEN_PE1_NOP 0x00000000 */
9909 +/** Set */
9910 +#define SYS_GPE_CLKEN_PE1_SET 0x00020000
9911 +/** Set Clock Enable PE0
9912 +    Sets the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
9913 +#define SYS_GPE_CLKEN_PE0 0x00010000
9914 +/* No-Operation
9915 +#define SYS_GPE_CLKEN_PE0_NOP 0x00000000 */
9916 +/** Set */
9917 +#define SYS_GPE_CLKEN_PE0_SET 0x00010000
9918 +/** Set Clock Enable ARB
9919 +    Sets the clock enable bit of the ARB domain. This domain contains the Arbiter. */
9920 +#define SYS_GPE_CLKEN_ARB 0x00002000
9921 +/* No-Operation
9922 +#define SYS_GPE_CLKEN_ARB_NOP 0x00000000 */
9923 +/** Set */
9924 +#define SYS_GPE_CLKEN_ARB_SET 0x00002000
9925 +/** Set Clock Enable FSQM
9926 +    Sets the clock enable bit of the FSQM domain. This domain contains the FSQM. */
9927 +#define SYS_GPE_CLKEN_FSQM 0x00001000
9928 +/* No-Operation
9929 +#define SYS_GPE_CLKEN_FSQM_NOP 0x00000000 */
9930 +/** Set */
9931 +#define SYS_GPE_CLKEN_FSQM_SET 0x00001000
9932 +/** Set Clock Enable TMU
9933 +    Sets the clock enable bit of the TMU domain. This domain contains the TMU. */
9934 +#define SYS_GPE_CLKEN_TMU 0x00000800
9935 +/* No-Operation
9936 +#define SYS_GPE_CLKEN_TMU_NOP 0x00000000 */
9937 +/** Set */
9938 +#define SYS_GPE_CLKEN_TMU_SET 0x00000800
9939 +/** Set Clock Enable MRG
9940 +    Sets the clock enable bit of the MRG domain. This domain contains the Merger. */
9941 +#define SYS_GPE_CLKEN_MRG 0x00000400
9942 +/* No-Operation
9943 +#define SYS_GPE_CLKEN_MRG_NOP 0x00000000 */
9944 +/** Set */
9945 +#define SYS_GPE_CLKEN_MRG_SET 0x00000400
9946 +/** Set Clock Enable DISP
9947 +    Sets the clock enable bit of the DISP domain. This domain contains the Dispatcher. */
9948 +#define SYS_GPE_CLKEN_DISP 0x00000200
9949 +/* No-Operation
9950 +#define SYS_GPE_CLKEN_DISP_NOP 0x00000000 */
9951 +/** Set */
9952 +#define SYS_GPE_CLKEN_DISP_SET 0x00000200
9953 +/** Set Clock Enable IQM
9954 +    Sets the clock enable bit of the IQM domain. This domain contains the IQM. */
9955 +#define SYS_GPE_CLKEN_IQM 0x00000100
9956 +/* No-Operation
9957 +#define SYS_GPE_CLKEN_IQM_NOP 0x00000000 */
9958 +/** Set */
9959 +#define SYS_GPE_CLKEN_IQM_SET 0x00000100
9960 +/** Set Clock Enable CPUE
9961 +    Sets the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
9962 +#define SYS_GPE_CLKEN_CPUE 0x00000080
9963 +/* No-Operation
9964 +#define SYS_GPE_CLKEN_CPUE_NOP 0x00000000 */
9965 +/** Set */
9966 +#define SYS_GPE_CLKEN_CPUE_SET 0x00000080
9967 +/** Set Clock Enable CPUI
9968 +    Sets the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
9969 +#define SYS_GPE_CLKEN_CPUI 0x00000040
9970 +/* No-Operation
9971 +#define SYS_GPE_CLKEN_CPUI_NOP 0x00000000 */
9972 +/** Set */
9973 +#define SYS_GPE_CLKEN_CPUI_SET 0x00000040
9974 +/** Set Clock Enable GPONE
9975 +    Sets the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
9976 +#define SYS_GPE_CLKEN_GPONE 0x00000020
9977 +/* No-Operation
9978 +#define SYS_GPE_CLKEN_GPONE_NOP 0x00000000 */
9979 +/** Set */
9980 +#define SYS_GPE_CLKEN_GPONE_SET 0x00000020
9981 +/** Set Clock Enable GPONI
9982 +    Sets the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
9983 +#define SYS_GPE_CLKEN_GPONI 0x00000010
9984 +/* No-Operation
9985 +#define SYS_GPE_CLKEN_GPONI_NOP 0x00000000 */
9986 +/** Set */
9987 +#define SYS_GPE_CLKEN_GPONI_SET 0x00000010
9988 +/** Set Clock Enable LAN3
9989 +    Sets the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
9990 +#define SYS_GPE_CLKEN_LAN3 0x00000008
9991 +/* No-Operation
9992 +#define SYS_GPE_CLKEN_LAN3_NOP 0x00000000 */
9993 +/** Set */
9994 +#define SYS_GPE_CLKEN_LAN3_SET 0x00000008
9995 +/** Set Clock Enable LAN2
9996 +    Sets the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
9997 +#define SYS_GPE_CLKEN_LAN2 0x00000004
9998 +/* No-Operation
9999 +#define SYS_GPE_CLKEN_LAN2_NOP 0x00000000 */
10000 +/** Set */
10001 +#define SYS_GPE_CLKEN_LAN2_SET 0x00000004
10002 +/** Set Clock Enable LAN1
10003 +    Sets the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10004 +#define SYS_GPE_CLKEN_LAN1 0x00000002
10005 +/* No-Operation
10006 +#define SYS_GPE_CLKEN_LAN1_NOP 0x00000000 */
10007 +/** Set */
10008 +#define SYS_GPE_CLKEN_LAN1_SET 0x00000002
10009 +/** Set Clock Enable LAN0
10010 +    Sets the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10011 +#define SYS_GPE_CLKEN_LAN0 0x00000001
10012 +/* No-Operation
10013 +#define SYS_GPE_CLKEN_LAN0_NOP 0x00000000 */
10014 +/** Set */
10015 +#define SYS_GPE_CLKEN_LAN0_SET 0x00000001
10016 +
10017 +/* Fields of "Clock Clear Register" */
10018 +/** Clear Clock Enable COP7
10019 +    Clears the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
10020 +#define SYS_GPE_CLKCLR_COP7 0x80000000
10021 +/* No-Operation
10022 +#define SYS_GPE_CLKCLR_COP7_NOP 0x00000000 */
10023 +/** Clear */
10024 +#define SYS_GPE_CLKCLR_COP7_CLR 0x80000000
10025 +/** Clear Clock Enable COP6
10026 +    Clears the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
10027 +#define SYS_GPE_CLKCLR_COP6 0x40000000
10028 +/* No-Operation
10029 +#define SYS_GPE_CLKCLR_COP6_NOP 0x00000000 */
10030 +/** Clear */
10031 +#define SYS_GPE_CLKCLR_COP6_CLR 0x40000000
10032 +/** Clear Clock Enable COP5
10033 +    Clears the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
10034 +#define SYS_GPE_CLKCLR_COP5 0x20000000
10035 +/* No-Operation
10036 +#define SYS_GPE_CLKCLR_COP5_NOP 0x00000000 */
10037 +/** Clear */
10038 +#define SYS_GPE_CLKCLR_COP5_CLR 0x20000000
10039 +/** Clear Clock Enable COP4
10040 +    Clears the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
10041 +#define SYS_GPE_CLKCLR_COP4 0x10000000
10042 +/* No-Operation
10043 +#define SYS_GPE_CLKCLR_COP4_NOP 0x00000000 */
10044 +/** Clear */
10045 +#define SYS_GPE_CLKCLR_COP4_CLR 0x10000000
10046 +/** Clear Clock Enable COP3
10047 +    Clears the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
10048 +#define SYS_GPE_CLKCLR_COP3 0x08000000
10049 +/* No-Operation
10050 +#define SYS_GPE_CLKCLR_COP3_NOP 0x00000000 */
10051 +/** Clear */
10052 +#define SYS_GPE_CLKCLR_COP3_CLR 0x08000000
10053 +/** Clear Clock Enable COP2
10054 +    Clears the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
10055 +#define SYS_GPE_CLKCLR_COP2 0x04000000
10056 +/* No-Operation
10057 +#define SYS_GPE_CLKCLR_COP2_NOP 0x00000000 */
10058 +/** Clear */
10059 +#define SYS_GPE_CLKCLR_COP2_CLR 0x04000000
10060 +/** Clear Clock Enable COP1
10061 +    Clears the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
10062 +#define SYS_GPE_CLKCLR_COP1 0x02000000
10063 +/* No-Operation
10064 +#define SYS_GPE_CLKCLR_COP1_NOP 0x00000000 */
10065 +/** Clear */
10066 +#define SYS_GPE_CLKCLR_COP1_CLR 0x02000000
10067 +/** Clear Clock Enable COP0
10068 +    Clears the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
10069 +#define SYS_GPE_CLKCLR_COP0 0x01000000
10070 +/* No-Operation
10071 +#define SYS_GPE_CLKCLR_COP0_NOP 0x00000000 */
10072 +/** Clear */
10073 +#define SYS_GPE_CLKCLR_COP0_CLR 0x01000000
10074 +/** Clear Clock Enable PE5
10075 +    Clears the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
10076 +#define SYS_GPE_CLKCLR_PE5 0x00200000
10077 +/* No-Operation
10078 +#define SYS_GPE_CLKCLR_PE5_NOP 0x00000000 */
10079 +/** Clear */
10080 +#define SYS_GPE_CLKCLR_PE5_CLR 0x00200000
10081 +/** Clear Clock Enable PE4
10082 +    Clears the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
10083 +#define SYS_GPE_CLKCLR_PE4 0x00100000
10084 +/* No-Operation
10085 +#define SYS_GPE_CLKCLR_PE4_NOP 0x00000000 */
10086 +/** Clear */
10087 +#define SYS_GPE_CLKCLR_PE4_CLR 0x00100000
10088 +/** Clear Clock Enable PE3
10089 +    Clears the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
10090 +#define SYS_GPE_CLKCLR_PE3 0x00080000
10091 +/* No-Operation
10092 +#define SYS_GPE_CLKCLR_PE3_NOP 0x00000000 */
10093 +/** Clear */
10094 +#define SYS_GPE_CLKCLR_PE3_CLR 0x00080000
10095 +/** Clear Clock Enable PE2
10096 +    Clears the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
10097 +#define SYS_GPE_CLKCLR_PE2 0x00040000
10098 +/* No-Operation
10099 +#define SYS_GPE_CLKCLR_PE2_NOP 0x00000000 */
10100 +/** Clear */
10101 +#define SYS_GPE_CLKCLR_PE2_CLR 0x00040000
10102 +/** Clear Clock Enable PE1
10103 +    Clears the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
10104 +#define SYS_GPE_CLKCLR_PE1 0x00020000
10105 +/* No-Operation
10106 +#define SYS_GPE_CLKCLR_PE1_NOP 0x00000000 */
10107 +/** Clear */
10108 +#define SYS_GPE_CLKCLR_PE1_CLR 0x00020000
10109 +/** Clear Clock Enable PE0
10110 +    Clears the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
10111 +#define SYS_GPE_CLKCLR_PE0 0x00010000
10112 +/* No-Operation
10113 +#define SYS_GPE_CLKCLR_PE0_NOP 0x00000000 */
10114 +/** Clear */
10115 +#define SYS_GPE_CLKCLR_PE0_CLR 0x00010000
10116 +/** Clear Clock Enable ARB
10117 +    Clears the clock enable bit of the ARB domain. This domain contains the Arbiter. */
10118 +#define SYS_GPE_CLKCLR_ARB 0x00002000
10119 +/* No-Operation
10120 +#define SYS_GPE_CLKCLR_ARB_NOP 0x00000000 */
10121 +/** Clear */
10122 +#define SYS_GPE_CLKCLR_ARB_CLR 0x00002000
10123 +/** Clear Clock Enable FSQM
10124 +    Clears the clock enable bit of the FSQM domain. This domain contains the FSQM. */
10125 +#define SYS_GPE_CLKCLR_FSQM 0x00001000
10126 +/* No-Operation
10127 +#define SYS_GPE_CLKCLR_FSQM_NOP 0x00000000 */
10128 +/** Clear */
10129 +#define SYS_GPE_CLKCLR_FSQM_CLR 0x00001000
10130 +/** Clear Clock Enable TMU
10131 +    Clears the clock enable bit of the TMU domain. This domain contains the TMU. */
10132 +#define SYS_GPE_CLKCLR_TMU 0x00000800
10133 +/* No-Operation
10134 +#define SYS_GPE_CLKCLR_TMU_NOP 0x00000000 */
10135 +/** Clear */
10136 +#define SYS_GPE_CLKCLR_TMU_CLR 0x00000800
10137 +/** Clear Clock Enable MRG
10138 +    Clears the clock enable bit of the MRG domain. This domain contains the Merger. */
10139 +#define SYS_GPE_CLKCLR_MRG 0x00000400
10140 +/* No-Operation
10141 +#define SYS_GPE_CLKCLR_MRG_NOP 0x00000000 */
10142 +/** Clear */
10143 +#define SYS_GPE_CLKCLR_MRG_CLR 0x00000400
10144 +/** Clear Clock Enable DISP
10145 +    Clears the clock enable bit of the DISP domain. This domain contains the Dispatcher. */
10146 +#define SYS_GPE_CLKCLR_DISP 0x00000200
10147 +/* No-Operation
10148 +#define SYS_GPE_CLKCLR_DISP_NOP 0x00000000 */
10149 +/** Clear */
10150 +#define SYS_GPE_CLKCLR_DISP_CLR 0x00000200
10151 +/** Clear Clock Enable IQM
10152 +    Clears the clock enable bit of the IQM domain. This domain contains the IQM. */
10153 +#define SYS_GPE_CLKCLR_IQM 0x00000100
10154 +/* No-Operation
10155 +#define SYS_GPE_CLKCLR_IQM_NOP 0x00000000 */
10156 +/** Clear */
10157 +#define SYS_GPE_CLKCLR_IQM_CLR 0x00000100
10158 +/** Clear Clock Enable CPUE
10159 +    Clears the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10160 +#define SYS_GPE_CLKCLR_CPUE 0x00000080
10161 +/* No-Operation
10162 +#define SYS_GPE_CLKCLR_CPUE_NOP 0x00000000 */
10163 +/** Clear */
10164 +#define SYS_GPE_CLKCLR_CPUE_CLR 0x00000080
10165 +/** Clear Clock Enable CPUI
10166 +    Clears the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10167 +#define SYS_GPE_CLKCLR_CPUI 0x00000040
10168 +/* No-Operation
10169 +#define SYS_GPE_CLKCLR_CPUI_NOP 0x00000000 */
10170 +/** Clear */
10171 +#define SYS_GPE_CLKCLR_CPUI_CLR 0x00000040
10172 +/** Clear Clock Enable GPONE
10173 +    Clears the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10174 +#define SYS_GPE_CLKCLR_GPONE 0x00000020
10175 +/* No-Operation
10176 +#define SYS_GPE_CLKCLR_GPONE_NOP 0x00000000 */
10177 +/** Clear */
10178 +#define SYS_GPE_CLKCLR_GPONE_CLR 0x00000020
10179 +/** Clear Clock Enable GPONI
10180 +    Clears the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10181 +#define SYS_GPE_CLKCLR_GPONI 0x00000010
10182 +/* No-Operation
10183 +#define SYS_GPE_CLKCLR_GPONI_NOP 0x00000000 */
10184 +/** Clear */
10185 +#define SYS_GPE_CLKCLR_GPONI_CLR 0x00000010
10186 +/** Clear Clock Enable LAN3
10187 +    Clears the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10188 +#define SYS_GPE_CLKCLR_LAN3 0x00000008
10189 +/* No-Operation
10190 +#define SYS_GPE_CLKCLR_LAN3_NOP 0x00000000 */
10191 +/** Clear */
10192 +#define SYS_GPE_CLKCLR_LAN3_CLR 0x00000008
10193 +/** Clear Clock Enable LAN2
10194 +    Clears the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10195 +#define SYS_GPE_CLKCLR_LAN2 0x00000004
10196 +/* No-Operation
10197 +#define SYS_GPE_CLKCLR_LAN2_NOP 0x00000000 */
10198 +/** Clear */
10199 +#define SYS_GPE_CLKCLR_LAN2_CLR 0x00000004
10200 +/** Clear Clock Enable LAN1
10201 +    Clears the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10202 +#define SYS_GPE_CLKCLR_LAN1 0x00000002
10203 +/* No-Operation
10204 +#define SYS_GPE_CLKCLR_LAN1_NOP 0x00000000 */
10205 +/** Clear */
10206 +#define SYS_GPE_CLKCLR_LAN1_CLR 0x00000002
10207 +/** Clear Clock Enable LAN0
10208 +    Clears the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10209 +#define SYS_GPE_CLKCLR_LAN0 0x00000001
10210 +/* No-Operation
10211 +#define SYS_GPE_CLKCLR_LAN0_NOP 0x00000000 */
10212 +/** Clear */
10213 +#define SYS_GPE_CLKCLR_LAN0_CLR 0x00000001
10214 +
10215 +/* Fields of "Activation Status Register" */
10216 +/** COP7 Status
10217 +    Shows the activation status of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
10218 +#define SYS_GPE_ACTS_COP7 0x80000000
10219 +/* The block is inactive.
10220 +#define SYS_GPE_ACTS_COP7_INACT 0x00000000 */
10221 +/** The block is active. */
10222 +#define SYS_GPE_ACTS_COP7_ACT 0x80000000
10223 +/** COP6 Status
10224 +    Shows the activation status of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
10225 +#define SYS_GPE_ACTS_COP6 0x40000000
10226 +/* The block is inactive.
10227 +#define SYS_GPE_ACTS_COP6_INACT 0x00000000 */
10228 +/** The block is active. */
10229 +#define SYS_GPE_ACTS_COP6_ACT 0x40000000
10230 +/** COP5 Status
10231 +    Shows the activation status of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
10232 +#define SYS_GPE_ACTS_COP5 0x20000000
10233 +/* The block is inactive.
10234 +#define SYS_GPE_ACTS_COP5_INACT 0x00000000 */
10235 +/** The block is active. */
10236 +#define SYS_GPE_ACTS_COP5_ACT 0x20000000
10237 +/** COP4 Status
10238 +    Shows the activation status of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
10239 +#define SYS_GPE_ACTS_COP4 0x10000000
10240 +/* The block is inactive.
10241 +#define SYS_GPE_ACTS_COP4_INACT 0x00000000 */
10242 +/** The block is active. */
10243 +#define SYS_GPE_ACTS_COP4_ACT 0x10000000
10244 +/** COP3 Status
10245 +    Shows the activation status of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
10246 +#define SYS_GPE_ACTS_COP3 0x08000000
10247 +/* The block is inactive.
10248 +#define SYS_GPE_ACTS_COP3_INACT 0x00000000 */
10249 +/** The block is active. */
10250 +#define SYS_GPE_ACTS_COP3_ACT 0x08000000
10251 +/** COP2 Status
10252 +    Shows the activation status of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
10253 +#define SYS_GPE_ACTS_COP2 0x04000000
10254 +/* The block is inactive.
10255 +#define SYS_GPE_ACTS_COP2_INACT 0x00000000 */
10256 +/** The block is active. */
10257 +#define SYS_GPE_ACTS_COP2_ACT 0x04000000
10258 +/** COP1 Status
10259 +    Shows the activation status of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
10260 +#define SYS_GPE_ACTS_COP1 0x02000000
10261 +/* The block is inactive.
10262 +#define SYS_GPE_ACTS_COP1_INACT 0x00000000 */
10263 +/** The block is active. */
10264 +#define SYS_GPE_ACTS_COP1_ACT 0x02000000
10265 +/** COP0 Status
10266 +    Shows the activation status of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
10267 +#define SYS_GPE_ACTS_COP0 0x01000000
10268 +/* The block is inactive.
10269 +#define SYS_GPE_ACTS_COP0_INACT 0x00000000 */
10270 +/** The block is active. */
10271 +#define SYS_GPE_ACTS_COP0_ACT 0x01000000
10272 +/** PE5 Status
10273 +    Shows the activation status of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
10274 +#define SYS_GPE_ACTS_PE5 0x00200000
10275 +/* The block is inactive.
10276 +#define SYS_GPE_ACTS_PE5_INACT 0x00000000 */
10277 +/** The block is active. */
10278 +#define SYS_GPE_ACTS_PE5_ACT 0x00200000
10279 +/** PE4 Status
10280 +    Shows the activation status of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
10281 +#define SYS_GPE_ACTS_PE4 0x00100000
10282 +/* The block is inactive.
10283 +#define SYS_GPE_ACTS_PE4_INACT 0x00000000 */
10284 +/** The block is active. */
10285 +#define SYS_GPE_ACTS_PE4_ACT 0x00100000
10286 +/** PE3 Status
10287 +    Shows the activation status of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
10288 +#define SYS_GPE_ACTS_PE3 0x00080000
10289 +/* The block is inactive.
10290 +#define SYS_GPE_ACTS_PE3_INACT 0x00000000 */
10291 +/** The block is active. */
10292 +#define SYS_GPE_ACTS_PE3_ACT 0x00080000
10293 +/** PE2 Status
10294 +    Shows the activation status of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
10295 +#define SYS_GPE_ACTS_PE2 0x00040000
10296 +/* The block is inactive.
10297 +#define SYS_GPE_ACTS_PE2_INACT 0x00000000 */
10298 +/** The block is active. */
10299 +#define SYS_GPE_ACTS_PE2_ACT 0x00040000
10300 +/** PE1 Status
10301 +    Shows the activation status of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
10302 +#define SYS_GPE_ACTS_PE1 0x00020000
10303 +/* The block is inactive.
10304 +#define SYS_GPE_ACTS_PE1_INACT 0x00000000 */
10305 +/** The block is active. */
10306 +#define SYS_GPE_ACTS_PE1_ACT 0x00020000
10307 +/** PE0 Status
10308 +    Shows the activation status of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
10309 +#define SYS_GPE_ACTS_PE0 0x00010000
10310 +/* The block is inactive.
10311 +#define SYS_GPE_ACTS_PE0_INACT 0x00000000 */
10312 +/** The block is active. */
10313 +#define SYS_GPE_ACTS_PE0_ACT 0x00010000
10314 +/** ARB Status
10315 +    Shows the activation status of the ARB domain. This domain contains the Arbiter. */
10316 +#define SYS_GPE_ACTS_ARB 0x00002000
10317 +/* The block is inactive.
10318 +#define SYS_GPE_ACTS_ARB_INACT 0x00000000 */
10319 +/** The block is active. */
10320 +#define SYS_GPE_ACTS_ARB_ACT 0x00002000
10321 +/** FSQM Status
10322 +    Shows the activation status of the FSQM domain. This domain contains the FSQM. */
10323 +#define SYS_GPE_ACTS_FSQM 0x00001000
10324 +/* The block is inactive.
10325 +#define SYS_GPE_ACTS_FSQM_INACT 0x00000000 */
10326 +/** The block is active. */
10327 +#define SYS_GPE_ACTS_FSQM_ACT 0x00001000
10328 +/** TMU Status
10329 +    Shows the activation status of the TMU domain. This domain contains the TMU. */
10330 +#define SYS_GPE_ACTS_TMU 0x00000800
10331 +/* The block is inactive.
10332 +#define SYS_GPE_ACTS_TMU_INACT 0x00000000 */
10333 +/** The block is active. */
10334 +#define SYS_GPE_ACTS_TMU_ACT 0x00000800
10335 +/** MRG Status
10336 +    Shows the activation status of the MRG domain. This domain contains the Merger. */
10337 +#define SYS_GPE_ACTS_MRG 0x00000400
10338 +/* The block is inactive.
10339 +#define SYS_GPE_ACTS_MRG_INACT 0x00000000 */
10340 +/** The block is active. */
10341 +#define SYS_GPE_ACTS_MRG_ACT 0x00000400
10342 +/** DISP Status
10343 +    Shows the activation status of the DISP domain. This domain contains the Dispatcher. */
10344 +#define SYS_GPE_ACTS_DISP 0x00000200
10345 +/* The block is inactive.
10346 +#define SYS_GPE_ACTS_DISP_INACT 0x00000000 */
10347 +/** The block is active. */
10348 +#define SYS_GPE_ACTS_DISP_ACT 0x00000200
10349 +/** IQM Status
10350 +    Shows the activation status of the IQM domain. This domain contains the IQM. */
10351 +#define SYS_GPE_ACTS_IQM 0x00000100
10352 +/* The block is inactive.
10353 +#define SYS_GPE_ACTS_IQM_INACT 0x00000000 */
10354 +/** The block is active. */
10355 +#define SYS_GPE_ACTS_IQM_ACT 0x00000100
10356 +/** CPUE Status
10357 +    Shows the activation status of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10358 +#define SYS_GPE_ACTS_CPUE 0x00000080
10359 +/* The block is inactive.
10360 +#define SYS_GPE_ACTS_CPUE_INACT 0x00000000 */
10361 +/** The block is active. */
10362 +#define SYS_GPE_ACTS_CPUE_ACT 0x00000080
10363 +/** CPUI Status
10364 +    Shows the activation status of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10365 +#define SYS_GPE_ACTS_CPUI 0x00000040
10366 +/* The block is inactive.
10367 +#define SYS_GPE_ACTS_CPUI_INACT 0x00000000 */
10368 +/** The block is active. */
10369 +#define SYS_GPE_ACTS_CPUI_ACT 0x00000040
10370 +/** GPONE Status
10371 +    Shows the activation status of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10372 +#define SYS_GPE_ACTS_GPONE 0x00000020
10373 +/* The block is inactive.
10374 +#define SYS_GPE_ACTS_GPONE_INACT 0x00000000 */
10375 +/** The block is active. */
10376 +#define SYS_GPE_ACTS_GPONE_ACT 0x00000020
10377 +/** GPONI Status
10378 +    Shows the activation status of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10379 +#define SYS_GPE_ACTS_GPONI 0x00000010
10380 +/* The block is inactive.
10381 +#define SYS_GPE_ACTS_GPONI_INACT 0x00000000 */
10382 +/** The block is active. */
10383 +#define SYS_GPE_ACTS_GPONI_ACT 0x00000010
10384 +/** LAN3 Status
10385 +    Shows the activation status of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10386 +#define SYS_GPE_ACTS_LAN3 0x00000008
10387 +/* The block is inactive.
10388 +#define SYS_GPE_ACTS_LAN3_INACT 0x00000000 */
10389 +/** The block is active. */
10390 +#define SYS_GPE_ACTS_LAN3_ACT 0x00000008
10391 +/** LAN2 Status
10392 +    Shows the activation status of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10393 +#define SYS_GPE_ACTS_LAN2 0x00000004
10394 +/* The block is inactive.
10395 +#define SYS_GPE_ACTS_LAN2_INACT 0x00000000 */
10396 +/** The block is active. */
10397 +#define SYS_GPE_ACTS_LAN2_ACT 0x00000004
10398 +/** LAN1 Status
10399 +    Shows the activation status of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10400 +#define SYS_GPE_ACTS_LAN1 0x00000002
10401 +/* The block is inactive.
10402 +#define SYS_GPE_ACTS_LAN1_INACT 0x00000000 */
10403 +/** The block is active. */
10404 +#define SYS_GPE_ACTS_LAN1_ACT 0x00000002
10405 +/** LAN0 Status
10406 +    Shows the activation status of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10407 +#define SYS_GPE_ACTS_LAN0 0x00000001
10408 +/* The block is inactive.
10409 +#define SYS_GPE_ACTS_LAN0_INACT 0x00000000 */
10410 +/** The block is active. */
10411 +#define SYS_GPE_ACTS_LAN0_ACT 0x00000001
10412 +
10413 +/* Fields of "Activation Register" */
10414 +/** Activate COP7
10415 +    Sets the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
10416 +#define SYS_GPE_ACT_COP7 0x80000000
10417 +/* No-Operation
10418 +#define SYS_GPE_ACT_COP7_NOP 0x00000000 */
10419 +/** Set */
10420 +#define SYS_GPE_ACT_COP7_SET 0x80000000
10421 +/** Activate COP6
10422 +    Sets the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
10423 +#define SYS_GPE_ACT_COP6 0x40000000
10424 +/* No-Operation
10425 +#define SYS_GPE_ACT_COP6_NOP 0x00000000 */
10426 +/** Set */
10427 +#define SYS_GPE_ACT_COP6_SET 0x40000000
10428 +/** Activate COP5
10429 +    Sets the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
10430 +#define SYS_GPE_ACT_COP5 0x20000000
10431 +/* No-Operation
10432 +#define SYS_GPE_ACT_COP5_NOP 0x00000000 */
10433 +/** Set */
10434 +#define SYS_GPE_ACT_COP5_SET 0x20000000
10435 +/** Activate COP4
10436 +    Sets the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
10437 +#define SYS_GPE_ACT_COP4 0x10000000
10438 +/* No-Operation
10439 +#define SYS_GPE_ACT_COP4_NOP 0x00000000 */
10440 +/** Set */
10441 +#define SYS_GPE_ACT_COP4_SET 0x10000000
10442 +/** Activate COP3
10443 +    Sets the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
10444 +#define SYS_GPE_ACT_COP3 0x08000000
10445 +/* No-Operation
10446 +#define SYS_GPE_ACT_COP3_NOP 0x00000000 */
10447 +/** Set */
10448 +#define SYS_GPE_ACT_COP3_SET 0x08000000
10449 +/** Activate COP2
10450 +    Sets the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
10451 +#define SYS_GPE_ACT_COP2 0x04000000
10452 +/* No-Operation
10453 +#define SYS_GPE_ACT_COP2_NOP 0x00000000 */
10454 +/** Set */
10455 +#define SYS_GPE_ACT_COP2_SET 0x04000000
10456 +/** Activate COP1
10457 +    Sets the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
10458 +#define SYS_GPE_ACT_COP1 0x02000000
10459 +/* No-Operation
10460 +#define SYS_GPE_ACT_COP1_NOP 0x00000000 */
10461 +/** Set */
10462 +#define SYS_GPE_ACT_COP1_SET 0x02000000
10463 +/** Activate COP0
10464 +    Sets the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
10465 +#define SYS_GPE_ACT_COP0 0x01000000
10466 +/* No-Operation
10467 +#define SYS_GPE_ACT_COP0_NOP 0x00000000 */
10468 +/** Set */
10469 +#define SYS_GPE_ACT_COP0_SET 0x01000000
10470 +/** Activate PE5
10471 +    Sets the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
10472 +#define SYS_GPE_ACT_PE5 0x00200000
10473 +/* No-Operation
10474 +#define SYS_GPE_ACT_PE5_NOP 0x00000000 */
10475 +/** Set */
10476 +#define SYS_GPE_ACT_PE5_SET 0x00200000
10477 +/** Activate PE4
10478 +    Sets the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
10479 +#define SYS_GPE_ACT_PE4 0x00100000
10480 +/* No-Operation
10481 +#define SYS_GPE_ACT_PE4_NOP 0x00000000 */
10482 +/** Set */
10483 +#define SYS_GPE_ACT_PE4_SET 0x00100000
10484 +/** Activate PE3
10485 +    Sets the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
10486 +#define SYS_GPE_ACT_PE3 0x00080000
10487 +/* No-Operation
10488 +#define SYS_GPE_ACT_PE3_NOP 0x00000000 */
10489 +/** Set */
10490 +#define SYS_GPE_ACT_PE3_SET 0x00080000
10491 +/** Activate PE2
10492 +    Sets the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
10493 +#define SYS_GPE_ACT_PE2 0x00040000
10494 +/* No-Operation
10495 +#define SYS_GPE_ACT_PE2_NOP 0x00000000 */
10496 +/** Set */
10497 +#define SYS_GPE_ACT_PE2_SET 0x00040000
10498 +/** Activate PE1
10499 +    Sets the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
10500 +#define SYS_GPE_ACT_PE1 0x00020000
10501 +/* No-Operation
10502 +#define SYS_GPE_ACT_PE1_NOP 0x00000000 */
10503 +/** Set */
10504 +#define SYS_GPE_ACT_PE1_SET 0x00020000
10505 +/** Activate PE0
10506 +    Sets the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
10507 +#define SYS_GPE_ACT_PE0 0x00010000
10508 +/* No-Operation
10509 +#define SYS_GPE_ACT_PE0_NOP 0x00000000 */
10510 +/** Set */
10511 +#define SYS_GPE_ACT_PE0_SET 0x00010000
10512 +/** Activate ARB
10513 +    Sets the activation flag of the ARB domain. This domain contains the Arbiter. */
10514 +#define SYS_GPE_ACT_ARB 0x00002000
10515 +/* No-Operation
10516 +#define SYS_GPE_ACT_ARB_NOP 0x00000000 */
10517 +/** Set */
10518 +#define SYS_GPE_ACT_ARB_SET 0x00002000
10519 +/** Activate FSQM
10520 +    Sets the activation flag of the FSQM domain. This domain contains the FSQM. */
10521 +#define SYS_GPE_ACT_FSQM 0x00001000
10522 +/* No-Operation
10523 +#define SYS_GPE_ACT_FSQM_NOP 0x00000000 */
10524 +/** Set */
10525 +#define SYS_GPE_ACT_FSQM_SET 0x00001000
10526 +/** Activate TMU
10527 +    Sets the activation flag of the TMU domain. This domain contains the TMU. */
10528 +#define SYS_GPE_ACT_TMU 0x00000800
10529 +/* No-Operation
10530 +#define SYS_GPE_ACT_TMU_NOP 0x00000000 */
10531 +/** Set */
10532 +#define SYS_GPE_ACT_TMU_SET 0x00000800
10533 +/** Activate MRG
10534 +    Sets the activation flag of the MRG domain. This domain contains the Merger. */
10535 +#define SYS_GPE_ACT_MRG 0x00000400
10536 +/* No-Operation
10537 +#define SYS_GPE_ACT_MRG_NOP 0x00000000 */
10538 +/** Set */
10539 +#define SYS_GPE_ACT_MRG_SET 0x00000400
10540 +/** Activate DISP
10541 +    Sets the activation flag of the DISP domain. This domain contains the Dispatcher. */
10542 +#define SYS_GPE_ACT_DISP 0x00000200
10543 +/* No-Operation
10544 +#define SYS_GPE_ACT_DISP_NOP 0x00000000 */
10545 +/** Set */
10546 +#define SYS_GPE_ACT_DISP_SET 0x00000200
10547 +/** Activate IQM
10548 +    Sets the activation flag of the IQM domain. This domain contains the IQM. */
10549 +#define SYS_GPE_ACT_IQM 0x00000100
10550 +/* No-Operation
10551 +#define SYS_GPE_ACT_IQM_NOP 0x00000000 */
10552 +/** Set */
10553 +#define SYS_GPE_ACT_IQM_SET 0x00000100
10554 +/** Activate CPUE
10555 +    Sets the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10556 +#define SYS_GPE_ACT_CPUE 0x00000080
10557 +/* No-Operation
10558 +#define SYS_GPE_ACT_CPUE_NOP 0x00000000 */
10559 +/** Set */
10560 +#define SYS_GPE_ACT_CPUE_SET 0x00000080
10561 +/** Activate CPUI
10562 +    Sets the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10563 +#define SYS_GPE_ACT_CPUI 0x00000040
10564 +/* No-Operation
10565 +#define SYS_GPE_ACT_CPUI_NOP 0x00000000 */
10566 +/** Set */
10567 +#define SYS_GPE_ACT_CPUI_SET 0x00000040
10568 +/** Activate GPONE
10569 +    Sets the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10570 +#define SYS_GPE_ACT_GPONE 0x00000020
10571 +/* No-Operation
10572 +#define SYS_GPE_ACT_GPONE_NOP 0x00000000 */
10573 +/** Set */
10574 +#define SYS_GPE_ACT_GPONE_SET 0x00000020
10575 +/** Activate GPONI
10576 +    Sets the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10577 +#define SYS_GPE_ACT_GPONI 0x00000010
10578 +/* No-Operation
10579 +#define SYS_GPE_ACT_GPONI_NOP 0x00000000 */
10580 +/** Set */
10581 +#define SYS_GPE_ACT_GPONI_SET 0x00000010
10582 +/** Activate LAN3
10583 +    Sets the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10584 +#define SYS_GPE_ACT_LAN3 0x00000008
10585 +/* No-Operation
10586 +#define SYS_GPE_ACT_LAN3_NOP 0x00000000 */
10587 +/** Set */
10588 +#define SYS_GPE_ACT_LAN3_SET 0x00000008
10589 +/** Activate LAN2
10590 +    Sets the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10591 +#define SYS_GPE_ACT_LAN2 0x00000004
10592 +/* No-Operation
10593 +#define SYS_GPE_ACT_LAN2_NOP 0x00000000 */
10594 +/** Set */
10595 +#define SYS_GPE_ACT_LAN2_SET 0x00000004
10596 +/** Activate LAN1
10597 +    Sets the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10598 +#define SYS_GPE_ACT_LAN1 0x00000002
10599 +/* No-Operation
10600 +#define SYS_GPE_ACT_LAN1_NOP 0x00000000 */
10601 +/** Set */
10602 +#define SYS_GPE_ACT_LAN1_SET 0x00000002
10603 +/** Activate LAN0
10604 +    Sets the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10605 +#define SYS_GPE_ACT_LAN0 0x00000001
10606 +/* No-Operation
10607 +#define SYS_GPE_ACT_LAN0_NOP 0x00000000 */
10608 +/** Set */
10609 +#define SYS_GPE_ACT_LAN0_SET 0x00000001
10610 +
10611 +/* Fields of "Deactivation Register" */
10612 +/** Deactivate COP7
10613 +    Clears the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
10614 +#define SYS_GPE_DEACT_COP7 0x80000000
10615 +/* No-Operation
10616 +#define SYS_GPE_DEACT_COP7_NOP 0x00000000 */
10617 +/** Clear */
10618 +#define SYS_GPE_DEACT_COP7_CLR 0x80000000
10619 +/** Deactivate COP6
10620 +    Clears the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
10621 +#define SYS_GPE_DEACT_COP6 0x40000000
10622 +/* No-Operation
10623 +#define SYS_GPE_DEACT_COP6_NOP 0x00000000 */
10624 +/** Clear */
10625 +#define SYS_GPE_DEACT_COP6_CLR 0x40000000
10626 +/** Deactivate COP5
10627 +    Clears the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
10628 +#define SYS_GPE_DEACT_COP5 0x20000000
10629 +/* No-Operation
10630 +#define SYS_GPE_DEACT_COP5_NOP 0x00000000 */
10631 +/** Clear */
10632 +#define SYS_GPE_DEACT_COP5_CLR 0x20000000
10633 +/** Deactivate COP4
10634 +    Clears the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
10635 +#define SYS_GPE_DEACT_COP4 0x10000000
10636 +/* No-Operation
10637 +#define SYS_GPE_DEACT_COP4_NOP 0x00000000 */
10638 +/** Clear */
10639 +#define SYS_GPE_DEACT_COP4_CLR 0x10000000
10640 +/** Deactivate COP3
10641 +    Clears the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
10642 +#define SYS_GPE_DEACT_COP3 0x08000000
10643 +/* No-Operation
10644 +#define SYS_GPE_DEACT_COP3_NOP 0x00000000 */
10645 +/** Clear */
10646 +#define SYS_GPE_DEACT_COP3_CLR 0x08000000
10647 +/** Deactivate COP2
10648 +    Clears the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
10649 +#define SYS_GPE_DEACT_COP2 0x04000000
10650 +/* No-Operation
10651 +#define SYS_GPE_DEACT_COP2_NOP 0x00000000 */
10652 +/** Clear */
10653 +#define SYS_GPE_DEACT_COP2_CLR 0x04000000
10654 +/** Deactivate COP1
10655 +    Clears the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
10656 +#define SYS_GPE_DEACT_COP1 0x02000000
10657 +/* No-Operation
10658 +#define SYS_GPE_DEACT_COP1_NOP 0x00000000 */
10659 +/** Clear */
10660 +#define SYS_GPE_DEACT_COP1_CLR 0x02000000
10661 +/** Deactivate COP0
10662 +    Clears the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
10663 +#define SYS_GPE_DEACT_COP0 0x01000000
10664 +/* No-Operation
10665 +#define SYS_GPE_DEACT_COP0_NOP 0x00000000 */
10666 +/** Clear */
10667 +#define SYS_GPE_DEACT_COP0_CLR 0x01000000
10668 +/** Deactivate PE5
10669 +    Clears the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
10670 +#define SYS_GPE_DEACT_PE5 0x00200000
10671 +/* No-Operation
10672 +#define SYS_GPE_DEACT_PE5_NOP 0x00000000 */
10673 +/** Clear */
10674 +#define SYS_GPE_DEACT_PE5_CLR 0x00200000
10675 +/** Deactivate PE4
10676 +    Clears the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
10677 +#define SYS_GPE_DEACT_PE4 0x00100000
10678 +/* No-Operation
10679 +#define SYS_GPE_DEACT_PE4_NOP 0x00000000 */
10680 +/** Clear */
10681 +#define SYS_GPE_DEACT_PE4_CLR 0x00100000
10682 +/** Deactivate PE3
10683 +    Clears the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
10684 +#define SYS_GPE_DEACT_PE3 0x00080000
10685 +/* No-Operation
10686 +#define SYS_GPE_DEACT_PE3_NOP 0x00000000 */
10687 +/** Clear */
10688 +#define SYS_GPE_DEACT_PE3_CLR 0x00080000
10689 +/** Deactivate PE2
10690 +    Clears the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
10691 +#define SYS_GPE_DEACT_PE2 0x00040000
10692 +/* No-Operation
10693 +#define SYS_GPE_DEACT_PE2_NOP 0x00000000 */
10694 +/** Clear */
10695 +#define SYS_GPE_DEACT_PE2_CLR 0x00040000
10696 +/** Deactivate PE1
10697 +    Clears the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
10698 +#define SYS_GPE_DEACT_PE1 0x00020000
10699 +/* No-Operation
10700 +#define SYS_GPE_DEACT_PE1_NOP 0x00000000 */
10701 +/** Clear */
10702 +#define SYS_GPE_DEACT_PE1_CLR 0x00020000
10703 +/** Deactivate PE0
10704 +    Clears the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
10705 +#define SYS_GPE_DEACT_PE0 0x00010000
10706 +/* No-Operation
10707 +#define SYS_GPE_DEACT_PE0_NOP 0x00000000 */
10708 +/** Clear */
10709 +#define SYS_GPE_DEACT_PE0_CLR 0x00010000
10710 +/** Deactivate ARB
10711 +    Clears the activation flag of the ARB domain. This domain contains the Arbiter. */
10712 +#define SYS_GPE_DEACT_ARB 0x00002000
10713 +/* No-Operation
10714 +#define SYS_GPE_DEACT_ARB_NOP 0x00000000 */
10715 +/** Clear */
10716 +#define SYS_GPE_DEACT_ARB_CLR 0x00002000
10717 +/** Deactivate FSQM
10718 +    Clears the activation flag of the FSQM domain. This domain contains the FSQM. */
10719 +#define SYS_GPE_DEACT_FSQM 0x00001000
10720 +/* No-Operation
10721 +#define SYS_GPE_DEACT_FSQM_NOP 0x00000000 */
10722 +/** Clear */
10723 +#define SYS_GPE_DEACT_FSQM_CLR 0x00001000
10724 +/** Deactivate TMU
10725 +    Clears the activation flag of the TMU domain. This domain contains the TMU. */
10726 +#define SYS_GPE_DEACT_TMU 0x00000800
10727 +/* No-Operation
10728 +#define SYS_GPE_DEACT_TMU_NOP 0x00000000 */
10729 +/** Clear */
10730 +#define SYS_GPE_DEACT_TMU_CLR 0x00000800
10731 +/** Deactivate MRG
10732 +    Clears the activation flag of the MRG domain. This domain contains the Merger. */
10733 +#define SYS_GPE_DEACT_MRG 0x00000400
10734 +/* No-Operation
10735 +#define SYS_GPE_DEACT_MRG_NOP 0x00000000 */
10736 +/** Clear */
10737 +#define SYS_GPE_DEACT_MRG_CLR 0x00000400
10738 +/** Deactivate DISP
10739 +    Clears the activation flag of the DISP domain. This domain contains the Dispatcher. */
10740 +#define SYS_GPE_DEACT_DISP 0x00000200
10741 +/* No-Operation
10742 +#define SYS_GPE_DEACT_DISP_NOP 0x00000000 */
10743 +/** Clear */
10744 +#define SYS_GPE_DEACT_DISP_CLR 0x00000200
10745 +/** Deactivate IQM
10746 +    Clears the activation flag of the IQM domain. This domain contains the IQM. */
10747 +#define SYS_GPE_DEACT_IQM 0x00000100
10748 +/* No-Operation
10749 +#define SYS_GPE_DEACT_IQM_NOP 0x00000000 */
10750 +/** Clear */
10751 +#define SYS_GPE_DEACT_IQM_CLR 0x00000100
10752 +/** Deactivate CPUE
10753 +    Clears the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10754 +#define SYS_GPE_DEACT_CPUE 0x00000080
10755 +/* No-Operation
10756 +#define SYS_GPE_DEACT_CPUE_NOP 0x00000000 */
10757 +/** Clear */
10758 +#define SYS_GPE_DEACT_CPUE_CLR 0x00000080
10759 +/** Deactivate CPUI
10760 +    Clears the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10761 +#define SYS_GPE_DEACT_CPUI 0x00000040
10762 +/* No-Operation
10763 +#define SYS_GPE_DEACT_CPUI_NOP 0x00000000 */
10764 +/** Clear */
10765 +#define SYS_GPE_DEACT_CPUI_CLR 0x00000040
10766 +/** Deactivate GPONE
10767 +    Clears the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10768 +#define SYS_GPE_DEACT_GPONE 0x00000020
10769 +/* No-Operation
10770 +#define SYS_GPE_DEACT_GPONE_NOP 0x00000000 */
10771 +/** Clear */
10772 +#define SYS_GPE_DEACT_GPONE_CLR 0x00000020
10773 +/** Deactivate GPONI
10774 +    Clears the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10775 +#define SYS_GPE_DEACT_GPONI 0x00000010
10776 +/* No-Operation
10777 +#define SYS_GPE_DEACT_GPONI_NOP 0x00000000 */
10778 +/** Clear */
10779 +#define SYS_GPE_DEACT_GPONI_CLR 0x00000010
10780 +/** Deactivate LAN3
10781 +    Clears the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10782 +#define SYS_GPE_DEACT_LAN3 0x00000008
10783 +/* No-Operation
10784 +#define SYS_GPE_DEACT_LAN3_NOP 0x00000000 */
10785 +/** Clear */
10786 +#define SYS_GPE_DEACT_LAN3_CLR 0x00000008
10787 +/** Deactivate LAN2
10788 +    Clears the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10789 +#define SYS_GPE_DEACT_LAN2 0x00000004
10790 +/* No-Operation
10791 +#define SYS_GPE_DEACT_LAN2_NOP 0x00000000 */
10792 +/** Clear */
10793 +#define SYS_GPE_DEACT_LAN2_CLR 0x00000004
10794 +/** Deactivate LAN1
10795 +    Clears the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10796 +#define SYS_GPE_DEACT_LAN1 0x00000002
10797 +/* No-Operation
10798 +#define SYS_GPE_DEACT_LAN1_NOP 0x00000000 */
10799 +/** Clear */
10800 +#define SYS_GPE_DEACT_LAN1_CLR 0x00000002
10801 +/** Deactivate LAN0
10802 +    Clears the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
10803 +#define SYS_GPE_DEACT_LAN0 0x00000001
10804 +/* No-Operation
10805 +#define SYS_GPE_DEACT_LAN0_NOP 0x00000000 */
10806 +/** Clear */
10807 +#define SYS_GPE_DEACT_LAN0_CLR 0x00000001
10808 +
10809 +/* Fields of "Reboot Trigger Register" */
10810 +/** Reboot COP7
10811 +    Triggers a reboot of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
10812 +#define SYS_GPE_RBT_COP7 0x80000000
10813 +/* No-Operation
10814 +#define SYS_GPE_RBT_COP7_NOP 0x00000000 */
10815 +/** Trigger */
10816 +#define SYS_GPE_RBT_COP7_TRIG 0x80000000
10817 +/** Reboot COP6
10818 +    Triggers a reboot of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
10819 +#define SYS_GPE_RBT_COP6 0x40000000
10820 +/* No-Operation
10821 +#define SYS_GPE_RBT_COP6_NOP 0x00000000 */
10822 +/** Trigger */
10823 +#define SYS_GPE_RBT_COP6_TRIG 0x40000000
10824 +/** Reboot COP5
10825 +    Triggers a reboot of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
10826 +#define SYS_GPE_RBT_COP5 0x20000000
10827 +/* No-Operation
10828 +#define SYS_GPE_RBT_COP5_NOP 0x00000000 */
10829 +/** Trigger */
10830 +#define SYS_GPE_RBT_COP5_TRIG 0x20000000
10831 +/** Reboot COP4
10832 +    Triggers a reboot of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
10833 +#define SYS_GPE_RBT_COP4 0x10000000
10834 +/* No-Operation
10835 +#define SYS_GPE_RBT_COP4_NOP 0x00000000 */
10836 +/** Trigger */
10837 +#define SYS_GPE_RBT_COP4_TRIG 0x10000000
10838 +/** Reboot COP3
10839 +    Triggers a reboot of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
10840 +#define SYS_GPE_RBT_COP3 0x08000000
10841 +/* No-Operation
10842 +#define SYS_GPE_RBT_COP3_NOP 0x00000000 */
10843 +/** Trigger */
10844 +#define SYS_GPE_RBT_COP3_TRIG 0x08000000
10845 +/** Reboot COP2
10846 +    Triggers a reboot of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
10847 +#define SYS_GPE_RBT_COP2 0x04000000
10848 +/* No-Operation
10849 +#define SYS_GPE_RBT_COP2_NOP 0x00000000 */
10850 +/** Trigger */
10851 +#define SYS_GPE_RBT_COP2_TRIG 0x04000000
10852 +/** Reboot COP1
10853 +    Triggers a reboot of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
10854 +#define SYS_GPE_RBT_COP1 0x02000000
10855 +/* No-Operation
10856 +#define SYS_GPE_RBT_COP1_NOP 0x00000000 */
10857 +/** Trigger */
10858 +#define SYS_GPE_RBT_COP1_TRIG 0x02000000
10859 +/** Reboot COP0
10860 +    Triggers a reboot of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
10861 +#define SYS_GPE_RBT_COP0 0x01000000
10862 +/* No-Operation
10863 +#define SYS_GPE_RBT_COP0_NOP 0x00000000 */
10864 +/** Trigger */
10865 +#define SYS_GPE_RBT_COP0_TRIG 0x01000000
10866 +/** Reboot PE5
10867 +    Triggers a reboot of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
10868 +#define SYS_GPE_RBT_PE5 0x00200000
10869 +/* No-Operation
10870 +#define SYS_GPE_RBT_PE5_NOP 0x00000000 */
10871 +/** Trigger */
10872 +#define SYS_GPE_RBT_PE5_TRIG 0x00200000
10873 +/** Reboot PE4
10874 +    Triggers a reboot of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
10875 +#define SYS_GPE_RBT_PE4 0x00100000
10876 +/* No-Operation
10877 +#define SYS_GPE_RBT_PE4_NOP 0x00000000 */
10878 +/** Trigger */
10879 +#define SYS_GPE_RBT_PE4_TRIG 0x00100000
10880 +/** Reboot PE3
10881 +    Triggers a reboot of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
10882 +#define SYS_GPE_RBT_PE3 0x00080000
10883 +/* No-Operation
10884 +#define SYS_GPE_RBT_PE3_NOP 0x00000000 */
10885 +/** Trigger */
10886 +#define SYS_GPE_RBT_PE3_TRIG 0x00080000
10887 +/** Reboot PE2
10888 +    Triggers a reboot of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
10889 +#define SYS_GPE_RBT_PE2 0x00040000
10890 +/* No-Operation
10891 +#define SYS_GPE_RBT_PE2_NOP 0x00000000 */
10892 +/** Trigger */
10893 +#define SYS_GPE_RBT_PE2_TRIG 0x00040000
10894 +/** Reboot PE1
10895 +    Triggers a reboot of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
10896 +#define SYS_GPE_RBT_PE1 0x00020000
10897 +/* No-Operation
10898 +#define SYS_GPE_RBT_PE1_NOP 0x00000000 */
10899 +/** Trigger */
10900 +#define SYS_GPE_RBT_PE1_TRIG 0x00020000
10901 +/** Reboot PE0
10902 +    Triggers a reboot of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
10903 +#define SYS_GPE_RBT_PE0 0x00010000
10904 +/* No-Operation
10905 +#define SYS_GPE_RBT_PE0_NOP 0x00000000 */
10906 +/** Trigger */
10907 +#define SYS_GPE_RBT_PE0_TRIG 0x00010000
10908 +/** Reboot ARB
10909 +    Triggers a reboot of the ARB domain. This domain contains the Arbiter. */
10910 +#define SYS_GPE_RBT_ARB 0x00002000
10911 +/* No-Operation
10912 +#define SYS_GPE_RBT_ARB_NOP 0x00000000 */
10913 +/** Trigger */
10914 +#define SYS_GPE_RBT_ARB_TRIG 0x00002000
10915 +/** Reboot FSQM
10916 +    Triggers a reboot of the FSQM domain. This domain contains the FSQM. */
10917 +#define SYS_GPE_RBT_FSQM 0x00001000
10918 +/* No-Operation
10919 +#define SYS_GPE_RBT_FSQM_NOP 0x00000000 */
10920 +/** Trigger */
10921 +#define SYS_GPE_RBT_FSQM_TRIG 0x00001000
10922 +/** Reboot TMU
10923 +    Triggers a reboot of the TMU domain. This domain contains the TMU. */
10924 +#define SYS_GPE_RBT_TMU 0x00000800
10925 +/* No-Operation
10926 +#define SYS_GPE_RBT_TMU_NOP 0x00000000 */
10927 +/** Trigger */
10928 +#define SYS_GPE_RBT_TMU_TRIG 0x00000800
10929 +/** Reboot MRG
10930 +    Triggers a reboot of the MRG domain. This domain contains the Merger. */
10931 +#define SYS_GPE_RBT_MRG 0x00000400
10932 +/* No-Operation
10933 +#define SYS_GPE_RBT_MRG_NOP 0x00000000 */
10934 +/** Trigger */
10935 +#define SYS_GPE_RBT_MRG_TRIG 0x00000400
10936 +/** Reboot DISP
10937 +    Triggers a reboot of the DISP domain. This domain contains the Dispatcher. */
10938 +#define SYS_GPE_RBT_DISP 0x00000200
10939 +/* No-Operation
10940 +#define SYS_GPE_RBT_DISP_NOP 0x00000000 */
10941 +/** Trigger */
10942 +#define SYS_GPE_RBT_DISP_TRIG 0x00000200
10943 +/** Reboot IQM
10944 +    Triggers a reboot of the IQM domain. This domain contains the IQM. */
10945 +#define SYS_GPE_RBT_IQM 0x00000100
10946 +/* No-Operation
10947 +#define SYS_GPE_RBT_IQM_NOP 0x00000000 */
10948 +/** Trigger */
10949 +#define SYS_GPE_RBT_IQM_TRIG 0x00000100
10950 +/** Reboot CPUE
10951 +    Triggers a reboot of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
10952 +#define SYS_GPE_RBT_CPUE 0x00000080
10953 +/* No-Operation
10954 +#define SYS_GPE_RBT_CPUE_NOP 0x00000000 */
10955 +/** Trigger */
10956 +#define SYS_GPE_RBT_CPUE_TRIG 0x00000080
10957 +/** Reboot CPUI
10958 +    Triggers a reboot of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
10959 +#define SYS_GPE_RBT_CPUI 0x00000040
10960 +/* No-Operation
10961 +#define SYS_GPE_RBT_CPUI_NOP 0x00000000 */
10962 +/** Trigger */
10963 +#define SYS_GPE_RBT_CPUI_TRIG 0x00000040
10964 +/** Reboot GPONE
10965 +    Triggers a reboot of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
10966 +#define SYS_GPE_RBT_GPONE 0x00000020
10967 +/* No-Operation
10968 +#define SYS_GPE_RBT_GPONE_NOP 0x00000000 */
10969 +/** Trigger */
10970 +#define SYS_GPE_RBT_GPONE_TRIG 0x00000020
10971 +/** Reboot GPONI
10972 +    Triggers a reboot of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
10973 +#define SYS_GPE_RBT_GPONI 0x00000010
10974 +/* No-Operation
10975 +#define SYS_GPE_RBT_GPONI_NOP 0x00000000 */
10976 +/** Trigger */
10977 +#define SYS_GPE_RBT_GPONI_TRIG 0x00000010
10978 +/** Reboot LAN3
10979 +    Triggers a reboot of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
10980 +#define SYS_GPE_RBT_LAN3 0x00000008
10981 +/* No-Operation
10982 +#define SYS_GPE_RBT_LAN3_NOP 0x00000000 */
10983 +/** Trigger */
10984 +#define SYS_GPE_RBT_LAN3_TRIG 0x00000008
10985 +/** Reboot LAN2
10986 +    Triggers a reboot of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
10987 +#define SYS_GPE_RBT_LAN2 0x00000004
10988 +/* No-Operation
10989 +#define SYS_GPE_RBT_LAN2_NOP 0x00000000 */
10990 +/** Trigger */
10991 +#define SYS_GPE_RBT_LAN2_TRIG 0x00000004
10992 +/** Reboot LAN1
10993 +    Triggers a reboot of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
10994 +#define SYS_GPE_RBT_LAN1 0x00000002
10995 +/* No-Operation
10996 +#define SYS_GPE_RBT_LAN1_NOP 0x00000000 */
10997 +/** Trigger */
10998 +#define SYS_GPE_RBT_LAN1_TRIG 0x00000002
10999 +/** Reboot LAN0
11000 +    Triggers a reboot of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
11001 +#define SYS_GPE_RBT_LAN0 0x00000001
11002 +/* No-Operation
11003 +#define SYS_GPE_RBT_LAN0_NOP 0x00000000 */
11004 +/** Trigger */
11005 +#define SYS_GPE_RBT_LAN0_TRIG 0x00000001
11006 +
11007 +/* Fields of "Power Down Configuration Register" */
11008 +/** Enable Power Down COP7
11009 +    Ignore this bit as power-gating is not supported for this chip. */
11010 +#define SYS_GPE_PDCFG_COP7 0x80000000
11011 +/* Disable
11012 +#define SYS_GPE_PDCFG_COP7_DIS 0x00000000 */
11013 +/** Enable */
11014 +#define SYS_GPE_PDCFG_COP7_EN 0x80000000
11015 +/** Enable Power Down COP6
11016 +    Ignore this bit as power-gating is not supported for this chip. */
11017 +#define SYS_GPE_PDCFG_COP6 0x40000000
11018 +/* Disable
11019 +#define SYS_GPE_PDCFG_COP6_DIS 0x00000000 */
11020 +/** Enable */
11021 +#define SYS_GPE_PDCFG_COP6_EN 0x40000000
11022 +/** Enable Power Down COP5
11023 +    Ignore this bit as power-gating is not supported for this chip. */
11024 +#define SYS_GPE_PDCFG_COP5 0x20000000
11025 +/* Disable
11026 +#define SYS_GPE_PDCFG_COP5_DIS 0x00000000 */
11027 +/** Enable */
11028 +#define SYS_GPE_PDCFG_COP5_EN 0x20000000
11029 +/** Enable Power Down COP4
11030 +    Ignore this bit as power-gating is not supported for this chip. */
11031 +#define SYS_GPE_PDCFG_COP4 0x10000000
11032 +/* Disable
11033 +#define SYS_GPE_PDCFG_COP4_DIS 0x00000000 */
11034 +/** Enable */
11035 +#define SYS_GPE_PDCFG_COP4_EN 0x10000000
11036 +/** Enable Power Down COP3
11037 +    Ignore this bit as power-gating is not supported for this chip. */
11038 +#define SYS_GPE_PDCFG_COP3 0x08000000
11039 +/* Disable
11040 +#define SYS_GPE_PDCFG_COP3_DIS 0x00000000 */
11041 +/** Enable */
11042 +#define SYS_GPE_PDCFG_COP3_EN 0x08000000
11043 +/** Enable Power Down COP2
11044 +    Ignore this bit as power-gating is not supported for this chip. */
11045 +#define SYS_GPE_PDCFG_COP2 0x04000000
11046 +/* Disable
11047 +#define SYS_GPE_PDCFG_COP2_DIS 0x00000000 */
11048 +/** Enable */
11049 +#define SYS_GPE_PDCFG_COP2_EN 0x04000000
11050 +/** Enable Power Down COP1
11051 +    Ignore this bit as power-gating is not supported for this chip. */
11052 +#define SYS_GPE_PDCFG_COP1 0x02000000
11053 +/* Disable
11054 +#define SYS_GPE_PDCFG_COP1_DIS 0x00000000 */
11055 +/** Enable */
11056 +#define SYS_GPE_PDCFG_COP1_EN 0x02000000
11057 +/** Enable Power Down COP0
11058 +    Ignore this bit as power-gating is not supported for this chip. */
11059 +#define SYS_GPE_PDCFG_COP0 0x01000000
11060 +/* Disable
11061 +#define SYS_GPE_PDCFG_COP0_DIS 0x00000000 */
11062 +/** Enable */
11063 +#define SYS_GPE_PDCFG_COP0_EN 0x01000000
11064 +/** Enable Power Down PE5
11065 +    Ignore this bit as power-gating is not supported for this chip. */
11066 +#define SYS_GPE_PDCFG_PE5 0x00200000
11067 +/* Disable
11068 +#define SYS_GPE_PDCFG_PE5_DIS 0x00000000 */
11069 +/** Enable */
11070 +#define SYS_GPE_PDCFG_PE5_EN 0x00200000
11071 +/** Enable Power Down PE4
11072 +    Ignore this bit as power-gating is not supported for this chip. */
11073 +#define SYS_GPE_PDCFG_PE4 0x00100000
11074 +/* Disable
11075 +#define SYS_GPE_PDCFG_PE4_DIS 0x00000000 */
11076 +/** Enable */
11077 +#define SYS_GPE_PDCFG_PE4_EN 0x00100000
11078 +/** Enable Power Down PE3
11079 +    Ignore this bit as power-gating is not supported for this chip. */
11080 +#define SYS_GPE_PDCFG_PE3 0x00080000
11081 +/* Disable
11082 +#define SYS_GPE_PDCFG_PE3_DIS 0x00000000 */
11083 +/** Enable */
11084 +#define SYS_GPE_PDCFG_PE3_EN 0x00080000
11085 +/** Enable Power Down PE2
11086 +    Ignore this bit as power-gating is not supported for this chip. */
11087 +#define SYS_GPE_PDCFG_PE2 0x00040000
11088 +/* Disable
11089 +#define SYS_GPE_PDCFG_PE2_DIS 0x00000000 */
11090 +/** Enable */
11091 +#define SYS_GPE_PDCFG_PE2_EN 0x00040000
11092 +/** Enable Power Down PE1
11093 +    Ignore this bit as power-gating is not supported for this chip. */
11094 +#define SYS_GPE_PDCFG_PE1 0x00020000
11095 +/* Disable
11096 +#define SYS_GPE_PDCFG_PE1_DIS 0x00000000 */
11097 +/** Enable */
11098 +#define SYS_GPE_PDCFG_PE1_EN 0x00020000
11099 +/** Enable Power Down PE0
11100 +    Ignore this bit as power-gating is not supported for this chip. */
11101 +#define SYS_GPE_PDCFG_PE0 0x00010000
11102 +/* Disable
11103 +#define SYS_GPE_PDCFG_PE0_DIS 0x00000000 */
11104 +/** Enable */
11105 +#define SYS_GPE_PDCFG_PE0_EN 0x00010000
11106 +/** Enable Power Down ARB
11107 +    Ignore this bit as power-gating is not supported for this chip. */
11108 +#define SYS_GPE_PDCFG_ARB 0x00002000
11109 +/* Disable
11110 +#define SYS_GPE_PDCFG_ARB_DIS 0x00000000 */
11111 +/** Enable */
11112 +#define SYS_GPE_PDCFG_ARB_EN 0x00002000
11113 +/** Enable Power Down FSQM
11114 +    Ignore this bit as power-gating is not supported for this chip. */
11115 +#define SYS_GPE_PDCFG_FSQM 0x00001000
11116 +/* Disable
11117 +#define SYS_GPE_PDCFG_FSQM_DIS 0x00000000 */
11118 +/** Enable */
11119 +#define SYS_GPE_PDCFG_FSQM_EN 0x00001000
11120 +/** Enable Power Down TMU
11121 +    Ignore this bit as power-gating is not supported for this chip. */
11122 +#define SYS_GPE_PDCFG_TMU 0x00000800
11123 +/* Disable
11124 +#define SYS_GPE_PDCFG_TMU_DIS 0x00000000 */
11125 +/** Enable */
11126 +#define SYS_GPE_PDCFG_TMU_EN 0x00000800
11127 +/** Enable Power Down MRG
11128 +    Ignore this bit as power-gating is not supported for this chip. */
11129 +#define SYS_GPE_PDCFG_MRG 0x00000400
11130 +/* Disable
11131 +#define SYS_GPE_PDCFG_MRG_DIS 0x00000000 */
11132 +/** Enable */
11133 +#define SYS_GPE_PDCFG_MRG_EN 0x00000400
11134 +/** Enable Power Down DISP
11135 +    Ignore this bit as power-gating is not supported for this chip. */
11136 +#define SYS_GPE_PDCFG_DISP 0x00000200
11137 +/* Disable
11138 +#define SYS_GPE_PDCFG_DISP_DIS 0x00000000 */
11139 +/** Enable */
11140 +#define SYS_GPE_PDCFG_DISP_EN 0x00000200
11141 +/** Enable Power Down IQM
11142 +    Ignore this bit as power-gating is not supported for this chip. */
11143 +#define SYS_GPE_PDCFG_IQM 0x00000100
11144 +/* Disable
11145 +#define SYS_GPE_PDCFG_IQM_DIS 0x00000000 */
11146 +/** Enable */
11147 +#define SYS_GPE_PDCFG_IQM_EN 0x00000100
11148 +/** Enable Power Down CPUE
11149 +    Ignore this bit as power-gating is not supported for this chip. */
11150 +#define SYS_GPE_PDCFG_CPUE 0x00000080
11151 +/* Disable
11152 +#define SYS_GPE_PDCFG_CPUE_DIS 0x00000000 */
11153 +/** Enable */
11154 +#define SYS_GPE_PDCFG_CPUE_EN 0x00000080
11155 +/** Enable Power Down CPUI
11156 +    Ignore this bit as power-gating is not supported for this chip. */
11157 +#define SYS_GPE_PDCFG_CPUI 0x00000040
11158 +/* Disable
11159 +#define SYS_GPE_PDCFG_CPUI_DIS 0x00000000 */
11160 +/** Enable */
11161 +#define SYS_GPE_PDCFG_CPUI_EN 0x00000040
11162 +/** Enable Power Down GPONE
11163 +    Ignore this bit as power-gating is not supported for this chip. */
11164 +#define SYS_GPE_PDCFG_GPONE 0x00000020
11165 +/* Disable
11166 +#define SYS_GPE_PDCFG_GPONE_DIS 0x00000000 */
11167 +/** Enable */
11168 +#define SYS_GPE_PDCFG_GPONE_EN 0x00000020
11169 +/** Enable Power Down GPONI
11170 +    Ignore this bit as power-gating is not supported for this chip. */
11171 +#define SYS_GPE_PDCFG_GPONI 0x00000010
11172 +/* Disable
11173 +#define SYS_GPE_PDCFG_GPONI_DIS 0x00000000 */
11174 +/** Enable */
11175 +#define SYS_GPE_PDCFG_GPONI_EN 0x00000010
11176 +/** Enable Power Down LAN3
11177 +    Ignore this bit as power-gating is not supported for this chip. */
11178 +#define SYS_GPE_PDCFG_LAN3 0x00000008
11179 +/* Disable
11180 +#define SYS_GPE_PDCFG_LAN3_DIS 0x00000000 */
11181 +/** Enable */
11182 +#define SYS_GPE_PDCFG_LAN3_EN 0x00000008
11183 +/** Enable Power Down LAN2
11184 +    Ignore this bit as power-gating is not supported for this chip. */
11185 +#define SYS_GPE_PDCFG_LAN2 0x00000004
11186 +/* Disable
11187 +#define SYS_GPE_PDCFG_LAN2_DIS 0x00000000 */
11188 +/** Enable */
11189 +#define SYS_GPE_PDCFG_LAN2_EN 0x00000004
11190 +/** Enable Power Down LAN1
11191 +    Ignore this bit as power-gating is not supported for this chip. */
11192 +#define SYS_GPE_PDCFG_LAN1 0x00000002
11193 +/* Disable
11194 +#define SYS_GPE_PDCFG_LAN1_DIS 0x00000000 */
11195 +/** Enable */
11196 +#define SYS_GPE_PDCFG_LAN1_EN 0x00000002
11197 +/** Enable Power Down LAN0
11198 +    Ignore this bit as power-gating is not supported for this chip. */
11199 +#define SYS_GPE_PDCFG_LAN0 0x00000001
11200 +/* Disable
11201 +#define SYS_GPE_PDCFG_LAN0_DIS 0x00000000 */
11202 +/** Enable */
11203 +#define SYS_GPE_PDCFG_LAN0_EN 0x00000001
11204 +
11205 +/* Fields of "Sleep Source Configuration Register" */
11206 +/** Sleep/Wakeup Source CPU
11207 +    Selects the CPU access signal as sleep/wakeup source. */
11208 +#define SYS_GPE_SSCFG_CPU 0x00020000
11209 +/* Not selected
11210 +#define SYS_GPE_SSCFG_CPU_NSEL 0x00000000 */
11211 +/** Selected */
11212 +#define SYS_GPE_SSCFG_CPU_SEL 0x00020000
11213 +/** Sleep/Wakeup Source FSQM
11214 +    Selects the FSQM signal as sleep/wakeup source. */
11215 +#define SYS_GPE_SSCFG_FSQM 0x00008000
11216 +/* Not selected
11217 +#define SYS_GPE_SSCFG_FSQM_NSEL 0x00000000 */
11218 +/** Selected */
11219 +#define SYS_GPE_SSCFG_FSQM_SEL 0x00008000
11220 +/** Sleep/Wakeup Source GPONT
11221 +    Selects the FIFO empty signal of the TCONT Request FIFO of port GPON as sleep/wakeup source. */
11222 +#define SYS_GPE_SSCFG_GPONT 0x00002000
11223 +/* Not selected
11224 +#define SYS_GPE_SSCFG_GPONT_NSEL 0x00000000 */
11225 +/** Selected */
11226 +#define SYS_GPE_SSCFG_GPONT_SEL 0x00002000
11227 +/** Sleep/Wakeup Source GPONE
11228 +    Selects the FIFO empty signal of the EGRESS FIFO of port GPON as sleep/wakeup source. */
11229 +#define SYS_GPE_SSCFG_GPONE 0x00001000
11230 +/* Not selected
11231 +#define SYS_GPE_SSCFG_GPONE_NSEL 0x00000000 */
11232 +/** Selected */
11233 +#define SYS_GPE_SSCFG_GPONE_SEL 0x00001000
11234 +/** Sleep/Wakeup Source LAN3E
11235 +    Selects the FIFO empty signal of the EGRESS FIFO of port LAN3 as sleep/wakeup source. */
11236 +#define SYS_GPE_SSCFG_LAN3E 0x00000800
11237 +/* Not selected
11238 +#define SYS_GPE_SSCFG_LAN3E_NSEL 0x00000000 */
11239 +/** Selected */
11240 +#define SYS_GPE_SSCFG_LAN3E_SEL 0x00000800
11241 +/** Sleep/Wakeup Source LAN2E
11242 +    Selects the FIFO empty signal of the EGRESS FIFO of port LAN2 as sleep/wakeup source. */
11243 +#define SYS_GPE_SSCFG_LAN2E 0x00000400
11244 +/* Not selected
11245 +#define SYS_GPE_SSCFG_LAN2E_NSEL 0x00000000 */
11246 +/** Selected */
11247 +#define SYS_GPE_SSCFG_LAN2E_SEL 0x00000400
11248 +/** Sleep/Wakeup Source LAN1E
11249 +    Selects the FIFO empty signal of the EGRESS FIFO of port LAN1 as sleep/wakeup source. */
11250 +#define SYS_GPE_SSCFG_LAN1E 0x00000200
11251 +/* Not selected
11252 +#define SYS_GPE_SSCFG_LAN1E_NSEL 0x00000000 */
11253 +/** Selected */
11254 +#define SYS_GPE_SSCFG_LAN1E_SEL 0x00000200
11255 +/** Sleep/Wakeup Source LAN0E
11256 +    Selects the FIFO empty signal of the EGRESS FIFO of port LAN0 as sleep/wakeup source. */
11257 +#define SYS_GPE_SSCFG_LAN0E 0x00000100
11258 +/* Not selected
11259 +#define SYS_GPE_SSCFG_LAN0E_NSEL 0x00000000 */
11260 +/** Selected */
11261 +#define SYS_GPE_SSCFG_LAN0E_SEL 0x00000100
11262 +/** Sleep/Wakeup Source GPONI
11263 +    Selects the FIFO empty signal of the INGRESS FIFO of port GPON as sleep/wakeup source. */
11264 +#define SYS_GPE_SSCFG_GPONI 0x00000010
11265 +/* Not selected
11266 +#define SYS_GPE_SSCFG_GPONI_NSEL 0x00000000 */
11267 +/** Selected */
11268 +#define SYS_GPE_SSCFG_GPONI_SEL 0x00000010
11269 +/** Sleep/Wakeup Source LAN3I
11270 +    Selects the FIFO empty signal of the INGRESS FIFO of port LAN3 as sleep/wakeup source. */
11271 +#define SYS_GPE_SSCFG_LAN3I 0x00000008
11272 +/* Not selected
11273 +#define SYS_GPE_SSCFG_LAN3I_NSEL 0x00000000 */
11274 +/** Selected */
11275 +#define SYS_GPE_SSCFG_LAN3I_SEL 0x00000008
11276 +/** Sleep/Wakeup Source LAN2I
11277 +    Selects the FIFO empty signal of the INGRESS FIFO of port LAN2 as sleep/wakeup source. */
11278 +#define SYS_GPE_SSCFG_LAN2I 0x00000004
11279 +/* Not selected
11280 +#define SYS_GPE_SSCFG_LAN2I_NSEL 0x00000000 */
11281 +/** Selected */
11282 +#define SYS_GPE_SSCFG_LAN2I_SEL 0x00000004
11283 +/** Sleep/Wakeup Source LAN1I
11284 +    Selects the FIFO empty signal of the INGRESS FIFO of port LAN1 as sleep/wakeup source. */
11285 +#define SYS_GPE_SSCFG_LAN1I 0x00000002
11286 +/* Not selected
11287 +#define SYS_GPE_SSCFG_LAN1I_NSEL 0x00000000 */
11288 +/** Selected */
11289 +#define SYS_GPE_SSCFG_LAN1I_SEL 0x00000002
11290 +/** Sleep/Wakeup Source LAN0I
11291 +    Selects the FIFO empty signal of the INGRESS FIFO of port LAN0 as sleep/wakeup source. */
11292 +#define SYS_GPE_SSCFG_LAN0I 0x00000001
11293 +/* Not selected
11294 +#define SYS_GPE_SSCFG_LAN0I_NSEL 0x00000000 */
11295 +/** Selected */
11296 +#define SYS_GPE_SSCFG_LAN0I_SEL 0x00000001
11297 +
11298 +/* Fields of "Sleep Source Timer Register" */
11299 +/** Sleep Delay Value
11300 +    A HW sleep request is delayed by this value multiplied by 3.2ns before it takes effect. A wakeup request is not delayed but takes effect immediately. Values lower than 256 are limited to 256. */
11301 +#define SYS_GPE_SST_SDV_MASK 0x7FFFFFFF
11302 +/** field offset */
11303 +#define SYS_GPE_SST_SDV_OFFSET 0
11304 +
11305 +/* Fields of "Sleep Destination Status Register" */
11306 +/** Shutoff COP7 on HW Sleep
11307 +    If selected the domain COP7 is shutoff on a hardware sleep request. This domain contains the Coprocessor 7 of the SCE. */
11308 +#define SYS_GPE_SDS_COP7 0x80000000
11309 +/* Not selected
11310 +#define SYS_GPE_SDS_COP7_NSEL 0x00000000 */
11311 +/** Selected */
11312 +#define SYS_GPE_SDS_COP7_SEL 0x80000000
11313 +/** Shutoff COP6 on HW Sleep
11314 +    If selected the domain COP6 is shutoff on a hardware sleep request. This domain contains the Coprocessor 6 of the SCE. */
11315 +#define SYS_GPE_SDS_COP6 0x40000000
11316 +/* Not selected
11317 +#define SYS_GPE_SDS_COP6_NSEL 0x00000000 */
11318 +/** Selected */
11319 +#define SYS_GPE_SDS_COP6_SEL 0x40000000
11320 +/** Shutoff COP5 on HW Sleep
11321 +    If selected the domain COP5 is shutoff on a hardware sleep request. This domain contains the Coprocessor 5 of the SCE. */
11322 +#define SYS_GPE_SDS_COP5 0x20000000
11323 +/* Not selected
11324 +#define SYS_GPE_SDS_COP5_NSEL 0x00000000 */
11325 +/** Selected */
11326 +#define SYS_GPE_SDS_COP5_SEL 0x20000000
11327 +/** Shutoff COP4 on HW Sleep
11328 +    If selected the domain COP4 is shutoff on a hardware sleep request. This domain contains the Coprocessor 4 of the SCE. */
11329 +#define SYS_GPE_SDS_COP4 0x10000000
11330 +/* Not selected
11331 +#define SYS_GPE_SDS_COP4_NSEL 0x00000000 */
11332 +/** Selected */
11333 +#define SYS_GPE_SDS_COP4_SEL 0x10000000
11334 +/** Shutoff COP3 on HW Sleep
11335 +    If selected the domain COP3 is shutoff on a hardware sleep request. This domain contains the Coprocessor 3 of the SCE. */
11336 +#define SYS_GPE_SDS_COP3 0x08000000
11337 +/* Not selected
11338 +#define SYS_GPE_SDS_COP3_NSEL 0x00000000 */
11339 +/** Selected */
11340 +#define SYS_GPE_SDS_COP3_SEL 0x08000000
11341 +/** Shutoff COP2 on HW Sleep
11342 +    If selected the domain COP2 is shutoff on a hardware sleep request. This domain contains the Coprocessor 2 of the SCE. */
11343 +#define SYS_GPE_SDS_COP2 0x04000000
11344 +/* Not selected
11345 +#define SYS_GPE_SDS_COP2_NSEL 0x00000000 */
11346 +/** Selected */
11347 +#define SYS_GPE_SDS_COP2_SEL 0x04000000
11348 +/** Shutoff COP1 on HW Sleep
11349 +    If selected the domain COP1 is shutoff on a hardware sleep request. This domain contains the Coprocessor 1 of the SCE. */
11350 +#define SYS_GPE_SDS_COP1 0x02000000
11351 +/* Not selected
11352 +#define SYS_GPE_SDS_COP1_NSEL 0x00000000 */
11353 +/** Selected */
11354 +#define SYS_GPE_SDS_COP1_SEL 0x02000000
11355 +/** Shutoff COP0 on HW Sleep
11356 +    If selected the domain COP0 is shutoff on a hardware sleep request. This domain contains the Coprocessor 0 of the SCE. */
11357 +#define SYS_GPE_SDS_COP0 0x01000000
11358 +/* Not selected
11359 +#define SYS_GPE_SDS_COP0_NSEL 0x00000000 */
11360 +/** Selected */
11361 +#define SYS_GPE_SDS_COP0_SEL 0x01000000
11362 +/** Shutoff PE5 on HW Sleep
11363 +    If selected the domain PE5 is shutoff on a hardware sleep request. This domain contains the Processing Element 5 of the SCE. */
11364 +#define SYS_GPE_SDS_PE5 0x00200000
11365 +/* Not selected
11366 +#define SYS_GPE_SDS_PE5_NSEL 0x00000000 */
11367 +/** Selected */
11368 +#define SYS_GPE_SDS_PE5_SEL 0x00200000
11369 +/** Shutoff PE4 on HW Sleep
11370 +    If selected the domain PE4 is shutoff on a hardware sleep request. This domain contains the Processing Element 4 of the SCE. */
11371 +#define SYS_GPE_SDS_PE4 0x00100000
11372 +/* Not selected
11373 +#define SYS_GPE_SDS_PE4_NSEL 0x00000000 */
11374 +/** Selected */
11375 +#define SYS_GPE_SDS_PE4_SEL 0x00100000
11376 +/** Shutoff PE3 on HW Sleep
11377 +    If selected the domain PE3 is shutoff on a hardware sleep request. This domain contains the Processing Element 3 of the SCE. */
11378 +#define SYS_GPE_SDS_PE3 0x00080000
11379 +/* Not selected
11380 +#define SYS_GPE_SDS_PE3_NSEL 0x00000000 */
11381 +/** Selected */
11382 +#define SYS_GPE_SDS_PE3_SEL 0x00080000
11383 +/** Shutoff PE2 on HW Sleep
11384 +    If selected the domain PE2 is shutoff on a hardware sleep request. This domain contains the Processing Element 2 of the SCE. */
11385 +#define SYS_GPE_SDS_PE2 0x00040000
11386 +/* Not selected
11387 +#define SYS_GPE_SDS_PE2_NSEL 0x00000000 */
11388 +/** Selected */
11389 +#define SYS_GPE_SDS_PE2_SEL 0x00040000
11390 +/** Shutoff PE1 on HW Sleep
11391 +    If selected the domain PE1 is shutoff on a hardware sleep request. This domain contains the Processing Element 1 of the SCE. */
11392 +#define SYS_GPE_SDS_PE1 0x00020000
11393 +/* Not selected
11394 +#define SYS_GPE_SDS_PE1_NSEL 0x00000000 */
11395 +/** Selected */
11396 +#define SYS_GPE_SDS_PE1_SEL 0x00020000
11397 +/** Shutoff PE0 on HW Sleep
11398 +    If selected the domain PE0 is shutoff on a hardware sleep request. This domain contains the Processing Element 0 of the SCE. */
11399 +#define SYS_GPE_SDS_PE0 0x00010000
11400 +/* Not selected
11401 +#define SYS_GPE_SDS_PE0_NSEL 0x00000000 */
11402 +/** Selected */
11403 +#define SYS_GPE_SDS_PE0_SEL 0x00010000
11404 +/** Shutoff ARB on HW Sleep
11405 +    If selected the domain ARB is shutoff on a hardware sleep request. This domain contains the Arbiter. */
11406 +#define SYS_GPE_SDS_ARB 0x00002000
11407 +/* Not selected
11408 +#define SYS_GPE_SDS_ARB_NSEL 0x00000000 */
11409 +/** Selected */
11410 +#define SYS_GPE_SDS_ARB_SEL 0x00002000
11411 +/** Shutoff FSQM on HW Sleep
11412 +    If selected the domain FSQM is shutoff on a hardware sleep request. This domain contains the FSQM. */
11413 +#define SYS_GPE_SDS_FSQM 0x00001000
11414 +/* Not selected
11415 +#define SYS_GPE_SDS_FSQM_NSEL 0x00000000 */
11416 +/** Selected */
11417 +#define SYS_GPE_SDS_FSQM_SEL 0x00001000
11418 +/** Shutoff TMU on HW Sleep
11419 +    If selected the domain TMU is shutoff on a hardware sleep request. This domain contains the TMU. */
11420 +#define SYS_GPE_SDS_TMU 0x00000800
11421 +/* Not selected
11422 +#define SYS_GPE_SDS_TMU_NSEL 0x00000000 */
11423 +/** Selected */
11424 +#define SYS_GPE_SDS_TMU_SEL 0x00000800
11425 +/** Shutoff MRG on HW Sleep
11426 +    If selected the domain MRG is shutoff on a hardware sleep request. This domain contains the Merger. */
11427 +#define SYS_GPE_SDS_MRG 0x00000400
11428 +/* Not selected
11429 +#define SYS_GPE_SDS_MRG_NSEL 0x00000000 */
11430 +/** Selected */
11431 +#define SYS_GPE_SDS_MRG_SEL 0x00000400
11432 +/** Shutoff DISP on HW Sleep
11433 +    If selected the domain DISP is shutoff on a hardware sleep request. This domain contains the Dispatcher. */
11434 +#define SYS_GPE_SDS_DISP 0x00000200
11435 +/* Not selected
11436 +#define SYS_GPE_SDS_DISP_NSEL 0x00000000 */
11437 +/** Selected */
11438 +#define SYS_GPE_SDS_DISP_SEL 0x00000200
11439 +/** Shutoff IQM on HW Sleep
11440 +    If selected the domain IQM is shutoff on a hardware sleep request. This domain contains the IQM. */
11441 +#define SYS_GPE_SDS_IQM 0x00000100
11442 +/* Not selected
11443 +#define SYS_GPE_SDS_IQM_NSEL 0x00000000 */
11444 +/** Selected */
11445 +#define SYS_GPE_SDS_IQM_SEL 0x00000100
11446 +/** Shutoff CPUE on HW Sleep
11447 +    If selected the domain CPUE is shutoff on a hardware sleep request. This domain contains all parts related to the CPU EGRESS interface. */
11448 +#define SYS_GPE_SDS_CPUE 0x00000080
11449 +/* Not selected
11450 +#define SYS_GPE_SDS_CPUE_NSEL 0x00000000 */
11451 +/** Selected */
11452 +#define SYS_GPE_SDS_CPUE_SEL 0x00000080
11453 +/** Shutoff CPUI on HW Sleep
11454 +    If selected the domain CPUI is shutoff on a hardware sleep request. This domain contains all parts related to the CPU INGRESS interface. */
11455 +#define SYS_GPE_SDS_CPUI 0x00000040
11456 +/* Not selected
11457 +#define SYS_GPE_SDS_CPUI_NSEL 0x00000000 */
11458 +/** Selected */
11459 +#define SYS_GPE_SDS_CPUI_SEL 0x00000040
11460 +/** Shutoff GPONE on HW Sleep
11461 +    If selected the domain GPONE is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
11462 +#define SYS_GPE_SDS_GPONE 0x00000020
11463 +/* Not selected
11464 +#define SYS_GPE_SDS_GPONE_NSEL 0x00000000 */
11465 +/** Selected */
11466 +#define SYS_GPE_SDS_GPONE_SEL 0x00000020
11467 +/** Shutoff GPONI on HW Sleep
11468 +    If selected the domain GPONI is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
11469 +#define SYS_GPE_SDS_GPONI 0x00000010
11470 +/* Not selected
11471 +#define SYS_GPE_SDS_GPONI_NSEL 0x00000000 */
11472 +/** Selected */
11473 +#define SYS_GPE_SDS_GPONI_SEL 0x00000010
11474 +/** Shutoff LAN3 on HW Sleep
11475 +    If selected the domain LAN3 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN3 interface. */
11476 +#define SYS_GPE_SDS_LAN3 0x00000008
11477 +/* Not selected
11478 +#define SYS_GPE_SDS_LAN3_NSEL 0x00000000 */
11479 +/** Selected */
11480 +#define SYS_GPE_SDS_LAN3_SEL 0x00000008
11481 +/** Shutoff LAN2 on HW Sleep
11482 +    If selected the domain LAN2 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN2 interface. */
11483 +#define SYS_GPE_SDS_LAN2 0x00000004
11484 +/* Not selected
11485 +#define SYS_GPE_SDS_LAN2_NSEL 0x00000000 */
11486 +/** Selected */
11487 +#define SYS_GPE_SDS_LAN2_SEL 0x00000004
11488 +/** Shutoff LAN1 on HW Sleep
11489 +    If selected the domain LAN1 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN1 interface. */
11490 +#define SYS_GPE_SDS_LAN1 0x00000002
11491 +/* Not selected
11492 +#define SYS_GPE_SDS_LAN1_NSEL 0x00000000 */
11493 +/** Selected */
11494 +#define SYS_GPE_SDS_LAN1_SEL 0x00000002
11495 +/** Shutoff LAN0 on HW Sleep
11496 +    If selected the domain LAN0 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN0 interface. */
11497 +#define SYS_GPE_SDS_LAN0 0x00000001
11498 +/* Not selected
11499 +#define SYS_GPE_SDS_LAN0_NSEL 0x00000000 */
11500 +/** Selected */
11501 +#define SYS_GPE_SDS_LAN0_SEL 0x00000001
11502 +
11503 +/* Fields of "Sleep Destination Set Register" */
11504 +/** Set Sleep Selection COP7
11505 +    Sets the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */
11506 +#define SYS_GPE_SDSET_COP7 0x80000000
11507 +/* No-Operation
11508 +#define SYS_GPE_SDSET_COP7_NOP 0x00000000 */
11509 +/** Set */
11510 +#define SYS_GPE_SDSET_COP7_SET 0x80000000
11511 +/** Set Sleep Selection COP6
11512 +    Sets the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */
11513 +#define SYS_GPE_SDSET_COP6 0x40000000
11514 +/* No-Operation
11515 +#define SYS_GPE_SDSET_COP6_NOP 0x00000000 */
11516 +/** Set */
11517 +#define SYS_GPE_SDSET_COP6_SET 0x40000000
11518 +/** Set Sleep Selection COP5
11519 +    Sets the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */
11520 +#define SYS_GPE_SDSET_COP5 0x20000000
11521 +/* No-Operation
11522 +#define SYS_GPE_SDSET_COP5_NOP 0x00000000 */
11523 +/** Set */
11524 +#define SYS_GPE_SDSET_COP5_SET 0x20000000
11525 +/** Set Sleep Selection COP4
11526 +    Sets the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */
11527 +#define SYS_GPE_SDSET_COP4 0x10000000
11528 +/* No-Operation
11529 +#define SYS_GPE_SDSET_COP4_NOP 0x00000000 */
11530 +/** Set */
11531 +#define SYS_GPE_SDSET_COP4_SET 0x10000000
11532 +/** Set Sleep Selection COP3
11533 +    Sets the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */
11534 +#define SYS_GPE_SDSET_COP3 0x08000000
11535 +/* No-Operation
11536 +#define SYS_GPE_SDSET_COP3_NOP 0x00000000 */
11537 +/** Set */
11538 +#define SYS_GPE_SDSET_COP3_SET 0x08000000
11539 +/** Set Sleep Selection COP2
11540 +    Sets the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */
11541 +#define SYS_GPE_SDSET_COP2 0x04000000
11542 +/* No-Operation
11543 +#define SYS_GPE_SDSET_COP2_NOP 0x00000000 */
11544 +/** Set */
11545 +#define SYS_GPE_SDSET_COP2_SET 0x04000000
11546 +/** Set Sleep Selection COP1
11547 +    Sets the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */
11548 +#define SYS_GPE_SDSET_COP1 0x02000000
11549 +/* No-Operation
11550 +#define SYS_GPE_SDSET_COP1_NOP 0x00000000 */
11551 +/** Set */
11552 +#define SYS_GPE_SDSET_COP1_SET 0x02000000
11553 +/** Set Sleep Selection COP0
11554 +    Sets the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */
11555 +#define SYS_GPE_SDSET_COP0 0x01000000
11556 +/* No-Operation
11557 +#define SYS_GPE_SDSET_COP0_NOP 0x00000000 */
11558 +/** Set */
11559 +#define SYS_GPE_SDSET_COP0_SET 0x01000000
11560 +/** Set Sleep Selection PE5
11561 +    Sets the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */
11562 +#define SYS_GPE_SDSET_PE5 0x00200000
11563 +/* No-Operation
11564 +#define SYS_GPE_SDSET_PE5_NOP 0x00000000 */
11565 +/** Set */
11566 +#define SYS_GPE_SDSET_PE5_SET 0x00200000
11567 +/** Set Sleep Selection PE4
11568 +    Sets the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */
11569 +#define SYS_GPE_SDSET_PE4 0x00100000
11570 +/* No-Operation
11571 +#define SYS_GPE_SDSET_PE4_NOP 0x00000000 */
11572 +/** Set */
11573 +#define SYS_GPE_SDSET_PE4_SET 0x00100000
11574 +/** Set Sleep Selection PE3
11575 +    Sets the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */
11576 +#define SYS_GPE_SDSET_PE3 0x00080000
11577 +/* No-Operation
11578 +#define SYS_GPE_SDSET_PE3_NOP 0x00000000 */
11579 +/** Set */
11580 +#define SYS_GPE_SDSET_PE3_SET 0x00080000
11581 +/** Set Sleep Selection PE2
11582 +    Sets the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */
11583 +#define SYS_GPE_SDSET_PE2 0x00040000
11584 +/* No-Operation
11585 +#define SYS_GPE_SDSET_PE2_NOP 0x00000000 */
11586 +/** Set */
11587 +#define SYS_GPE_SDSET_PE2_SET 0x00040000
11588 +/** Set Sleep Selection PE1
11589 +    Sets the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */
11590 +#define SYS_GPE_SDSET_PE1 0x00020000
11591 +/* No-Operation
11592 +#define SYS_GPE_SDSET_PE1_NOP 0x00000000 */
11593 +/** Set */
11594 +#define SYS_GPE_SDSET_PE1_SET 0x00020000
11595 +/** Set Sleep Selection PE0
11596 +    Sets the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */
11597 +#define SYS_GPE_SDSET_PE0 0x00010000
11598 +/* No-Operation
11599 +#define SYS_GPE_SDSET_PE0_NOP 0x00000000 */
11600 +/** Set */
11601 +#define SYS_GPE_SDSET_PE0_SET 0x00010000
11602 +/** Set Sleep Selection ARB
11603 +    Sets the selection bit for domain ARBThis domain contains the Arbiter. */
11604 +#define SYS_GPE_SDSET_ARB 0x00002000
11605 +/* No-Operation
11606 +#define SYS_GPE_SDSET_ARB_NOP 0x00000000 */
11607 +/** Set */
11608 +#define SYS_GPE_SDSET_ARB_SET 0x00002000
11609 +/** Set Sleep Selection FSQM
11610 +    Sets the selection bit for domain FSQMThis domain contains the FSQM. */
11611 +#define SYS_GPE_SDSET_FSQM 0x00001000
11612 +/* No-Operation
11613 +#define SYS_GPE_SDSET_FSQM_NOP 0x00000000 */
11614 +/** Set */
11615 +#define SYS_GPE_SDSET_FSQM_SET 0x00001000
11616 +/** Set Sleep Selection TMU
11617 +    Sets the selection bit for domain TMUThis domain contains the TMU. */
11618 +#define SYS_GPE_SDSET_TMU 0x00000800
11619 +/* No-Operation
11620 +#define SYS_GPE_SDSET_TMU_NOP 0x00000000 */
11621 +/** Set */
11622 +#define SYS_GPE_SDSET_TMU_SET 0x00000800
11623 +/** Set Sleep Selection MRG
11624 +    Sets the selection bit for domain MRGThis domain contains the Merger. */
11625 +#define SYS_GPE_SDSET_MRG 0x00000400
11626 +/* No-Operation
11627 +#define SYS_GPE_SDSET_MRG_NOP 0x00000000 */
11628 +/** Set */
11629 +#define SYS_GPE_SDSET_MRG_SET 0x00000400
11630 +/** Set Sleep Selection DISP
11631 +    Sets the selection bit for domain DISPThis domain contains the Dispatcher. */
11632 +#define SYS_GPE_SDSET_DISP 0x00000200
11633 +/* No-Operation
11634 +#define SYS_GPE_SDSET_DISP_NOP 0x00000000 */
11635 +/** Set */
11636 +#define SYS_GPE_SDSET_DISP_SET 0x00000200
11637 +/** Set Sleep Selection IQM
11638 +    Sets the selection bit for domain IQMThis domain contains the IQM. */
11639 +#define SYS_GPE_SDSET_IQM 0x00000100
11640 +/* No-Operation
11641 +#define SYS_GPE_SDSET_IQM_NOP 0x00000000 */
11642 +/** Set */
11643 +#define SYS_GPE_SDSET_IQM_SET 0x00000100
11644 +/** Set Sleep Selection CPUE
11645 +    Sets the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */
11646 +#define SYS_GPE_SDSET_CPUE 0x00000080
11647 +/* No-Operation
11648 +#define SYS_GPE_SDSET_CPUE_NOP 0x00000000 */
11649 +/** Set */
11650 +#define SYS_GPE_SDSET_CPUE_SET 0x00000080
11651 +/** Set Sleep Selection CPUI
11652 +    Sets the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */
11653 +#define SYS_GPE_SDSET_CPUI 0x00000040
11654 +/* No-Operation
11655 +#define SYS_GPE_SDSET_CPUI_NOP 0x00000000 */
11656 +/** Set */
11657 +#define SYS_GPE_SDSET_CPUI_SET 0x00000040
11658 +/** Set Sleep Selection GPONE
11659 +    Sets the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */
11660 +#define SYS_GPE_SDSET_GPONE 0x00000020
11661 +/* No-Operation
11662 +#define SYS_GPE_SDSET_GPONE_NOP 0x00000000 */
11663 +/** Set */
11664 +#define SYS_GPE_SDSET_GPONE_SET 0x00000020
11665 +/** Set Sleep Selection GPONI
11666 +    Sets the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */
11667 +#define SYS_GPE_SDSET_GPONI 0x00000010
11668 +/* No-Operation
11669 +#define SYS_GPE_SDSET_GPONI_NOP 0x00000000 */
11670 +/** Set */
11671 +#define SYS_GPE_SDSET_GPONI_SET 0x00000010
11672 +/** Set Sleep Selection LAN3
11673 +    Sets the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */
11674 +#define SYS_GPE_SDSET_LAN3 0x00000008
11675 +/* No-Operation
11676 +#define SYS_GPE_SDSET_LAN3_NOP 0x00000000 */
11677 +/** Set */
11678 +#define SYS_GPE_SDSET_LAN3_SET 0x00000008
11679 +/** Set Sleep Selection LAN2
11680 +    Sets the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */
11681 +#define SYS_GPE_SDSET_LAN2 0x00000004
11682 +/* No-Operation
11683 +#define SYS_GPE_SDSET_LAN2_NOP 0x00000000 */
11684 +/** Set */
11685 +#define SYS_GPE_SDSET_LAN2_SET 0x00000004
11686 +/** Set Sleep Selection LAN1
11687 +    Sets the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */
11688 +#define SYS_GPE_SDSET_LAN1 0x00000002
11689 +/* No-Operation
11690 +#define SYS_GPE_SDSET_LAN1_NOP 0x00000000 */
11691 +/** Set */
11692 +#define SYS_GPE_SDSET_LAN1_SET 0x00000002
11693 +/** Set Sleep Selection LAN0
11694 +    Sets the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */
11695 +#define SYS_GPE_SDSET_LAN0 0x00000001
11696 +/* No-Operation
11697 +#define SYS_GPE_SDSET_LAN0_NOP 0x00000000 */
11698 +/** Set */
11699 +#define SYS_GPE_SDSET_LAN0_SET 0x00000001
11700 +
11701 +/* Fields of "Sleep Destination Clear Register" */
11702 +/** Clear Sleep Selection COP7
11703 +    Clears the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */
11704 +#define SYS_GPE_SDCLR_COP7 0x80000000
11705 +/* No-Operation
11706 +#define SYS_GPE_SDCLR_COP7_NOP 0x00000000 */
11707 +/** Clear */
11708 +#define SYS_GPE_SDCLR_COP7_CLR 0x80000000
11709 +/** Clear Sleep Selection COP6
11710 +    Clears the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */
11711 +#define SYS_GPE_SDCLR_COP6 0x40000000
11712 +/* No-Operation
11713 +#define SYS_GPE_SDCLR_COP6_NOP 0x00000000 */
11714 +/** Clear */
11715 +#define SYS_GPE_SDCLR_COP6_CLR 0x40000000
11716 +/** Clear Sleep Selection COP5
11717 +    Clears the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */
11718 +#define SYS_GPE_SDCLR_COP5 0x20000000
11719 +/* No-Operation
11720 +#define SYS_GPE_SDCLR_COP5_NOP 0x00000000 */
11721 +/** Clear */
11722 +#define SYS_GPE_SDCLR_COP5_CLR 0x20000000
11723 +/** Clear Sleep Selection COP4
11724 +    Clears the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */
11725 +#define SYS_GPE_SDCLR_COP4 0x10000000
11726 +/* No-Operation
11727 +#define SYS_GPE_SDCLR_COP4_NOP 0x00000000 */
11728 +/** Clear */
11729 +#define SYS_GPE_SDCLR_COP4_CLR 0x10000000
11730 +/** Clear Sleep Selection COP3
11731 +    Clears the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */
11732 +#define SYS_GPE_SDCLR_COP3 0x08000000
11733 +/* No-Operation
11734 +#define SYS_GPE_SDCLR_COP3_NOP 0x00000000 */
11735 +/** Clear */
11736 +#define SYS_GPE_SDCLR_COP3_CLR 0x08000000
11737 +/** Clear Sleep Selection COP2
11738 +    Clears the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */
11739 +#define SYS_GPE_SDCLR_COP2 0x04000000
11740 +/* No-Operation
11741 +#define SYS_GPE_SDCLR_COP2_NOP 0x00000000 */
11742 +/** Clear */
11743 +#define SYS_GPE_SDCLR_COP2_CLR 0x04000000
11744 +/** Clear Sleep Selection COP1
11745 +    Clears the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */
11746 +#define SYS_GPE_SDCLR_COP1 0x02000000
11747 +/* No-Operation
11748 +#define SYS_GPE_SDCLR_COP1_NOP 0x00000000 */
11749 +/** Clear */
11750 +#define SYS_GPE_SDCLR_COP1_CLR 0x02000000
11751 +/** Clear Sleep Selection COP0
11752 +    Clears the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */
11753 +#define SYS_GPE_SDCLR_COP0 0x01000000
11754 +/* No-Operation
11755 +#define SYS_GPE_SDCLR_COP0_NOP 0x00000000 */
11756 +/** Clear */
11757 +#define SYS_GPE_SDCLR_COP0_CLR 0x01000000
11758 +/** Clear Sleep Selection PE5
11759 +    Clears the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */
11760 +#define SYS_GPE_SDCLR_PE5 0x00200000
11761 +/* No-Operation
11762 +#define SYS_GPE_SDCLR_PE5_NOP 0x00000000 */
11763 +/** Clear */
11764 +#define SYS_GPE_SDCLR_PE5_CLR 0x00200000
11765 +/** Clear Sleep Selection PE4
11766 +    Clears the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */
11767 +#define SYS_GPE_SDCLR_PE4 0x00100000
11768 +/* No-Operation
11769 +#define SYS_GPE_SDCLR_PE4_NOP 0x00000000 */
11770 +/** Clear */
11771 +#define SYS_GPE_SDCLR_PE4_CLR 0x00100000
11772 +/** Clear Sleep Selection PE3
11773 +    Clears the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */
11774 +#define SYS_GPE_SDCLR_PE3 0x00080000
11775 +/* No-Operation
11776 +#define SYS_GPE_SDCLR_PE3_NOP 0x00000000 */
11777 +/** Clear */
11778 +#define SYS_GPE_SDCLR_PE3_CLR 0x00080000
11779 +/** Clear Sleep Selection PE2
11780 +    Clears the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */
11781 +#define SYS_GPE_SDCLR_PE2 0x00040000
11782 +/* No-Operation
11783 +#define SYS_GPE_SDCLR_PE2_NOP 0x00000000 */
11784 +/** Clear */
11785 +#define SYS_GPE_SDCLR_PE2_CLR 0x00040000
11786 +/** Clear Sleep Selection PE1
11787 +    Clears the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */
11788 +#define SYS_GPE_SDCLR_PE1 0x00020000
11789 +/* No-Operation
11790 +#define SYS_GPE_SDCLR_PE1_NOP 0x00000000 */
11791 +/** Clear */
11792 +#define SYS_GPE_SDCLR_PE1_CLR 0x00020000
11793 +/** Clear Sleep Selection PE0
11794 +    Clears the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */
11795 +#define SYS_GPE_SDCLR_PE0 0x00010000
11796 +/* No-Operation
11797 +#define SYS_GPE_SDCLR_PE0_NOP 0x00000000 */
11798 +/** Clear */
11799 +#define SYS_GPE_SDCLR_PE0_CLR 0x00010000
11800 +/** Clear Sleep Selection ARB
11801 +    Clears the selection bit for domain ARBThis domain contains the Arbiter. */
11802 +#define SYS_GPE_SDCLR_ARB 0x00002000
11803 +/* No-Operation
11804 +#define SYS_GPE_SDCLR_ARB_NOP 0x00000000 */
11805 +/** Clear */
11806 +#define SYS_GPE_SDCLR_ARB_CLR 0x00002000
11807 +/** Clear Sleep Selection FSQM
11808 +    Clears the selection bit for domain FSQMThis domain contains the FSQM. */
11809 +#define SYS_GPE_SDCLR_FSQM 0x00001000
11810 +/* No-Operation
11811 +#define SYS_GPE_SDCLR_FSQM_NOP 0x00000000 */
11812 +/** Clear */
11813 +#define SYS_GPE_SDCLR_FSQM_CLR 0x00001000
11814 +/** Clear Sleep Selection TMU
11815 +    Clears the selection bit for domain TMUThis domain contains the TMU. */
11816 +#define SYS_GPE_SDCLR_TMU 0x00000800
11817 +/* No-Operation
11818 +#define SYS_GPE_SDCLR_TMU_NOP 0x00000000 */
11819 +/** Clear */
11820 +#define SYS_GPE_SDCLR_TMU_CLR 0x00000800
11821 +/** Clear Sleep Selection MRG
11822 +    Clears the selection bit for domain MRGThis domain contains the Merger. */
11823 +#define SYS_GPE_SDCLR_MRG 0x00000400
11824 +/* No-Operation
11825 +#define SYS_GPE_SDCLR_MRG_NOP 0x00000000 */
11826 +/** Clear */
11827 +#define SYS_GPE_SDCLR_MRG_CLR 0x00000400
11828 +/** Clear Sleep Selection DISP
11829 +    Clears the selection bit for domain DISPThis domain contains the Dispatcher. */
11830 +#define SYS_GPE_SDCLR_DISP 0x00000200
11831 +/* No-Operation
11832 +#define SYS_GPE_SDCLR_DISP_NOP 0x00000000 */
11833 +/** Clear */
11834 +#define SYS_GPE_SDCLR_DISP_CLR 0x00000200
11835 +/** Clear Sleep Selection IQM
11836 +    Clears the selection bit for domain IQMThis domain contains the IQM. */
11837 +#define SYS_GPE_SDCLR_IQM 0x00000100
11838 +/* No-Operation
11839 +#define SYS_GPE_SDCLR_IQM_NOP 0x00000000 */
11840 +/** Clear */
11841 +#define SYS_GPE_SDCLR_IQM_CLR 0x00000100
11842 +/** Clear Sleep Selection CPUE
11843 +    Clears the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */
11844 +#define SYS_GPE_SDCLR_CPUE 0x00000080
11845 +/* No-Operation
11846 +#define SYS_GPE_SDCLR_CPUE_NOP 0x00000000 */
11847 +/** Clear */
11848 +#define SYS_GPE_SDCLR_CPUE_CLR 0x00000080
11849 +/** Clear Sleep Selection CPUI
11850 +    Clears the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */
11851 +#define SYS_GPE_SDCLR_CPUI 0x00000040
11852 +/* No-Operation
11853 +#define SYS_GPE_SDCLR_CPUI_NOP 0x00000000 */
11854 +/** Clear */
11855 +#define SYS_GPE_SDCLR_CPUI_CLR 0x00000040
11856 +/** Clear Sleep Selection GPONE
11857 +    Clears the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */
11858 +#define SYS_GPE_SDCLR_GPONE 0x00000020
11859 +/* No-Operation
11860 +#define SYS_GPE_SDCLR_GPONE_NOP 0x00000000 */
11861 +/** Clear */
11862 +#define SYS_GPE_SDCLR_GPONE_CLR 0x00000020
11863 +/** Clear Sleep Selection GPONI
11864 +    Clears the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */
11865 +#define SYS_GPE_SDCLR_GPONI 0x00000010
11866 +/* No-Operation
11867 +#define SYS_GPE_SDCLR_GPONI_NOP 0x00000000 */
11868 +/** Clear */
11869 +#define SYS_GPE_SDCLR_GPONI_CLR 0x00000010
11870 +/** Clear Sleep Selection LAN3
11871 +    Clears the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */
11872 +#define SYS_GPE_SDCLR_LAN3 0x00000008
11873 +/* No-Operation
11874 +#define SYS_GPE_SDCLR_LAN3_NOP 0x00000000 */
11875 +/** Clear */
11876 +#define SYS_GPE_SDCLR_LAN3_CLR 0x00000008
11877 +/** Clear Sleep Selection LAN2
11878 +    Clears the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */
11879 +#define SYS_GPE_SDCLR_LAN2 0x00000004
11880 +/* No-Operation
11881 +#define SYS_GPE_SDCLR_LAN2_NOP 0x00000000 */
11882 +/** Clear */
11883 +#define SYS_GPE_SDCLR_LAN2_CLR 0x00000004
11884 +/** Clear Sleep Selection LAN1
11885 +    Clears the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */
11886 +#define SYS_GPE_SDCLR_LAN1 0x00000002
11887 +/* No-Operation
11888 +#define SYS_GPE_SDCLR_LAN1_NOP 0x00000000 */
11889 +/** Clear */
11890 +#define SYS_GPE_SDCLR_LAN1_CLR 0x00000002
11891 +/** Clear Sleep Selection LAN0
11892 +    Clears the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */
11893 +#define SYS_GPE_SDCLR_LAN0 0x00000001
11894 +/* No-Operation
11895 +#define SYS_GPE_SDCLR_LAN0_NOP 0x00000000 */
11896 +/** Clear */
11897 +#define SYS_GPE_SDCLR_LAN0_CLR 0x00000001
11898 +
11899 +/* Fields of "IRNCS Capture Register" */
11900 +/** FSQM wakeup request
11901 +    The FSQM submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11902 +#define SYS_GPE_IRNCSCR_FSQMWR 0x80000000
11903 +/* Nothing
11904 +#define SYS_GPE_IRNCSCR_FSQMWR_NULL 0x00000000 */
11905 +/** Write: Acknowledge the interrupt. */
11906 +#define SYS_GPE_IRNCSCR_FSQMWR_INTACK 0x80000000
11907 +/** Read: Interrupt occurred. */
11908 +#define SYS_GPE_IRNCSCR_FSQMWR_INTOCC 0x80000000
11909 +/** GPONT wakeup request
11910 +    The TCONT Request FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11911 +#define SYS_GPE_IRNCSCR_GPONTWR 0x20000000
11912 +/* Nothing
11913 +#define SYS_GPE_IRNCSCR_GPONTWR_NULL 0x00000000 */
11914 +/** Write: Acknowledge the interrupt. */
11915 +#define SYS_GPE_IRNCSCR_GPONTWR_INTACK 0x20000000
11916 +/** Read: Interrupt occurred. */
11917 +#define SYS_GPE_IRNCSCR_GPONTWR_INTOCC 0x20000000
11918 +/** GPONE wakeup request
11919 +    The EGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11920 +#define SYS_GPE_IRNCSCR_GPONEWR 0x10000000
11921 +/* Nothing
11922 +#define SYS_GPE_IRNCSCR_GPONEWR_NULL 0x00000000 */
11923 +/** Write: Acknowledge the interrupt. */
11924 +#define SYS_GPE_IRNCSCR_GPONEWR_INTACK 0x10000000
11925 +/** Read: Interrupt occurred. */
11926 +#define SYS_GPE_IRNCSCR_GPONEWR_INTOCC 0x10000000
11927 +/** LAN3E wakeup request
11928 +    The EGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11929 +#define SYS_GPE_IRNCSCR_LAN3EWR 0x08000000
11930 +/* Nothing
11931 +#define SYS_GPE_IRNCSCR_LAN3EWR_NULL 0x00000000 */
11932 +/** Write: Acknowledge the interrupt. */
11933 +#define SYS_GPE_IRNCSCR_LAN3EWR_INTACK 0x08000000
11934 +/** Read: Interrupt occurred. */
11935 +#define SYS_GPE_IRNCSCR_LAN3EWR_INTOCC 0x08000000
11936 +/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
11937 +    This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11938 +#define SYS_GPE_IRNCSCR_LAN2EWR 0x04000000
11939 +/* Nothing
11940 +#define SYS_GPE_IRNCSCR_LAN2EWR_NULL 0x00000000 */
11941 +/** Write: Acknowledge the interrupt. */
11942 +#define SYS_GPE_IRNCSCR_LAN2EWR_INTACK 0x04000000
11943 +/** Read: Interrupt occurred. */
11944 +#define SYS_GPE_IRNCSCR_LAN2EWR_INTOCC 0x04000000
11945 +/** LAN1E wakeup request
11946 +    The EGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11947 +#define SYS_GPE_IRNCSCR_LAN1EWR 0x02000000
11948 +/* Nothing
11949 +#define SYS_GPE_IRNCSCR_LAN1EWR_NULL 0x00000000 */
11950 +/** Write: Acknowledge the interrupt. */
11951 +#define SYS_GPE_IRNCSCR_LAN1EWR_INTACK 0x02000000
11952 +/** Read: Interrupt occurred. */
11953 +#define SYS_GPE_IRNCSCR_LAN1EWR_INTOCC 0x02000000
11954 +/** LAN0E wakeup request
11955 +    The EGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11956 +#define SYS_GPE_IRNCSCR_LAN0EWR 0x01000000
11957 +/* Nothing
11958 +#define SYS_GPE_IRNCSCR_LAN0EWR_NULL 0x00000000 */
11959 +/** Write: Acknowledge the interrupt. */
11960 +#define SYS_GPE_IRNCSCR_LAN0EWR_INTACK 0x01000000
11961 +/** Read: Interrupt occurred. */
11962 +#define SYS_GPE_IRNCSCR_LAN0EWR_INTOCC 0x01000000
11963 +/** GPONI wakeup request
11964 +    The INGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11965 +#define SYS_GPE_IRNCSCR_GPONIWR 0x00100000
11966 +/* Nothing
11967 +#define SYS_GPE_IRNCSCR_GPONIWR_NULL 0x00000000 */
11968 +/** Write: Acknowledge the interrupt. */
11969 +#define SYS_GPE_IRNCSCR_GPONIWR_INTACK 0x00100000
11970 +/** Read: Interrupt occurred. */
11971 +#define SYS_GPE_IRNCSCR_GPONIWR_INTOCC 0x00100000
11972 +/** LAN3I wakeup request
11973 +    The INGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11974 +#define SYS_GPE_IRNCSCR_LAN3IWR 0x00080000
11975 +/* Nothing
11976 +#define SYS_GPE_IRNCSCR_LAN3IWR_NULL 0x00000000 */
11977 +/** Write: Acknowledge the interrupt. */
11978 +#define SYS_GPE_IRNCSCR_LAN3IWR_INTACK 0x00080000
11979 +/** Read: Interrupt occurred. */
11980 +#define SYS_GPE_IRNCSCR_LAN3IWR_INTOCC 0x00080000
11981 +/** LAN2I wakeup request
11982 +    The INGRESS FIFO of port LAN2 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11983 +#define SYS_GPE_IRNCSCR_LAN2IWR 0x00040000
11984 +/* Nothing
11985 +#define SYS_GPE_IRNCSCR_LAN2IWR_NULL 0x00000000 */
11986 +/** Write: Acknowledge the interrupt. */
11987 +#define SYS_GPE_IRNCSCR_LAN2IWR_INTACK 0x00040000
11988 +/** Read: Interrupt occurred. */
11989 +#define SYS_GPE_IRNCSCR_LAN2IWR_INTOCC 0x00040000
11990 +/** LAN1I wakeup request
11991 +    The INGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
11992 +#define SYS_GPE_IRNCSCR_LAN1IWR 0x00020000
11993 +/* Nothing
11994 +#define SYS_GPE_IRNCSCR_LAN1IWR_NULL 0x00000000 */
11995 +/** Write: Acknowledge the interrupt. */
11996 +#define SYS_GPE_IRNCSCR_LAN1IWR_INTACK 0x00020000
11997 +/** Read: Interrupt occurred. */
11998 +#define SYS_GPE_IRNCSCR_LAN1IWR_INTOCC 0x00020000
11999 +/** LAN0I wakeup request
12000 +    The INGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12001 +#define SYS_GPE_IRNCSCR_LAN0IWR 0x00010000
12002 +/* Nothing
12003 +#define SYS_GPE_IRNCSCR_LAN0IWR_NULL 0x00000000 */
12004 +/** Write: Acknowledge the interrupt. */
12005 +#define SYS_GPE_IRNCSCR_LAN0IWR_INTACK 0x00010000
12006 +/** Read: Interrupt occurred. */
12007 +#define SYS_GPE_IRNCSCR_LAN0IWR_INTOCC 0x00010000
12008 +/** FSQM sleep request
12009 +    The FSQM submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12010 +#define SYS_GPE_IRNCSCR_FSQMSR 0x00008000
12011 +/* Nothing
12012 +#define SYS_GPE_IRNCSCR_FSQMSR_NULL 0x00000000 */
12013 +/** Write: Acknowledge the interrupt. */
12014 +#define SYS_GPE_IRNCSCR_FSQMSR_INTACK 0x00008000
12015 +/** Read: Interrupt occurred. */
12016 +#define SYS_GPE_IRNCSCR_FSQMSR_INTOCC 0x00008000
12017 +/** GPONT sleep request
12018 +    The TCONT Request FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12019 +#define SYS_GPE_IRNCSCR_GPONTSR 0x00002000
12020 +/* Nothing
12021 +#define SYS_GPE_IRNCSCR_GPONTSR_NULL 0x00000000 */
12022 +/** Write: Acknowledge the interrupt. */
12023 +#define SYS_GPE_IRNCSCR_GPONTSR_INTACK 0x00002000
12024 +/** Read: Interrupt occurred. */
12025 +#define SYS_GPE_IRNCSCR_GPONTSR_INTOCC 0x00002000
12026 +/** GPONE sleep request
12027 +    The EGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12028 +#define SYS_GPE_IRNCSCR_GPONESR 0x00001000
12029 +/* Nothing
12030 +#define SYS_GPE_IRNCSCR_GPONESR_NULL 0x00000000 */
12031 +/** Write: Acknowledge the interrupt. */
12032 +#define SYS_GPE_IRNCSCR_GPONESR_INTACK 0x00001000
12033 +/** Read: Interrupt occurred. */
12034 +#define SYS_GPE_IRNCSCR_GPONESR_INTOCC 0x00001000
12035 +/** LAN3E sleep request
12036 +    The EGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12037 +#define SYS_GPE_IRNCSCR_LAN3ESR 0x00000800
12038 +/* Nothing
12039 +#define SYS_GPE_IRNCSCR_LAN3ESR_NULL 0x00000000 */
12040 +/** Write: Acknowledge the interrupt. */
12041 +#define SYS_GPE_IRNCSCR_LAN3ESR_INTACK 0x00000800
12042 +/** Read: Interrupt occurred. */
12043 +#define SYS_GPE_IRNCSCR_LAN3ESR_INTOCC 0x00000800
12044 +/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
12045 +    This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12046 +#define SYS_GPE_IRNCSCR_LAN2ESR 0x00000400
12047 +/* Nothing
12048 +#define SYS_GPE_IRNCSCR_LAN2ESR_NULL 0x00000000 */
12049 +/** Write: Acknowledge the interrupt. */
12050 +#define SYS_GPE_IRNCSCR_LAN2ESR_INTACK 0x00000400
12051 +/** Read: Interrupt occurred. */
12052 +#define SYS_GPE_IRNCSCR_LAN2ESR_INTOCC 0x00000400
12053 +/** LAN1E sleep request
12054 +    The EGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12055 +#define SYS_GPE_IRNCSCR_LAN1ESR 0x00000200
12056 +/* Nothing
12057 +#define SYS_GPE_IRNCSCR_LAN1ESR_NULL 0x00000000 */
12058 +/** Write: Acknowledge the interrupt. */
12059 +#define SYS_GPE_IRNCSCR_LAN1ESR_INTACK 0x00000200
12060 +/** Read: Interrupt occurred. */
12061 +#define SYS_GPE_IRNCSCR_LAN1ESR_INTOCC 0x00000200
12062 +/** LAN0E sleep request
12063 +    The EGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12064 +#define SYS_GPE_IRNCSCR_LAN0ESR 0x00000100
12065 +/* Nothing
12066 +#define SYS_GPE_IRNCSCR_LAN0ESR_NULL 0x00000000 */
12067 +/** Write: Acknowledge the interrupt. */
12068 +#define SYS_GPE_IRNCSCR_LAN0ESR_INTACK 0x00000100
12069 +/** Read: Interrupt occurred. */
12070 +#define SYS_GPE_IRNCSCR_LAN0ESR_INTOCC 0x00000100
12071 +/** GPONI sleep request
12072 +    The INGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12073 +#define SYS_GPE_IRNCSCR_GPONISR 0x00000010
12074 +/* Nothing
12075 +#define SYS_GPE_IRNCSCR_GPONISR_NULL 0x00000000 */
12076 +/** Write: Acknowledge the interrupt. */
12077 +#define SYS_GPE_IRNCSCR_GPONISR_INTACK 0x00000010
12078 +/** Read: Interrupt occurred. */
12079 +#define SYS_GPE_IRNCSCR_GPONISR_INTOCC 0x00000010
12080 +/** LAN3I sleep request
12081 +    The INGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12082 +#define SYS_GPE_IRNCSCR_LAN3ISR 0x00000008
12083 +/* Nothing
12084 +#define SYS_GPE_IRNCSCR_LAN3ISR_NULL 0x00000000 */
12085 +/** Write: Acknowledge the interrupt. */
12086 +#define SYS_GPE_IRNCSCR_LAN3ISR_INTACK 0x00000008
12087 +/** Read: Interrupt occurred. */
12088 +#define SYS_GPE_IRNCSCR_LAN3ISR_INTOCC 0x00000008
12089 +/** LAN2I sleep request
12090 +    The INGRESS FIFO of port LAN2 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12091 +#define SYS_GPE_IRNCSCR_LAN2ISR 0x00000004
12092 +/* Nothing
12093 +#define SYS_GPE_IRNCSCR_LAN2ISR_NULL 0x00000000 */
12094 +/** Write: Acknowledge the interrupt. */
12095 +#define SYS_GPE_IRNCSCR_LAN2ISR_INTACK 0x00000004
12096 +/** Read: Interrupt occurred. */
12097 +#define SYS_GPE_IRNCSCR_LAN2ISR_INTOCC 0x00000004
12098 +/** LAN1I sleep request
12099 +    The INGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12100 +#define SYS_GPE_IRNCSCR_LAN1ISR 0x00000002
12101 +/* Nothing
12102 +#define SYS_GPE_IRNCSCR_LAN1ISR_NULL 0x00000000 */
12103 +/** Write: Acknowledge the interrupt. */
12104 +#define SYS_GPE_IRNCSCR_LAN1ISR_INTACK 0x00000002
12105 +/** Read: Interrupt occurred. */
12106 +#define SYS_GPE_IRNCSCR_LAN1ISR_INTOCC 0x00000002
12107 +/** LAN0I sleep request
12108 +    The INGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
12109 +#define SYS_GPE_IRNCSCR_LAN0ISR 0x00000001
12110 +/* Nothing
12111 +#define SYS_GPE_IRNCSCR_LAN0ISR_NULL 0x00000000 */
12112 +/** Write: Acknowledge the interrupt. */
12113 +#define SYS_GPE_IRNCSCR_LAN0ISR_INTACK 0x00000001
12114 +/** Read: Interrupt occurred. */
12115 +#define SYS_GPE_IRNCSCR_LAN0ISR_INTOCC 0x00000001
12116 +
12117 +/* Fields of "IRNCS Interrupt Control Register" */
12118 +/** FSQM wakeup request
12119 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12120 +#define SYS_GPE_IRNCSICR_FSQMWR 0x80000000
12121 +/** GPONT wakeup request
12122 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12123 +#define SYS_GPE_IRNCSICR_GPONTWR 0x20000000
12124 +/** GPONE wakeup request
12125 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12126 +#define SYS_GPE_IRNCSICR_GPONEWR 0x10000000
12127 +/** LAN3E wakeup request
12128 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12129 +#define SYS_GPE_IRNCSICR_LAN3EWR 0x08000000
12130 +/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
12131 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12132 +#define SYS_GPE_IRNCSICR_LAN2EWR 0x04000000
12133 +/** LAN1E wakeup request
12134 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12135 +#define SYS_GPE_IRNCSICR_LAN1EWR 0x02000000
12136 +/** LAN0E wakeup request
12137 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12138 +#define SYS_GPE_IRNCSICR_LAN0EWR 0x01000000
12139 +/** GPONI wakeup request
12140 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12141 +#define SYS_GPE_IRNCSICR_GPONIWR 0x00100000
12142 +/** LAN3I wakeup request
12143 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12144 +#define SYS_GPE_IRNCSICR_LAN3IWR 0x00080000
12145 +/** LAN2I wakeup request
12146 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12147 +#define SYS_GPE_IRNCSICR_LAN2IWR 0x00040000
12148 +/** LAN1I wakeup request
12149 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12150 +#define SYS_GPE_IRNCSICR_LAN1IWR 0x00020000
12151 +/** LAN0I wakeup request
12152 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12153 +#define SYS_GPE_IRNCSICR_LAN0IWR 0x00010000
12154 +/** FSQM sleep request
12155 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12156 +#define SYS_GPE_IRNCSICR_FSQMSR 0x00008000
12157 +/** GPONT sleep request
12158 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12159 +#define SYS_GPE_IRNCSICR_GPONTSR 0x00002000
12160 +/** GPONE sleep request
12161 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12162 +#define SYS_GPE_IRNCSICR_GPONESR 0x00001000
12163 +/** LAN3E sleep request
12164 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12165 +#define SYS_GPE_IRNCSICR_LAN3ESR 0x00000800
12166 +/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
12167 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12168 +#define SYS_GPE_IRNCSICR_LAN2ESR 0x00000400
12169 +/** LAN1E sleep request
12170 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12171 +#define SYS_GPE_IRNCSICR_LAN1ESR 0x00000200
12172 +/** LAN0E sleep request
12173 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12174 +#define SYS_GPE_IRNCSICR_LAN0ESR 0x00000100
12175 +/** GPONI sleep request
12176 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12177 +#define SYS_GPE_IRNCSICR_GPONISR 0x00000010
12178 +/** LAN3I sleep request
12179 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12180 +#define SYS_GPE_IRNCSICR_LAN3ISR 0x00000008
12181 +/** LAN2I sleep request
12182 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12183 +#define SYS_GPE_IRNCSICR_LAN2ISR 0x00000004
12184 +/** LAN1I sleep request
12185 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12186 +#define SYS_GPE_IRNCSICR_LAN1ISR 0x00000002
12187 +/** LAN0I sleep request
12188 +    Interrupt control bit for the corresponding bit in the IRNCSCR register. */
12189 +#define SYS_GPE_IRNCSICR_LAN0ISR 0x00000001
12190 +
12191 +/* Fields of "IRNCS Interrupt Enable Register" */
12192 +/** FSQM wakeup request
12193 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12194 +#define SYS_GPE_IRNCSEN_FSQMWR 0x80000000
12195 +/* Disable
12196 +#define SYS_GPE_IRNCSEN_FSQMWR_DIS 0x00000000 */
12197 +/** Enable */
12198 +#define SYS_GPE_IRNCSEN_FSQMWR_EN 0x80000000
12199 +/** GPONT wakeup request
12200 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12201 +#define SYS_GPE_IRNCSEN_GPONTWR 0x20000000
12202 +/* Disable
12203 +#define SYS_GPE_IRNCSEN_GPONTWR_DIS 0x00000000 */
12204 +/** Enable */
12205 +#define SYS_GPE_IRNCSEN_GPONTWR_EN 0x20000000
12206 +/** GPONE wakeup request
12207 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12208 +#define SYS_GPE_IRNCSEN_GPONEWR 0x10000000
12209 +/* Disable
12210 +#define SYS_GPE_IRNCSEN_GPONEWR_DIS 0x00000000 */
12211 +/** Enable */
12212 +#define SYS_GPE_IRNCSEN_GPONEWR_EN 0x10000000
12213 +/** LAN3E wakeup request
12214 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12215 +#define SYS_GPE_IRNCSEN_LAN3EWR 0x08000000
12216 +/* Disable
12217 +#define SYS_GPE_IRNCSEN_LAN3EWR_DIS 0x00000000 */
12218 +/** Enable */
12219 +#define SYS_GPE_IRNCSEN_LAN3EWR_EN 0x08000000
12220 +/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
12221 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12222 +#define SYS_GPE_IRNCSEN_LAN2EWR 0x04000000
12223 +/* Disable
12224 +#define SYS_GPE_IRNCSEN_LAN2EWR_DIS 0x00000000 */
12225 +/** Enable */
12226 +#define SYS_GPE_IRNCSEN_LAN2EWR_EN 0x04000000
12227 +/** LAN1E wakeup request
12228 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12229 +#define SYS_GPE_IRNCSEN_LAN1EWR 0x02000000
12230 +/* Disable
12231 +#define SYS_GPE_IRNCSEN_LAN1EWR_DIS 0x00000000 */
12232 +/** Enable */
12233 +#define SYS_GPE_IRNCSEN_LAN1EWR_EN 0x02000000
12234 +/** LAN0E wakeup request
12235 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12236 +#define SYS_GPE_IRNCSEN_LAN0EWR 0x01000000
12237 +/* Disable
12238 +#define SYS_GPE_IRNCSEN_LAN0EWR_DIS 0x00000000 */
12239 +/** Enable */
12240 +#define SYS_GPE_IRNCSEN_LAN0EWR_EN 0x01000000
12241 +/** GPONI wakeup request
12242 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12243 +#define SYS_GPE_IRNCSEN_GPONIWR 0x00100000
12244 +/* Disable
12245 +#define SYS_GPE_IRNCSEN_GPONIWR_DIS 0x00000000 */
12246 +/** Enable */
12247 +#define SYS_GPE_IRNCSEN_GPONIWR_EN 0x00100000
12248 +/** LAN3I wakeup request
12249 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12250 +#define SYS_GPE_IRNCSEN_LAN3IWR 0x00080000
12251 +/* Disable
12252 +#define SYS_GPE_IRNCSEN_LAN3IWR_DIS 0x00000000 */
12253 +/** Enable */
12254 +#define SYS_GPE_IRNCSEN_LAN3IWR_EN 0x00080000
12255 +/** LAN2I wakeup request
12256 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12257 +#define SYS_GPE_IRNCSEN_LAN2IWR 0x00040000
12258 +/* Disable
12259 +#define SYS_GPE_IRNCSEN_LAN2IWR_DIS 0x00000000 */
12260 +/** Enable */
12261 +#define SYS_GPE_IRNCSEN_LAN2IWR_EN 0x00040000
12262 +/** LAN1I wakeup request
12263 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12264 +#define SYS_GPE_IRNCSEN_LAN1IWR 0x00020000
12265 +/* Disable
12266 +#define SYS_GPE_IRNCSEN_LAN1IWR_DIS 0x00000000 */
12267 +/** Enable */
12268 +#define SYS_GPE_IRNCSEN_LAN1IWR_EN 0x00020000
12269 +/** LAN0I wakeup request
12270 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12271 +#define SYS_GPE_IRNCSEN_LAN0IWR 0x00010000
12272 +/* Disable
12273 +#define SYS_GPE_IRNCSEN_LAN0IWR_DIS 0x00000000 */
12274 +/** Enable */
12275 +#define SYS_GPE_IRNCSEN_LAN0IWR_EN 0x00010000
12276 +/** FSQM sleep request
12277 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12278 +#define SYS_GPE_IRNCSEN_FSQMSR 0x00008000
12279 +/* Disable
12280 +#define SYS_GPE_IRNCSEN_FSQMSR_DIS 0x00000000 */
12281 +/** Enable */
12282 +#define SYS_GPE_IRNCSEN_FSQMSR_EN 0x00008000
12283 +/** GPONT sleep request
12284 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12285 +#define SYS_GPE_IRNCSEN_GPONTSR 0x00002000
12286 +/* Disable
12287 +#define SYS_GPE_IRNCSEN_GPONTSR_DIS 0x00000000 */
12288 +/** Enable */
12289 +#define SYS_GPE_IRNCSEN_GPONTSR_EN 0x00002000
12290 +/** GPONE sleep request
12291 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12292 +#define SYS_GPE_IRNCSEN_GPONESR 0x00001000
12293 +/* Disable
12294 +#define SYS_GPE_IRNCSEN_GPONESR_DIS 0x00000000 */
12295 +/** Enable */
12296 +#define SYS_GPE_IRNCSEN_GPONESR_EN 0x00001000
12297 +/** LAN3E sleep request
12298 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12299 +#define SYS_GPE_IRNCSEN_LAN3ESR 0x00000800
12300 +/* Disable
12301 +#define SYS_GPE_IRNCSEN_LAN3ESR_DIS 0x00000000 */
12302 +/** Enable */
12303 +#define SYS_GPE_IRNCSEN_LAN3ESR_EN 0x00000800
12304 +/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
12305 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12306 +#define SYS_GPE_IRNCSEN_LAN2ESR 0x00000400
12307 +/* Disable
12308 +#define SYS_GPE_IRNCSEN_LAN2ESR_DIS 0x00000000 */
12309 +/** Enable */
12310 +#define SYS_GPE_IRNCSEN_LAN2ESR_EN 0x00000400
12311 +/** LAN1E sleep request
12312 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12313 +#define SYS_GPE_IRNCSEN_LAN1ESR 0x00000200
12314 +/* Disable
12315 +#define SYS_GPE_IRNCSEN_LAN1ESR_DIS 0x00000000 */
12316 +/** Enable */
12317 +#define SYS_GPE_IRNCSEN_LAN1ESR_EN 0x00000200
12318 +/** LAN0E sleep request
12319 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12320 +#define SYS_GPE_IRNCSEN_LAN0ESR 0x00000100
12321 +/* Disable
12322 +#define SYS_GPE_IRNCSEN_LAN0ESR_DIS 0x00000000 */
12323 +/** Enable */
12324 +#define SYS_GPE_IRNCSEN_LAN0ESR_EN 0x00000100
12325 +/** GPONI sleep request
12326 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12327 +#define SYS_GPE_IRNCSEN_GPONISR 0x00000010
12328 +/* Disable
12329 +#define SYS_GPE_IRNCSEN_GPONISR_DIS 0x00000000 */
12330 +/** Enable */
12331 +#define SYS_GPE_IRNCSEN_GPONISR_EN 0x00000010
12332 +/** LAN3I sleep request
12333 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12334 +#define SYS_GPE_IRNCSEN_LAN3ISR 0x00000008
12335 +/* Disable
12336 +#define SYS_GPE_IRNCSEN_LAN3ISR_DIS 0x00000000 */
12337 +/** Enable */
12338 +#define SYS_GPE_IRNCSEN_LAN3ISR_EN 0x00000008
12339 +/** LAN2I sleep request
12340 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12341 +#define SYS_GPE_IRNCSEN_LAN2ISR 0x00000004
12342 +/* Disable
12343 +#define SYS_GPE_IRNCSEN_LAN2ISR_DIS 0x00000000 */
12344 +/** Enable */
12345 +#define SYS_GPE_IRNCSEN_LAN2ISR_EN 0x00000004
12346 +/** LAN1I sleep request
12347 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12348 +#define SYS_GPE_IRNCSEN_LAN1ISR 0x00000002
12349 +/* Disable
12350 +#define SYS_GPE_IRNCSEN_LAN1ISR_DIS 0x00000000 */
12351 +/** Enable */
12352 +#define SYS_GPE_IRNCSEN_LAN1ISR_EN 0x00000002
12353 +/** LAN0I sleep request
12354 +    Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
12355 +#define SYS_GPE_IRNCSEN_LAN0ISR 0x00000001
12356 +/* Disable
12357 +#define SYS_GPE_IRNCSEN_LAN0ISR_DIS 0x00000000 */
12358 +/** Enable */
12359 +#define SYS_GPE_IRNCSEN_LAN0ISR_EN 0x00000001
12360 +
12361 +/*! @} */ /* SYS_GPE_REGISTER */
12362 +
12363 +#endif /* _sys_gpe_reg_h */
12364 --- /dev/null
12365 +++ b/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h
12366 @@ -0,0 +1,42 @@
12367 +/*
12368 + * This program is free software; you can redistribute it and/or
12369 + * modify it under the terms of the GNU General Public License as
12370 + * published by the Free Software Foundation; either version 2 of
12371 + * the License, or (at your option) any later version.
12372 + *
12373 + * This program is distributed in the hope that it will be useful,
12374 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
12375 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12376 + * GNU General Public License for more details.
12377 + *
12378 + * You should have received a copy of the GNU General Public License
12379 + * along with this program; if not, write to the Free Software
12380 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
12381 + * MA 02111-1307 USA
12382 + *
12383 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
12384 + */
12385 +
12386 +#ifndef __FALCON_SYSCTRL_H
12387 +#define __FALCON_SYSCTRL_H
12388 +
12389 +extern void sys1_hw_activate(u32 mask);
12390 +extern void sys1_hw_deactivate(u32 mask);
12391 +extern void sys1_hw_clk_enable(u32 mask);
12392 +extern void sys1_hw_clk_disable(u32 mask);
12393 +extern void sys1_hw_activate_or_reboot(u32 mask);
12394 +
12395 +extern void sys_eth_hw_activate(u32 mask);
12396 +extern void sys_eth_hw_deactivate(u32 mask);
12397 +extern void sys_eth_hw_clk_enable(u32 mask);
12398 +extern void sys_eth_hw_clk_disable(u32 mask);
12399 +extern void sys_eth_hw_activate_or_reboot(u32 mask);
12400 +
12401 +extern void sys_gpe_hw_activate(u32 mask);
12402 +extern void sys_gpe_hw_deactivate(u32 mask);
12403 +extern void sys_gpe_hw_clk_enable(u32 mask);
12404 +extern void sys_gpe_hw_clk_disable(u32 mask);
12405 +extern void sys_gpe_hw_activate_or_reboot(u32 mask);
12406 +extern int sys_gpe_hw_is_activated(u32 mask);
12407 +
12408 +#endif /* __FALCON_SYSCTRL_H */
12409 --- /dev/null
12410 +++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
12411 @@ -0,0 +1,58 @@
12412 +/*
12413 + *  Lantiq FALCON specific CPU feature overrides
12414 + *
12415 + *  Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
12416 + *
12417 + *  This file was derived from: include/asm-mips/cpu-features.h
12418 + *     Copyright (C) 2003, 2004 Ralf Baechle
12419 + *     Copyright (C) 2004 Maciej W. Rozycki
12420 + *
12421 + *  This program is free software; you can redistribute it and/or modify it
12422 + *  under the terms of the GNU General Public License version 2 as published
12423 + *  by the Free Software Foundation.
12424 + *
12425 + */
12426 +#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
12427 +#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
12428 +
12429 +#define cpu_has_tlb            1
12430 +#define cpu_has_4kex           1
12431 +#define cpu_has_3k_cache       0
12432 +#define cpu_has_4k_cache       1
12433 +#define cpu_has_tx39_cache     0
12434 +#define cpu_has_sb1_cache      0
12435 +#define cpu_has_fpu            0
12436 +#define cpu_has_32fpr          0
12437 +#define cpu_has_counter                1
12438 +#define cpu_has_watch          1
12439 +#define cpu_has_divec          1
12440 +
12441 +#define cpu_has_prefetch       1
12442 +#define cpu_has_ejtag          1
12443 +#define cpu_has_llsc           1
12444 +
12445 +#define cpu_has_mips16         1
12446 +#define cpu_has_mdmx           0
12447 +#define cpu_has_mips3d         0
12448 +#define cpu_has_smartmips      0
12449 +
12450 +#define cpu_has_mips32r1       1
12451 +#define cpu_has_mips32r2       1
12452 +#define cpu_has_mips64r1       0
12453 +#define cpu_has_mips64r2       0
12454 +
12455 +#define cpu_has_dsp            1
12456 +#define cpu_has_mipsmt         1
12457 +
12458 +#define cpu_has_vint           1
12459 +#define cpu_has_veic           1
12460 +
12461 +#define cpu_has_64bits         0
12462 +#define cpu_has_64bit_zero_reg 0
12463 +#define cpu_has_64bit_gp_regs  0
12464 +#define cpu_has_64bit_addresses        0
12465 +
12466 +#define cpu_dcache_line_size() 32
12467 +#define cpu_icache_line_size() 32
12468 +
12469 +#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
12470 --- /dev/null
12471 +++ b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h
12472 @@ -0,0 +1,1520 @@
12473 +/******************************************************************************
12474 +
12475 +                               Copyright (c) 2010
12476 +                            Lantiq Deutschland GmbH
12477 +
12478 +  For licensing information, see the file 'LICENSE' in the root folder of
12479 +  this software module.
12480 +
12481 +******************************************************************************/
12482 +
12483 +#ifndef _ebu_reg_h
12484 +#define _ebu_reg_h
12485 +
12486 +/** \addtogroup EBU_REGISTER
12487 +   @{
12488 +*/
12489 +/* access macros */
12490 +#define ebu_r32(reg) reg_r32(&ebu->reg)
12491 +#define ebu_w32(val, reg) reg_w32(val, &ebu->reg)
12492 +#define ebu_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ebu->reg)
12493 +#define ebu_r32_table(reg, idx) reg_r32_table(ebu->reg, idx)
12494 +#define ebu_w32_table(val, reg, idx) reg_w32_table(val, ebu->reg, idx)
12495 +#define ebu_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ebu->reg, idx)
12496 +#define ebu_adr_table(reg, idx) adr_table(ebu->reg, idx)
12497 +
12498 +
12499 +/** EBU register structure */
12500 +struct gpon_reg_ebu
12501 +{
12502 +   /** Reserved */
12503 +   unsigned int res_0[2]; /* 0x00000000 */
12504 +   /** Module ID Register
12505 +       Module type and version identifier */
12506 +   unsigned int modid; /* 0x00000008 */
12507 +   /** Module Control Register
12508 +       This register contains general configuration information observed for all CS regions or dealing with EBU functionality that is not directly related to external memory access. */
12509 +   unsigned int modcon; /* 0x0000000C */
12510 +   /** Bus Read Configuration Register0
12511 +       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
12512 +   unsigned int busrcon0; /* 0x00000010 */
12513 +   /** Bus Read Parameters Register0 */
12514 +   unsigned int busrp0; /* 0x00000014 */
12515 +   /** Bus Write Configuration Register0
12516 +       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
12517 +   unsigned int buswcon0; /* 0x00000018 */
12518 +   /** Bus Write Parameters Register0 */
12519 +   unsigned int buswp0; /* 0x0000001C */
12520 +   /** Bus Read Configuration Register1
12521 +       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
12522 +   unsigned int busrcon1; /* 0x00000020 */
12523 +   /** Bus Read Parameters Register1 */
12524 +   unsigned int busrp1; /* 0x00000024 */
12525 +   /** Bus Write Configuration Register1
12526 +       Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
12527 +   unsigned int buswcon1; /* 0x00000028 */
12528 +   /** Bus Write Parameters Register1 */
12529 +   unsigned int buswp1; /* 0x0000002C */
12530 +   /** Reserved */
12531 +   unsigned int res_1[8]; /* 0x00000030 */
12532 +   /** Bus Protocol Configuration Extension Register 0 */
12533 +   unsigned int busconext0; /* 0x00000050 */
12534 +   /** Bus Protocol Configuration Extension Register 1 */
12535 +   unsigned int busconext1; /* 0x00000054 */
12536 +   /** Reserved */
12537 +   unsigned int res_2[10]; /* 0x00000058 */
12538 +   /** Serial Flash Configuration Register
12539 +       The content of this register configures the EBU's Serial Flash protocol engine. */
12540 +   unsigned int sfcon; /* 0x00000080 */
12541 +   /** Serial Flash Timing Register
12542 +       This register defines the signal timing for the Serial Flash Access. See Section 3.18.3 on page 112 for details. */
12543 +   unsigned int sftime; /* 0x00000084 */
12544 +   /** Serial Flash Status Register
12545 +       This register holds status information on the Serial Flash device(s) attached and the EBU's Serial Flash protocol engine. */
12546 +   unsigned int sfstat; /* 0x00000088 */
12547 +   /** Serial Flash Command Register
12548 +       When writing to this register's opcode field, a command is started in the EBU's Serial Flash controller. */
12549 +   unsigned int sfcmd; /* 0x0000008C */
12550 +   /** Serial Flash Address Register
12551 +       This register holds the address to be sent (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 3.18.2.4.1 on page 103). */
12552 +   unsigned int sfaddr; /* 0x00000090 */
12553 +   /** Serial Flash Data Register
12554 +       This register holds the data being transferred (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 4.18.2.4.1 on page 116). */
12555 +   unsigned int sfdata; /* 0x00000094 */
12556 +   /** Serial Flash I/O Control Register
12557 +       This register provides additional configuration for controlling the IO pads of the Serial Flash interface. */
12558 +   unsigned int sfio; /* 0x00000098 */
12559 +   /** Reserved */
12560 +   unsigned int res_3[25]; /* 0x0000009C */
12561 +};
12562 +
12563 +
12564 +/* Fields of "Module ID Register" */
12565 +/** Feature Select
12566 +    This field indicates the types of external devices/protocols supported by the GPON version of the EBU. */
12567 +#define MODID_FSEL_MASK 0xE0000000
12568 +/** field offset */
12569 +#define MODID_FSEL_OFFSET 29
12570 +/** Support for SRAM, NAND/NOR/OneNand Flash and Cellular RAM is implemented. */
12571 +#define MODID_FSEL_SRAM_FLASH_CRAM 0x00000000
12572 +/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR SDRAM is implemented. */
12573 +#define MODID_FSEL_SRAM_FLASH_CRAM_SDR 0x20000000
12574 +/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR/DDR SDRAM is implemented. */
12575 +#define MODID_FSEL_SRAM_FLASH_CRAM_DDR 0x40000000
12576 +/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM, SDR/DDR SDRAM 0nd LPDDR-Flash is implemented. */
12577 +#define MODID_FSEL_SRAM_FLASH_CRAM_DDR_LPNVM 0x60000000
12578 +/** Serial Flash Support
12579 +    Indicates whether or not the support of Serial Flash devices is available. */
12580 +#define MODID_SF 0x10000000
12581 +/* Not Available
12582 +#define MODID_SF_NAV 0x00000000 */
12583 +/** Available */
12584 +#define MODID_SF_AV 0x10000000
12585 +/** AAD-mux Support
12586 +    Indicates whether or not the GPON EBU supports AAD-mux protocol for Burst Flash and Cellular RAM. */
12587 +#define MODID_AAD 0x08000000
12588 +/* Not Available
12589 +#define MODID_AAD_NAV 0x00000000 */
12590 +/** Available */
12591 +#define MODID_AAD_AV 0x08000000
12592 +/** Indicates whether or not the GPON EBU implements a DLL which is e.g. used for 50% duty cycle external clock generation. Note that a DLL is always implemented if DDR-SDRAM support is selected. */
12593 +#define MODID_DLL 0x04000000
12594 +/* Not Available
12595 +#define MODID_DLL_NAV 0x00000000 */
12596 +/** Available */
12597 +#define MODID_DLL_AV 0x04000000
12598 +/** Pad Multiplexing Scheme */
12599 +#define MODID_PMS_MASK 0x03000000
12600 +/** field offset */
12601 +#define MODID_PMS_OFFSET 24
12602 +/** The EBU comprises of dedicated address pins A[EXTAW-1=:16]. */
12603 +#define MODID_PMS_PMS_CLASSIC 0x00000000
12604 +/** Revision
12605 +    Revision Number */
12606 +#define MODID_REV_MASK 0x000F0000
12607 +/** field offset */
12608 +#define MODID_REV_OFFSET 16
12609 +/** Module ID
12610 +    This field contains the EBU's unique peripheral ID. */
12611 +#define MODID_ID_MASK 0x0000FF00
12612 +/** field offset */
12613 +#define MODID_ID_OFFSET 8
12614 +/** Version
12615 +    This field gives the EBU version number. */
12616 +#define MODID_VERSION_MASK 0x000000FF
12617 +/** field offset */
12618 +#define MODID_VERSION_OFFSET 0
12619 +
12620 +/* Fields of "Module Control Register" */
12621 +/** Reserved */
12622 +#define MODCON_DLLUPDINT_MASK 0xC0000000
12623 +/** field offset */
12624 +#define MODCON_DLLUPDINT_OFFSET 30
12625 +/** Access Inhibit Acknowledge
12626 +    After suspension of all accesses to the External Bus has been requested by setting bit acc_inh, acc_inh_ack acknowledges the request and inidcates that access suspension is now in effect. The bit is cleared when acc_inh gets deasserted. */
12627 +#define MODCON_AIA 0x02000000
12628 +/* no access restriction are active in the EBU subsystem
12629 +#define MODCON_AIA_NO_INHIBIT 0x00000000 */
12630 +/** accesses are restricted to selected (configuration) system bus port(s) */
12631 +#define MODCON_AIA_INHIBIT 0x02000000
12632 +/** Access Inhibit request
12633 +    Setting this bit will suspend all non-CPU system bus ports and the EBU itself from accessing the External Bus. This feature is usually used when the CPU needs to reconfigure protocol parameters in the EBU in order to avoid external accesses with invalid settings. The EBU acknowledges that the access suspension is in effect by asserting acc_inh_ack. */
12634 +#define MODCON_AI 0x01000000
12635 +/* no access restriction are active in the EBU subsystem
12636 +#define MODCON_AI_NO_INHIBIT 0x00000000 */
12637 +/** accesses are restricted to selected (configuration) system bus port(s) */
12638 +#define MODCON_AI_INHIBIT 0x01000000
12639 +/** Lock Timeout */
12640 +#define MODCON_LTO_MASK 0x00FF0000
12641 +/** field offset */
12642 +#define MODCON_LTO_OFFSET 16
12643 +/** Reserved */
12644 +#define MODCON_DDREN 0x00008000
12645 +/** Pad Drive Control
12646 +    Intended to be used to control the EBU pad''s drive strength. Refer to the GPON chip specification to see which drive strnegth options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
12647 +#define MODCON_PEXT 0x00004000
12648 +/* Normal drive
12649 +#define MODCON_PEXT_NORMAL 0x00000000 */
12650 +/** Strong drive */
12651 +#define MODCON_PEXT_STRONG 0x00004000
12652 +/** Pad Slew Falling Edge Control
12653 +    Intended to be used to trim the External Bus pad's falling edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
12654 +#define MODCON_SLF 0x00002000
12655 +/* Slow slew rate
12656 +#define MODCON_SLF_SLOW 0x00000000 */
12657 +/** Fast slew rate */
12658 +#define MODCON_SLF_FAST 0x00002000
12659 +/** Pad Slew Rising Edge Control
12660 +    Intended to be used to trim the External Bus pad's rising edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
12661 +#define MODCON_SLR 0x00001000
12662 +/* Slow slew rate
12663 +#define MODCON_SLR_SLOW 0x00000000 */
12664 +/** Fast slew rate */
12665 +#define MODCON_SLR_FAST 0x00001000
12666 +/** Write Buffering Mode
12667 +    This bit controls when the EBU starts a new write burst transaction from the Memport interface. */
12668 +#define MODCON_WBM 0x00000040
12669 +/* The EBU starts a write transaction on the External Bus as early as possible, expecting that the n beats of the write burst will be transferred within n or n+1 clock cycles over the EBU's Memport interface. Use this mode if the EBU is clocked at the same or a slower frequency than the system bus interconnect.
12670 +#define MODCON_WBM_START_WRITE_EARLY 0x00000000 */
12671 +/** The EBU start a write transaction only after all data of a write burst have been received over the EBU's Memport interface. Use this mode if the EBU is clocked at a higher frequency than the system bus interrconnect. */
12672 +#define MODCON_WBM_START_WRITE_LATE 0x00000040
12673 +/** Reserved */
12674 +#define MODCON_SDCLKEN 0x00000020
12675 +/** Standby Mode Enable
12676 +    When set allows the EBU subsystem to enter standby mode in response to a rising edge on input signal standby_req_i. See Section 3.9.3 for details. */
12677 +#define MODCON_STBYEN 0x00000010
12678 +/* Disable
12679 +#define MODCON_STBYEN_DIS 0x00000000 */
12680 +/** Enable */
12681 +#define MODCON_STBYEN_EN 0x00000010
12682 +/** Enable BFCLK1
12683 +    This field will enables or disables mirroring the clock that is output on BFCLKO_0 also on pad BFCLKO_1 to double the drive strength. See also Section 3.17.3) */
12684 +#define MODCON_BFCLK1EN 0x00000008
12685 +/* Disable
12686 +#define MODCON_BFCLK1EN_DIS 0x00000000 */
12687 +/** Enable */
12688 +#define MODCON_BFCLK1EN_EN 0x00000008
12689 +/** Ready/Busy Status Edge
12690 +    This is a read-only bit which shows a change of the logic level shown in the sts field since last read. It is reset by a read access. */
12691 +#define MODCON_STSEDGE 0x00000004
12692 +/** Ready/Busy Status
12693 +    This is a read-only bit which reflects the current logic level present on the RDY/BSY or STS input pin which is (optionally) fed-in from a General Purpose I/O pad which is not part of the EBU via the EBU's input pin signal gpio_nand_rdy_ */
12694 +#define MODCON_STS 0x00000002
12695 +/** External Bus Arbitration Mode
12696 +    This bit allows to disconnect the EBU from the External Bus. While EBU_MODCON.acc_inh_ack is 0, the value of arb_mode is forced to OWN_BUS. */
12697 +#define MODCON_AM 0x00000001
12698 +/* The EBU does not own the bus (multi-master)
12699 +#define MODCON_AM_SHAREDBUS 0x00000000 */
12700 +/** The EBU owns the external bus. */
12701 +#define MODCON_AM_OWNBUS 0x00000001
12702 +
12703 +/* Fields of "Bus Read Configuration Register0" */
12704 +/** Device Type For Region
12705 +    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
12706 +#define BUSRCON0_AGEN_MASK 0xF0000000
12707 +/** field offset */
12708 +#define BUSRCON0_AGEN_OFFSET 28
12709 +/** Muxed Asynchronous Type External Memory */
12710 +#define BUSRCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
12711 +/** Muxed Burst Type External Memory */
12712 +#define BUSRCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
12713 +/** NAND Flash (page optimised) */
12714 +#define BUSRCON0_AGEN_NAND_FLASH 0x20000000
12715 +/** Muxed Cellular RAM External Memory */
12716 +#define BUSRCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
12717 +/** Demuxed Asynchronous Type External Memory */
12718 +#define BUSRCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
12719 +/** Demuxed Burst Type External Memory */
12720 +#define BUSRCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
12721 +/** Demuxed Page Mode External Memory */
12722 +#define BUSRCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
12723 +/** Demuxed Cellular RAM External Memory */
12724 +#define BUSRCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
12725 +/** Serial Flash */
12726 +#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
12727 +/** Device Addressing Mode
12728 +    t.b.d. */
12729 +#define BUSRCON0_PORTW_MASK 0x0C000000
12730 +/** field offset */
12731 +#define BUSRCON0_PORTW_OFFSET 26
12732 +/** 8-bit multiplexed */
12733 +#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
12734 +/** 16-bit multiplexed */
12735 +#define BUSRCON0_PORTW_16_BIT_MUX 0x04000000
12736 +/** Twin, 16-bit multiplexed */
12737 +#define BUSRCON0_PORTW_TWIN_16_BIT_MUX 0x08000000
12738 +/** 32-bit multiplexed */
12739 +#define BUSRCON0_PORTW_32_BIT_MUX 0x0C000000
12740 +/** External Wait Control
12741 +    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
12742 +#define BUSRCON0_WAIT_MASK 0x03000000
12743 +/** field offset */
12744 +#define BUSRCON0_WAIT_OFFSET 24
12745 +/** WAIT is ignored (default after reset). */
12746 +#define BUSRCON0_WAIT_OFF 0x00000000
12747 +/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
12748 +#define BUSRCON0_WAIT_EARLY_WAIT 0x01000000
12749 +/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
12750 +#define BUSRCON0_WAIT_TWO_STAGE_SYNC 0x01000000
12751 +/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
12752 +#define BUSRCON0_WAIT_WAIT_WITH_DATA 0x02000000
12753 +/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
12754 +#define BUSRCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000
12755 +/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
12756 +#define BUSRCON0_WAIT_ABORT_AND_RETRY 0x03000000
12757 +/** Disable Burst Address Wrapping */
12758 +#define BUSRCON0_DBA 0x00800000
12759 +/** Reversed polarity at wait */
12760 +#define BUSRCON0_WAITINV 0x00400000
12761 +/* Low active.
12762 +#define BUSRCON0_WAITINV_ACTLOW 0x00000000 */
12763 +/** High active */
12764 +#define BUSRCON0_WAITINV_ACTHI 0x00400000
12765 +/** Early ADV Enable for Synchronous Bursts */
12766 +#define BUSRCON0_EBSE 0x00200000
12767 +/* Low active.
12768 +#define BUSRCON0_EBSE_DELAYED 0x00000000 */
12769 +/** High active */
12770 +#define BUSRCON0_EBSE_NOT_DELAYED 0x00200000
12771 +/** Early Control Signals for Synchronous Bursts */
12772 +#define BUSRCON0_ECSE 0x00100000
12773 +/* Low active.
12774 +#define BUSRCON0_ECSE_DELAYED 0x00000000 */
12775 +/** High active */
12776 +#define BUSRCON0_ECSE_NOT_DELAYED 0x00100000
12777 +/** Synchronous Burst Buffer Mode Select */
12778 +#define BUSRCON0_FBBMSEL 0x00080000
12779 +/* FIXED_LENGTH
12780 +#define BUSRCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */
12781 +/** CONTINUOUS */
12782 +#define BUSRCON0_FBBMSEL_CONTINUOUS 0x00080000
12783 +/** Burst Length for Synchronous Burst */
12784 +#define BUSRCON0_FETBLEN_MASK 0x00070000
12785 +/** field offset */
12786 +#define BUSRCON0_FETBLEN_OFFSET 16
12787 +/** Up to 1 data cycle (default after reset). */
12788 +#define BUSRCON0_FETBLEN_SINGLE 0x00000000
12789 +/** Up to 2 data cycles. */
12790 +#define BUSRCON0_FETBLEN_BURST2 0x00010000
12791 +/** Up to 4 data cycles. */
12792 +#define BUSRCON0_FETBLEN_BURST4 0x00020000
12793 +/** Up to 8 data cycles. */
12794 +#define BUSRCON0_FETBLEN_BURST8 0x00030000
12795 +/** Up to 16 data cycles. */
12796 +#define BUSRCON0_FETBLEN_BURST16 0x00040000
12797 +/** Reserved
12798 +    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
12799 +#define BUSRCON0_NANDAMAP_MASK 0x0000C000
12800 +/** field offset */
12801 +#define BUSRCON0_NANDAMAP_OFFSET 14
12802 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
12803 +#define BUSRCON0_NANDAMAP_NAND_A17_16 0x00000000
12804 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
12805 +#define BUSRCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000
12806 +/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
12807 +#define BUSRCON0_NANDAMAP_NAND_AD9_8 0x00008000
12808 +/** Reserved for future use. Do not use or unpredictable results may occur. */
12809 +#define BUSRCON0_NANDAMAP_NAND_RFU 0x0000C000
12810 +/** AAD-mux Protocol
12811 +    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
12812 +#define BUSRCON0_AADMUX 0x00002000
12813 +/* Muxed device is write accessed in AD-mux mode.
12814 +#define BUSRCON0_AADMUX_AD_MUX 0x00000000 */
12815 +/** Muxed device is write accessed in AAD-mux mode. */
12816 +#define BUSRCON0_AADMUX_AAD_MUX 0x00002000
12817 +/** Asynchronous Address Phase */
12818 +#define BUSRCON0_AAP 0x00001000
12819 +/* Clock is enabled at beginning of access.
12820 +#define BUSRCON0_AAP_EARLY 0x00000000 */
12821 +/** Clock is enabled after address phase. */
12822 +#define BUSRCON0_AAP_LATE 0x00001000
12823 +/** Burst Flash Read Single Stage Synchronisation */
12824 +#define BUSRCON0_BFSSS 0x00000800
12825 +/* Two stages of synchronisation used.
12826 +#define BUSRCON0_BFSSS_TWO_STAGE 0x00000000 */
12827 +/** Single stage of synchronisation used. */
12828 +#define BUSRCON0_BFSSS_SINGLE_STAGE 0x00000800
12829 +/** Burst Flash Clock Feedback Enable */
12830 +#define BUSRCON0_FDBKEN 0x00000400
12831 +/* Disable
12832 +#define BUSRCON0_FDBKEN_DIS 0x00000000 */
12833 +/** Enable */
12834 +#define BUSRCON0_FDBKEN_EN 0x00000400
12835 +/** Auxiliary Chip Select Enable
12836 +    Not supported in GPON-EBU, field must be set to 0. */
12837 +#define BUSRCON0_CSA 0x00000200
12838 +/* Disable
12839 +#define BUSRCON0_CSA_DIS 0x00000000 */
12840 +/** Enable */
12841 +#define BUSRCON0_CSA_EN 0x00000200
12842 +/** Flash Non-Array Access Enable
12843 +    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
12844 +#define BUSRCON0_NAA 0x00000100
12845 +/* Disable
12846 +#define BUSRCON0_NAA_DIS 0x00000000 */
12847 +/** Enable */
12848 +#define BUSRCON0_NAA_EN 0x00000100
12849 +/** Module Enable */
12850 +#define BUSRCON0_ENABLE 0x00000001
12851 +/* Disable
12852 +#define BUSRCON0_ENABLE_DIS 0x00000000 */
12853 +/** Enable */
12854 +#define BUSRCON0_ENABLE_EN 0x00000001
12855 +
12856 +/* Fields of "Bus Read Parameters Register0" */
12857 +/** Address Cycles
12858 +    Number of cycles for address phase. */
12859 +#define BUSRP0_ADDRC_MASK 0xF0000000
12860 +/** field offset */
12861 +#define BUSRP0_ADDRC_OFFSET 28
12862 +/** Address Hold Cycles For Multiplexed Address
12863 +    Number of address hold cycles during multiplexed accesses. */
12864 +#define BUSRP0_ADHOLC_MASK 0x0F000000
12865 +/** field offset */
12866 +#define BUSRP0_ADHOLC_OFFSET 24
12867 +/** Programmed Command Delay Cycles
12868 +    Number of delay cycles during command delay phase. */
12869 +#define BUSRP0_CMDDELAY_MASK 0x00F00000
12870 +/** field offset */
12871 +#define BUSRP0_CMDDELAY_OFFSET 20
12872 +/** Extended Data */
12873 +#define BUSRP0_EXTDATA_MASK 0x000C0000
12874 +/** field offset */
12875 +#define BUSRP0_EXTDATA_OFFSET 18
12876 +/** External device outputs data every BFCLK cycle */
12877 +#define BUSRP0_EXTDATA_ONE 0x00000000
12878 +/** External device outputs data every 2nd BFCLK cycles */
12879 +#define BUSRP0_EXTDATA_TWO 0x00040000
12880 +/** External device outputs data every 4th BFCLK cycles */
12881 +#define BUSRP0_EXTDATA_FOUR 0x00080000
12882 +/** External device outputs data every 8th BFCLK cycles */
12883 +#define BUSRP0_EXTDATA_EIGHT 0x000C0000
12884 +/** Frequency of external clock at pin BFCLKO */
12885 +#define BUSRP0_EXTCLOCK_MASK 0x00030000
12886 +/** field offset */
12887 +#define BUSRP0_EXTCLOCK_OFFSET 16
12888 +/** Equal to ebu_clk frequency. */
12889 +#define BUSRP0_EXTCLOCK_ONE_TO_ONE 0x00000000
12890 +/** 1/2 of ebu_clk frequency. */
12891 +#define BUSRP0_EXTCLOCK_ONE_TO_TWO 0x00010000
12892 +/** 1/3 of ebu_clk frequency. */
12893 +#define BUSRP0_EXTCLOCK_ONE_TO_THREE 0x00020000
12894 +/** 1/4 of ebu_clk frequency (default after reset). */
12895 +#define BUSRP0_EXTCLOCK_ONE_TO_FOUR 0x00030000
12896 +/** Data Hold Cycles For read Accesses
12897 +    Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */
12898 +#define BUSRP0_DATAC_MASK 0x0000F000
12899 +/** field offset */
12900 +#define BUSRP0_DATAC_OFFSET 12
12901 +/** Programmed Wait States for read accesses
12902 +    Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
12903 +#define BUSRP0_WAITRDC_MASK 0x00000F80
12904 +/** field offset */
12905 +#define BUSRP0_WAITRDC_OFFSET 7
12906 +/** Recovery Cycles After read Accesses, same CS
12907 +    Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
12908 +#define BUSRP0_RECOVC_MASK 0x00000070
12909 +/** field offset */
12910 +#define BUSRP0_RECOVC_OFFSET 4
12911 +/** Recovery Cycles After read Accesses, other CS
12912 +    Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
12913 +#define BUSRP0_DTACS_MASK 0x0000000F
12914 +/** field offset */
12915 +#define BUSRP0_DTACS_OFFSET 0
12916 +
12917 +/* Fields of "Bus Write Configuration Register0" */
12918 +/** Device Type For Region
12919 +    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
12920 +#define BUSWCON0_AGEN_MASK 0xF0000000
12921 +/** field offset */
12922 +#define BUSWCON0_AGEN_OFFSET 28
12923 +/** Muxed Asynchronous Type External Memory */
12924 +#define BUSWCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
12925 +/** Muxed Burst Type External Memory */
12926 +#define BUSWCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
12927 +/** NAND Flash (page optimised) */
12928 +#define BUSWCON0_AGEN_NAND_FLASH 0x20000000
12929 +/** Muxed Cellular RAM External Memory */
12930 +#define BUSWCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
12931 +/** Demuxed Asynchronous Type External Memory */
12932 +#define BUSWCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
12933 +/** Demuxed Burst Type External Memory */
12934 +#define BUSWCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
12935 +/** Demuxed Page Mode External Memory */
12936 +#define BUSWCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
12937 +/** Demuxed Cellular RAM External Memory */
12938 +#define BUSWCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
12939 +/** Serial Flash */
12940 +#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
12941 +/** Device Addressing Mode
12942 +    t.b.d. */
12943 +#define BUSWCON0_PORTW_MASK 0x0C000000
12944 +/** field offset */
12945 +#define BUSWCON0_PORTW_OFFSET 26
12946 +/** External Wait Control
12947 +    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
12948 +#define BUSWCON0_WAIT_MASK 0x03000000
12949 +/** field offset */
12950 +#define BUSWCON0_WAIT_OFFSET 24
12951 +/** WAIT is ignored (default after reset). */
12952 +#define BUSWCON0_WAIT_OFF 0x00000000
12953 +/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
12954 +#define BUSWCON0_WAIT_EARLY_WAIT 0x01000000
12955 +/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
12956 +#define BUSWCON0_WAIT_TWO_STAGE_SYNC 0x01000000
12957 +/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
12958 +#define BUSWCON0_WAIT_WAIT_WITH_DATA 0x02000000
12959 +/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
12960 +#define BUSWCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000
12961 +/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
12962 +#define BUSWCON0_WAIT_ABORT_AND_RETRY 0x03000000
12963 +/** Reserved */
12964 +#define BUSWCON0_LOCKCS 0x00800000
12965 +/** Reversed polarity at wait */
12966 +#define BUSWCON0_WAITINV 0x00400000
12967 +/* Low active.
12968 +#define BUSWCON0_WAITINV_ACTLOW 0x00000000 */
12969 +/** High active */
12970 +#define BUSWCON0_WAITINV_ACTHI 0x00400000
12971 +/** Early ADV Enable for Synchronous Bursts */
12972 +#define BUSWCON0_EBSE 0x00200000
12973 +/* Low active.
12974 +#define BUSWCON0_EBSE_DELAYED 0x00000000 */
12975 +/** High active */
12976 +#define BUSWCON0_EBSE_NOT_DELAYED 0x00200000
12977 +/** Early Control Signals for Synchronous Bursts */
12978 +#define BUSWCON0_ECSE 0x00100000
12979 +/* Low active.
12980 +#define BUSWCON0_ECSE_DELAYED 0x00000000 */
12981 +/** High active */
12982 +#define BUSWCON0_ECSE_NOT_DELAYED 0x00100000
12983 +/** Synchronous Burst Buffer Mode Select */
12984 +#define BUSWCON0_FBBMSEL 0x00080000
12985 +/* FIXED_LENGTH
12986 +#define BUSWCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */
12987 +/** CONTINUOUS */
12988 +#define BUSWCON0_FBBMSEL_CONTINUOUS 0x00080000
12989 +/** Burst Length for Synchronous Burst */
12990 +#define BUSWCON0_FETBLEN_MASK 0x00070000
12991 +/** field offset */
12992 +#define BUSWCON0_FETBLEN_OFFSET 16
12993 +/** Up to 1 data cycle (default after reset). */
12994 +#define BUSWCON0_FETBLEN_SINGLE 0x00000000
12995 +/** Up to 2 data cycles. */
12996 +#define BUSWCON0_FETBLEN_BURST2 0x00010000
12997 +/** Up to 4 data cycles. */
12998 +#define BUSWCON0_FETBLEN_BURST4 0x00020000
12999 +/** Up to 8 data cycles. */
13000 +#define BUSWCON0_FETBLEN_BURST8 0x00030000
13001 +/** Up to 16 data cycles. */
13002 +#define BUSWCON0_FETBLEN_BURST16 0x00040000
13003 +/** Reserved
13004 +    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
13005 +#define BUSWCON0_NANDAMAP_MASK 0x0000C000
13006 +/** field offset */
13007 +#define BUSWCON0_NANDAMAP_OFFSET 14
13008 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
13009 +#define BUSWCON0_NANDAMAP_NAND_A17_16 0x00000000
13010 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
13011 +#define BUSWCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000
13012 +/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
13013 +#define BUSWCON0_NANDAMAP_NAND_AD9_8 0x00008000
13014 +/** Reserved for future use. Do not use or unpredictable results may occur. */
13015 +#define BUSWCON0_NANDAMAP_NAND_RFU 0x0000C000
13016 +/** AAD-mux Protocol
13017 +    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
13018 +#define BUSWCON0_AADMUX 0x00002000
13019 +/* Muxed device is write accessed in AD-mux mode.
13020 +#define BUSWCON0_AADMUX_AD_MUX 0x00000000 */
13021 +/** Muxed device is write accessed in AAD-mux mode. */
13022 +#define BUSWCON0_AADMUX_AAD_MUX 0x00002000
13023 +/** Asynchronous Address Phase */
13024 +#define BUSWCON0_AAP 0x00001000
13025 +/* Clock is enabled at beginning of access.
13026 +#define BUSWCON0_AAP_EARLY 0x00000000 */
13027 +/** Clock is enabled after address phase. */
13028 +#define BUSWCON0_AAP_LATE 0x00001000
13029 +/** Auxiliary Chip Select Enable
13030 +    Not supported in GPON-EBU, field must be set to 0. */
13031 +#define BUSWCON0_CSA 0x00000200
13032 +/* Disable
13033 +#define BUSWCON0_CSA_DIS 0x00000000 */
13034 +/** Enable */
13035 +#define BUSWCON0_CSA_EN 0x00000200
13036 +/** Flash Non-Array Access Enable
13037 +    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
13038 +#define BUSWCON0_NAA 0x00000100
13039 +/* Disable
13040 +#define BUSWCON0_NAA_DIS 0x00000000 */
13041 +/** Enable */
13042 +#define BUSWCON0_NAA_EN 0x00000100
13043 +/** Module Enable */
13044 +#define BUSWCON0_ENABLE 0x00000001
13045 +/* Disable
13046 +#define BUSWCON0_ENABLE_DIS 0x00000000 */
13047 +/** Enable */
13048 +#define BUSWCON0_ENABLE_EN 0x00000001
13049 +
13050 +/* Fields of "Bus Write Parameters Register0" */
13051 +/** Address Cycles
13052 +    Number of cycles for address phase. */
13053 +#define BUSWP0_ADDRC_MASK 0xF0000000
13054 +/** field offset */
13055 +#define BUSWP0_ADDRC_OFFSET 28
13056 +/** Address Hold Cycles For Multiplexed Address
13057 +    Number of address hold cycles during multiplexed accesses. */
13058 +#define BUSWP0_ADHOLC_MASK 0x0F000000
13059 +/** field offset */
13060 +#define BUSWP0_ADHOLC_OFFSET 24
13061 +/** Programmed Command Delay Cycles
13062 +    Number of delay cycles during command delay phase. */
13063 +#define BUSWP0_CMDDELAY_MASK 0x00F00000
13064 +/** field offset */
13065 +#define BUSWP0_CMDDELAY_OFFSET 20
13066 +/** Extended Data */
13067 +#define BUSWP0_EXTDATA_MASK 0x000C0000
13068 +/** field offset */
13069 +#define BUSWP0_EXTDATA_OFFSET 18
13070 +/** External device outputs data every BFCLK cycle */
13071 +#define BUSWP0_EXTDATA_ONE 0x00000000
13072 +/** External device outputs data every 2nd BFCLK cycles */
13073 +#define BUSWP0_EXTDATA_TWO 0x00040000
13074 +/** External device outputs data every 4th BFCLK cycles */
13075 +#define BUSWP0_EXTDATA_FOUR 0x00080000
13076 +/** External device outputs data every 8th BFCLK cycles */
13077 +#define BUSWP0_EXTDATA_EIGHT 0x000C0000
13078 +/** Frequency of external clock at pin BFCLKO */
13079 +#define BUSWP0_EXTCLOCK_MASK 0x00030000
13080 +/** field offset */
13081 +#define BUSWP0_EXTCLOCK_OFFSET 16
13082 +/** Equal to ebu_clk frequency. */
13083 +#define BUSWP0_EXTCLOCK_ONE_TO_ONE 0x00000000
13084 +/** 1/2 of ebu_clk frequency. */
13085 +#define BUSWP0_EXTCLOCK_ONE_TO_TWO 0x00010000
13086 +/** 1/3 of ebu_clk frequency. */
13087 +#define BUSWP0_EXTCLOCK_ONE_TO_THREE 0x00020000
13088 +/** 1/4 of ebu_clk frequency (default after reset). */
13089 +#define BUSWP0_EXTCLOCK_ONE_TO_FOUR 0x00030000
13090 +/** Data Hold Cycles For write Accesses
13091 +    Number of data hold cycles during write accesses. */
13092 +#define BUSWP0_DATAC_MASK 0x0000F000
13093 +/** field offset */
13094 +#define BUSWP0_DATAC_OFFSET 12
13095 +/** Programmed Wait States For write Accesses
13096 +    Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
13097 +#define BUSWP0_WAITWDC_MASK 0x00000F80
13098 +/** field offset */
13099 +#define BUSWP0_WAITWDC_OFFSET 7
13100 +/** Recovery Cycles After write Accesses, same CS
13101 +    Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
13102 +#define BUSWP0_RECOVC_MASK 0x00000070
13103 +/** field offset */
13104 +#define BUSWP0_RECOVC_OFFSET 4
13105 +/** Recovery Cycles After write Accesses, other CS
13106 +    Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
13107 +#define BUSWP0_DTACS_MASK 0x0000000F
13108 +/** field offset */
13109 +#define BUSWP0_DTACS_OFFSET 0
13110 +
13111 +/* Fields of "Bus Read Configuration Register1" */
13112 +/** Device Type For Region
13113 +    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
13114 +#define BUSRCON1_AGEN_MASK 0xF0000000
13115 +/** field offset */
13116 +#define BUSRCON1_AGEN_OFFSET 28
13117 +/** Muxed Asynchronous Type External Memory */
13118 +#define BUSRCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
13119 +/** Muxed Burst Type External Memory */
13120 +#define BUSRCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
13121 +/** NAND Flash (page optimised) */
13122 +#define BUSRCON1_AGEN_NAND_FLASH 0x20000000
13123 +/** Muxed Cellular RAM External Memory */
13124 +#define BUSRCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
13125 +/** Demuxed Asynchronous Type External Memory */
13126 +#define BUSRCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
13127 +/** Demuxed Burst Type External Memory */
13128 +#define BUSRCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
13129 +/** Demuxed Page Mode External Memory */
13130 +#define BUSRCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
13131 +/** Demuxed Cellular RAM External Memory */
13132 +#define BUSRCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
13133 +/** Serial Flash */
13134 +#define BUSRCON1_AGEN_SERIAL_FLASH 0xF0000000
13135 +/** Device Addressing Mode
13136 +    t.b.d. */
13137 +#define BUSRCON1_PORTW_MASK 0x0C000000
13138 +/** field offset */
13139 +#define BUSRCON1_PORTW_OFFSET 26
13140 +/** 8-bit multiplexed */
13141 +#define BUSRCON1_PORTW_8_BIT_MUX 0x00000000
13142 +/** 16-bit multiplexed */
13143 +#define BUSRCON1_PORTW_16_BIT_MUX 0x04000000
13144 +/** Twin, 16-bit multiplexed */
13145 +#define BUSRCON1_PORTW_TWIN_16_BIT_MUX 0x08000000
13146 +/** 32-bit multiplexed */
13147 +#define BUSRCON1_PORTW_32_BIT_MUX 0x0C000000
13148 +/** External Wait Control
13149 +    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
13150 +#define BUSRCON1_WAIT_MASK 0x03000000
13151 +/** field offset */
13152 +#define BUSRCON1_WAIT_OFFSET 24
13153 +/** WAIT is ignored (default after reset). */
13154 +#define BUSRCON1_WAIT_OFF 0x00000000
13155 +/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
13156 +#define BUSRCON1_WAIT_EARLY_WAIT 0x01000000
13157 +/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
13158 +#define BUSRCON1_WAIT_TWO_STAGE_SYNC 0x01000000
13159 +/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
13160 +#define BUSRCON1_WAIT_WAIT_WITH_DATA 0x02000000
13161 +/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
13162 +#define BUSRCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000
13163 +/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
13164 +#define BUSRCON1_WAIT_ABORT_AND_RETRY 0x03000000
13165 +/** Disable Burst Address Wrapping */
13166 +#define BUSRCON1_DBA 0x00800000
13167 +/** Reversed polarity at wait */
13168 +#define BUSRCON1_WAITINV 0x00400000
13169 +/* Low active.
13170 +#define BUSRCON1_WAITINV_ACTLOW 0x00000000 */
13171 +/** High active */
13172 +#define BUSRCON1_WAITINV_ACTHI 0x00400000
13173 +/** Early ADV Enable for Synchronous Bursts */
13174 +#define BUSRCON1_EBSE 0x00200000
13175 +/* Low active.
13176 +#define BUSRCON1_EBSE_DELAYED 0x00000000 */
13177 +/** High active */
13178 +#define BUSRCON1_EBSE_NOT_DELAYED 0x00200000
13179 +/** Early Control Signals for Synchronous Bursts */
13180 +#define BUSRCON1_ECSE 0x00100000
13181 +/* Low active.
13182 +#define BUSRCON1_ECSE_DELAYED 0x00000000 */
13183 +/** High active */
13184 +#define BUSRCON1_ECSE_NOT_DELAYED 0x00100000
13185 +/** Synchronous Burst Buffer Mode Select */
13186 +#define BUSRCON1_FBBMSEL 0x00080000
13187 +/* FIXED_LENGTH
13188 +#define BUSRCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */
13189 +/** CONTINUOUS */
13190 +#define BUSRCON1_FBBMSEL_CONTINUOUS 0x00080000
13191 +/** Burst Length for Synchronous Burst */
13192 +#define BUSRCON1_FETBLEN_MASK 0x00070000
13193 +/** field offset */
13194 +#define BUSRCON1_FETBLEN_OFFSET 16
13195 +/** Up to 1 data cycle (default after reset). */
13196 +#define BUSRCON1_FETBLEN_SINGLE 0x00000000
13197 +/** Up to 2 data cycles. */
13198 +#define BUSRCON1_FETBLEN_BURST2 0x00010000
13199 +/** Up to 4 data cycles. */
13200 +#define BUSRCON1_FETBLEN_BURST4 0x00020000
13201 +/** Up to 8 data cycles. */
13202 +#define BUSRCON1_FETBLEN_BURST8 0x00030000
13203 +/** Up to 16 data cycles. */
13204 +#define BUSRCON1_FETBLEN_BURST16 0x00040000
13205 +/** Reserved
13206 +    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
13207 +#define BUSRCON1_NANDAMAP_MASK 0x0000C000
13208 +/** field offset */
13209 +#define BUSRCON1_NANDAMAP_OFFSET 14
13210 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
13211 +#define BUSRCON1_NANDAMAP_NAND_A17_16 0x00000000
13212 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
13213 +#define BUSRCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000
13214 +/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
13215 +#define BUSRCON1_NANDAMAP_NAND_AD9_8 0x00008000
13216 +/** Reserved for future use. Do not use or unpredictable results may occur. */
13217 +#define BUSRCON1_NANDAMAP_NAND_RFU 0x0000C000
13218 +/** AAD-mux Protocol
13219 +    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
13220 +#define BUSRCON1_AADMUX 0x00002000
13221 +/* Muxed device is write accessed in AD-mux mode.
13222 +#define BUSRCON1_AADMUX_AD_MUX 0x00000000 */
13223 +/** Muxed device is write accessed in AAD-mux mode. */
13224 +#define BUSRCON1_AADMUX_AAD_MUX 0x00002000
13225 +/** Asynchronous Address Phase */
13226 +#define BUSRCON1_AAP 0x00001000
13227 +/* Clock is enabled at beginning of access.
13228 +#define BUSRCON1_AAP_EARLY 0x00000000 */
13229 +/** Clock is enabled after address phase. */
13230 +#define BUSRCON1_AAP_LATE 0x00001000
13231 +/** Burst Flash Read Single Stage Synchronisation */
13232 +#define BUSRCON1_BFSSS 0x00000800
13233 +/* Two stages of synchronisation used.
13234 +#define BUSRCON1_BFSSS_TWO_STAGE 0x00000000 */
13235 +/** Single stage of synchronisation used. */
13236 +#define BUSRCON1_BFSSS_SINGLE_STAGE 0x00000800
13237 +/** Burst Flash Clock Feedback Enable */
13238 +#define BUSRCON1_FDBKEN 0x00000400
13239 +/* Disable
13240 +#define BUSRCON1_FDBKEN_DIS 0x00000000 */
13241 +/** Enable */
13242 +#define BUSRCON1_FDBKEN_EN 0x00000400
13243 +/** Auxiliary Chip Select Enable
13244 +    Not supported in GPON-EBU, field must be set to 0. */
13245 +#define BUSRCON1_CSA 0x00000200
13246 +/* Disable
13247 +#define BUSRCON1_CSA_DIS 0x00000000 */
13248 +/** Enable */
13249 +#define BUSRCON1_CSA_EN 0x00000200
13250 +/** Flash Non-Array Access Enable
13251 +    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
13252 +#define BUSRCON1_NAA 0x00000100
13253 +/* Disable
13254 +#define BUSRCON1_NAA_DIS 0x00000000 */
13255 +/** Enable */
13256 +#define BUSRCON1_NAA_EN 0x00000100
13257 +/** Module Enable */
13258 +#define BUSRCON1_ENABLE 0x00000001
13259 +/* Disable
13260 +#define BUSRCON1_ENABLE_DIS 0x00000000 */
13261 +/** Enable */
13262 +#define BUSRCON1_ENABLE_EN 0x00000001
13263 +
13264 +/* Fields of "Bus Read Parameters Register1" */
13265 +/** Address Cycles
13266 +    Number of cycles for address phase. */
13267 +#define BUSRP1_ADDRC_MASK 0xF0000000
13268 +/** field offset */
13269 +#define BUSRP1_ADDRC_OFFSET 28
13270 +/** Address Hold Cycles For Multiplexed Address
13271 +    Number of address hold cycles during multiplexed accesses. */
13272 +#define BUSRP1_ADHOLC_MASK 0x0F000000
13273 +/** field offset */
13274 +#define BUSRP1_ADHOLC_OFFSET 24
13275 +/** Programmed Command Delay Cycles
13276 +    Number of delay cycles during command delay phase. */
13277 +#define BUSRP1_CMDDELAY_MASK 0x00F00000
13278 +/** field offset */
13279 +#define BUSRP1_CMDDELAY_OFFSET 20
13280 +/** Extended Data */
13281 +#define BUSRP1_EXTDATA_MASK 0x000C0000
13282 +/** field offset */
13283 +#define BUSRP1_EXTDATA_OFFSET 18
13284 +/** External device outputs data every BFCLK cycle */
13285 +#define BUSRP1_EXTDATA_ONE 0x00000000
13286 +/** External device outputs data every 2nd BFCLK cycles */
13287 +#define BUSRP1_EXTDATA_TWO 0x00040000
13288 +/** External device outputs data every 4th BFCLK cycles */
13289 +#define BUSRP1_EXTDATA_FOUR 0x00080000
13290 +/** External device outputs data every 8th BFCLK cycles */
13291 +#define BUSRP1_EXTDATA_EIGHT 0x000C0000
13292 +/** Frequency of external clock at pin BFCLKO */
13293 +#define BUSRP1_EXTCLOCK_MASK 0x00030000
13294 +/** field offset */
13295 +#define BUSRP1_EXTCLOCK_OFFSET 16
13296 +/** Equal to ebu_clk frequency. */
13297 +#define BUSRP1_EXTCLOCK_ONE_TO_ONE 0x00000000
13298 +/** 1/2 of ebu_clk frequency. */
13299 +#define BUSRP1_EXTCLOCK_ONE_TO_TWO 0x00010000
13300 +/** 1/3 of ebu_clk frequency. */
13301 +#define BUSRP1_EXTCLOCK_ONE_TO_THREE 0x00020000
13302 +/** 1/4 of ebu_clk frequency (default after reset). */
13303 +#define BUSRP1_EXTCLOCK_ONE_TO_FOUR 0x00030000
13304 +/** Data Hold Cycles For read Accesses
13305 +    Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */
13306 +#define BUSRP1_DATAC_MASK 0x0000F000
13307 +/** field offset */
13308 +#define BUSRP1_DATAC_OFFSET 12
13309 +/** Programmed Wait States for read accesses
13310 +    Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
13311 +#define BUSRP1_WAITRDC_MASK 0x00000F80
13312 +/** field offset */
13313 +#define BUSRP1_WAITRDC_OFFSET 7
13314 +/** Recovery Cycles After read Accesses, same CS
13315 +    Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
13316 +#define BUSRP1_RECOVC_MASK 0x00000070
13317 +/** field offset */
13318 +#define BUSRP1_RECOVC_OFFSET 4
13319 +/** Recovery Cycles After read Accesses, other CS
13320 +    Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
13321 +#define BUSRP1_DTACS_MASK 0x0000000F
13322 +/** field offset */
13323 +#define BUSRP1_DTACS_OFFSET 0
13324 +
13325 +/* Fields of "Bus Write Configuration Register1" */
13326 +/** Device Type For Region
13327 +    After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
13328 +#define BUSWCON1_AGEN_MASK 0xF0000000
13329 +/** field offset */
13330 +#define BUSWCON1_AGEN_OFFSET 28
13331 +/** Muxed Asynchronous Type External Memory */
13332 +#define BUSWCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
13333 +/** Muxed Burst Type External Memory */
13334 +#define BUSWCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
13335 +/** NAND Flash (page optimised) */
13336 +#define BUSWCON1_AGEN_NAND_FLASH 0x20000000
13337 +/** Muxed Cellular RAM External Memory */
13338 +#define BUSWCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
13339 +/** Demuxed Asynchronous Type External Memory */
13340 +#define BUSWCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
13341 +/** Demuxed Burst Type External Memory */
13342 +#define BUSWCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
13343 +/** Demuxed Page Mode External Memory */
13344 +#define BUSWCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
13345 +/** Demuxed Cellular RAM External Memory */
13346 +#define BUSWCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
13347 +/** Serial Flash */
13348 +#define BUSWCON1_AGEN_SERIAL_FLASH 0xF0000000
13349 +/** Device Addressing Mode
13350 +    t.b.d. */
13351 +#define BUSWCON1_PORTW_MASK 0x0C000000
13352 +/** field offset */
13353 +#define BUSWCON1_PORTW_OFFSET 26
13354 +/** External Wait Control
13355 +    Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
13356 +#define BUSWCON1_WAIT_MASK 0x03000000
13357 +/** field offset */
13358 +#define BUSWCON1_WAIT_OFFSET 24
13359 +/** WAIT is ignored (default after reset). */
13360 +#define BUSWCON1_WAIT_OFF 0x00000000
13361 +/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
13362 +#define BUSWCON1_WAIT_EARLY_WAIT 0x01000000
13363 +/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
13364 +#define BUSWCON1_WAIT_TWO_STAGE_SYNC 0x01000000
13365 +/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
13366 +#define BUSWCON1_WAIT_WAIT_WITH_DATA 0x02000000
13367 +/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
13368 +#define BUSWCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000
13369 +/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
13370 +#define BUSWCON1_WAIT_ABORT_AND_RETRY 0x03000000
13371 +/** Reserved */
13372 +#define BUSWCON1_LOCKCS 0x00800000
13373 +/** Reversed polarity at wait */
13374 +#define BUSWCON1_WAITINV 0x00400000
13375 +/* Low active.
13376 +#define BUSWCON1_WAITINV_ACTLOW 0x00000000 */
13377 +/** High active */
13378 +#define BUSWCON1_WAITINV_ACTHI 0x00400000
13379 +/** Early ADV Enable for Synchronous Bursts */
13380 +#define BUSWCON1_EBSE 0x00200000
13381 +/* Low active.
13382 +#define BUSWCON1_EBSE_DELAYED 0x00000000 */
13383 +/** High active */
13384 +#define BUSWCON1_EBSE_NOT_DELAYED 0x00200000
13385 +/** Early Control Signals for Synchronous Bursts */
13386 +#define BUSWCON1_ECSE 0x00100000
13387 +/* Low active.
13388 +#define BUSWCON1_ECSE_DELAYED 0x00000000 */
13389 +/** High active */
13390 +#define BUSWCON1_ECSE_NOT_DELAYED 0x00100000
13391 +/** Synchronous Burst Buffer Mode Select */
13392 +#define BUSWCON1_FBBMSEL 0x00080000
13393 +/* FIXED_LENGTH
13394 +#define BUSWCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */
13395 +/** CONTINUOUS */
13396 +#define BUSWCON1_FBBMSEL_CONTINUOUS 0x00080000
13397 +/** Burst Length for Synchronous Burst */
13398 +#define BUSWCON1_FETBLEN_MASK 0x00070000
13399 +/** field offset */
13400 +#define BUSWCON1_FETBLEN_OFFSET 16
13401 +/** Up to 1 data cycle (default after reset). */
13402 +#define BUSWCON1_FETBLEN_SINGLE 0x00000000
13403 +/** Up to 2 data cycles. */
13404 +#define BUSWCON1_FETBLEN_BURST2 0x00010000
13405 +/** Up to 4 data cycles. */
13406 +#define BUSWCON1_FETBLEN_BURST4 0x00020000
13407 +/** Up to 8 data cycles. */
13408 +#define BUSWCON1_FETBLEN_BURST8 0x00030000
13409 +/** Up to 16 data cycles. */
13410 +#define BUSWCON1_FETBLEN_BURST16 0x00040000
13411 +/** Reserved
13412 +    This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
13413 +#define BUSWCON1_NANDAMAP_MASK 0x0000C000
13414 +/** field offset */
13415 +#define BUSWCON1_NANDAMAP_OFFSET 14
13416 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
13417 +#define BUSWCON1_NANDAMAP_NAND_A17_16 0x00000000
13418 +/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
13419 +#define BUSWCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000
13420 +/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
13421 +#define BUSWCON1_NANDAMAP_NAND_AD9_8 0x00008000
13422 +/** Reserved for future use. Do not use or unpredictable results may occur. */
13423 +#define BUSWCON1_NANDAMAP_NAND_RFU 0x0000C000
13424 +/** AAD-mux Protocol
13425 +    If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
13426 +#define BUSWCON1_AADMUX 0x00002000
13427 +/* Muxed device is write accessed in AD-mux mode.
13428 +#define BUSWCON1_AADMUX_AD_MUX 0x00000000 */
13429 +/** Muxed device is write accessed in AAD-mux mode. */
13430 +#define BUSWCON1_AADMUX_AAD_MUX 0x00002000
13431 +/** Asynchronous Address Phase */
13432 +#define BUSWCON1_AAP 0x00001000
13433 +/* Clock is enabled at beginning of access.
13434 +#define BUSWCON1_AAP_EARLY 0x00000000 */
13435 +/** Clock is enabled after address phase. */
13436 +#define BUSWCON1_AAP_LATE 0x00001000
13437 +/** Auxiliary Chip Select Enable
13438 +    Not supported in GPON-EBU, field must be set to 0. */
13439 +#define BUSWCON1_CSA 0x00000200
13440 +/* Disable
13441 +#define BUSWCON1_CSA_DIS 0x00000000 */
13442 +/** Enable */
13443 +#define BUSWCON1_CSA_EN 0x00000200
13444 +/** Flash Non-Array Access Enable
13445 +    Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
13446 +#define BUSWCON1_NAA 0x00000100
13447 +/* Disable
13448 +#define BUSWCON1_NAA_DIS 0x00000000 */
13449 +/** Enable */
13450 +#define BUSWCON1_NAA_EN 0x00000100
13451 +/** Module Enable */
13452 +#define BUSWCON1_ENABLE 0x00000001
13453 +/* Disable
13454 +#define BUSWCON1_ENABLE_DIS 0x00000000 */
13455 +/** Enable */
13456 +#define BUSWCON1_ENABLE_EN 0x00000001
13457 +
13458 +/* Fields of "Bus Write Parameters Register1" */
13459 +/** Address Cycles
13460 +    Number of cycles for address phase. */
13461 +#define BUSWP1_ADDRC_MASK 0xF0000000
13462 +/** field offset */
13463 +#define BUSWP1_ADDRC_OFFSET 28
13464 +/** Address Hold Cycles For Multiplexed Address
13465 +    Number of address hold cycles during multiplexed accesses. */
13466 +#define BUSWP1_ADHOLC_MASK 0x0F000000
13467 +/** field offset */
13468 +#define BUSWP1_ADHOLC_OFFSET 24
13469 +/** Programmed Command Delay Cycles
13470 +    Number of delay cycles during command delay phase. */
13471 +#define BUSWP1_CMDDELAY_MASK 0x00F00000
13472 +/** field offset */
13473 +#define BUSWP1_CMDDELAY_OFFSET 20
13474 +/** Extended Data */
13475 +#define BUSWP1_EXTDATA_MASK 0x000C0000
13476 +/** field offset */
13477 +#define BUSWP1_EXTDATA_OFFSET 18
13478 +/** External device outputs data every BFCLK cycle */
13479 +#define BUSWP1_EXTDATA_ONE 0x00000000
13480 +/** External device outputs data every 2nd BFCLK cycles */
13481 +#define BUSWP1_EXTDATA_TWO 0x00040000
13482 +/** External device outputs data every 4th BFCLK cycles */
13483 +#define BUSWP1_EXTDATA_FOUR 0x00080000
13484 +/** External device outputs data every 8th BFCLK cycles */
13485 +#define BUSWP1_EXTDATA_EIGHT 0x000C0000
13486 +/** Frequency of external clock at pin BFCLKO */
13487 +#define BUSWP1_EXTCLOCK_MASK 0x00030000
13488 +/** field offset */
13489 +#define BUSWP1_EXTCLOCK_OFFSET 16
13490 +/** Equal to ebu_clk frequency. */
13491 +#define BUSWP1_EXTCLOCK_ONE_TO_ONE 0x00000000
13492 +/** 1/2 of ebu_clk frequency. */
13493 +#define BUSWP1_EXTCLOCK_ONE_TO_TWO 0x00010000
13494 +/** 1/3 of ebu_clk frequency. */
13495 +#define BUSWP1_EXTCLOCK_ONE_TO_THREE 0x00020000
13496 +/** 1/4 of ebu_clk frequency (default after reset). */
13497 +#define BUSWP1_EXTCLOCK_ONE_TO_FOUR 0x00030000
13498 +/** Data Hold Cycles For write Accesses
13499 +    Number of data hold cycles during write accesses. */
13500 +#define BUSWP1_DATAC_MASK 0x0000F000
13501 +/** field offset */
13502 +#define BUSWP1_DATAC_OFFSET 12
13503 +/** Programmed Wait States For write Accesses
13504 +    Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
13505 +#define BUSWP1_WAITWDC_MASK 0x00000F80
13506 +/** field offset */
13507 +#define BUSWP1_WAITWDC_OFFSET 7
13508 +/** Recovery Cycles After write Accesses, same CS
13509 +    Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
13510 +#define BUSWP1_RECOVC_MASK 0x00000070
13511 +/** field offset */
13512 +#define BUSWP1_RECOVC_OFFSET 4
13513 +/** Recovery Cycles After write Accesses, other CS
13514 +    Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
13515 +#define BUSWP1_DTACS_MASK 0x0000000F
13516 +/** field offset */
13517 +#define BUSWP1_DTACS_OFFSET 0
13518 +
13519 +/* Fields of "Bus Protocol Configuration Extension Register 0" */
13520 +/** Byte Control Mapping
13521 +    Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */
13522 +#define BUSCONEXT0_BCMAP_MASK 0x00030000
13523 +/** field offset */
13524 +#define BUSCONEXT0_BCMAP_OFFSET 16
13525 +/** No mirroring of byte enables. */
13526 +#define BUSCONEXT0_BCMAP_NOBCMAP 0x00000000
13527 +/** Asynchronous Early Write
13528 +    This bit is obsolete and must be set to 0 or unpredictable results may result. */
13529 +#define BUSCONEXT0_AEW 0x00008000
13530 +/** AAD-mux Consecutive Address Cycles
13531 +    This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */
13532 +#define BUSCONEXT0_ACAC 0x00004000
13533 +/* ADV is deasserted between high and low address phase.
13534 +#define BUSCONEXT0_ACAC_SEPERATED 0x00000000 */
13535 +/** ADV is not deasserted between high and low address phase. */
13536 +#define BUSCONEXT0_ACAC_CONSECUTIVE 0x00004000
13537 +/** AAD-mux Write Address-to-Address Delay
13538 +    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */
13539 +#define BUSCONEXT0_WAAC_MASK 0x00003800
13540 +/** field offset */
13541 +#define BUSCONEXT0_WAAC_OFFSET 11
13542 +/** AAD-mux Read Address-to-Address Delay
13543 +    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */
13544 +#define BUSCONEXT0_RAAC_MASK 0x00000700
13545 +/** field offset */
13546 +#define BUSCONEXT0_RAAC_OFFSET 8
13547 +/** AAD-mux Paging Enable for CS0
13548 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
13549 +#define BUSCONEXT0_PAGE_EN 0x00000080
13550 +/* Disable
13551 +#define BUSCONEXT0_PAGE_EN_DIS 0x00000000 */
13552 +/** Enable */
13553 +#define BUSCONEXT0_PAGE_EN_EN 0x00000080
13554 +/** AAD-mux Address Extension Bit Generation Mode
13555 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
13556 +#define BUSCONEXT0_AEBM_MASK 0x00000070
13557 +/** field offset */
13558 +#define BUSCONEXT0_AEBM_OFFSET 4
13559 +/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */
13560 +#define BUSCONEXT0_AEBM_AMAP_CRE_RFU0 0x00000000
13561 +/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */
13562 +#define BUSCONEXT0_AEBM_AMAP_CRE_RFU1 0x00000010
13563 +/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */
13564 +#define BUSCONEXT0_AEBM_AMAP_CRE_AND_RFU 0x00000020
13565 +/** Do not use */
13566 +#define BUSCONEXT0_AEBM_reserved 0x00000030
13567 +/** A[15:14] in the high address cycle is set to 00B. */
13568 +#define BUSCONEXT0_AEBM_DIRECT_00 0x00000040
13569 +/** A[15:14] in the high address cycle is set to 01B */
13570 +#define BUSCONEXT0_AEBM_DIRECT_01 0x00000050
13571 +/** A[15:14] in the high address cycle is set to 10B */
13572 +#define BUSCONEXT0_AEBM_DIRECT_10 0x00000060
13573 +/** A[15:14] in the high address cycle is set to 11B. */
13574 +#define BUSCONEXT0_AEBM_DIRECT_11 0x00000070
13575 +/** Most Significant Address Bit of External Device
13576 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */
13577 +#define BUSCONEXT0_AMSB_MASK 0x0000000F
13578 +/** field offset */
13579 +#define BUSCONEXT0_AMSB_OFFSET 0
13580 +
13581 +/* Fields of "Bus Protocol Configuration Extension Register 1" */
13582 +/** Byte Control Mapping
13583 +    Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */
13584 +#define BUSCONEXT1_BCMAP_MASK 0x00030000
13585 +/** field offset */
13586 +#define BUSCONEXT1_BCMAP_OFFSET 16
13587 +/** No mirroring of byte enables. */
13588 +#define BUSCONEXT1_BCMAP_NOBCMAP 0x00000000
13589 +/** Asynchronous Early Write
13590 +    This bit is obsolete and must be set to 0 or unpredictable results may result. */
13591 +#define BUSCONEXT1_AEW 0x00008000
13592 +/** AAD-mux Consecutive Address Cycles
13593 +    This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */
13594 +#define BUSCONEXT1_ACAC 0x00004000
13595 +/* ADV is deasserted between high and low address phase.
13596 +#define BUSCONEXT1_ACAC_SEPERATED 0x00000000 */
13597 +/** ADV is not deasserted between high and low address phase. */
13598 +#define BUSCONEXT1_ACAC_CONSECUTIVE 0x00004000
13599 +/** AAD-mux Write Address-to-Address Delay
13600 +    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */
13601 +#define BUSCONEXT1_WAAC_MASK 0x00003800
13602 +/** field offset */
13603 +#define BUSCONEXT1_WAAC_OFFSET 11
13604 +/** AAD-mux Read Address-to-Address Delay
13605 +    Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */
13606 +#define BUSCONEXT1_RAAC_MASK 0x00000700
13607 +/** field offset */
13608 +#define BUSCONEXT1_RAAC_OFFSET 8
13609 +/** AAD-mux Paging Enable for CS0
13610 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
13611 +#define BUSCONEXT1_PAGE_EN 0x00000080
13612 +/* Disable
13613 +#define BUSCONEXT1_PAGE_EN_DIS 0x00000000 */
13614 +/** Enable */
13615 +#define BUSCONEXT1_PAGE_EN_EN 0x00000080
13616 +/** AAD-mux Address Extension Bit Generation Mode
13617 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
13618 +#define BUSCONEXT1_AEBM_MASK 0x00000070
13619 +/** field offset */
13620 +#define BUSCONEXT1_AEBM_OFFSET 4
13621 +/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */
13622 +#define BUSCONEXT1_AEBM_AMAP_CRE_RFU0 0x00000000
13623 +/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */
13624 +#define BUSCONEXT1_AEBM_AMAP_CRE_RFU1 0x00000010
13625 +/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */
13626 +#define BUSCONEXT1_AEBM_AMAP_CRE_AND_RFU 0x00000020
13627 +/** Do not use */
13628 +#define BUSCONEXT1_AEBM_reserved 0x00000030
13629 +/** A[15:14] in the high address cycle is set to 00B. */
13630 +#define BUSCONEXT1_AEBM_DIRECT_00 0x00000040
13631 +/** A[15:14] in the high address cycle is set to 01B */
13632 +#define BUSCONEXT1_AEBM_DIRECT_01 0x00000050
13633 +/** A[15:14] in the high address cycle is set to 10B */
13634 +#define BUSCONEXT1_AEBM_DIRECT_10 0x00000060
13635 +/** A[15:14] in the high address cycle is set to 11B. */
13636 +#define BUSCONEXT1_AEBM_DIRECT_11 0x00000070
13637 +/** Most Significant Address Bit of External Device
13638 +    If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */
13639 +#define BUSCONEXT1_AMSB_MASK 0x0000000F
13640 +/** field offset */
13641 +#define BUSCONEXT1_AMSB_OFFSET 0
13642 +
13643 +/* Fields of "Serial Flash Configuration Register" */
13644 +/** Direct Access Device Port Width
13645 +    DA_PORTW Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode rd_opc. Depending on thedevice type and/or command, the number of used signal lines might differbetween command, address, and data phase of the transaction. */
13646 +#define SFCON_DA_PORTW_MASK 0xE0000000
13647 +/** field offset */
13648 +#define SFCON_DA_PORTW_OFFSET 29
13649 +/** One signal line used in all phases of the transaction. */
13650 +#define SFCON_DA_PORTW_WIDTH_1_1_1 0x00000000
13651 +/** One signal line used in the COMMAND and ADDRESS phase of the transaction and two signal lines used in the DATA phase. */
13652 +#define SFCON_DA_PORTW_WIDTH_1_1_2 0x20000000
13653 +/** One signal used in the COMMAND phase of the transaction and two signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */
13654 +#define SFCON_DA_PORTW_WIDTH_1_2_2 0x40000000
13655 +/** Two signal lines used in all phases of the transaction. */
13656 +#define SFCON_DA_PORTW_WIDTH_2_2_2 0x60000000
13657 +/** One signal line used in the COMMAND and ADDRESS phase of the transaction and four signal lines used in the DATA phase. */
13658 +#define SFCON_DA_PORTW_WIDTH_1_1_4 0x80000000
13659 +/** One signal used in the COMMAND phase of the transaction and four signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */
13660 +#define SFCON_DA_PORTW_WIDTH_1_4_4 0xA0000000
13661 +/** Four signal lines used in all phases of the transaction. */
13662 +#define SFCON_DA_PORTW_WIDTH_4_4_4 0xC0000000
13663 +/** for future use. */
13664 +#define SFCON_DA_PORTW_WIDTH_reserved 0xE0000000
13665 +/** Read Abort Enable
13666 +    If set, a read access from the external device can be aborted via signal sf_rd_abort_i. See Section 3.18.2.9 for details. */
13667 +#define SFCON_RD_ABORT_EN 0x10000000
13668 +/** Device Size
13669 +    Defines the number of significant address bits for the Serial Flash device(s). All address bits above the MSB are forced to 0. The configuration in this field also defines for the address auto-increment feature when to wrap around from the upper most address to 0. */
13670 +#define SFCON_DEV_SIZE_MASK 0x0F000000
13671 +/** field offset */
13672 +#define SFCON_DEV_SIZE_OFFSET 24
13673 +/** 16 MBit device */
13674 +#define SFCON_DEV_SIZE_A20_0 0x00000000
13675 +/** 32 MBit device */
13676 +#define SFCON_DEV_SIZE_A21_0 0x01000000
13677 +/** 64 MBit device */
13678 +#define SFCON_DEV_SIZE_A22_0 0x02000000
13679 +/** 128 MBit device */
13680 +#define SFCON_DEV_SIZE_A23_0 0x03000000
13681 +/** 256 MBit device */
13682 +#define SFCON_DEV_SIZE_A24_0 0x04000000
13683 +/** 512 MBit device */
13684 +#define SFCON_DEV_SIZE_A25_0 0x05000000
13685 +/** 1 GBit device */
13686 +#define SFCON_DEV_SIZE_A26_0 0x06000000
13687 +/** 2 GBit device */
13688 +#define SFCON_DEV_SIZE_A27_0 0x07000000
13689 +/** 4 GBit device */
13690 +#define SFCON_DEV_SIZE_A28_0 0x08000000
13691 +/** 8 GBit device */
13692 +#define SFCON_DEV_SIZE_A29_0 0x09000000
13693 +/** 16 GBit device */
13694 +#define SFCON_DEV_SIZE_A30_0 0x0A000000
13695 +/** 32 GBit device */
13696 +#define SFCON_DEV_SIZE_A31_0 0x0B000000
13697 +/** Device Page Size
13698 +    Defines the page size employed by all connected Serial Flash devices. The device page size is used to determine the address wrap-around for the write address auto-increment feature. */
13699 +#define SFCON_DPS_MASK 0x00C00000
13700 +/** field offset */
13701 +#define SFCON_DPS_OFFSET 22
13702 +/** Device page size is 256 Bytes */
13703 +#define SFCON_DPS_DPS_256 0x00000000
13704 +/** Device page size is 512 Bytes */
13705 +#define SFCON_DPS_DPS_512 0x00400000
13706 +/** Page Buffer Size
13707 +    Defines the size of the EBU's page buffer used in Buffered Access. Page buffer size configured here must be less than or equal to the maximum page buffer size which is a built option of the EBU (256 Bytes for GPON). */
13708 +#define SFCON_PB_SIZE_MASK 0x00300000
13709 +/** field offset */
13710 +#define SFCON_PB_SIZE_OFFSET 20
13711 +/** No read buffer is available/used. */
13712 +#define SFCON_PB_SIZE_NONE 0x00000000
13713 +/** 128 Bytes */
13714 +#define SFCON_PB_SIZE_SIZE_128 0x00100000
13715 +/** 256 Bytes */
13716 +#define SFCON_PB_SIZE_SIZE_256 0x00200000
13717 +/** Bidirectional Data Bus
13718 +    Defines whether the Serial Flash uses a unidirectional or a bidirectional data bus. */
13719 +#define SFCON_BIDIR 0x00080000
13720 +/* The Serial Flash interface uses a pair of two unidirectional busses (one for write, one for read)
13721 +#define SFCON_BIDIR_UNIDIRECTIONAL 0x00000000 */
13722 +/** The Serial Flash interface uses a bidirectional data bus. */
13723 +#define SFCON_BIDIR_BIDIRECTIONAL 0x00080000
13724 +/** No Busy Error termination
13725 +    By default, the EBU error-terminates all direct access to a Serial Flash while EBU_SFSTAT.busy is set. By setting NO_BUSY_ERR, the EBU can be configured to permit direct accesses to proceed to the Serial Flash, e.g. for devices that support a read-while-write functionality. */
13726 +#define SFCON_NO_BUSY_ERR 0x00040000
13727 +/** End-of-Busy Detection Mode
13728 +    Defines how the EBU detects the end of a busy phase in the Serial Flash device. The current version of the EBU requires the software to explicitly poll the device's status register and then inform the EBU on the end of the busy status by clearing the corresponding bit in register EBU_SF_STAT. */
13729 +#define SFCON_EOBDM_MASK 0x00030000
13730 +/** field offset */
13731 +#define SFCON_EOBDM_OFFSET 16
13732 +/** No read buffer is available/used. */
13733 +#define SFCON_EOBDM_SOFTWARE 0x00000000
13734 +/** Poll device status register (not supported yet) */
13735 +#define SFCON_EOBDM_POLL_SR 0x00010000
13736 +/** Poll devices busy/ready pin fed into EBU via WAIT pin (not supported yet). */
13737 +#define SFCON_EOBDM_POLL_RDY 0x00020000
13738 +/** Same as POLL_RDY, but CS must be asserted to have the device output its busy/ready status (not supported yet). */
13739 +#define SFCON_EOBDM_POLL_RDY_WITH_CS 0x00030000
13740 +/** Direct Access Keep Chip Select
13741 +    Defines whether the Serial Flash remains selected after a direct access transaction has been finished. */
13742 +#define SFCON_DA_KEEP_CS 0x00008000
13743 +/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
13744 +#define SFCON_DA_KEEP_CS_DESELECT 0x00000000 */
13745 +/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */
13746 +#define SFCON_DA_KEEP_CS_KEEP_SELECTED 0x00008000
13747 +/** Early Read Abort Enable
13748 +    When aborting a Serial Flash Read is enabled in bit EBU_SFCON.rd_abort_en, bit early_abort selects at what point in the protocol an external access might be aborted. Datasheets of many Serial Flash devices are not explicit on what happens (and whether it is allowed) when a read access is cut-short by deselecting the device during the CMD, ADDR or DUMMY phase of the protocol. */
13749 +#define SFCON_EARLY_ABORT 0x00004000
13750 +/* DISABLE Early abortion is disabled (default after reset). Once the EBU has started the access on the External Bus (first bit time slot), the EBU continues the external transfer until the first data byte has been received. After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
13751 +#define SFCON_EARLY_ABORT_DISABLE 0x00000000 */
13752 +/** Early abortion is not yet supported in the current version of the EBU. Do not use. The feature is a late improvement to the EBU and could not be verified completely before the final release. After proven to work, it should be made officially available to reduce access latency after aborted Serial Flash reads. Setting early_abort to ENABLE alters the read abort handling in the following way: Once the EBU has started the access on the External Bus, the transfer is cut-short after transferring the CMD byte, the three address bytes, any DUMMY bits or at the end of the next data byte - whatever comes first. */
13753 +#define SFCON_EARLY_ABORT_ENABLE 0x00004000
13754 +/** Direct Access Address Length
13755 +    Defines the number of address bytes to be sent (MSB first) to the device with a direct read access transaction. Other values than listed below are not supported and have unpredictable results. */
13756 +#define SFCON_DA_ALEN_MASK 0x00003000
13757 +/** field offset */
13758 +#define SFCON_DA_ALEN_OFFSET 12
13759 +/** 3 address bytes (bits 23:0 of the internal address) */
13760 +#define SFCON_DA_ALEN_THREE 0x00000000
13761 +/** Read Access Dummy Bytes
13762 +    This field defines the number of dummy bytes to send between the last address byte before the EBU starts capturing read data from the bus for a direct read access. The number of dummy bytes depends on the data access command being used (see field), the clock frequency and the type of device being used. */
13763 +#define SFCON_RD_DUMLEN_MASK 0x00000F00
13764 +/** field offset */
13765 +#define SFCON_RD_DUMLEN_OFFSET 8
13766 +/** Direct Read Access Command Opcode
13767 +    This byte defines the command opcode to send when performing a data read from the Serial Flash in Direct Access Mode. Any value can be set (the EBU does not interpret the value, but directly uses the contents of this register field in the command phase of the transaction). Common opcodes to be used and understood by most devices are READ (03H) and FAST_READ (0BH), but some devices might provide additional opcodes, e.g. to support higher clock frequencies requiring additional dummy bytes or to define a wider interface bus. */
13768 +#define SFCON_RD_OPC_MASK 0x000000FF
13769 +/** field offset */
13770 +#define SFCON_RD_OPC_OFFSET 0
13771 +/** READ */
13772 +#define SFCON_RD_OPC_READ 0x00000003
13773 +/** FAST_READ */
13774 +#define SFCON_RD_OPC_FAST_READ 0x0000000B
13775 +
13776 +/* Fields of "Serial Flash Timing Register" */
13777 +/** CS Idle time
13778 +    This field defines the minimum time the device's Chip Select has to be deasserted in between accesses. Most devices require a minimum deselect time between 50 and 100 ns. See Table 43 for the encoding used in this field. */
13779 +#define SFTIME_CS_IDLE_MASK 0xF0000000
13780 +/** field offset */
13781 +#define SFTIME_CS_IDLE_OFFSET 28
13782 +/** 1 EBU clock cycles */
13783 +#define SFTIME_CS_IDLE_CLKC_0 0x00000000
13784 +/** 2 EBU clock cycles */
13785 +#define SFTIME_CS_IDLE_CLKC_1 0x10000000
13786 +/** 3 EBU clock cycles */
13787 +#define SFTIME_CS_IDLE_CLKC_2 0x20000000
13788 +/** 4 EBU clock cycles */
13789 +#define SFTIME_CS_IDLE_CLKC_3 0x30000000
13790 +/** 6 EBU clock cycles */
13791 +#define SFTIME_CS_IDLE_CLKC_4 0x40000000
13792 +/** 8 EBU clock cycles */
13793 +#define SFTIME_CS_IDLE_CLKC_5 0x50000000
13794 +/** 10 EBU clock cycles */
13795 +#define SFTIME_CS_IDLE_CLKC_6 0x60000000
13796 +/** 12 EBU clock cycles */
13797 +#define SFTIME_CS_IDLE_CLKC_7 0x70000000
13798 +/** 14 EBU clock cycles */
13799 +#define SFTIME_CS_IDLE_CLKC_8 0x80000000
13800 +/** 16 EBU clock cycles */
13801 +#define SFTIME_CS_IDLE_CLKC_9 0x90000000
13802 +/** 20 EBU clock cycles */
13803 +#define SFTIME_CS_IDLE_CLKC_10 0xA0000000
13804 +/** 24 EBU clock cycles */
13805 +#define SFTIME_CS_IDLE_CLKC_11 0xB0000000
13806 +/** 32 EBU clock cycles */
13807 +#define SFTIME_CS_IDLE_CLKC_12 0xC0000000
13808 +/** 40 EBU clock cycles */
13809 +#define SFTIME_CS_IDLE_CLKC_13 0xD0000000
13810 +/** 48 EBU clock cycles */
13811 +#define SFTIME_CS_IDLE_CLKC_14 0xE0000000
13812 +/** 64 EBU clock cycles */
13813 +#define SFTIME_CS_IDLE_CLKC_15 0xF0000000
13814 +/** CS Hold time
13815 +    This field defines (in multiples of the EBU internal clock's period) the minimum time the device's Chip Select must remain asserted after transfer of the last bit of a write transaction. This CS hold time does not apply to read accesses */
13816 +#define SFTIME_CS_HOLD_MASK 0x0C000000
13817 +/** field offset */
13818 +#define SFTIME_CS_HOLD_OFFSET 26
13819 +/** CS Setup time
13820 +    This field defines (in multiples of the EBU internal clock's period) when to assert the device's Chip Select before the first SCK clock period for transferring the command is started on the External Bus */
13821 +#define SFTIME_CS_SETUP_MASK 0x03000000
13822 +/** field offset */
13823 +#define SFTIME_CS_SETUP_OFFSET 24
13824 +/** Write-to-Read Pause
13825 +    This field defines the length of the optional pause when switching from write to read direction in the transaction. During this pause, SCK is held stable. */
13826 +#define SFTIME_WR2RD_PAUSE_MASK 0x00300000
13827 +/** field offset */
13828 +#define SFTIME_WR2RD_PAUSE_OFFSET 20
13829 +/** Read Data Position
13830 +    This field defines when to capture valid read data bit(s) (in multiples of half of the EBU internal clock's period) relative to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. RD_POS must be less than or equal to EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. */
13831 +#define SFTIME_RD_POS_MASK 0x000F0000
13832 +/** field offset */
13833 +#define SFTIME_RD_POS_OFFSET 16
13834 +/** SCK Fall-edge Position
13835 +    This field defines the positioning of the SCK fall edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKF_POS must be less than or equal to SCK_PER (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKF_POS defines the positioning of the falling instead of the rising edge of SCK. In the current version of the EBU, SCKF_POS must be set 0 or unpredictable results may occur. */
13836 +#define SFTIME_SCKF_POS_MASK 0x0000F000
13837 +/** field offset */
13838 +#define SFTIME_SCKF_POS_OFFSET 12
13839 +/** SCK Rise-edge Position
13840 +    This field defines the positioning of the SCK rise edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKR_POS must be less than EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKR_POS defines the positioning of the falling instead of the rising edge of SCK. */
13841 +#define SFTIME_SCKR_POS_MASK 0x00000F00
13842 +/** field offset */
13843 +#define SFTIME_SCKR_POS_OFFSET 8
13844 +/** SCK Feedback Clock Inversion
13845 +    If set, read data gets captured with the falling instead of the rising edge of SCK if clock feedback is enabled in EBU_SFTIME.sck_fdbk_en. */
13846 +#define SFTIME_SCK_FDBK_INV 0x00000040
13847 +/** SCK Clock Feedback
13848 +    If set, read data is captured using the external SCK clock feedback into the chip instead of the EBU's internal clock. Using the feedback clock compensate for the high delay over the pads and its use is required at higher frequencies. A penalty for synchronizing the read data from the SCK into the ebu_clk domain applies to the read access latency. */
13849 +#define SFTIME_SCK_FDBK_EN 0x00000020
13850 +/** Inverted SCK
13851 +    If set, the clock to the Serial Flash devices is inverted. This also results in SCK high while a Serial Flash remains selected between transactions (keep_cs feature). In the current version of the EBU, clock inversion is not supported. SCK_INV must be set to 0 or unpredictable results may occur. */
13852 +#define SFTIME_SCK_INV 0x00000010
13853 +/** SCK Period
13854 +    This field defines the period of the SCK clock in multiples of half of the EBU clock period. The EBU supports values between 2 and 14, corresponding to a frequency ratio range from 1:1. to 1:7 between SCK and the internal clock. Other values are prohibited and result in unpredictable behaviour. In the current version of the EBU, odd values for SCK_PER are not supported. */
13855 +#define SFTIME_SCK_PER_MASK 0x0000000F
13856 +/** field offset */
13857 +#define SFTIME_SCK_PER_OFFSET 0
13858 +
13859 +/* Fields of "Serial Flash Status Register" */
13860 +/** Command Overwrite Error
13861 +    This bit is set on an attempt to start an indirect access while a previous indirect access has not finished. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */
13862 +#define SFSTAT_CMD_OVWRT_ERR 0x40000000
13863 +/** Command Error
13864 +    This bit is set when the EBU discards an indirect or direct access to/from a Serial Flash. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */
13865 +#define SFSTAT_CMD_ERR 0x20000000
13866 +/** Access Command Pending
13867 +    If set, indicates that access from/to a Serial Flash device has not finished yet. */
13868 +#define SFSTAT_CMD_PEND 0x00400000
13869 +/** External Device Selected
13870 +    If set, indicates that the Chip Select of a Serial Flash device is currently active on the External Bus. */
13871 +#define SFSTAT_SELECTED 0x00200000
13872 +/** Protocol Engine Active
13873 +    If set, indicates that the EBU's Serial Flash protocol engine is active. */
13874 +#define SFSTAT_ACTIVE 0x00100000
13875 +/** Page Buffer Invalidate
13876 +    When writing a one to this bit, bits PB_VALID and PB_UPDATE are both cleared, thereby invalidating the page buffer for access to/from the Serial Flash device. After invalidating the buffer, PB_INVALID is automatically cleared so that it always reads as 0. */
13877 +#define SFSTAT_PB_INVALID 0x00010000
13878 +/** Page Buffer Update
13879 +    This bit is set when data in the page buffer gets modified. It is cleared when new data gets loaded to the page buffer, when it is written back to the device (WRITE_PAGE command) or when PB_VALID gets cleared. */
13880 +#define SFSTAT_PB_UPDATE 0x00002000
13881 +/** Page Buffer Valid
13882 +    This bit is set after the last data byte of a LOAD_PAGE command has been stored in the page buffer or when the page buffer is explicitely validated via a VALIDATE_PAGE special command. It remains set until the page buffer gets invalidated by writing a 1 to PB_INVALID or any of the LOAD_PAGE special commands. While PB_VALID is set, all accesses to the buffered address range are diverted to the page buffer with no access being performed on the External Bus. */
13883 +#define SFSTAT_PB_VALID 0x00001000
13884 +/** Page Buffer Busy
13885 +    The bit is set when the EBU starts executing a LOAD_PAGE or a WRITE_PAGE command and cleared when the last byte of the requested page has been transferred from/to the external device. The inverted value of PB_BUSY is output on the EBU interface and may trigger a system interrupt. */
13886 +#define SFSTAT_PB_BUSY 0x00000100
13887 +/** Device Busy
13888 +    This bit is set by the Serial Flash protocol engine when an indirect access is performed via register EBU_SFCMD with SET_BUSY being set. While busy is set, access to the Serial Flash is very limited and all transactions are error-terminated except when explicitly marked to ignore the busy status. If the EBU is configured in EBU_SFCON.EOBDM to automatically poll the busy status of the device, busy is cleared as soon as the device is found to be idle again. On a software write, busy remains unaltered when written with a '0' and is toggled when written with a '1', respectively.This toggle-by-write-1 behaviour allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit after it got set by the Serial Flash protocol engine and no automatic busy detection is configured in EBU_SFCON.EOBDM Then the software has to clear busy when it finds the device to be no longer busy by either polling the device's status register via the EBU or by waiting for the maximum busy time of the operation started in the device. */
13889 +#define SFSTAT_BUSY 0x00000001
13890 +
13891 +/* Fields of "Serial Flash Command Register" */
13892 +/** Command Type
13893 +    This field is a qualifier of the command opcode in EBU_SFCMD.opc. Two types */
13894 +#define SFCMD_CMDTYPE 0x80000000
13895 +/* The opcode in EBU_SFCMD.opc is directly used in the command phase of a single transaction to the Serial Flash device.
13896 +#define SFCMD_CMDTYPE_ACCESS_CMD 0x00000000 */
13897 +/** The opcode in EBU_SFCMD.opc is used to start a special command in the Serial Flash Controller which might include any number of external transactions to/from the Serial Flash device. */
13898 +#define SFCMD_CMDTYPE_SPECIAL_CMD 0x80000000
13899 +/** Device Port Width
13900 +    Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode opc. The encoding of this field is the same as forDA_PORTW. */
13901 +#define SFCMD_PORTW_MASK 0x70000000
13902 +/** field offset */
13903 +#define SFCMD_PORTW_OFFSET 28
13904 +/** Bidirectional Signal Lines
13905 +    If set selects bidirectional signal lines to be used for the data transfer. */
13906 +#define SFCMD_BIDIR 0x08000000
13907 +/** Chip Select
13908 +    This field selects which of the EBU's Chip Selects to activated for the command that is written to EBU_SFCMD.opc. A value between 0 and 3 selects one of the EBU's main CSs while 4 to 7 chooses one of the Auxiliary Chip Selects CSA[3:0], respectively. */
13909 +#define SFCMD_CS_MASK 0x07000000
13910 +/** field offset */
13911 +#define SFCMD_CS_OFFSET 24
13912 +/** Disable Auto Address Increment
13913 +    By default, the address in register EBU_SFADDR is automatically incremented with each data byte being transferred. By setting this bit, the auto-increment can be disabled. */
13914 +#define SFCMD_DIS_AAI 0x00800000
13915 +/** Address Length
13916 +    Defines the number of address bytes from register EBU_SFADDR to sent in the address phase of the transaction to/from the Serial Flash. Note: Address bytes are also sent when the command has no data. */
13917 +#define SFCMD_ALEN_MASK 0x00700000
13918 +/** field offset */
13919 +#define SFCMD_ALEN_OFFSET 20
13920 +/** Dummy Phase Length
13921 +    Defines the number of dummy bytes to send to the device between the command/address phase and the data phase of a transaction. Note:Dummy bytes are also sent when the command has no address and/or no data. */
13922 +#define SFCMD_DUMLEN_MASK 0x000F0000
13923 +/** field offset */
13924 +#define SFCMD_DUMLEN_OFFSET 16
13925 +/** Keep Chip Select
13926 +    Defines whether the Serial Flash remains selected after the indirect access transaction has been finished. */
13927 +#define SFCMD_KEEP_CS 0x00008000
13928 +/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
13929 +#define SFCMD_KEEP_CS_DESELECT 0x00000000 */
13930 +/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */
13931 +#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
13932 +/** Set Busy Flag
13933 +    If set, starting the command sets EBU_SFSTAT.busy. */
13934 +#define SFCMD_SET_BUSY 0x00004000
13935 +/** Ignore Busy
13936 +    By default, the EBU error terminates all attempts to access a Serial Flash while EBU_SFSTAT.busy is set. Setting this bit overrules this error termination and permits the command written to EBU_SFCMD.opc to proceed to the External Bus. Normally, this bit is only set to execute a Read Status Register command to the Serial Flash, but may also be used for any other type of access the device is able to handle while it is busy. */
13937 +#define SFCMD_IGNORE_BUSY 0x00002000
13938 +/** Skip Opcode
13939 +    If this bit is set, the opcode in field OPC is not sent to the External Bus, but the external transaction starts with sending the first address byte (if ALEN 0), the first dummy byte (if alen = 0 and DUMLEN 0), or directly with transferring the data bytes (if ALEN = DUMLEN = 0 and DLEN 0). Limiting the external transfer to just the data phase - together with the keep_cs feature - allow to transfer any number of data bytes for a device command sent via EBU_SFCMD by keeping the device selected between accesses and chaining multiple indirect access commands each transferring up to 4 data bytes from/to register EBU_SFDATA. */
13940 +#define SFCMD_SKIP_OPC 0x00001000
13941 +/** Data Length
13942 +    This field defines the number of data bytes to transfer in the data phase of the command. For a read command, the data bytes are stored in register EBU_SFDATA, for a write transfer they are taken from that register. As the data register can hold at most 4 bytes, DLEN is restricted to the range [0..4]. */
13943 +#define SFCMD_DLEN_MASK 0x00000E00
13944 +/** field offset */
13945 +#define SFCMD_DLEN_OFFSET 9
13946 +/** Direction
13947 +    Defines the direction of the data transfer (if any) in the data phase of the transaction to/from the serial bus. */
13948 +#define SFCMD_DIR 0x00000100
13949 +/* dlen bytes of data are read from the Serial Flash during the data phase of the transaction and stored in register EBU_SFDATA.
13950 +#define SFCMD_DIR_READ 0x00000000 */
13951 +/** dlen bytes of data are read from register EBU_SFDATA and written to the Serial Flash during the data phase of the transactione */
13952 +#define SFCMD_DIR_WRITE 0x00000100
13953 +/** Command Opcode
13954 +    A write access to this field starts an Indirect Access command in the EBU's Serial Flash controller. Two types of commands are supported (selected in EBU_SFCMD.cmdtype) and determine how the EBU interprets the opcode:- - For a ACCESS_CMD, a single transaction is executed to/from the Serial Flash device and the OPC is sent to the device in the command phase of the protocol. The number of address, dummy and data bytes to transfer with the command are given in fields ALEN, DUMLEN, and DLEN of register EBU_SFCMD, respectively. - For a SPECIAL_CMD, the EBU starts a complex operation that usually involves multiple transactions to/from the Serial Flash device. See Section 3.18.2.5 for an overview of the complex commands currently supported. */
13955 +#define SFCMD_OPC_MASK 0x000000FF
13956 +/** field offset */
13957 +#define SFCMD_OPC_OFFSET 0
13958 +
13959 +/* Fields of "Serial Flash Address Register" */
13960 +/** Address
13961 +    Before writing to register EBU_SFCMD to start a command that requires the transfer of an address, the address to use must be stored in this register. If not disabled in EBU_SFCMD.dis_aai, ADDR is incremented automatically with each data byte transferred between the EBU and the Serial Flash for an indirect access. Note:Register EBU_SFADDR is only used for access in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */
13962 +#define SFADDR_ADDR_MASK 0xFFFFFFFF
13963 +/** field offset */
13964 +#define SFADDR_ADDR_OFFSET 0
13965 +
13966 +/* Fields of "Serial Flash Data Register" */
13967 +/** Data Bytes
13968 +    Before writing to register EBU_SFCMD to start a command that requires the transfer of data from the EBU to the Serial Flash device (write access), the data to send must be stored in this register. The data bytes have to be right-aligned in this register, that is, the last byte to send must be placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc.. Similarly, for a read access with data being transferred from the Serial Flash to the EBU, this register collects the read data received from the device. The read data is right-aligned, that is, the last byte received gets placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc... The number of data bytes to be transferred between EBU and the Serial Flash is defined in EBU_SFCMD.DLEN. Note:Register EBU_SFDATA is only used for accesses in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */
13969 +#define SFDATA_DATA_MASK 0xFFFFFFFF
13970 +/** field offset */
13971 +#define SFDATA_DATA_OFFSET 0
13972 +
13973 +/* Fields of "Serial Flash I/O Control Register" */
13974 +/** Start of Write Delay
13975 +    By default, the EBU starts driving to AD[3:0] two EBU clock cycles before asserting the CS for an external Serial Flash access. For write accesses, this delay can be increased via field SOWD. */
13976 +#define SFIO_SOWD_MASK 0x0000F000
13977 +/** field offset */
13978 +#define SFIO_SOWD_OFFSET 12
13979 +/** End of Write Delay
13980 +    This field defines the time (in number of EBU clock cycles) for which the EBU keeps driving the External Bus AD[3:0] after deassertion of the device's CS. */
13981 +#define SFIO_EOWD_MASK 0x00000F00
13982 +/** field offset */
13983 +#define SFIO_EOWD_OFFSET 8
13984 +/** Data Output
13985 +    The EBU always controls the AD[3:0] pins while a CS for a Serial Flash device is asserted. Field UNUSED_WD defines the values being driven to these pins while the Serial Flash controller is not writing data to or is reading data from the device via the respective line. See Section 3.18.6 for details. */
13986 +#define SFIO_UNUSED_WD_MASK 0x0000000F
13987 +/** field offset */
13988 +#define SFIO_UNUSED_WD_OFFSET 0
13989 +
13990 +/*! @} */ /* EBU_REGISTER */
13991 +
13992 +#endif /* _ebu_reg_h */