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generic: rtl8366: add generic code to enable VLANs
[openwrt.git] / target / linux / generic / patches-2.6.34 / 975-ssb_update.patch
1 --- a/drivers/net/b44.c
2 +++ b/drivers/net/b44.c
3 @@ -135,7 +135,6 @@ static void b44_init_rings(struct b44 *)
4
5 static void b44_init_hw(struct b44 *, int);
6
7 -static int dma_desc_align_mask;
8 static int dma_desc_sync_size;
9 static int instance;
10
11 @@ -150,9 +149,8 @@ static inline void b44_sync_dma_desc_for
12 unsigned long offset,
13 enum dma_data_direction dir)
14 {
15 - ssb_dma_sync_single_range_for_device(sdev, dma_base,
16 - offset & dma_desc_align_mask,
17 - dma_desc_sync_size, dir);
18 + dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
19 + dma_desc_sync_size, dir);
20 }
21
22 static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
23 @@ -160,9 +158,8 @@ static inline void b44_sync_dma_desc_for
24 unsigned long offset,
25 enum dma_data_direction dir)
26 {
27 - ssb_dma_sync_single_range_for_cpu(sdev, dma_base,
28 - offset & dma_desc_align_mask,
29 - dma_desc_sync_size, dir);
30 + dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
31 + dma_desc_sync_size, dir);
32 }
33
34 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
35 @@ -608,10 +605,10 @@ static void b44_tx(struct b44 *bp)
36
37 BUG_ON(skb == NULL);
38
39 - ssb_dma_unmap_single(bp->sdev,
40 - rp->mapping,
41 - skb->len,
42 - DMA_TO_DEVICE);
43 + dma_unmap_single(bp->sdev->dma_dev,
44 + rp->mapping,
45 + skb->len,
46 + DMA_TO_DEVICE);
47 rp->skb = NULL;
48 dev_kfree_skb_irq(skb);
49 }
50 @@ -648,29 +645,29 @@ static int b44_alloc_rx_skb(struct b44 *
51 if (skb == NULL)
52 return -ENOMEM;
53
54 - mapping = ssb_dma_map_single(bp->sdev, skb->data,
55 - RX_PKT_BUF_SZ,
56 - DMA_FROM_DEVICE);
57 + mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
58 + RX_PKT_BUF_SZ,
59 + DMA_FROM_DEVICE);
60
61 /* Hardware bug work-around, the chip is unable to do PCI DMA
62 to/from anything above 1GB :-( */
63 - if (ssb_dma_mapping_error(bp->sdev, mapping) ||
64 + if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
65 mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
66 /* Sigh... */
67 - if (!ssb_dma_mapping_error(bp->sdev, mapping))
68 - ssb_dma_unmap_single(bp->sdev, mapping,
69 + if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
70 + dma_unmap_single(bp->sdev->dma_dev, mapping,
71 RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
72 dev_kfree_skb_any(skb);
73 skb = __netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ, GFP_ATOMIC|GFP_DMA);
74 if (skb == NULL)
75 return -ENOMEM;
76 - mapping = ssb_dma_map_single(bp->sdev, skb->data,
77 - RX_PKT_BUF_SZ,
78 - DMA_FROM_DEVICE);
79 - if (ssb_dma_mapping_error(bp->sdev, mapping) ||
80 - mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
81 - if (!ssb_dma_mapping_error(bp->sdev, mapping))
82 - ssb_dma_unmap_single(bp->sdev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
83 + mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
84 + RX_PKT_BUF_SZ,
85 + DMA_FROM_DEVICE);
86 + if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
87 + mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
88 + if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
89 + dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
90 dev_kfree_skb_any(skb);
91 return -ENOMEM;
92 }
93 @@ -745,9 +742,9 @@ static void b44_recycle_rx(struct b44 *b
94 dest_idx * sizeof(*dest_desc),
95 DMA_BIDIRECTIONAL);
96
97 - ssb_dma_sync_single_for_device(bp->sdev, dest_map->mapping,
98 - RX_PKT_BUF_SZ,
99 - DMA_FROM_DEVICE);
100 + dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
101 + RX_PKT_BUF_SZ,
102 + DMA_FROM_DEVICE);
103 }
104
105 static int b44_rx(struct b44 *bp, int budget)
106 @@ -767,9 +764,9 @@ static int b44_rx(struct b44 *bp, int bu
107 struct rx_header *rh;
108 u16 len;
109
110 - ssb_dma_sync_single_for_cpu(bp->sdev, map,
111 - RX_PKT_BUF_SZ,
112 - DMA_FROM_DEVICE);
113 + dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
114 + RX_PKT_BUF_SZ,
115 + DMA_FROM_DEVICE);
116 rh = (struct rx_header *) skb->data;
117 len = le16_to_cpu(rh->len);
118 if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
119 @@ -801,8 +798,8 @@ static int b44_rx(struct b44 *bp, int bu
120 skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
121 if (skb_size < 0)
122 goto drop_it;
123 - ssb_dma_unmap_single(bp->sdev, map,
124 - skb_size, DMA_FROM_DEVICE);
125 + dma_unmap_single(bp->sdev->dma_dev, map,
126 + skb_size, DMA_FROM_DEVICE);
127 /* Leave out rx_header */
128 skb_put(skb, len + RX_PKT_OFFSET);
129 skb_pull(skb, RX_PKT_OFFSET);
130 @@ -954,24 +951,24 @@ static netdev_tx_t b44_start_xmit(struct
131 goto err_out;
132 }
133
134 - mapping = ssb_dma_map_single(bp->sdev, skb->data, len, DMA_TO_DEVICE);
135 - if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
136 + mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
137 + if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
138 struct sk_buff *bounce_skb;
139
140 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
141 - if (!ssb_dma_mapping_error(bp->sdev, mapping))
142 - ssb_dma_unmap_single(bp->sdev, mapping, len,
143 + if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
144 + dma_unmap_single(bp->sdev->dma_dev, mapping, len,
145 DMA_TO_DEVICE);
146
147 bounce_skb = __netdev_alloc_skb(dev, len, GFP_ATOMIC | GFP_DMA);
148 if (!bounce_skb)
149 goto err_out;
150
151 - mapping = ssb_dma_map_single(bp->sdev, bounce_skb->data,
152 - len, DMA_TO_DEVICE);
153 - if (ssb_dma_mapping_error(bp->sdev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
154 - if (!ssb_dma_mapping_error(bp->sdev, mapping))
155 - ssb_dma_unmap_single(bp->sdev, mapping,
156 + mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
157 + len, DMA_TO_DEVICE);
158 + if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
159 + if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
160 + dma_unmap_single(bp->sdev->dma_dev, mapping,
161 len, DMA_TO_DEVICE);
162 dev_kfree_skb_any(bounce_skb);
163 goto err_out;
164 @@ -1014,8 +1011,6 @@ static netdev_tx_t b44_start_xmit(struct
165 if (TX_BUFFS_AVAIL(bp) < 1)
166 netif_stop_queue(dev);
167
168 - dev->trans_start = jiffies;
169 -
170 out_unlock:
171 spin_unlock_irqrestore(&bp->lock, flags);
172
173 @@ -1070,8 +1065,8 @@ static void b44_free_rings(struct b44 *b
174
175 if (rp->skb == NULL)
176 continue;
177 - ssb_dma_unmap_single(bp->sdev, rp->mapping, RX_PKT_BUF_SZ,
178 - DMA_FROM_DEVICE);
179 + dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
180 + DMA_FROM_DEVICE);
181 dev_kfree_skb_any(rp->skb);
182 rp->skb = NULL;
183 }
184 @@ -1082,8 +1077,8 @@ static void b44_free_rings(struct b44 *b
185
186 if (rp->skb == NULL)
187 continue;
188 - ssb_dma_unmap_single(bp->sdev, rp->mapping, rp->skb->len,
189 - DMA_TO_DEVICE);
190 + dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
191 + DMA_TO_DEVICE);
192 dev_kfree_skb_any(rp->skb);
193 rp->skb = NULL;
194 }
195 @@ -1105,14 +1100,12 @@ static void b44_init_rings(struct b44 *b
196 memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
197
198 if (bp->flags & B44_FLAG_RX_RING_HACK)
199 - ssb_dma_sync_single_for_device(bp->sdev, bp->rx_ring_dma,
200 - DMA_TABLE_BYTES,
201 - DMA_BIDIRECTIONAL);
202 + dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
203 + DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
204
205 if (bp->flags & B44_FLAG_TX_RING_HACK)
206 - ssb_dma_sync_single_for_device(bp->sdev, bp->tx_ring_dma,
207 - DMA_TABLE_BYTES,
208 - DMA_TO_DEVICE);
209 + dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
210 + DMA_TABLE_BYTES, DMA_TO_DEVICE);
211
212 for (i = 0; i < bp->rx_pending; i++) {
213 if (b44_alloc_rx_skb(bp, -1, i) < 0)
214 @@ -1132,27 +1125,23 @@ static void b44_free_consistent(struct b
215 bp->tx_buffers = NULL;
216 if (bp->rx_ring) {
217 if (bp->flags & B44_FLAG_RX_RING_HACK) {
218 - ssb_dma_unmap_single(bp->sdev, bp->rx_ring_dma,
219 - DMA_TABLE_BYTES,
220 - DMA_BIDIRECTIONAL);
221 + dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
222 + DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
223 kfree(bp->rx_ring);
224 } else
225 - ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
226 - bp->rx_ring, bp->rx_ring_dma,
227 - GFP_KERNEL);
228 + dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
229 + bp->rx_ring, bp->rx_ring_dma);
230 bp->rx_ring = NULL;
231 bp->flags &= ~B44_FLAG_RX_RING_HACK;
232 }
233 if (bp->tx_ring) {
234 if (bp->flags & B44_FLAG_TX_RING_HACK) {
235 - ssb_dma_unmap_single(bp->sdev, bp->tx_ring_dma,
236 - DMA_TABLE_BYTES,
237 - DMA_TO_DEVICE);
238 + dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
239 + DMA_TABLE_BYTES, DMA_TO_DEVICE);
240 kfree(bp->tx_ring);
241 } else
242 - ssb_dma_free_consistent(bp->sdev, DMA_TABLE_BYTES,
243 - bp->tx_ring, bp->tx_ring_dma,
244 - GFP_KERNEL);
245 + dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
246 + bp->tx_ring, bp->tx_ring_dma);
247 bp->tx_ring = NULL;
248 bp->flags &= ~B44_FLAG_TX_RING_HACK;
249 }
250 @@ -1177,7 +1166,8 @@ static int b44_alloc_consistent(struct b
251 goto out_err;
252
253 size = DMA_TABLE_BYTES;
254 - bp->rx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->rx_ring_dma, gfp);
255 + bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
256 + &bp->rx_ring_dma, gfp);
257 if (!bp->rx_ring) {
258 /* Allocation may have failed due to pci_alloc_consistent
259 insisting on use of GFP_DMA, which is more restrictive
260 @@ -1189,11 +1179,11 @@ static int b44_alloc_consistent(struct b
261 if (!rx_ring)
262 goto out_err;
263
264 - rx_ring_dma = ssb_dma_map_single(bp->sdev, rx_ring,
265 - DMA_TABLE_BYTES,
266 - DMA_BIDIRECTIONAL);
267 + rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
268 + DMA_TABLE_BYTES,
269 + DMA_BIDIRECTIONAL);
270
271 - if (ssb_dma_mapping_error(bp->sdev, rx_ring_dma) ||
272 + if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
273 rx_ring_dma + size > DMA_BIT_MASK(30)) {
274 kfree(rx_ring);
275 goto out_err;
276 @@ -1204,7 +1194,8 @@ static int b44_alloc_consistent(struct b
277 bp->flags |= B44_FLAG_RX_RING_HACK;
278 }
279
280 - bp->tx_ring = ssb_dma_alloc_consistent(bp->sdev, size, &bp->tx_ring_dma, gfp);
281 + bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
282 + &bp->tx_ring_dma, gfp);
283 if (!bp->tx_ring) {
284 /* Allocation may have failed due to ssb_dma_alloc_consistent
285 insisting on use of GFP_DMA, which is more restrictive
286 @@ -1216,11 +1207,11 @@ static int b44_alloc_consistent(struct b
287 if (!tx_ring)
288 goto out_err;
289
290 - tx_ring_dma = ssb_dma_map_single(bp->sdev, tx_ring,
291 - DMA_TABLE_BYTES,
292 - DMA_TO_DEVICE);
293 + tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
294 + DMA_TABLE_BYTES,
295 + DMA_TO_DEVICE);
296
297 - if (ssb_dma_mapping_error(bp->sdev, tx_ring_dma) ||
298 + if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
299 tx_ring_dma + size > DMA_BIT_MASK(30)) {
300 kfree(tx_ring);
301 goto out_err;
302 @@ -2178,12 +2169,14 @@ static int __devinit b44_init_one(struct
303 "Failed to powerup the bus\n");
304 goto err_out_free_dev;
305 }
306 - err = ssb_dma_set_mask(sdev, DMA_BIT_MASK(30));
307 - if (err) {
308 +
309 + if (dma_set_mask(sdev->dma_dev, DMA_BIT_MASK(30)) ||
310 + dma_set_coherent_mask(sdev->dma_dev, DMA_BIT_MASK(30))) {
311 dev_err(sdev->dev,
312 "Required 30BIT DMA mask unsupported by the system\n");
313 goto err_out_powerdown;
314 }
315 +
316 err = b44_get_invariants(bp);
317 if (err) {
318 dev_err(sdev->dev,
319 @@ -2346,7 +2339,6 @@ static int __init b44_init(void)
320 int err;
321
322 /* Setup paramaters for syncing RX/TX DMA descriptors */
323 - dma_desc_align_mask = ~(dma_desc_align_size - 1);
324 dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
325
326 err = b44_pci_init();
327 --- a/drivers/ssb/driver_chipcommon.c
328 +++ b/drivers/ssb/driver_chipcommon.c
329 @@ -209,6 +209,24 @@ static void chipco_powercontrol_init(str
330 }
331 }
332
333 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
334 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
335 +{
336 + struct ssb_bus *bus = cc->dev->bus;
337 +
338 + switch (bus->chip_id) {
339 + case 0x4312:
340 + case 0x4322:
341 + case 0x4328:
342 + return 7000;
343 + case 0x4325:
344 + /* TODO: */
345 + default:
346 + return 15000;
347 + }
348 +}
349 +
350 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
351 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
352 {
353 struct ssb_bus *bus = cc->dev->bus;
354 @@ -218,6 +236,12 @@ static void calc_fast_powerup_delay(stru
355
356 if (bus->bustype != SSB_BUSTYPE_PCI)
357 return;
358 +
359 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
360 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
361 + return;
362 + }
363 +
364 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
365 return;
366
367 @@ -233,6 +257,9 @@ void ssb_chipcommon_init(struct ssb_chip
368 {
369 if (!cc->dev)
370 return; /* We don't have a ChipCommon */
371 + if (cc->dev->id.revision >= 11)
372 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
373 + ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
374 ssb_pmu_init(cc);
375 chipco_powercontrol_init(cc);
376 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
377 @@ -370,6 +397,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
378 {
379 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
380 }
381 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
382
383 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
384 {
385 --- a/drivers/ssb/driver_chipcommon_pmu.c
386 +++ b/drivers/ssb/driver_chipcommon_pmu.c
387 @@ -502,9 +502,9 @@ static void ssb_pmu_resources_init(struc
388 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
389 }
390
391 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
392 void ssb_pmu_init(struct ssb_chipcommon *cc)
393 {
394 - struct ssb_bus *bus = cc->dev->bus;
395 u32 pmucap;
396
397 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
398 @@ -516,15 +516,12 @@ void ssb_pmu_init(struct ssb_chipcommon
399 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
400 cc->pmu.rev, pmucap);
401
402 - if (cc->pmu.rev >= 1) {
403 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
404 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
405 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
406 - } else {
407 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
408 - SSB_CHIPCO_PMU_CTL_NOILPONW);
409 - }
410 - }
411 + if (cc->pmu.rev == 1)
412 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
413 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
414 + else
415 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
416 + SSB_CHIPCO_PMU_CTL_NOILPONW);
417 ssb_pmu_pll_init(cc);
418 ssb_pmu_resources_init(cc);
419 }
420 --- a/drivers/ssb/main.c
421 +++ b/drivers/ssb/main.c
422 @@ -486,11 +486,12 @@ static int ssb_devices_register(struct s
423 #ifdef CONFIG_SSB_PCIHOST
424 sdev->irq = bus->host_pci->irq;
425 dev->parent = &bus->host_pci->dev;
426 + sdev->dma_dev = dev->parent;
427 #endif
428 break;
429 case SSB_BUSTYPE_PCMCIA:
430 #ifdef CONFIG_SSB_PCMCIAHOST
431 - sdev->irq = bus->host_pcmcia->irq.AssignedIRQ;
432 + sdev->irq = bus->host_pcmcia->irq;
433 dev->parent = &bus->host_pcmcia->dev;
434 #endif
435 break;
436 @@ -501,6 +502,7 @@ static int ssb_devices_register(struct s
437 break;
438 case SSB_BUSTYPE_SSB:
439 dev->dma_mask = &dev->coherent_dma_mask;
440 + sdev->dma_dev = dev;
441 break;
442 }
443
444 @@ -834,6 +836,9 @@ int ssb_bus_pcibus_register(struct ssb_b
445 if (!err) {
446 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
447 "PCI device %s\n", dev_name(&host_pci->dev));
448 + } else {
449 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
450 + " of SSB with error %d\n", err);
451 }
452
453 return err;
454 @@ -1223,80 +1228,6 @@ u32 ssb_dma_translation(struct ssb_devic
455 }
456 EXPORT_SYMBOL(ssb_dma_translation);
457
458 -int ssb_dma_set_mask(struct ssb_device *dev, u64 mask)
459 -{
460 -#ifdef CONFIG_SSB_PCIHOST
461 - int err;
462 -#endif
463 -
464 - switch (dev->bus->bustype) {
465 - case SSB_BUSTYPE_PCI:
466 -#ifdef CONFIG_SSB_PCIHOST
467 - err = pci_set_dma_mask(dev->bus->host_pci, mask);
468 - if (err)
469 - return err;
470 - err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask);
471 - return err;
472 -#endif
473 - case SSB_BUSTYPE_SSB:
474 - return dma_set_mask(dev->dev, mask);
475 - default:
476 - __ssb_dma_not_implemented(dev);
477 - }
478 - return -ENOSYS;
479 -}
480 -EXPORT_SYMBOL(ssb_dma_set_mask);
481 -
482 -void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
483 - dma_addr_t *dma_handle, gfp_t gfp_flags)
484 -{
485 - switch (dev->bus->bustype) {
486 - case SSB_BUSTYPE_PCI:
487 -#ifdef CONFIG_SSB_PCIHOST
488 - if (gfp_flags & GFP_DMA) {
489 - /* Workaround: The PCI API does not support passing
490 - * a GFP flag. */
491 - return dma_alloc_coherent(&dev->bus->host_pci->dev,
492 - size, dma_handle, gfp_flags);
493 - }
494 - return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle);
495 -#endif
496 - case SSB_BUSTYPE_SSB:
497 - return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags);
498 - default:
499 - __ssb_dma_not_implemented(dev);
500 - }
501 - return NULL;
502 -}
503 -EXPORT_SYMBOL(ssb_dma_alloc_consistent);
504 -
505 -void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
506 - void *vaddr, dma_addr_t dma_handle,
507 - gfp_t gfp_flags)
508 -{
509 - switch (dev->bus->bustype) {
510 - case SSB_BUSTYPE_PCI:
511 -#ifdef CONFIG_SSB_PCIHOST
512 - if (gfp_flags & GFP_DMA) {
513 - /* Workaround: The PCI API does not support passing
514 - * a GFP flag. */
515 - dma_free_coherent(&dev->bus->host_pci->dev,
516 - size, vaddr, dma_handle);
517 - return;
518 - }
519 - pci_free_consistent(dev->bus->host_pci, size,
520 - vaddr, dma_handle);
521 - return;
522 -#endif
523 - case SSB_BUSTYPE_SSB:
524 - dma_free_coherent(dev->dev, size, vaddr, dma_handle);
525 - return;
526 - default:
527 - __ssb_dma_not_implemented(dev);
528 - }
529 -}
530 -EXPORT_SYMBOL(ssb_dma_free_consistent);
531 -
532 int ssb_bus_may_powerdown(struct ssb_bus *bus)
533 {
534 struct ssb_chipcommon *cc;
535 --- a/drivers/ssb/pci.c
536 +++ b/drivers/ssb/pci.c
537 @@ -168,7 +168,7 @@ err_pci:
538 }
539
540 /* Get the word-offset for a SSB_SPROM_XXX define. */
541 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
542 +#define SPOFF(offset) ((offset) / sizeof(u16))
543 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
544 #define SPEX16(_outvar, _offset, _mask, _shift) \
545 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
546 @@ -254,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
547 int i;
548
549 for (i = 0; i < bus->sprom_size; i++)
550 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
551 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
552
553 return 0;
554 }
555 @@ -285,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
556 ssb_printk("75%%");
557 else if (i % 2)
558 ssb_printk(".");
559 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
560 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
561 mmiowb();
562 msleep(20);
563 }
564 @@ -621,6 +621,28 @@ static int ssb_pci_sprom_get(struct ssb_
565 int err = -ENOMEM;
566 u16 *buf;
567
568 + if (!ssb_is_sprom_available(bus)) {
569 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
570 + return -ENODEV;
571 + }
572 + if (bus->chipco.dev) { /* can be unavailible! */
573 + /*
574 + * get SPROM offset: SSB_SPROM_BASE1 except for
575 + * chipcommon rev >= 31 or chip ID is 0x4312 and
576 + * chipcommon status & 3 == 2
577 + */
578 + if (bus->chipco.dev->id.revision >= 31)
579 + bus->sprom_offset = SSB_SPROM_BASE31;
580 + else if (bus->chip_id == 0x4312 &&
581 + (bus->chipco.status & 0x03) == 2)
582 + bus->sprom_offset = SSB_SPROM_BASE31;
583 + else
584 + bus->sprom_offset = SSB_SPROM_BASE1;
585 + } else {
586 + bus->sprom_offset = SSB_SPROM_BASE1;
587 + }
588 + ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
589 +
590 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
591 if (!buf)
592 goto out;
593 --- a/drivers/ssb/sprom.c
594 +++ b/drivers/ssb/sprom.c
595 @@ -176,3 +176,18 @@ const struct ssb_sprom *ssb_get_fallback
596 {
597 return fallback_sprom;
598 }
599 +
600 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
601 +bool ssb_is_sprom_available(struct ssb_bus *bus)
602 +{
603 + /* status register only exists on chipcomon rev >= 11 and we need check
604 + for >= 31 only */
605 + /* this routine differs from specs as we do not access SPROM directly
606 + on PCMCIA */
607 + if (bus->bustype == SSB_BUSTYPE_PCI &&
608 + bus->chipco.dev && /* can be unavailible! */
609 + bus->chipco.dev->id.revision >= 31)
610 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
611 +
612 + return true;
613 +}
614 --- a/include/linux/ssb/ssb.h
615 +++ b/include/linux/ssb/ssb.h
616 @@ -167,7 +167,7 @@ struct ssb_device {
617 * is an optimization. */
618 const struct ssb_bus_ops *ops;
619
620 - struct device *dev;
621 + struct device *dev, *dma_dev;
622
623 struct ssb_bus *bus;
624 struct ssb_device_id id;
625 @@ -305,6 +305,7 @@ struct ssb_bus {
626 /* ID information about the Chip. */
627 u16 chip_id;
628 u16 chip_rev;
629 + u16 sprom_offset;
630 u16 sprom_size; /* number of words in sprom */
631 u8 chip_package;
632
633 @@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru
634
635 extern void ssb_bus_unregister(struct ssb_bus *bus);
636
637 +/* Does the device have an SPROM? */
638 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
639 +
640 /* Set a fallback SPROM.
641 * See kdoc at the function definition for complete documentation. */
642 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
643 @@ -466,14 +470,6 @@ extern u32 ssb_dma_translation(struct ss
644 #define SSB_DMA_TRANSLATION_MASK 0xC0000000
645 #define SSB_DMA_TRANSLATION_SHIFT 30
646
647 -extern int ssb_dma_set_mask(struct ssb_device *dev, u64 mask);
648 -
649 -extern void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size,
650 - dma_addr_t *dma_handle, gfp_t gfp_flags);
651 -extern void ssb_dma_free_consistent(struct ssb_device *dev, size_t size,
652 - void *vaddr, dma_addr_t dma_handle,
653 - gfp_t gfp_flags);
654 -
655 static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev)
656 {
657 #ifdef CONFIG_SSB_DEBUG
658 @@ -482,155 +478,6 @@ static inline void __cold __ssb_dma_not_
659 #endif /* DEBUG */
660 }
661
662 -static inline int ssb_dma_mapping_error(struct ssb_device *dev, dma_addr_t addr)
663 -{
664 - switch (dev->bus->bustype) {
665 - case SSB_BUSTYPE_PCI:
666 -#ifdef CONFIG_SSB_PCIHOST
667 - return pci_dma_mapping_error(dev->bus->host_pci, addr);
668 -#endif
669 - break;
670 - case SSB_BUSTYPE_SSB:
671 - return dma_mapping_error(dev->dev, addr);
672 - default:
673 - break;
674 - }
675 - __ssb_dma_not_implemented(dev);
676 - return -ENOSYS;
677 -}
678 -
679 -static inline dma_addr_t ssb_dma_map_single(struct ssb_device *dev, void *p,
680 - size_t size, enum dma_data_direction dir)
681 -{
682 - switch (dev->bus->bustype) {
683 - case SSB_BUSTYPE_PCI:
684 -#ifdef CONFIG_SSB_PCIHOST
685 - return pci_map_single(dev->bus->host_pci, p, size, dir);
686 -#endif
687 - break;
688 - case SSB_BUSTYPE_SSB:
689 - return dma_map_single(dev->dev, p, size, dir);
690 - default:
691 - break;
692 - }
693 - __ssb_dma_not_implemented(dev);
694 - return 0;
695 -}
696 -
697 -static inline void ssb_dma_unmap_single(struct ssb_device *dev, dma_addr_t dma_addr,
698 - size_t size, enum dma_data_direction dir)
699 -{
700 - switch (dev->bus->bustype) {
701 - case SSB_BUSTYPE_PCI:
702 -#ifdef CONFIG_SSB_PCIHOST
703 - pci_unmap_single(dev->bus->host_pci, dma_addr, size, dir);
704 - return;
705 -#endif
706 - break;
707 - case SSB_BUSTYPE_SSB:
708 - dma_unmap_single(dev->dev, dma_addr, size, dir);
709 - return;
710 - default:
711 - break;
712 - }
713 - __ssb_dma_not_implemented(dev);
714 -}
715 -
716 -static inline void ssb_dma_sync_single_for_cpu(struct ssb_device *dev,
717 - dma_addr_t dma_addr,
718 - size_t size,
719 - enum dma_data_direction dir)
720 -{
721 - switch (dev->bus->bustype) {
722 - case SSB_BUSTYPE_PCI:
723 -#ifdef CONFIG_SSB_PCIHOST
724 - pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
725 - size, dir);
726 - return;
727 -#endif
728 - break;
729 - case SSB_BUSTYPE_SSB:
730 - dma_sync_single_for_cpu(dev->dev, dma_addr, size, dir);
731 - return;
732 - default:
733 - break;
734 - }
735 - __ssb_dma_not_implemented(dev);
736 -}
737 -
738 -static inline void ssb_dma_sync_single_for_device(struct ssb_device *dev,
739 - dma_addr_t dma_addr,
740 - size_t size,
741 - enum dma_data_direction dir)
742 -{
743 - switch (dev->bus->bustype) {
744 - case SSB_BUSTYPE_PCI:
745 -#ifdef CONFIG_SSB_PCIHOST
746 - pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
747 - size, dir);
748 - return;
749 -#endif
750 - break;
751 - case SSB_BUSTYPE_SSB:
752 - dma_sync_single_for_device(dev->dev, dma_addr, size, dir);
753 - return;
754 - default:
755 - break;
756 - }
757 - __ssb_dma_not_implemented(dev);
758 -}
759 -
760 -static inline void ssb_dma_sync_single_range_for_cpu(struct ssb_device *dev,
761 - dma_addr_t dma_addr,
762 - unsigned long offset,
763 - size_t size,
764 - enum dma_data_direction dir)
765 -{
766 - switch (dev->bus->bustype) {
767 - case SSB_BUSTYPE_PCI:
768 -#ifdef CONFIG_SSB_PCIHOST
769 - /* Just sync everything. That's all the PCI API can do. */
770 - pci_dma_sync_single_for_cpu(dev->bus->host_pci, dma_addr,
771 - offset + size, dir);
772 - return;
773 -#endif
774 - break;
775 - case SSB_BUSTYPE_SSB:
776 - dma_sync_single_range_for_cpu(dev->dev, dma_addr, offset,
777 - size, dir);
778 - return;
779 - default:
780 - break;
781 - }
782 - __ssb_dma_not_implemented(dev);
783 -}
784 -
785 -static inline void ssb_dma_sync_single_range_for_device(struct ssb_device *dev,
786 - dma_addr_t dma_addr,
787 - unsigned long offset,
788 - size_t size,
789 - enum dma_data_direction dir)
790 -{
791 - switch (dev->bus->bustype) {
792 - case SSB_BUSTYPE_PCI:
793 -#ifdef CONFIG_SSB_PCIHOST
794 - /* Just sync everything. That's all the PCI API can do. */
795 - pci_dma_sync_single_for_device(dev->bus->host_pci, dma_addr,
796 - offset + size, dir);
797 - return;
798 -#endif
799 - break;
800 - case SSB_BUSTYPE_SSB:
801 - dma_sync_single_range_for_device(dev->dev, dma_addr, offset,
802 - size, dir);
803 - return;
804 - default:
805 - break;
806 - }
807 - __ssb_dma_not_implemented(dev);
808 -}
809 -
810 -
811 #ifdef CONFIG_SSB_PCIHOST
812 /* PCI-host wrapper driver */
813 extern int ssb_pcihost_register(struct pci_driver *driver);
814 --- a/include/linux/ssb/ssb_driver_chipcommon.h
815 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
816 @@ -53,6 +53,7 @@
817 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
818 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
819 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
820 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
821 #define SSB_CHIPCO_CORECTL 0x0008
822 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
823 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
824 @@ -385,6 +386,7 @@
825
826
827 /** Chip specific Chip-Status register contents. */
828 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
829 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
830 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
831 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
832 @@ -398,6 +400,18 @@
833 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
834 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
835
836 +/** Macros to determine SPROM presence based on Chip-Status register. */
837 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
838 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
839 + SSB_CHIPCO_CHST_4325_OTP_SEL)
840 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
841 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
842 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
843 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
844 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
845 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
846 + SSB_CHIPCO_CHST_4325_OTP_SEL))
847 +
848
849
850 /** Clockcontrol masks and values **/
851 @@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
852 struct ssb_chipcommon {
853 struct ssb_device *dev;
854 u32 capabilities;
855 + u32 status;
856 /* Fast Powerup Delay constant */
857 u16 fast_pwrup_delay;
858 struct ssb_chipcommon_pmu pmu;
859 --- a/include/linux/ssb/ssb_regs.h
860 +++ b/include/linux/ssb/ssb_regs.h
861 @@ -170,26 +170,27 @@
862 #define SSB_SPROMSIZE_WORDS_R4 220
863 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
864 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
865 -#define SSB_SPROM_BASE 0x1000
866 -#define SSB_SPROM_REVISION 0x107E
867 +#define SSB_SPROM_BASE1 0x1000
868 +#define SSB_SPROM_BASE31 0x0800
869 +#define SSB_SPROM_REVISION 0x007E
870 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
871 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
872 #define SSB_SPROM_REVISION_CRC_SHIFT 8
873
874 /* SPROM Revision 1 */
875 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
876 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
877 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
878 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
879 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
880 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
881 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
882 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
883 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
884 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
885 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
886 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
887 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
888 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
889 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
890 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
891 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
892 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
893 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
894 -#define SSB_SPROM1_BINF 0x105C /* Board info */
895 +#define SSB_SPROM1_BINF 0x005C /* Board info */
896 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
897 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
898 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
899 @@ -197,63 +198,63 @@
900 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
901 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
902 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
903 -#define SSB_SPROM1_PA0B0 0x105E
904 -#define SSB_SPROM1_PA0B1 0x1060
905 -#define SSB_SPROM1_PA0B2 0x1062
906 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
907 +#define SSB_SPROM1_PA0B0 0x005E
908 +#define SSB_SPROM1_PA0B1 0x0060
909 +#define SSB_SPROM1_PA0B2 0x0062
910 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
911 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
912 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
913 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
914 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
915 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
916 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
917 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
918 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
919 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
920 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
921 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
922 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
923 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
924 -#define SSB_SPROM1_PA1B0 0x106A
925 -#define SSB_SPROM1_PA1B1 0x106C
926 -#define SSB_SPROM1_PA1B2 0x106E
927 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
928 +#define SSB_SPROM1_PA1B0 0x006A
929 +#define SSB_SPROM1_PA1B1 0x006C
930 +#define SSB_SPROM1_PA1B2 0x006E
931 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
932 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
933 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
934 #define SSB_SPROM1_ITSSI_A_SHIFT 8
935 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
936 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
937 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
938 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
939 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
940 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
941 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
942 #define SSB_SPROM1_AGAIN_A_SHIFT 8
943
944 /* SPROM Revision 2 (inherits from rev 1) */
945 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
946 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
947 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
948 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
949 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
950 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
951 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
952 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
953 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
954 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
955 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
956 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
957 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
958 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
959 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
960 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
961 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
962 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
963 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
964 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
965 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
966 #define SSB_SPROM2_OPO_VALUE 0x00FF
967 #define SSB_SPROM2_OPO_UNUSED 0xFF00
968 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
969 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
970
971 /* SPROM Revision 3 (inherits most data from rev 2) */
972 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
973 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
974 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
975 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
976 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
977 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
978 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
979 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
980 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
981 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
982 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
983 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
984 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
985 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
986 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
987 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
988 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
989 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
990 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
991 @@ -264,100 +265,100 @@
992 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
993
994 /* SPROM Revision 4 */
995 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
996 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
997 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
998 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
999 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
1000 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
1001 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
1002 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
1003 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
1004 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
1005 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
1006 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
1007 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
1008 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
1009 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
1010 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
1011 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
1012 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
1013 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
1014 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
1015 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
1016 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
1017 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1018 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1019 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1020 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1021 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
1022 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
1023 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
1024 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1025 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1026 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1027 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1028 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
1029 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
1030 #define SSB_SPROM4_AGAIN0_SHIFT 0
1031 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
1032 #define SSB_SPROM4_AGAIN1_SHIFT 8
1033 -#define SSB_SPROM4_AGAIN23 0x1060
1034 +#define SSB_SPROM4_AGAIN23 0x0060
1035 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
1036 #define SSB_SPROM4_AGAIN2_SHIFT 0
1037 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
1038 #define SSB_SPROM4_AGAIN3_SHIFT 8
1039 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
1040 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
1041 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
1042 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
1043 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1044 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
1045 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
1046 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
1047 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
1048 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1049 #define SSB_SPROM4_ITSSI_A_SHIFT 8
1050 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
1051 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
1052 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
1053 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
1054 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
1055 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
1056 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
1057 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
1058 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
1059 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
1060 -#define SSB_SPROM4_PA0B2 0x1086
1061 -#define SSB_SPROM4_PA1B0 0x108E
1062 -#define SSB_SPROM4_PA1B1 0x1090
1063 -#define SSB_SPROM4_PA1B2 0x1092
1064 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
1065 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
1066 +#define SSB_SPROM4_PA0B2 0x0086
1067 +#define SSB_SPROM4_PA1B0 0x008E
1068 +#define SSB_SPROM4_PA1B1 0x0090
1069 +#define SSB_SPROM4_PA1B2 0x0092
1070
1071 /* SPROM Revision 5 (inherits most data from rev 4) */
1072 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
1073 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
1074 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
1075 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
1076 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
1077 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
1078 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
1079 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
1080 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
1081 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
1082 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1083 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
1084 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
1085 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
1086 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
1087 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
1088 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
1089 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
1090
1091 /* SPROM Revision 8 */
1092 -#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */
1093 -#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */
1094 -#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */
1095 -#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */
1096 -#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */
1097 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
1098 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
1099 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
1100 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1101 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1102 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1103 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1104 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
1105 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
1106 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
1107 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
1108 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
1109 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
1110 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
1111 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
1112 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
1113 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1114 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1115 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1116 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
1117 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1118 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1119 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1120 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
1121 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1122 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1123 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1124 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1125 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
1126 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1127 #define SSB_SPROM8_AGAIN0_SHIFT 0
1128 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1129 #define SSB_SPROM8_AGAIN1_SHIFT 8
1130 -#define SSB_SPROM8_AGAIN23 0x10A0
1131 +#define SSB_SPROM8_AGAIN23 0x00A0
1132 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1133 #define SSB_SPROM8_AGAIN2_SHIFT 0
1134 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1135 #define SSB_SPROM8_AGAIN3_SHIFT 8
1136 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1137 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1138 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1139 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1140 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1141 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1142 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1143 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1144 -#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */
1145 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
1146 #define SSB_SPROM8_RSSISMF2G 0x000F
1147 #define SSB_SPROM8_RSSISMC2G 0x00F0
1148 #define SSB_SPROM8_RSSISMC2G_SHIFT 4
1149 @@ -365,7 +366,7 @@
1150 #define SSB_SPROM8_RSSISAV2G_SHIFT 8
1151 #define SSB_SPROM8_BXA2G 0x1800
1152 #define SSB_SPROM8_BXA2G_SHIFT 11
1153 -#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */
1154 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
1155 #define SSB_SPROM8_RSSISMF5G 0x000F
1156 #define SSB_SPROM8_RSSISMC5G 0x00F0
1157 #define SSB_SPROM8_RSSISMC5G_SHIFT 4
1158 @@ -373,47 +374,47 @@
1159 #define SSB_SPROM8_RSSISAV5G_SHIFT 8
1160 #define SSB_SPROM8_BXA5G 0x1800
1161 #define SSB_SPROM8_BXA5G_SHIFT 11
1162 -#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */
1163 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
1164 #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1165 #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1166 #define SSB_SPROM8_TRI5G_SHIFT 8
1167 -#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */
1168 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
1169 #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1170 #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1171 #define SSB_SPROM8_TRI5GH_SHIFT 8
1172 -#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */
1173 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
1174 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1175 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1176 #define SSB_SPROM8_RXPO5G_SHIFT 8
1177 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */
1178 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1179 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1180 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1181 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
1182 -#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */
1183 -#define SSB_SPROM8_PA0B1 0x10C4
1184 -#define SSB_SPROM8_PA0B2 0x10C6
1185 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */
1186 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1187 +#define SSB_SPROM8_PA0B1 0x00C4
1188 +#define SSB_SPROM8_PA0B2 0x00C6
1189 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
1190 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1191 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1192 #define SSB_SPROM8_ITSSI_A_SHIFT 8
1193 -#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */
1194 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
1195 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1196 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1197 #define SSB_SPROM8_MAXP_AL_SHIFT 8
1198 -#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */
1199 -#define SSB_SPROM8_PA1B1 0x10CE
1200 -#define SSB_SPROM8_PA1B2 0x10D0
1201 -#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */
1202 -#define SSB_SPROM8_PA1LOB1 0x10D4
1203 -#define SSB_SPROM8_PA1LOB2 0x10D6
1204 -#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */
1205 -#define SSB_SPROM8_PA1HIB1 0x10DA
1206 -#define SSB_SPROM8_PA1HIB2 0x10DC
1207 -#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */
1208 -#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */
1209 -#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */
1210 -#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */
1211 -#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */
1212 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1213 +#define SSB_SPROM8_PA1B1 0x00CE
1214 +#define SSB_SPROM8_PA1B2 0x00D0
1215 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1216 +#define SSB_SPROM8_PA1LOB1 0x00D4
1217 +#define SSB_SPROM8_PA1LOB2 0x00D6
1218 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1219 +#define SSB_SPROM8_PA1HIB1 0x00DA
1220 +#define SSB_SPROM8_PA1HIB2 0x00DC
1221 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1222 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1223 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1224 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1225 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1226
1227 /* Values for SSB_SPROM1_BINF_CCODE */
1228 enum {
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