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ar71xx: setup wdt_clock for AR913X to avoid a kernel bug
[openwrt.git] / target / linux / ar71xx / files / drivers / serial / ar933x_uart.c
1 /*
2 * linux/drivers/serial/hornet_serial.c
3 *
4 * Driver for hornet serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2010 Ryan Hsu.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id$
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/tty_flip.h>
33 #include <linux/serial_reg.h>
34 #include <linux/serial_core.h>
35 #include <linux/serial.h>
36 #include <linux/serial_8250.h>
37 #include <linux/nmi.h>
38 #include <linux/mutex.h>
39 #include <linux/slab.h>
40
41 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
42
43 #include <asm/io.h>
44 #include <asm/irq.h>
45
46 #include "8250.h"
47 #define ar7240_reg_rmw_clear(_reg, _val) do {} while (0)
48
49 #define DRIVER_NAME "ar933x-uart"
50
51 #define AR933X_UART_REGS_SIZE 20
52 #define AR933X_UART_FIFO_SIZE 16
53
54 /*
55 * Uart block
56 */
57 #define UARTDATA_UARTTXCSR_MSB 9
58 #define UARTDATA_UARTTXCSR_LSB 9
59 #define UARTDATA_UARTTXCSR_MASK 0x00000200
60 #define UARTDATA_UARTTXCSR_GET(x) (((x) & UARTDATA_UARTTXCSR_MASK) >> UARTDATA_UARTTXCSR_LSB)
61 #define UARTDATA_UARTTXCSR_SET(x) (((0 | (x)) << UARTDATA_UARTTXCSR_LSB) & UARTDATA_UARTTXCSR_MASK)
62 #define UARTDATA_UARTTXCSR_RESET 0
63 #define UARTDATA_UARTRXCSR_MSB 8
64 #define UARTDATA_UARTRXCSR_LSB 8
65 #define UARTDATA_UARTRXCSR_MASK 0x00000100
66 #define UARTDATA_UARTRXCSR_GET(x) (((x) & UARTDATA_UARTRXCSR_MASK) >> UARTDATA_UARTRXCSR_LSB)
67 #define UARTDATA_UARTRXCSR_SET(x) (((0 | (x)) << UARTDATA_UARTRXCSR_LSB) & UARTDATA_UARTRXCSR_MASK)
68 #define UARTDATA_UARTRXCSR_RESET 0
69 #define UARTDATA_UARTTXRXDATA_MSB 7
70 #define UARTDATA_UARTTXRXDATA_LSB 0
71 #define UARTDATA_UARTTXRXDATA_MASK 0x000000ff
72 #define UARTDATA_UARTTXRXDATA_GET(x) (((x) & UARTDATA_UARTTXRXDATA_MASK) >> UARTDATA_UARTTXRXDATA_LSB)
73 #define UARTDATA_UARTTXRXDATA_SET(x) (((0 | (x)) << UARTDATA_UARTTXRXDATA_LSB) & UARTDATA_UARTTXRXDATA_MASK)
74 #define UARTDATA_UARTTXRXDATA_RESET 0
75 #define UARTDATA_ADDRESS 0x0000
76 #define UARTDATA_HW_MASK 0x000003ff
77 #define UARTDATA_SW_MASK 0x000003ff
78 #define UARTDATA_RSTMASK 0x000003ff
79 #define UARTDATA_RESET 0x00000000
80
81 // 0x0004 (UARTCS)
82 #define UARTCS_UARTRXBUSY_MSB 15
83 #define UARTCS_UARTRXBUSY_LSB 15
84 #define UARTCS_UARTRXBUSY_MASK 0x00008000
85 #define UARTCS_UARTRXBUSY_GET(x) (((x) & UARTCS_UARTRXBUSY_MASK) >> UARTCS_UARTRXBUSY_LSB)
86 #define UARTCS_UARTRXBUSY_SET(x) (((0 | (x)) << UARTCS_UARTRXBUSY_LSB) & UARTCS_UARTRXBUSY_MASK)
87 #define UARTCS_UARTRXBUSY_RESET 0
88 #define UARTCS_UARTTXBUSY_MSB 14
89 #define UARTCS_UARTTXBUSY_LSB 14
90 #define UARTCS_UARTTXBUSY_MASK 0x00004000
91 #define UARTCS_UARTTXBUSY_GET(x) (((x) & UARTCS_UARTTXBUSY_MASK) >> UARTCS_UARTTXBUSY_LSB)
92 #define UARTCS_UARTTXBUSY_SET(x) (((0 | (x)) << UARTCS_UARTTXBUSY_LSB) & UARTCS_UARTTXBUSY_MASK)
93 #define UARTCS_UARTTXBUSY_RESET 0
94 #define UARTCS_UARTHOSTINTEN_MSB 13
95 #define UARTCS_UARTHOSTINTEN_LSB 13
96 #define UARTCS_UARTHOSTINTEN_MASK 0x00002000
97 #define UARTCS_UARTHOSTINTEN_GET(x) (((x) & UARTCS_UARTHOSTINTEN_MASK) >> UARTCS_UARTHOSTINTEN_LSB)
98 #define UARTCS_UARTHOSTINTEN_SET(x) (((0 | (x)) << UARTCS_UARTHOSTINTEN_LSB) & UARTCS_UARTHOSTINTEN_MASK)
99 #define UARTCS_UARTHOSTINTEN_RESET 0
100 #define UARTCS_UARTHOSTINT_MSB 12
101 #define UARTCS_UARTHOSTINT_LSB 12
102 #define UARTCS_UARTHOSTINT_MASK 0x00001000
103 #define UARTCS_UARTHOSTINT_GET(x) (((x) & UARTCS_UARTHOSTINT_MASK) >> UARTCS_UARTHOSTINT_LSB)
104 #define UARTCS_UARTHOSTINT_SET(x) (((0 | (x)) << UARTCS_UARTHOSTINT_LSB) & UARTCS_UARTHOSTINT_MASK)
105 #define UARTCS_UARTHOSTINT_RESET 0
106 #define UARTCS_UARTTXBREAK_MSB 11
107 #define UARTCS_UARTTXBREAK_LSB 11
108 #define UARTCS_UARTTXBREAK_MASK 0x00000800
109 #define UARTCS_UARTTXBREAK_GET(x) (((x) & UARTCS_UARTTXBREAK_MASK) >> UARTCS_UARTTXBREAK_LSB)
110 #define UARTCS_UARTTXBREAK_SET(x) (((0 | (x)) << UARTCS_UARTTXBREAK_LSB) & UARTCS_UARTTXBREAK_MASK)
111 #define UARTCS_UARTTXBREAK_RESET 0
112 #define UARTCS_UARTRXBREAK_MSB 10
113 #define UARTCS_UARTRXBREAK_LSB 10
114 #define UARTCS_UARTRXBREAK_MASK 0x00000400
115 #define UARTCS_UARTRXBREAK_GET(x) (((x) & UARTCS_UARTRXBREAK_MASK) >> UARTCS_UARTRXBREAK_LSB)
116 #define UARTCS_UARTRXBREAK_SET(x) (((0 | (x)) << UARTCS_UARTRXBREAK_LSB) & UARTCS_UARTRXBREAK_MASK)
117 #define UARTCS_UARTRXBREAK_RESET 0
118 #define UARTCS_UARTSERIATXREADY_MSB 9
119 #define UARTCS_UARTSERIATXREADY_LSB 9
120 #define UARTCS_UARTSERIATXREADY_MASK 0x00000200
121 #define UARTCS_UARTSERIATXREADY_GET(x) (((x) & UARTCS_UARTSERIATXREADY_MASK) >> UARTCS_UARTSERIATXREADY_LSB)
122 #define UARTCS_UARTSERIATXREADY_SET(x) (((0 | (x)) << UARTCS_UARTSERIATXREADY_LSB) & UARTCS_UARTSERIATXREADY_MASK)
123 #define UARTCS_UARTSERIATXREADY_RESET 0
124 #define UARTCS_UARTTXREADYORIDE_MSB 8
125 #define UARTCS_UARTTXREADYORIDE_LSB 8
126 #define UARTCS_UARTTXREADYORIDE_MASK 0x00000100
127 #define UARTCS_UARTTXREADYORIDE_GET(x) (((x) & UARTCS_UARTTXREADYORIDE_MASK) >> UARTCS_UARTTXREADYORIDE_LSB)
128 #define UARTCS_UARTTXREADYORIDE_SET(x) (((0 | (x)) << UARTCS_UARTTXREADYORIDE_LSB) & UARTCS_UARTTXREADYORIDE_MASK)
129 #define UARTCS_UARTTXREADYORIDE_RESET 0
130 #define UARTCS_UARTRXREADYORIDE_MSB 7
131 #define UARTCS_UARTRXREADYORIDE_LSB 7
132 #define UARTCS_UARTRXREADYORIDE_MASK 0x00000080
133 #define UARTCS_UARTRXREADYORIDE_GET(x) (((x) & UARTCS_UARTRXREADYORIDE_MASK) >> UARTCS_UARTRXREADYORIDE_LSB)
134 #define UARTCS_UARTRXREADYORIDE_SET(x) (((0 | (x)) << UARTCS_UARTRXREADYORIDE_LSB) & UARTCS_UARTRXREADYORIDE_MASK)
135 #define UARTCS_UARTRXREADYORIDE_RESET 0
136 #define UARTCS_UARTDMAEN_MSB 6
137 #define UARTCS_UARTDMAEN_LSB 6
138 #define UARTCS_UARTDMAEN_MASK 0x00000040
139 #define UARTCS_UARTDMAEN_GET(x) (((x) & UARTCS_UARTDMAEN_MASK) >> UARTCS_UARTDMAEN_LSB)
140 #define UARTCS_UARTDMAEN_SET(x) (((0 | (x)) << UARTCS_UARTDMAEN_LSB) & UARTCS_UARTDMAEN_MASK)
141 #define UARTCS_UARTDMAEN_RESET 0
142 #define UARTCS_UARTFLOWCONTROLMODE_MSB 5
143 #define UARTCS_UARTFLOWCONTROLMODE_LSB 4
144 #define UARTCS_UARTFLOWCONTROLMODE_MASK 0x00000030
145 #define UARTCS_UARTFLOWCONTROLMODE_GET(x) (((x) & UARTCS_UARTFLOWCONTROLMODE_MASK) >> UARTCS_UARTFLOWCONTROLMODE_LSB)
146 #define UARTCS_UARTFLOWCONTROLMODE_SET(x) (((0 | (x)) << UARTCS_UARTFLOWCONTROLMODE_LSB) & UARTCS_UARTFLOWCONTROLMODE_MASK)
147 #define UARTCS_UARTFLOWCONTROLMODE_RESET 0
148 #define UARTCS_UARTINTERFACEMODE_MSB 3
149 #define UARTCS_UARTINTERFACEMODE_LSB 2
150 #define UARTCS_UARTINTERFACEMODE_MASK 0x0000000c
151 #define UARTCS_UARTINTERFACEMODE_GET(x) (((x) & UARTCS_UARTINTERFACEMODE_MASK) >> UARTCS_UARTINTERFACEMODE_LSB)
152 #define UARTCS_UARTINTERFACEMODE_SET(x) (((0 | (x)) << UARTCS_UARTINTERFACEMODE_LSB) & UARTCS_UARTINTERFACEMODE_MASK)
153 #define UARTCS_UARTINTERFACEMODE_RESET 0
154 #define UARTCS_UARTPARITYMODE_MSB 1
155 #define UARTCS_UARTPARITYMODE_LSB 0
156 #define UARTCS_UARTPARITYMODE_MASK 0x00000003
157 #define UARTCS_UARTPARITYMODE_GET(x) (((x) & UARTCS_UARTPARITYMODE_MASK) >> UARTCS_UARTPARITYMODE_LSB)
158 #define UARTCS_UARTPARITYMODE_SET(x) (((0 | (x)) << UARTCS_UARTPARITYMODE_LSB) & UARTCS_UARTPARITYMODE_MASK)
159 #define UARTCS_UARTPARITYMODE_RESET 0
160 #define UARTCS_ADDRESS 0x0004
161 #define UARTCS_HW_MASK 0x0000ffff
162 #define UARTCS_SW_MASK 0x0000ffff
163 #define UARTCS_RSTMASK 0x000029ff
164 #define UARTCS_RESET 0x00000000
165
166 // 0x0008 (UARTCLOCK)
167 #define UARTCLOCK_UARTCLOCKSCALE_MSB 23
168 #define UARTCLOCK_UARTCLOCKSCALE_LSB 16
169 #define UARTCLOCK_UARTCLOCKSCALE_MASK 0x00ff0000
170 #define UARTCLOCK_UARTCLOCKSCALE_GET(x) (((x) & UARTCLOCK_UARTCLOCKSCALE_MASK) >> UARTCLOCK_UARTCLOCKSCALE_LSB)
171 #define UARTCLOCK_UARTCLOCKSCALE_SET(x) (((0 | (x)) << UARTCLOCK_UARTCLOCKSCALE_LSB) & UARTCLOCK_UARTCLOCKSCALE_MASK)
172 #define UARTCLOCK_UARTCLOCKSCALE_RESET 0
173 #define UARTCLOCK_UARTCLOCKSTEP_MSB 15
174 #define UARTCLOCK_UARTCLOCKSTEP_LSB 0
175 #define UARTCLOCK_UARTCLOCKSTEP_MASK 0x0000ffff
176 #define UARTCLOCK_UARTCLOCKSTEP_GET(x) (((x) & UARTCLOCK_UARTCLOCKSTEP_MASK) >> UARTCLOCK_UARTCLOCKSTEP_LSB)
177 #define UARTCLOCK_UARTCLOCKSTEP_SET(x) (((0 | (x)) << UARTCLOCK_UARTCLOCKSTEP_LSB) & UARTCLOCK_UARTCLOCKSTEP_MASK)
178 #define UARTCLOCK_UARTCLOCKSTEP_RESET 0
179 #define UARTCLOCK_ADDRESS 0x0008
180 #define UARTCLOCK_HW_MASK 0x00ffffff
181 #define UARTCLOCK_SW_MASK 0x00ffffff
182 #define UARTCLOCK_RSTMASK 0x00ffffff
183 #define UARTCLOCK_RESET 0x00000000
184
185 // 0x000c (UARTINT)
186 #define UARTINT_UARTTXEMPTYINT_MSB 9
187 #define UARTINT_UARTTXEMPTYINT_LSB 9
188 #define UARTINT_UARTTXEMPTYINT_MASK 0x00000200
189 #define UARTINT_UARTTXEMPTYINT_GET(x) (((x) & UARTINT_UARTTXEMPTYINT_MASK) >> UARTINT_UARTTXEMPTYINT_LSB)
190 #define UARTINT_UARTTXEMPTYINT_SET(x) (((0 | (x)) << UARTINT_UARTTXEMPTYINT_LSB) & UARTINT_UARTTXEMPTYINT_MASK)
191 #define UARTINT_UARTTXEMPTYINT_RESET 0
192 #define UARTINT_UARTRXFULLINT_MSB 8
193 #define UARTINT_UARTRXFULLINT_LSB 8
194 #define UARTINT_UARTRXFULLINT_MASK 0x00000100
195 #define UARTINT_UARTRXFULLINT_GET(x) (((x) & UARTINT_UARTRXFULLINT_MASK) >> UARTINT_UARTRXFULLINT_LSB)
196 #define UARTINT_UARTRXFULLINT_SET(x) (((0 | (x)) << UARTINT_UARTRXFULLINT_LSB) & UARTINT_UARTRXFULLINT_MASK)
197 #define UARTINT_UARTRXFULLINT_RESET 0
198 #define UARTINT_UARTRXBREAKOFFINT_MSB 7
199 #define UARTINT_UARTRXBREAKOFFINT_LSB 7
200 #define UARTINT_UARTRXBREAKOFFINT_MASK 0x00000080
201 #define UARTINT_UARTRXBREAKOFFINT_GET(x) (((x) & UARTINT_UARTRXBREAKOFFINT_MASK) >> UARTINT_UARTRXBREAKOFFINT_LSB)
202 #define UARTINT_UARTRXBREAKOFFINT_SET(x) (((0 | (x)) << UARTINT_UARTRXBREAKOFFINT_LSB) & UARTINT_UARTRXBREAKOFFINT_MASK)
203 #define UARTINT_UARTRXBREAKOFFINT_RESET 0
204 #define UARTINT_UARTRXBREAKONINT_MSB 6
205 #define UARTINT_UARTRXBREAKONINT_LSB 6
206 #define UARTINT_UARTRXBREAKONINT_MASK 0x00000040
207 #define UARTINT_UARTRXBREAKONINT_GET(x) (((x) & UARTINT_UARTRXBREAKONINT_MASK) >> UARTINT_UARTRXBREAKONINT_LSB)
208 #define UARTINT_UARTRXBREAKONINT_SET(x) (((0 | (x)) << UARTINT_UARTRXBREAKONINT_LSB) & UARTINT_UARTRXBREAKONINT_MASK)
209 #define UARTINT_UARTRXBREAKONINT_RESET 0
210 #define UARTINT_UARTRXPARITYERRINT_MSB 5
211 #define UARTINT_UARTRXPARITYERRINT_LSB 5
212 #define UARTINT_UARTRXPARITYERRINT_MASK 0x00000020
213 #define UARTINT_UARTRXPARITYERRINT_GET(x) (((x) & UARTINT_UARTRXPARITYERRINT_MASK) >> UARTINT_UARTRXPARITYERRINT_LSB)
214 #define UARTINT_UARTRXPARITYERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXPARITYERRINT_LSB) & UARTINT_UARTRXPARITYERRINT_MASK)
215 #define UARTINT_UARTRXPARITYERRINT_RESET 0
216 #define UARTINT_UARTTXOFLOWERRINT_MSB 4
217 #define UARTINT_UARTTXOFLOWERRINT_LSB 4
218 #define UARTINT_UARTTXOFLOWERRINT_MASK 0x00000010
219 #define UARTINT_UARTTXOFLOWERRINT_GET(x) (((x) & UARTINT_UARTTXOFLOWERRINT_MASK) >> UARTINT_UARTTXOFLOWERRINT_LSB)
220 #define UARTINT_UARTTXOFLOWERRINT_SET(x) (((0 | (x)) << UARTINT_UARTTXOFLOWERRINT_LSB) & UARTINT_UARTTXOFLOWERRINT_MASK)
221 #define UARTINT_UARTTXOFLOWERRINT_RESET 0
222 #define UARTINT_UARTRXOFLOWERRINT_MSB 3
223 #define UARTINT_UARTRXOFLOWERRINT_LSB 3
224 #define UARTINT_UARTRXOFLOWERRINT_MASK 0x00000008
225 #define UARTINT_UARTRXOFLOWERRINT_GET(x) (((x) & UARTINT_UARTRXOFLOWERRINT_MASK) >> UARTINT_UARTRXOFLOWERRINT_LSB)
226 #define UARTINT_UARTRXOFLOWERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXOFLOWERRINT_LSB) & UARTINT_UARTRXOFLOWERRINT_MASK)
227 #define UARTINT_UARTRXOFLOWERRINT_RESET 0
228 #define UARTINT_UARTRXFRAMINGERRINT_MSB 2
229 #define UARTINT_UARTRXFRAMINGERRINT_LSB 2
230 #define UARTINT_UARTRXFRAMINGERRINT_MASK 0x00000004
231 #define UARTINT_UARTRXFRAMINGERRINT_GET(x) (((x) & UARTINT_UARTRXFRAMINGERRINT_MASK) >> UARTINT_UARTRXFRAMINGERRINT_LSB)
232 #define UARTINT_UARTRXFRAMINGERRINT_SET(x) (((0 | (x)) << UARTINT_UARTRXFRAMINGERRINT_LSB) & UARTINT_UARTRXFRAMINGERRINT_MASK)
233 #define UARTINT_UARTRXFRAMINGERRINT_RESET 0
234 #define UARTINT_UARTTXREADYINT_MSB 1
235 #define UARTINT_UARTTXREADYINT_LSB 1
236 #define UARTINT_UARTTXREADYINT_MASK 0x00000002
237 #define UARTINT_UARTTXREADYINT_GET(x) (((x) & UARTINT_UARTTXREADYINT_MASK) >> UARTINT_UARTTXREADYINT_LSB)
238 #define UARTINT_UARTTXREADYINT_SET(x) (((0 | (x)) << UARTINT_UARTTXREADYINT_LSB) & UARTINT_UARTTXREADYINT_MASK)
239 #define UARTINT_UARTTXREADYINT_RESET 0
240 #define UARTINT_UARTRXVALIDINT_MSB 0
241 #define UARTINT_UARTRXVALIDINT_LSB 0
242 #define UARTINT_UARTRXVALIDINT_MASK 0x00000001
243 #define UARTINT_UARTRXVALIDINT_GET(x) (((x) & UARTINT_UARTRXVALIDINT_MASK) >> UARTINT_UARTRXVALIDINT_LSB)
244 #define UARTINT_UARTRXVALIDINT_SET(x) (((0 | (x)) << UARTINT_UARTRXVALIDINT_LSB) & UARTINT_UARTRXVALIDINT_MASK)
245 #define UARTINT_UARTRXVALIDINT_RESET 0
246 #define UARTINT_ADDRESS 0x000c
247 #define UARTINT_HW_MASK 0x000003ff
248 #define UARTINT_SW_MASK 0x000003ff
249 #define UARTINT_RSTMASK 0x000003ff
250 #define UARTINT_RESET 0x00000000
251
252 // 0x0010 (UARTINTEN)
253 #define UARTINTEN_UARTTXEMPTYINTEN_MSB 9
254 #define UARTINTEN_UARTTXEMPTYINTEN_LSB 9
255 #define UARTINTEN_UARTTXEMPTYINTEN_MASK 0x00000200
256 #define UARTINTEN_UARTTXEMPTYINTEN_GET(x) (((x) & UARTINTEN_UARTTXEMPTYINTEN_MASK) >> UARTINTEN_UARTTXEMPTYINTEN_LSB)
257 #define UARTINTEN_UARTTXEMPTYINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXEMPTYINTEN_LSB) & UARTINTEN_UARTTXEMPTYINTEN_MASK)
258 #define UARTINTEN_UARTTXEMPTYINTEN_RESET 0
259 #define UARTINTEN_UARTRXFULLINTEN_MSB 8
260 #define UARTINTEN_UARTRXFULLINTEN_LSB 8
261 #define UARTINTEN_UARTRXFULLINTEN_MASK 0x00000100
262 #define UARTINTEN_UARTRXFULLINTEN_GET(x) (((x) & UARTINTEN_UARTRXFULLINTEN_MASK) >> UARTINTEN_UARTRXFULLINTEN_LSB)
263 #define UARTINTEN_UARTRXFULLINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXFULLINTEN_LSB) & UARTINTEN_UARTRXFULLINTEN_MASK)
264 #define UARTINTEN_UARTRXFULLINTEN_RESET 0
265 #define UARTINTEN_UARTRXBREAKOFFINTEN_MSB 7
266 #define UARTINTEN_UARTRXBREAKOFFINTEN_LSB 7
267 #define UARTINTEN_UARTRXBREAKOFFINTEN_MASK 0x00000080
268 #define UARTINTEN_UARTRXBREAKOFFINTEN_GET(x) (((x) & UARTINTEN_UARTRXBREAKOFFINTEN_MASK) >> UARTINTEN_UARTRXBREAKOFFINTEN_LSB)
269 #define UARTINTEN_UARTRXBREAKOFFINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXBREAKOFFINTEN_LSB) & UARTINTEN_UARTRXBREAKOFFINTEN_MASK)
270 #define UARTINTEN_UARTRXBREAKOFFINTEN_RESET 0
271 #define UARTINTEN_UARTRXBREAKONINTEN_MSB 6
272 #define UARTINTEN_UARTRXBREAKONINTEN_LSB 6
273 #define UARTINTEN_UARTRXBREAKONINTEN_MASK 0x00000040
274 #define UARTINTEN_UARTRXBREAKONINTEN_GET(x) (((x) & UARTINTEN_UARTRXBREAKONINTEN_MASK) >> UARTINTEN_UARTRXBREAKONINTEN_LSB)
275 #define UARTINTEN_UARTRXBREAKONINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXBREAKONINTEN_LSB) & UARTINTEN_UARTRXBREAKONINTEN_MASK)
276 #define UARTINTEN_UARTRXBREAKONINTEN_RESET 0
277 #define UARTINTEN_UARTRXPARITYERRINTEN_MSB 5
278 #define UARTINTEN_UARTRXPARITYERRINTEN_LSB 5
279 #define UARTINTEN_UARTRXPARITYERRINTEN_MASK 0x00000020
280 #define UARTINTEN_UARTRXPARITYERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXPARITYERRINTEN_MASK) >> UARTINTEN_UARTRXPARITYERRINTEN_LSB)
281 #define UARTINTEN_UARTRXPARITYERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXPARITYERRINTEN_LSB) & UARTINTEN_UARTRXPARITYERRINTEN_MASK)
282 #define UARTINTEN_UARTRXPARITYERRINTEN_RESET 0
283 #define UARTINTEN_UARTTXOFLOWERRINTEN_MSB 4
284 #define UARTINTEN_UARTTXOFLOWERRINTEN_LSB 4
285 #define UARTINTEN_UARTTXOFLOWERRINTEN_MASK 0x00000010
286 #define UARTINTEN_UARTTXOFLOWERRINTEN_GET(x) (((x) & UARTINTEN_UARTTXOFLOWERRINTEN_MASK) >> UARTINTEN_UARTTXOFLOWERRINTEN_LSB)
287 #define UARTINTEN_UARTTXOFLOWERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXOFLOWERRINTEN_LSB) & UARTINTEN_UARTTXOFLOWERRINTEN_MASK)
288 #define UARTINTEN_UARTTXOFLOWERRINTEN_RESET 0
289 #define UARTINTEN_UARTRXOFLOWERRINTEN_MSB 3
290 #define UARTINTEN_UARTRXOFLOWERRINTEN_LSB 3
291 #define UARTINTEN_UARTRXOFLOWERRINTEN_MASK 0x00000008
292 #define UARTINTEN_UARTRXOFLOWERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXOFLOWERRINTEN_MASK) >> UARTINTEN_UARTRXOFLOWERRINTEN_LSB)
293 #define UARTINTEN_UARTRXOFLOWERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXOFLOWERRINTEN_LSB) & UARTINTEN_UARTRXOFLOWERRINTEN_MASK)
294 #define UARTINTEN_UARTRXOFLOWERRINTEN_RESET 0
295 #define UARTINTEN_UARTRXFRAMINGERRINTEN_MSB 2
296 #define UARTINTEN_UARTRXFRAMINGERRINTEN_LSB 2
297 #define UARTINTEN_UARTRXFRAMINGERRINTEN_MASK 0x00000004
298 #define UARTINTEN_UARTRXFRAMINGERRINTEN_GET(x) (((x) & UARTINTEN_UARTRXFRAMINGERRINTEN_MASK) >> UARTINTEN_UARTRXFRAMINGERRINTEN_LSB)
299 #define UARTINTEN_UARTRXFRAMINGERRINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXFRAMINGERRINTEN_LSB) & UARTINTEN_UARTRXFRAMINGERRINTEN_MASK)
300 #define UARTINTEN_UARTRXFRAMINGERRINTEN_RESET 0
301 #define UARTINTEN_UARTTXREADYINTEN_MSB 1
302 #define UARTINTEN_UARTTXREADYINTEN_LSB 1
303 #define UARTINTEN_UARTTXREADYINTEN_MASK 0x00000002
304 #define UARTINTEN_UARTTXREADYINTEN_GET(x) (((x) & UARTINTEN_UARTTXREADYINTEN_MASK) >> UARTINTEN_UARTTXREADYINTEN_LSB)
305 #define UARTINTEN_UARTTXREADYINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTTXREADYINTEN_LSB) & UARTINTEN_UARTTXREADYINTEN_MASK)
306 #define UARTINTEN_UARTTXREADYINTEN_RESET 0
307 #define UARTINTEN_UARTRXVALIDINTEN_MSB 0
308 #define UARTINTEN_UARTRXVALIDINTEN_LSB 0
309 #define UARTINTEN_UARTRXVALIDINTEN_MASK 0x00000001
310 #define UARTINTEN_UARTRXVALIDINTEN_GET(x) (((x) & UARTINTEN_UARTRXVALIDINTEN_MASK) >> UARTINTEN_UARTRXVALIDINTEN_LSB)
311 #define UARTINTEN_UARTRXVALIDINTEN_SET(x) (((0 | (x)) << UARTINTEN_UARTRXVALIDINTEN_LSB) & UARTINTEN_UARTRXVALIDINTEN_MASK)
312 #define UARTINTEN_UARTRXVALIDINTEN_RESET 0
313 #define UARTINTEN_ADDRESS 0x0010
314 #define UARTINTEN_HW_MASK 0x000003ff
315 #define UARTINTEN_SW_MASK 0x000003ff
316 #define UARTINTEN_RSTMASK 0x000003ff
317 #define UARTINTEN_RESET 0x00000000
318
319 /*
320 * uncomment below to enable WAR for EV81847.
321 */
322 //#define AR933X_EV81847_WAR
323
324 static struct uart_driver ar933x_uart_driver;
325
326 /*
327 * Debugging.
328 */
329 #if 0
330 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
331 #else
332 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
333 #endif
334
335 #if 0
336 #define DEBUG_INTR(fmt...) printk(fmt)
337 #else
338 #define DEBUG_INTR(fmt...) do { } while (0)
339 #endif
340
341 /*
342 * We default to IRQ0 for the "no irq" hack. Some
343 * machine types want others as well - they're free
344 * to redefine this in their header file.
345 */
346 #define is_real_interrupt(irq) ((irq) != 0)
347
348 #include <asm/serial.h>
349
350 struct ar933x_uart_port {
351 struct uart_port port;
352 struct timer_list timer; /* "no irq" timer */
353 unsigned char acr;
354 unsigned char ier;
355 unsigned char lcr;
356 unsigned char mcr;
357 };
358
359 static inline int ar933x_ev81847_war(void)
360 {
361 #if defined(AR933X_EV81847_WAR)
362 return 1;
363 #else
364 return 0;
365 #endif
366 }
367
368 static inline unsigned int ar933x_uart_read(struct ar933x_uart_port *up,
369 int offset)
370 {
371 return readl(up->port.membase + offset);
372 }
373
374 static inline void ar933x_uart_write(struct ar933x_uart_port *up,
375 int offset, unsigned int value)
376 {
377 writel(value, up->port.membase + offset);
378 }
379
380 static inline void ar933x_uart_rmw(struct ar933x_uart_port *up,
381 unsigned int offset,
382 unsigned int mask,
383 unsigned int val)
384 {
385 unsigned int t;
386
387 t = ar933x_uart_read(up, offset);
388 t &= ~mask;
389 t |= val;
390 ar933x_uart_write(up, offset, t);
391 }
392
393 static inline void ar933x_uart_rmw_set(struct ar933x_uart_port *up,
394 unsigned int offset,
395 unsigned int val)
396 {
397 ar933x_uart_rmw(up, offset, 0, val);
398 }
399
400 static inline void ar933x_uart_rmw_clear(struct ar933x_uart_port *up,
401 unsigned int offset,
402 unsigned int val)
403 {
404 ar933x_uart_rmw(up, offset, val, 0);
405 }
406
407 static inline void ar933x_uart_start_tx_interrupt(struct ar933x_uart_port *up)
408 {
409 ar933x_uart_rmw_set(up, UARTINTEN_ADDRESS,
410 UARTINTEN_UARTTXEMPTYINTEN_SET(1));
411 }
412
413 static inline void ar933x_uart_stop_tx_interrupt(struct ar933x_uart_port *up)
414 {
415 if (up->ier & UART_IER_THRI) {
416 up->ier &= ~UART_IER_THRI;
417
418 /* FIXME: why this uses RXVALIDINTEN? */
419 ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS,
420 UARTINTEN_UARTRXVALIDINTEN_SET(1));
421 }
422 }
423
424 static unsigned int ar933x_uart_tx_empty(struct uart_port *port)
425 {
426 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
427 unsigned long flags;
428 unsigned int rdata;
429
430 spin_lock_irqsave(&up->port.lock, flags);
431 rdata = ar933x_uart_read(up, UARTDATA_ADDRESS);
432 spin_unlock_irqrestore(&up->port.lock, flags);
433
434 return (rdata & UARTDATA_UARTTXCSR_MASK) ? 0 : TIOCSER_TEMT;
435 }
436
437 static unsigned int ar933x_uart_get_mctrl(struct uart_port *port)
438 {
439 return TIOCM_CAR;
440 }
441
442 static void ar933x_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
443 {
444 }
445
446 static void ar933x_uart_start_tx(struct uart_port *port)
447 {
448 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
449
450 ar933x_uart_start_tx_interrupt(up);
451 }
452
453 static void ar933x_uart_stop_tx(struct uart_port *port)
454 {
455 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
456
457 ar933x_uart_stop_tx_interrupt(up);
458 }
459
460 static void ar933x_uart_stop_rx(struct uart_port *port)
461 {
462 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
463
464 up->ier &= ~UART_IER_RLSI;
465 up->port.read_status_mask &= ~UART_LSR_DR;
466
467 ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS,
468 UARTINTEN_UARTRXVALIDINTEN_SET(1));
469 }
470
471 static void ar933x_uart_break_ctl(struct uart_port *port, int break_state)
472 {
473 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
474 unsigned long flags;
475 unsigned long rdata;
476
477 spin_lock_irqsave(&up->port.lock, flags);
478
479 if (break_state == -1)
480 up->lcr |= UART_LCR_SBC;
481 else
482 up->lcr &= ~UART_LCR_SBC;
483
484 rdata = ar933x_uart_read(up, UARTCS_ADDRESS);
485 if (up->lcr & UART_LCR_SBC)
486 rdata |= UARTCS_UARTTXBREAK_SET(1);
487 else
488 rdata &= ~UARTCS_UARTTXBREAK_SET(1);
489
490 ar933x_uart_write(up, UARTCS_ADDRESS, rdata);
491
492 spin_unlock_irqrestore(&up->port.lock, flags);
493 }
494
495 static void ar933x_uart_enable_ms(struct uart_port *port)
496 {
497 }
498
499 static inline unsigned int ar933x_uart_get_divisor(struct uart_port *port,
500 unsigned int baud)
501 {
502 return (port->uartclk / (16 * baud)) - 1;
503 }
504
505 static void ar933x_uart_set_termios(struct uart_port *port,
506 struct ktermios *termios,
507 struct ktermios *old)
508 {
509 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
510 unsigned char cval;
511 unsigned long flags;
512 unsigned int baud, quot;
513
514 switch (termios->c_cflag & CSIZE) {
515 case CS5:
516 cval = UART_LCR_WLEN5;
517 break;
518 case CS6:
519 cval = UART_LCR_WLEN6;
520 break;
521 case CS7:
522 cval = UART_LCR_WLEN7;
523 break;
524 default:
525 case CS8:
526 cval = UART_LCR_WLEN8;
527 break;
528 }
529
530 if (termios->c_cflag & CSTOPB)
531 cval |= UART_LCR_STOP;
532 if (termios->c_cflag & PARENB)
533 cval |= UART_LCR_PARITY;
534 if (!(termios->c_cflag & PARODD))
535 cval |= UART_LCR_EPAR;
536 #ifdef CMSPAR
537 if (termios->c_cflag & CMSPAR)
538 cval |= UART_LCR_SPAR;
539 #endif
540
541 /*
542 * Ask the core to calculate the divisor for us.
543 */
544 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
545 quot = ar933x_uart_get_divisor(port, baud);
546
547 #if 0
548 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
549 if (baud < 2400)
550 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
551 else
552 fcr = uart_config[up->port.type].fcr;
553 }
554
555 /*
556 * MCR-based auto flow control. When AFE is enabled, RTS will be
557 * deasserted when the receive FIFO contains more characters than
558 * the trigger, or the MCR RTS bit is cleared. In the case where
559 * the remote UART is not using CTS auto flow control, we must
560 * have sufficient FIFO entries for the latency of the remote
561 * UART to respond. IOW, at least 32 bytes of FIFO.
562 */
563 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
564 up->mcr &= ~UART_MCR_AFE;
565 if (termios->c_cflag & CRTSCTS)
566 up->mcr |= UART_MCR_AFE;
567 }
568 #endif
569
570 /*
571 * Ok, we're now changing the port state. Do it with
572 * interrupts disabled.
573 */
574 spin_lock_irqsave(&up->port.lock, flags);
575
576 /*
577 * Update the per-port timeout.
578 */
579 uart_update_timeout(port, termios->c_cflag, baud);
580
581 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
582 if (termios->c_iflag & INPCK)
583 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
584 if (termios->c_iflag & (BRKINT | PARMRK))
585 up->port.read_status_mask |= UART_LSR_BI;
586
587 /*
588 * Characteres to ignore
589 */
590 up->port.ignore_status_mask = 0;
591 if (termios->c_iflag & IGNPAR)
592 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
593 if (termios->c_iflag & IGNBRK) {
594 up->port.ignore_status_mask |= UART_LSR_BI;
595 /*
596 * If we're ignoring parity and break indicators,
597 * ignore overruns too (for real raw support).
598 */
599 if (termios->c_iflag & IGNPAR)
600 up->port.ignore_status_mask |= UART_LSR_OE;
601 }
602
603 /*
604 * ignore all characters if CREAD is not set
605 */
606 if ((termios->c_cflag & CREAD) == 0)
607 up->port.ignore_status_mask |= UART_LSR_DR;
608
609 /*
610 * CTS flow control flag and modem status interrupts
611 */
612 up->ier &= ~UART_IER_MSI;
613 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
614 up->ier |= UART_IER_MSI;
615
616 ar933x_uart_rmw_set(up, UARTCS_ADDRESS,
617 UARTCS_UARTHOSTINTEN_SET(1));
618
619 /* Save LCR */
620 up->lcr = cval;
621
622 ar933x_uart_set_mctrl(&up->port, up->port.mctrl);
623 spin_unlock_irqrestore(&up->port.lock, flags);
624 }
625
626 static void ar933x_uart_rx_chars(struct ar933x_uart_port *up, int *status)
627 {
628 struct tty_struct *tty = up->port.state->port.tty;
629 unsigned int lsr = *status;
630 unsigned char ch;
631 int max_count = 256;
632 char flag;
633
634 do {
635 ch = (unsigned char)UARTDATA_UARTTXRXDATA_GET(lsr);
636
637 flag = TTY_NORMAL;
638 up->port.icount.rx++;
639
640 lsr = UARTDATA_UARTRXCSR_SET(1);
641 ar933x_uart_write(up, UARTDATA_ADDRESS, lsr);
642
643 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
644 UART_LSR_FE | UART_LSR_OE))) {
645 /*
646 * For statistics only
647 */
648 if (lsr & UART_LSR_BI) {
649 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
650 up->port.icount.brk++;
651 /*
652 * We do the SysRQ and SAK checking
653 * here because otherwise the break
654 * may get masked by ignore_status_mask
655 * or read_status_mask.
656 */
657 if (uart_handle_break(&up->port))
658 goto ignore_char;
659 } else if (lsr & UART_LSR_PE)
660 up->port.icount.parity++;
661 else if (lsr & UART_LSR_FE)
662 up->port.icount.frame++;
663 if (lsr & UART_LSR_OE)
664 up->port.icount.overrun++;
665
666 /*
667 * Mask off conditions which should be ignored.
668 */
669 lsr &= up->port.read_status_mask;
670
671 if (lsr & UART_LSR_BI) {
672 DEBUG_INTR("handling break....");
673 flag = TTY_BREAK;
674 } else if (lsr & UART_LSR_PE)
675 flag = TTY_PARITY;
676 else if (lsr & UART_LSR_FE)
677 flag = TTY_FRAME;
678 }
679
680 if (uart_handle_sysrq_char(&up->port, ch))
681 goto ignore_char;
682
683 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
684
685 ignore_char:
686 lsr = ar933x_uart_read(up, UARTDATA_ADDRESS);
687 } while ((lsr & UARTDATA_UARTRXCSR_MASK) && (max_count-- > 0));
688
689 spin_unlock(&up->port.lock);
690 tty_flip_buffer_push(tty);
691 spin_lock(&up->port.lock);
692
693 *status = lsr;
694 }
695
696 static void ar933x_uart_tx_chars(struct ar933x_uart_port *up)
697 {
698 struct circ_buf *xmit = &up->port.state->xmit;
699 int count;
700 unsigned int rdata;
701
702 rdata = ar933x_uart_read(up, UARTDATA_ADDRESS);
703 if (UARTDATA_UARTTXCSR_GET(rdata) == 0) {
704 ar933x_uart_start_tx_interrupt(up);
705 return;
706 }
707
708 if (up->port.x_char) {
709 rdata = UARTDATA_UARTTXRXDATA_SET((unsigned int)(up->port.x_char));
710 rdata |= UARTDATA_UARTTXCSR_SET(1);
711 ar933x_uart_write(up, UARTDATA_ADDRESS, rdata);
712 up->port.icount.tx++;
713 up->port.x_char = 0;
714 ar933x_uart_start_tx_interrupt(up);
715 return;
716 }
717
718 if (uart_tx_stopped(&up->port)) {
719 ar933x_uart_stop_tx(&up->port);
720 return;
721 }
722
723 if (uart_circ_empty(xmit)) {
724 ar933x_uart_stop_tx_interrupt(up);
725 return;
726 }
727
728 count = up->port.fifosize / 4;
729 do {
730 rdata = ar933x_uart_read(up, UARTDATA_ADDRESS);
731 if (UARTDATA_UARTTXCSR_GET(rdata) == 0) {
732 ar933x_uart_start_tx_interrupt(up);
733 return;
734 }
735
736 rdata = UARTDATA_UARTTXRXDATA_SET((unsigned int)(xmit->buf[xmit->tail]));
737 rdata |= UARTDATA_UARTTXCSR_SET(1);
738 ar933x_uart_write(up, UARTDATA_ADDRESS, rdata);
739
740 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
741 up->port.icount.tx++;
742 if (uart_circ_empty(xmit))
743 break;
744 } while (--count > 0);
745
746 rdata = ar933x_uart_read(up, UARTDATA_ADDRESS);
747 if (UARTDATA_UARTTXCSR_GET(rdata) == 0) {
748 ar933x_uart_start_tx_interrupt(up);
749 return;
750 }
751
752 /* Re-enable TX Empty Interrupt to transmit pending chars */
753 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
754 uart_write_wakeup(&up->port);
755 ar933x_uart_start_tx_interrupt(up);
756 }
757
758 DEBUG_INTR("THRE...");
759
760 if (uart_circ_empty(xmit))
761 ar933x_uart_stop_tx_interrupt(up);
762 else
763 ar933x_uart_start_tx_interrupt(up);
764 }
765
766 /*! Hornet's interrupt status is not read clear, so that we have to...
767 * a. read out the interrupt status
768 * b. clear the interrupt mask to reset the interrupt status
769 * c. enable the interrupt to reactivate interrupt
770 *
771 * Disable and clear the interrupt status
772 */
773 static inline void ar933x_uart_clear_int(struct ar933x_uart_port *up)
774 {
775 #define BIT3 (0x1>>3)
776
777 /* 1. clear MISC interrupt mask */
778 //ar7240_reg_rmw_clear(AR7240_MISC_INT_MASK, BIT3);
779
780 /* 2. clear uartcs hostinten mask, bit13 */
781 ar933x_uart_rmw_clear(up, UARTCS_ADDRESS,
782 UARTCS_UARTHOSTINTEN_SET(1));
783
784 /* 3. clear rx uartint */
785 ar933x_uart_write(up, UARTINT_ADDRESS, UARTINT_UARTRXVALIDINT_SET(1));
786
787 /* 4. clear misc interrupt status */
788 ar7240_reg_rmw_clear(AR7240_MISC_INT_STATUS, BIT3);
789
790 /* 5. clear rx uartinten*/
791 ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS,
792 UARTINTEN_UARTRXVALIDINTEN_SET(1));
793
794 /* 6. enable rx int*/
795 ar933x_uart_rmw_set(up, UARTINTEN_ADDRESS,
796 UARTINTEN_UARTRXVALIDINTEN_SET(1));
797
798 /* 7. set uartcs hostinten mask */
799 ar933x_uart_rmw_set(up, UARTCS_ADDRESS,
800 UARTCS_UARTHOSTINTEN_SET(1));
801
802 /* 8. set misc int mask */
803 //ar7240_reg_wr(AR7240_MISC_INT_MASK, BIT3);
804 }
805
806 static inline void ar933x_uart_handle_port(struct ar933x_uart_port *up)
807 {
808 unsigned int status;
809 unsigned int int_status;
810 unsigned int en_status;
811 unsigned long flags;
812
813 status = ar933x_uart_read(up, UARTDATA_ADDRESS);
814 int_status = ar933x_uart_read(up, UARTINT_ADDRESS);
815 en_status = ar933x_uart_read(up, UARTINTEN_ADDRESS);
816
817 spin_lock_irqsave(&up->port.lock, flags);
818
819 if( (int_status & en_status) & UARTINT_UARTRXVALIDINT_MASK )
820 ar933x_uart_rx_chars(up, &status);
821
822 if (((int_status & en_status) & UARTINT_UARTTXEMPTYINT_MASK)) {
823 /* clear TX empty interrupts */
824 ar933x_uart_write(up, UARTINT_ADDRESS,
825 UARTINT_UARTTXEMPTYINT_SET(1));
826
827 /* disable TX empty interrupts */
828 ar933x_uart_rmw_clear(up, UARTINTEN_ADDRESS,
829 UARTINTEN_UARTTXEMPTYINTEN_SET(1));
830
831 if (!uart_circ_empty(&up->port.state->xmit))
832 ar933x_uart_tx_chars(up);
833 }
834
835 spin_unlock_irqrestore(&up->port.lock, flags);
836 }
837
838 static irqreturn_t ar933x_uart_interrupt(int irq, void *dev_id)
839 {
840 struct ar933x_uart_port *up;
841 unsigned int iir;
842
843 up = (struct ar933x_uart_port *) dev_id;
844
845 iir = ar933x_uart_read(up, UARTCS_ADDRESS);
846 if ((iir & UARTCS_UARTHOSTINT_MASK) == 0)
847 return IRQ_NONE;
848
849 DEBUG_INTR("ar933x_uart_interrupt(%d)...", irq);
850
851 spin_lock(&up->port.lock);
852 ar933x_uart_handle_port(up);
853 ar933x_uart_clear_int(up);
854 spin_unlock(&up->port.lock);
855
856 DEBUG_INTR("end.\n");
857
858 return IRQ_HANDLED;
859 }
860
861 static void ar933x_uart_timer(unsigned long data)
862 {
863 struct uart_port *port = (void *)data;
864 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
865 unsigned int iir;
866
867 if (ar933x_ev81847_war()) {
868 struct circ_buf *xmit = &up->port.state->xmit;
869 unsigned long flags;
870
871 if (!uart_circ_empty(xmit)) {
872 spin_lock_irqsave(&up->port.lock, flags);
873 ar933x_uart_tx_chars(up);
874 spin_unlock_irqrestore(&up->port.lock, flags);
875 }
876 } else {
877 iir = ar933x_uart_read(up, UARTCS_ADDRESS);
878 if (iir & UARTCS_UARTHOSTINT_MASK) {
879 spin_lock(&up->port.lock);
880 ar933x_uart_handle_port(up);
881 spin_unlock(&up->port.lock);
882 }
883 }
884
885 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
886 }
887
888 static int ar933x_uart_startup(struct uart_port *port)
889 {
890 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
891 unsigned long flags;
892 int ret;
893
894 ret = request_irq(up->port.irq, ar933x_uart_interrupt,
895 up->port.irqflags, dev_name(up->port.dev), up);
896 if (ret)
897 return ret;
898
899 up->mcr = 0;
900
901 /*
902 * Clear the interrupt registers.
903 */
904 ar933x_uart_read(up, UARTCS_ADDRESS);
905 ar933x_uart_read(up, UARTINT_ADDRESS);
906
907 if (!is_real_interrupt(up->port.irq) || ar933x_ev81847_war()) {
908 setup_timer(&up->timer, ar933x_uart_timer, (unsigned long)port);
909 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
910 return 0;
911 }
912
913 spin_lock_irqsave(&up->port.lock, flags);
914
915 /*
916 * Enable host interrupts
917 */
918 ar933x_uart_rmw_set(up, UARTCS_ADDRESS,
919 UARTCS_UARTHOSTINTEN_SET(1));
920
921 /*
922 * Enable RX interrupts
923 */
924 up->ier = UART_IER_RLSI | UART_IER_RDI;
925 ar933x_uart_write(up, UARTINTEN_ADDRESS,
926 UARTINTEN_UARTRXVALIDINTEN_SET(1));
927
928 /*
929 * And clear the interrupt registers again for luck.
930 */
931 ar933x_uart_read(up, UARTINT_ADDRESS);
932
933 spin_unlock_irqrestore(&up->port.lock, flags);
934
935 return 0;
936 }
937
938 static void ar933x_uart_shutdown(struct uart_port *port)
939 {
940 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
941 unsigned long flags;
942
943 /*
944 * Disable all interrupts from this port
945 */
946 up->ier = 0;
947 ar933x_uart_write(up, UARTINTEN_ADDRESS, 0);
948
949 spin_lock_irqsave(&up->port.lock, flags);
950 up->port.mctrl &= ~TIOCM_OUT2;
951 ar933x_uart_set_mctrl(&up->port, up->port.mctrl);
952 spin_unlock_irqrestore(&up->port.lock, flags);
953
954 /*
955 * Disable break condition
956 */
957 ar933x_uart_rmw_clear(up, UARTCS_ADDRESS,
958 UARTCS_UARTTXBREAK_SET(1));
959
960 if (!is_real_interrupt(up->port.irq) ||
961 ar933x_ev81847_war())
962 del_timer_sync(&up->timer);
963
964 free_irq(up->port.irq, up);
965 }
966
967 static const char *ar933x_uart_type(struct uart_port *port)
968 {
969 return (port->type == PORT_AR933X) ? "AR933X UART" : NULL;
970 }
971
972 static void ar933x_uart_release_port(struct uart_port *port)
973 {
974 /* Nothing to release ... */
975 }
976
977 static int ar933x_uart_request_port(struct uart_port *port)
978 {
979 /* UARTs always present */
980 return 0;
981 }
982
983 static void ar933x_uart_config_port(struct uart_port *port, int flags)
984 {
985 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
986
987 port->type = PORT_AR933X;
988
989 /* Clear mask, so no surprise interrupts. */
990 ar933x_uart_read(up, UARTCS_ADDRESS);
991 /* Clear interrupts status register */
992 ar933x_uart_read(up, UARTINT_ADDRESS);
993 }
994
995 static int ar933x_uart_verify_port(struct uart_port *port,
996 struct serial_struct *ser)
997 {
998 return -EINVAL;
999 }
1000
1001 static struct uart_ops ar933x_uart_ops = {
1002 .tx_empty = ar933x_uart_tx_empty,
1003 .set_mctrl = ar933x_uart_set_mctrl,
1004 .get_mctrl = ar933x_uart_get_mctrl,
1005 .stop_tx = ar933x_uart_stop_tx,
1006 .start_tx = ar933x_uart_start_tx,
1007 .stop_rx = ar933x_uart_stop_rx,
1008 .enable_ms = ar933x_uart_enable_ms,
1009 .break_ctl = ar933x_uart_break_ctl,
1010 .startup = ar933x_uart_startup,
1011 .shutdown = ar933x_uart_shutdown,
1012 .set_termios = ar933x_uart_set_termios,
1013 .type = ar933x_uart_type,
1014 .release_port = ar933x_uart_release_port,
1015 .request_port = ar933x_uart_request_port,
1016 .config_port = ar933x_uart_config_port,
1017 .verify_port = ar933x_uart_verify_port,
1018 };
1019
1020 #ifdef CONFIG_SERIAL_AR933X_CONSOLE
1021
1022 static struct ar933x_uart_port *ar933x_console_ports[CONFIG_SERIAL_AR933X_NR_UARTS];
1023
1024 static void ar933x_uart_wait_xmitr(struct ar933x_uart_port *up)
1025 {
1026 unsigned int status;
1027 unsigned int timeout = 60000;
1028
1029 /* Wait up to 60ms for the character(s) to be sent. */
1030 do {
1031 status = ar933x_uart_read(up, UARTDATA_ADDRESS);
1032 if (--timeout == 0)
1033 break;
1034 udelay(1);
1035 } while (UARTDATA_UARTTXCSR_GET(status) == 0);
1036 }
1037
1038 static void ar933x_uart_console_putchar(struct uart_port *port, int ch)
1039 {
1040 struct ar933x_uart_port *up = (struct ar933x_uart_port *) port;
1041 unsigned int rdata;
1042
1043 ar933x_uart_wait_xmitr(up);
1044
1045 rdata = UARTDATA_UARTTXRXDATA_SET(ch) |
1046 UARTDATA_UARTTXCSR_SET(1);
1047 ar933x_uart_write(up, UARTDATA_ADDRESS, rdata);
1048 }
1049
1050 static void ar933x_uart_console_write(struct console *co, const char *s,
1051 unsigned int count)
1052 {
1053 struct ar933x_uart_port *up = ar933x_console_ports[co->index];
1054 unsigned long flags;
1055 unsigned int ier;
1056 int locked = 1;
1057
1058 local_irq_save(flags);
1059
1060 if (up->port.sysrq) {
1061 locked = 0;
1062 } else if (oops_in_progress) {
1063 locked = spin_trylock(&up->port.lock);
1064 } else
1065 spin_lock(&up->port.lock);
1066
1067 /*
1068 * First save the IER then disable the interrupts
1069 */
1070 ier = ar933x_uart_read(up, UARTINTEN_ADDRESS);
1071 ar933x_uart_write(up, UARTINTEN_ADDRESS, 0);
1072
1073 uart_console_write(&up->port, s, count, ar933x_uart_console_putchar);
1074
1075 /*
1076 * Finally, wait for transmitter to become empty
1077 * and restore the IER
1078 */
1079 ar933x_uart_wait_xmitr(up);
1080
1081 ar933x_uart_write(up, UARTINTEN_ADDRESS, ier);
1082 ar933x_uart_write(up, UARTINT_ADDRESS, UARTINT_RSTMASK);
1083
1084 if (locked)
1085 spin_unlock(&up->port.lock);
1086
1087 local_irq_restore(flags);
1088 }
1089
1090 static int ar933x_uart_console_setup(struct console *co, char *options)
1091 {
1092 struct ar933x_uart_port *up;
1093 int baud = 115200;
1094 int bits = 8;
1095 int parity = 'n';
1096 int flow = 'n';
1097
1098 if (co->index < 0 || co->index >= CONFIG_SERIAL_AR933X_NR_UARTS)
1099 return -EINVAL;
1100
1101 up = ar933x_console_ports[co->index];
1102 if (!up)
1103 return -ENODEV;
1104
1105 if (options)
1106 uart_parse_options(options, &baud, &parity, &bits, &flow);
1107
1108 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1109 }
1110
1111 static struct console ar933x_uart_console = {
1112 .name = "ttyATH",
1113 .write = ar933x_uart_console_write,
1114 .device = uart_console_device,
1115 .setup = ar933x_uart_console_setup,
1116 .flags = CON_PRINTBUFFER,
1117 .index = -1,
1118 .data = &ar933x_uart_driver,
1119 };
1120
1121 static int __init ar933x_uart_console_init(void)
1122 {
1123 register_console(&ar933x_uart_console);
1124 return 0;
1125 }
1126 console_initcall(ar933x_uart_console_init);
1127
1128 static void ar933x_uart_add_console_port(struct ar933x_uart_port *up)
1129 {
1130 ar933x_console_ports[up->port.line] = up;
1131 }
1132
1133 #define AR933X_SERIAL_CONSOLE &ar933x_uart_console
1134
1135 #else
1136
1137 static inline void ar933x_uart_add_console_port(struct ar933x_uart_port *up) {}
1138
1139 #define AR933X_SERIAL_CONSOLE NULL
1140
1141 #endif /* CONFIG_SERIAL_AR933X_CONSOLE */
1142
1143 static struct uart_driver ar933x_uart_driver = {
1144 .owner = THIS_MODULE,
1145 .driver_name = DRIVER_NAME,
1146 .dev_name = "ttyATH",
1147 .nr = CONFIG_SERIAL_AR933X_NR_UARTS,
1148 .cons = AR933X_SERIAL_CONSOLE,
1149 };
1150
1151 static int __devinit ar933x_uart_probe(struct platform_device *pdev)
1152 {
1153 struct ar933x_uart_platform_data *pdata;
1154 struct ar933x_uart_port *up;
1155 struct uart_port *port;
1156 struct resource *mem_res;
1157 struct resource *irq_res;
1158 int id;
1159 int ret;
1160
1161 pdata = pdev->dev.platform_data;
1162 if (!pdata)
1163 return -EINVAL;
1164
1165 id = pdev->id;
1166 if (id == -1)
1167 id = 0;
1168
1169 if (id > CONFIG_SERIAL_AR933X_NR_UARTS)
1170 return -EINVAL;
1171
1172 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1173 if (!mem_res) {
1174 dev_err(&pdev->dev, "no MEM resource\n");
1175 return -EINVAL;
1176 }
1177
1178 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1179 if (!irq_res) {
1180 dev_err(&pdev->dev, "no IRQ resource\n");
1181 return -EINVAL;
1182 }
1183
1184 up = kzalloc(sizeof(struct ar933x_uart_port), GFP_KERNEL);
1185 if (!up)
1186 return -ENOMEM;
1187
1188 port = &up->port;
1189 port->mapbase = mem_res->start;
1190
1191 port->membase = ioremap(mem_res->start, AR933X_UART_REGS_SIZE);
1192 if (!port->membase) {
1193 ret = -ENOMEM;
1194 goto err_free_up;
1195 }
1196
1197 port->line = id;
1198 port->irq = irq_res->start;
1199 port->dev = &pdev->dev;
1200 port->type = PORT_AR933X;
1201 port->iotype = UPIO_MEM32;
1202 port->uartclk = pdata->uartclk;
1203
1204 port->regshift = 2;
1205 port->fifosize = AR933X_UART_FIFO_SIZE;
1206 port->ops = &ar933x_uart_ops;
1207
1208 ar933x_uart_add_console_port(up);
1209
1210 ret = uart_add_one_port(&ar933x_uart_driver, &up->port);
1211 if (ret)
1212 goto err_unmap;
1213
1214 platform_set_drvdata(pdev, up);
1215 return 0;
1216
1217 err_unmap:
1218 iounmap(up->port.membase);
1219 err_free_up:
1220 kfree(up);
1221 return ret;
1222 }
1223
1224 static int __devexit ar933x_uart_remove(struct platform_device *pdev)
1225 {
1226 struct ar933x_uart_port *up;
1227
1228 up = platform_get_drvdata(pdev);
1229 platform_set_drvdata(pdev, NULL);
1230
1231 if (up) {
1232 uart_remove_one_port(&ar933x_uart_driver, &up->port);
1233 iounmap(up->port.membase);
1234 kfree(up);
1235 }
1236
1237 return 0;
1238 }
1239
1240 static struct platform_driver ar933x_uart_platform_driver = {
1241 .probe = ar933x_uart_probe,
1242 .remove = __devexit_p(ar933x_uart_remove),
1243 .driver = {
1244 .name = DRIVER_NAME,
1245 .owner = THIS_MODULE,
1246 },
1247 };
1248
1249 static int __init ar933x_uart_init(void)
1250 {
1251 int ret;
1252
1253 ar933x_uart_driver.nr = CONFIG_SERIAL_AR933X_NR_UARTS;
1254 ret = uart_register_driver(&ar933x_uart_driver);
1255 if (ret)
1256 goto err_out;
1257
1258 ret = platform_driver_register(&ar933x_uart_platform_driver);
1259 if (ret)
1260 goto err_unregister_uart_driver;
1261
1262 return 0;
1263
1264 err_unregister_uart_driver:
1265 uart_unregister_driver(&ar933x_uart_driver);
1266 err_out:
1267 return ret;
1268 }
1269
1270 static void __exit ar933x_uart_exit(void)
1271 {
1272 platform_driver_unregister(&ar933x_uart_platform_driver);
1273 uart_unregister_driver(&ar933x_uart_driver);
1274 }
1275
1276 module_init(ar933x_uart_init);
1277 module_exit(ar933x_uart_exit);
1278
1279 MODULE_DESCRIPTION("Atheros AR933X UART driver");
1280 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1281 MODULE_LICENSE("GPL v2");
1282 MODULE_ALIAS("platform:" DRV_NAME);
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