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[tools] fix segfault when using the maxlen argument (#4359)
[openwrt.git] / package / mac80211 / patches / 302-rt2x00-Implement-support-for-rt2800pci.patch
1 From c5d3ab153ef4b68c9c6fab32f6f292c4394b72d3 Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Thu, 21 May 2009 19:21:31 +0200
4 Subject: [PATCH 2/2] rt2x00: Implement support for rt2800pci
5
6 Add support for the rt2800pci chipset.
7
8 Includes various patches from Mattias, Mark, Felix and Xose.
9
10 Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
11 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
12 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
13 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
14 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
15 ---
16 drivers/net/wireless/rt2x00/Kconfig | 26 +
17 drivers/net/wireless/rt2x00/Makefile | 1 +
18 drivers/net/wireless/rt2x00/rt2800pci.c | 3241 +++++++++++++++++++++++++++++++
19 drivers/net/wireless/rt2x00/rt2800pci.h | 1929 ++++++++++++++++++
20 drivers/net/wireless/rt2x00/rt2x00.h | 6 +
21 5 files changed, 5203 insertions(+), 0 deletions(-)
22 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
23 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
24
25 --- a/drivers/net/wireless/rt2x00/Makefile
26 +++ b/drivers/net/wireless/rt2x00/Makefile
27 @@ -17,6 +17,7 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
28 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
29 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
30 obj-$(CONFIG_RT61PCI) += rt61pci.o
31 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
32 obj-$(CONFIG_RT2500USB) += rt2500usb.o
33 obj-$(CONFIG_RT73USB) += rt73usb.o
34 obj-$(CONFIG_RT2800USB) += rt2800usb.o
35 --- /dev/null
36 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
37 @@ -0,0 +1,3241 @@
38 +/*
39 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
40 + <http://rt2x00.serialmonkey.com>
41 +
42 + This program is free software; you can redistribute it and/or modify
43 + it under the terms of the GNU General Public License as published by
44 + the Free Software Foundation; either version 2 of the License, or
45 + (at your option) any later version.
46 +
47 + This program is distributed in the hope that it will be useful,
48 + but WITHOUT ANY WARRANTY; without even the implied warranty of
49 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50 + GNU General Public License for more details.
51 +
52 + You should have received a copy of the GNU General Public License
53 + along with this program; if not, write to the
54 + Free Software Foundation, Inc.,
55 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
56 + */
57 +
58 +/*
59 + Module: rt2800pci
60 + Abstract: rt2800pci device specific routines.
61 + Supported chipsets: RT2800E & RT2800ED.
62 + */
63 +
64 +#include <linux/crc-ccitt.h>
65 +#include <linux/delay.h>
66 +#include <linux/etherdevice.h>
67 +#include <linux/init.h>
68 +#include <linux/kernel.h>
69 +#include <linux/module.h>
70 +#include <linux/pci.h>
71 +#include <linux/platform_device.h>
72 +#include <linux/eeprom_93cx6.h>
73 +
74 +#include "rt2x00.h"
75 +#include "rt2x00pci.h"
76 +#include "rt2x00soc.h"
77 +#include "rt2800pci.h"
78 +
79 +#ifdef CONFIG_RT2800PCI_PCI_MODULE
80 +#define CONFIG_RT2800PCI_PCI
81 +#endif
82 +
83 +#ifdef CONFIG_RT2800PCI_WISOC_MODULE
84 +#define CONFIG_RT2800PCI_WISOC
85 +#endif
86 +
87 +/*
88 + * Allow hardware encryption to be disabled.
89 + */
90 +static int modparam_nohwcrypt = 0;
91 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
92 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
93 +
94 +/*
95 + * Register access.
96 + * BBP and RF register require indirect register access,
97 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
98 + * These indirect registers work with busy bits,
99 + * and we will try maximal REGISTER_BUSY_COUNT times to access
100 + * the register while taking a REGISTER_BUSY_DELAY us delay
101 + * between each attampt. When the busy bit is still set at that time,
102 + * the access attempt is considered to have failed,
103 + * and we will print an error.
104 + */
105 +#define WAIT_FOR_BBP(__dev, __reg) \
106 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
107 +#define WAIT_FOR_RFCSR(__dev, __reg) \
108 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
109 +#define WAIT_FOR_RF(__dev, __reg) \
110 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
111 +#define WAIT_FOR_MCU(__dev, __reg) \
112 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
113 + H2M_MAILBOX_CSR_OWNER, (__reg))
114 +
115 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
116 + const unsigned int word, const u8 value)
117 +{
118 + u32 reg;
119 +
120 + mutex_lock(&rt2x00dev->csr_mutex);
121 +
122 + /*
123 + * Wait until the BBP becomes available, afterwards we
124 + * can safely write the new data into the register.
125 + */
126 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
127 + reg = 0;
128 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
129 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
130 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
131 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
132 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
133 +
134 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
135 + }
136 +
137 + mutex_unlock(&rt2x00dev->csr_mutex);
138 +}
139 +
140 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
141 + const unsigned int word, u8 *value)
142 +{
143 + u32 reg;
144 +
145 + mutex_lock(&rt2x00dev->csr_mutex);
146 +
147 + /*
148 + * Wait until the BBP becomes available, afterwards we
149 + * can safely write the read request into the register.
150 + * After the data has been written, we wait until hardware
151 + * returns the correct value, if at any time the register
152 + * doesn't become available in time, reg will be 0xffffffff
153 + * which means we return 0xff to the caller.
154 + */
155 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
156 + reg = 0;
157 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
158 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
159 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
160 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
161 +
162 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
163 +
164 + WAIT_FOR_BBP(rt2x00dev, &reg);
165 + }
166 +
167 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
168 +
169 + mutex_unlock(&rt2x00dev->csr_mutex);
170 +}
171 +
172 +static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
173 + const unsigned int word, const u8 value)
174 +{
175 + u32 reg;
176 +
177 + mutex_lock(&rt2x00dev->csr_mutex);
178 +
179 + /*
180 + * Wait until the RFCSR becomes available, afterwards we
181 + * can safely write the new data into the register.
182 + */
183 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
184 + reg = 0;
185 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
186 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
187 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
188 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
189 +
190 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
191 + }
192 +
193 + mutex_unlock(&rt2x00dev->csr_mutex);
194 +}
195 +
196 +static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
197 + const unsigned int word, u8 *value)
198 +{
199 + u32 reg;
200 +
201 + mutex_lock(&rt2x00dev->csr_mutex);
202 +
203 + /*
204 + * Wait until the RFCSR becomes available, afterwards we
205 + * can safely write the read request into the register.
206 + * After the data has been written, we wait until hardware
207 + * returns the correct value, if at any time the register
208 + * doesn't become available in time, reg will be 0xffffffff
209 + * which means we return 0xff to the caller.
210 + */
211 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
212 + reg = 0;
213 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
214 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
215 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
216 +
217 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG, reg);
218 +
219 + WAIT_FOR_RFCSR(rt2x00dev, &reg);
220 + }
221 +
222 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
223 +
224 + mutex_unlock(&rt2x00dev->csr_mutex);
225 +}
226 +
227 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
228 + const unsigned int word, const u32 value)
229 +{
230 + u32 reg;
231 +
232 + mutex_lock(&rt2x00dev->csr_mutex);
233 +
234 + /*
235 + * Wait until the RF becomes available, afterwards we
236 + * can safely write the new data into the register.
237 + */
238 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
239 + reg = 0;
240 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
241 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
242 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
243 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
244 +
245 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
246 + rt2x00_rf_write(rt2x00dev, word, value);
247 + }
248 +
249 + mutex_unlock(&rt2x00dev->csr_mutex);
250 +}
251 +
252 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
253 + const u8 command, const u8 token,
254 + const u8 arg0, const u8 arg1)
255 +{
256 + u32 reg;
257 +
258 + /*
259 + * RT2880 and RT3052 don't support MCU requests.
260 + */
261 + if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
262 + rt2x00_rt(&rt2x00dev->chip, RT3052))
263 + return;
264 +
265 + mutex_lock(&rt2x00dev->csr_mutex);
266 +
267 + /*
268 + * Wait until the MCU becomes available, afterwards we
269 + * can safely write the new data into the register.
270 + */
271 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
272 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
273 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
274 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
275 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
276 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
277 +
278 + reg = 0;
279 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
280 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
281 + }
282 +
283 + mutex_unlock(&rt2x00dev->csr_mutex);
284 +}
285 +
286 +static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
287 +{
288 + unsigned int i;
289 + u32 reg;
290 +
291 + for (i = 0; i < 200; i++) {
292 + rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
293 +
294 + if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
295 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
296 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
297 + (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
298 + break;
299 +
300 + udelay(REGISTER_BUSY_DELAY);
301 + }
302 +
303 + if (i == 200)
304 + ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
305 +
306 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
307 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
308 +}
309 +
310 +#ifdef CONFIG_RT2800PCI_WISOC
311 +static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
312 +{
313 + u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
314 +
315 + memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
316 +}
317 +#else
318 +static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
319 +{
320 +}
321 +#endif /* CONFIG_RT2800PCI_WISOC */
322 +
323 +#ifdef CONFIG_RT2800PCI_PCI
324 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
325 +{
326 + struct rt2x00_dev *rt2x00dev = eeprom->data;
327 + u32 reg;
328 +
329 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
330 +
331 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
332 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
333 + eeprom->reg_data_clock =
334 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
335 + eeprom->reg_chip_select =
336 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
337 +}
338 +
339 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
340 +{
341 + struct rt2x00_dev *rt2x00dev = eeprom->data;
342 + u32 reg = 0;
343 +
344 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
345 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
346 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
347 + !!eeprom->reg_data_clock);
348 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
349 + !!eeprom->reg_chip_select);
350 +
351 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
352 +}
353 +
354 +static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
355 +{
356 + struct eeprom_93cx6 eeprom;
357 + u32 reg;
358 +
359 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
360 +
361 + eeprom.data = rt2x00dev;
362 + eeprom.register_read = rt2800pci_eepromregister_read;
363 + eeprom.register_write = rt2800pci_eepromregister_write;
364 + eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
365 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
366 + eeprom.reg_data_in = 0;
367 + eeprom.reg_data_out = 0;
368 + eeprom.reg_data_clock = 0;
369 + eeprom.reg_chip_select = 0;
370 +
371 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
372 + EEPROM_SIZE / sizeof(u16));
373 +}
374 +#else
375 +static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
376 +{
377 +}
378 +#endif /* CONFIG_RT2800PCI_PCI */
379 +
380 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
381 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
382 + .owner = THIS_MODULE,
383 + .csr = {
384 + .read = rt2x00pci_register_read,
385 + .write = rt2x00pci_register_write,
386 + .flags = RT2X00DEBUGFS_OFFSET,
387 + .word_base = CSR_REG_BASE,
388 + .word_size = sizeof(u32),
389 + .word_count = CSR_REG_SIZE / sizeof(u32),
390 + },
391 + .eeprom = {
392 + .read = rt2x00_eeprom_read,
393 + .write = rt2x00_eeprom_write,
394 + .word_base = EEPROM_BASE,
395 + .word_size = sizeof(u16),
396 + .word_count = EEPROM_SIZE / sizeof(u16),
397 + },
398 + .bbp = {
399 + .read = rt2800pci_bbp_read,
400 + .write = rt2800pci_bbp_write,
401 + .word_base = BBP_BASE,
402 + .word_size = sizeof(u8),
403 + .word_count = BBP_SIZE / sizeof(u8),
404 + },
405 + .rf = {
406 + .read = rt2x00_rf_read,
407 + .write = rt2800pci_rf_write,
408 + .word_base = RF_BASE,
409 + .word_size = sizeof(u32),
410 + .word_count = RF_SIZE / sizeof(u32),
411 + },
412 +};
413 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
414 +
415 +#ifdef CONFIG_RT2X00_LIB_RFKILL
416 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
417 +{
418 + u32 reg;
419 +
420 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
421 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
422 +}
423 +#else
424 +#define rt2800pci_rfkill_poll NULL
425 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
426 +
427 +#ifdef CONFIG_RT2X00_LIB_LEDS
428 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
429 + enum led_brightness brightness)
430 +{
431 + struct rt2x00_led *led =
432 + container_of(led_cdev, struct rt2x00_led, led_dev);
433 + unsigned int enabled = brightness != LED_OFF;
434 + unsigned int bg_mode =
435 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
436 + unsigned int polarity =
437 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
438 + EEPROM_FREQ_LED_POLARITY);
439 + unsigned int ledmode =
440 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
441 + EEPROM_FREQ_LED_MODE);
442 +
443 + if (led->type == LED_TYPE_RADIO) {
444 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
445 + enabled ? 0x20 : 0);
446 + } else if (led->type == LED_TYPE_ASSOC) {
447 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
448 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
449 + } else if (led->type == LED_TYPE_QUALITY) {
450 + /*
451 + * The brightness is divided into 6 levels (0 - 5),
452 + * The specs tell us the following levels:
453 + * 0, 1 ,3, 7, 15, 31
454 + * to determine the level in a simple way we can simply
455 + * work with bitshifting:
456 + * (1 << level) - 1
457 + */
458 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
459 + (1 << brightness / (LED_FULL / 6)) - 1,
460 + polarity);
461 + }
462 +}
463 +
464 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
465 + unsigned long *delay_on,
466 + unsigned long *delay_off)
467 +{
468 + struct rt2x00_led *led =
469 + container_of(led_cdev, struct rt2x00_led, led_dev);
470 + u32 reg;
471 +
472 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
473 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
474 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
475 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
476 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
477 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
478 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
479 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
480 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
481 +
482 + return 0;
483 +}
484 +
485 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
486 + struct rt2x00_led *led,
487 + enum led_type type)
488 +{
489 + led->rt2x00dev = rt2x00dev;
490 + led->type = type;
491 + led->led_dev.brightness_set = rt2800pci_brightness_set;
492 + led->led_dev.blink_set = rt2800pci_blink_set;
493 + led->flags = LED_INITIALIZED;
494 +}
495 +#endif /* CONFIG_RT2X00_LIB_LEDS */
496 +
497 +/*
498 + * Configuration handlers.
499 + */
500 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
501 + struct rt2x00lib_crypto *crypto,
502 + struct ieee80211_key_conf *key)
503 +{
504 + struct mac_wcid_entry wcid_entry;
505 + struct mac_iveiv_entry iveiv_entry;
506 + u32 offset;
507 + u32 reg;
508 +
509 + offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
510 +
511 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
512 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
513 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
514 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
515 + (crypto->cmd == SET_KEY) * crypto->cipher);
516 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
517 + (crypto->cmd == SET_KEY) * crypto->bssidx);
518 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
519 + rt2x00pci_register_write(rt2x00dev, offset, reg);
520 +
521 + offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
522 +
523 + memset(&iveiv_entry, 0, sizeof(iveiv_entry));
524 + if ((crypto->cipher == CIPHER_TKIP) ||
525 + (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
526 + (crypto->cipher == CIPHER_AES))
527 + iveiv_entry.iv[3] |= 0x20;
528 + iveiv_entry.iv[3] |= key->keyidx << 6;
529 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
530 + &iveiv_entry, sizeof(iveiv_entry));
531 +
532 + offset = MAC_WCID_ENTRY(key->hw_key_idx);
533 +
534 + memset(&wcid_entry, 0, sizeof(wcid_entry));
535 + if (crypto->cmd == SET_KEY)
536 + memcpy(&wcid_entry, crypto->address, ETH_ALEN);
537 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
538 + &wcid_entry, sizeof(wcid_entry));
539 +}
540 +
541 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
542 + struct rt2x00lib_crypto *crypto,
543 + struct ieee80211_key_conf *key)
544 +{
545 + struct hw_key_entry key_entry;
546 + struct rt2x00_field32 field;
547 + u32 offset;
548 + u32 reg;
549 +
550 + if (crypto->cmd == SET_KEY) {
551 + key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
552 +
553 + memcpy(key_entry.key, crypto->key,
554 + sizeof(key_entry.key));
555 + memcpy(key_entry.tx_mic, crypto->tx_mic,
556 + sizeof(key_entry.tx_mic));
557 + memcpy(key_entry.rx_mic, crypto->rx_mic,
558 + sizeof(key_entry.rx_mic));
559 +
560 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
561 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
562 + &key_entry, sizeof(key_entry));
563 + }
564 +
565 + /*
566 + * The cipher types are stored over multiple registers
567 + * starting with SHARED_KEY_MODE_BASE each word will have
568 + * 32 bits and contains the cipher types for 2 bssidx each.
569 + * Using the correct defines correctly will cause overhead,
570 + * so just calculate the correct offset.
571 + */
572 + field.bit_offset = 4 * (key->hw_key_idx % 8);
573 + field.bit_mask = 0x7 << field.bit_offset;
574 +
575 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
576 +
577 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
578 + rt2x00_set_field32(&reg, field,
579 + (crypto->cmd == SET_KEY) * crypto->cipher);
580 + rt2x00pci_register_write(rt2x00dev, offset, reg);
581 +
582 + /*
583 + * Update WCID information
584 + */
585 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
586 +
587 + return 0;
588 +}
589 +
590 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
591 + struct rt2x00lib_crypto *crypto,
592 + struct ieee80211_key_conf *key)
593 +{
594 + struct hw_key_entry key_entry;
595 + u32 offset;
596 +
597 + if (crypto->cmd == SET_KEY) {
598 + /*
599 + * 1 pairwise key is possible per AID, this means that the AID
600 + * equals our hw_key_idx. Make sure the WCID starts _after_ the
601 + * last possible shared key entry.
602 + */
603 + if (crypto->aid > (256 - 32))
604 + return -ENOSPC;
605 +
606 + key->hw_key_idx = 32 + crypto->aid;
607 +
608 +
609 + memcpy(key_entry.key, crypto->key,
610 + sizeof(key_entry.key));
611 + memcpy(key_entry.tx_mic, crypto->tx_mic,
612 + sizeof(key_entry.tx_mic));
613 + memcpy(key_entry.rx_mic, crypto->rx_mic,
614 + sizeof(key_entry.rx_mic));
615 +
616 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
617 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
618 + &key_entry, sizeof(key_entry));
619 + }
620 +
621 + /*
622 + * Update WCID information
623 + */
624 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
625 +
626 + return 0;
627 +}
628 +
629 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
630 + const unsigned int filter_flags)
631 +{
632 + u32 reg;
633 +
634 + /*
635 + * Start configuration steps.
636 + * Note that the version error will always be dropped
637 + * and broadcast frames will always be accepted since
638 + * there is no filter for it at this time.
639 + */
640 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
641 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
642 + !(filter_flags & FIF_FCSFAIL));
643 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
644 + !(filter_flags & FIF_PLCPFAIL));
645 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
646 + !(filter_flags & FIF_PROMISC_IN_BSS));
647 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
648 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
649 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
650 + !(filter_flags & FIF_ALLMULTI));
651 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
652 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
653 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
654 + !(filter_flags & FIF_CONTROL));
655 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
656 + !(filter_flags & FIF_CONTROL));
657 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
658 + !(filter_flags & FIF_CONTROL));
659 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
660 + !(filter_flags & FIF_CONTROL));
661 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
662 + !(filter_flags & FIF_CONTROL));
663 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
664 + !(filter_flags & FIF_CONTROL));
665 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
666 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
667 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
668 + !(filter_flags & FIF_CONTROL));
669 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
670 +}
671 +
672 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
673 + struct rt2x00_intf *intf,
674 + struct rt2x00intf_conf *conf,
675 + const unsigned int flags)
676 +{
677 + unsigned int beacon_base;
678 + u32 reg;
679 +
680 + if (flags & CONFIG_UPDATE_TYPE) {
681 + /*
682 + * Clear current synchronisation setup.
683 + * For the Beacon base registers we only need to clear
684 + * the first byte since that byte contains the VALID and OWNER
685 + * bits which (when set to 0) will invalidate the entire beacon.
686 + */
687 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
688 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
689 +
690 + /*
691 + * Enable synchronisation.
692 + */
693 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
694 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
695 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
696 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
697 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
698 + }
699 +
700 + if (flags & CONFIG_UPDATE_MAC) {
701 + reg = le32_to_cpu(conf->mac[1]);
702 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
703 + conf->mac[1] = cpu_to_le32(reg);
704 +
705 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
706 + conf->mac, sizeof(conf->mac));
707 + }
708 +
709 + if (flags & CONFIG_UPDATE_BSSID) {
710 + reg = le32_to_cpu(conf->bssid[1]);
711 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
712 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
713 + conf->bssid[1] = cpu_to_le32(reg);
714 +
715 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
716 + conf->bssid, sizeof(conf->bssid));
717 + }
718 +}
719 +
720 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
721 + struct rt2x00lib_erp *erp)
722 +{
723 + u32 reg;
724 +
725 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
726 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
727 + DIV_ROUND_UP(erp->ack_timeout, erp->slot_time));
728 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
729 +
730 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
731 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
732 + !!erp->short_preamble);
733 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
734 + !!erp->short_preamble);
735 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
736 +
737 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
738 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
739 + erp->cts_protection ? 2 : 0);
740 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
741 +
742 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
743 + erp->basic_rates);
744 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
745 +
746 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
747 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
748 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
749 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
750 +
751 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
752 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
753 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
754 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
755 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
756 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
757 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
758 +
759 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
760 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
761 + erp->beacon_int * 16);
762 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
763 +}
764 +
765 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
766 + struct antenna_setup *ant)
767 +{
768 + u8 r1;
769 + u8 r3;
770 +
771 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
772 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
773 +
774 + /*
775 + * Configure the TX antenna.
776 + */
777 + switch ((int)ant->tx) {
778 + case 1:
779 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
780 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
781 + break;
782 + case 2:
783 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
784 + break;
785 + case 3:
786 + /* Do nothing */
787 + break;
788 + }
789 +
790 + /*
791 + * Configure the RX antenna.
792 + */
793 + switch ((int)ant->rx) {
794 + case 1:
795 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
796 + break;
797 + case 2:
798 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
799 + break;
800 + case 3:
801 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
802 + break;
803 + }
804 +
805 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
806 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
807 +}
808 +
809 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
810 + struct rt2x00lib_conf *libconf)
811 +{
812 + u16 eeprom;
813 + short lna_gain;
814 +
815 + if (libconf->rf.channel <= 14) {
816 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
817 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
818 + } else if (libconf->rf.channel <= 64) {
819 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
820 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
821 + } else if (libconf->rf.channel <= 128) {
822 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
823 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
824 + } else {
825 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
826 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
827 + }
828 +
829 + rt2x00dev->lna_gain = lna_gain;
830 +}
831 +
832 +static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
833 + struct ieee80211_conf *conf,
834 + struct rf_channel *rf,
835 + struct channel_info *info)
836 +{
837 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
838 +
839 + if (rt2x00dev->default_ant.tx == 1)
840 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
841 +
842 + if (rt2x00dev->default_ant.rx == 1) {
843 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
844 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
845 + } else if (rt2x00dev->default_ant.rx == 2)
846 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
847 +
848 + if (rf->channel > 14) {
849 + /*
850 + * When TX power is below 0, we should increase it by 7 to
851 + * make it a positive value (Minumum value is -7).
852 + * However this means that values between 0 and 7 have
853 + * double meaning, and we should set a 7DBm boost flag.
854 + */
855 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
856 + (info->tx_power1 >= 0));
857 +
858 + if (info->tx_power1 < 0)
859 + info->tx_power1 += 7;
860 +
861 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
862 + TXPOWER_A_TO_DEV(info->tx_power1));
863 +
864 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
865 + (info->tx_power2 >= 0));
866 +
867 + if (info->tx_power2 < 0)
868 + info->tx_power2 += 7;
869 +
870 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
871 + TXPOWER_A_TO_DEV(info->tx_power2));
872 + } else {
873 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
874 + TXPOWER_G_TO_DEV(info->tx_power1));
875 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
876 + TXPOWER_G_TO_DEV(info->tx_power2));
877 + }
878 +
879 + rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
880 +
881 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
882 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
883 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
884 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
885 +
886 + udelay(200);
887 +
888 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
889 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
890 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
891 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
892 +
893 + udelay(200);
894 +
895 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
896 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
897 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
898 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
899 +}
900 +
901 +static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
902 + struct ieee80211_conf *conf,
903 + struct rf_channel *rf,
904 + struct channel_info *info)
905 +{
906 + u8 rfcsr;
907 +
908 + rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf1);
909 + rt2800pci_rfcsr_write(rt2x00dev, 2, rf->rf3);
910 +
911 + rt2800pci_rfcsr_read(rt2x00dev, 6, &rfcsr);
912 + rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
913 + rt2800pci_rfcsr_write(rt2x00dev, 6, rfcsr);
914 +
915 + rt2800pci_rfcsr_read(rt2x00dev, 12, &rfcsr);
916 + rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
917 + TXPOWER_G_TO_DEV(info->tx_power1));
918 + rt2800pci_rfcsr_write(rt2x00dev, 12, rfcsr);
919 +
920 + rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
921 + rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
922 + rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
923 +
924 + rt2800pci_rfcsr_write(rt2x00dev, 24,
925 + rt2x00dev->calibration[conf_is_ht40(conf)]);
926 +
927 + rt2800pci_rfcsr_read(rt2x00dev, 23, &rfcsr);
928 + rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
929 + rt2800pci_rfcsr_write(rt2x00dev, 23, rfcsr);
930 +}
931 +
932 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
933 + struct ieee80211_conf *conf,
934 + struct rf_channel *rf,
935 + struct channel_info *info)
936 +{
937 + u32 reg;
938 + unsigned int tx_pin;
939 + u8 bbp;
940 +
941 + if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
942 + rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
943 + else
944 + rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
945 +
946 + /*
947 + * Change BBP settings
948 + */
949 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
950 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
951 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
952 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
953 +
954 + if (rf->channel <= 14) {
955 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
956 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
957 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
958 + } else {
959 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
960 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
961 + }
962 + } else {
963 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
964 +
965 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
966 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
967 + else
968 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
969 + }
970 +
971 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
972 + rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
973 + rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
974 + rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
975 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
976 +
977 + tx_pin = 0;
978 +
979 + /* Turn on unused PA or LNA when not using 1T or 1R */
980 + if (rt2x00dev->default_ant.tx != 1) {
981 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
982 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
983 + }
984 +
985 + /* Turn on unused PA or LNA when not using 1T or 1R */
986 + if (rt2x00dev->default_ant.rx != 1) {
987 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
988 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
989 + }
990 +
991 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
992 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
993 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
994 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
995 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
996 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
997 +
998 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
999 +
1000 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1001 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1002 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1003 +
1004 + rt2800pci_bbp_read(rt2x00dev, 3, &bbp);
1005 + rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1006 + rt2800pci_bbp_write(rt2x00dev, 3, bbp);
1007 +
1008 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1009 + if (conf_is_ht40(conf)) {
1010 + rt2800pci_bbp_write(rt2x00dev, 69, 0x1a);
1011 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1012 + rt2800pci_bbp_write(rt2x00dev, 73, 0x16);
1013 + } else {
1014 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1015 + rt2800pci_bbp_write(rt2x00dev, 70, 0x08);
1016 + rt2800pci_bbp_write(rt2x00dev, 73, 0x11);
1017 + }
1018 + }
1019 +
1020 + msleep(1);
1021 +}
1022 +
1023 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1024 + const int txpower)
1025 +{
1026 + u32 reg;
1027 + u32 value = TXPOWER_G_TO_DEV(txpower);
1028 + u8 r1;
1029 +
1030 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
1031 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1032 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
1033 +
1034 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1035 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1036 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1037 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1038 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1039 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1040 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1041 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1042 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1043 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1044 +
1045 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1046 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1047 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1048 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1049 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1050 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1051 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1052 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1053 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1054 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1055 +
1056 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1057 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1058 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1059 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1060 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1061 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1062 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1063 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1064 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1065 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1066 +
1067 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1068 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1069 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1070 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1071 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1072 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1073 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1074 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1075 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1076 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1077 +
1078 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1079 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1080 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1081 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1082 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1083 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1084 +}
1085 +
1086 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1087 + struct rt2x00lib_conf *libconf)
1088 +{
1089 + u32 reg;
1090 +
1091 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1092 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1093 + libconf->conf->short_frame_max_tx_count);
1094 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1095 + libconf->conf->long_frame_max_tx_count);
1096 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1097 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1098 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1099 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1100 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
1101 +}
1102 +
1103 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1104 + struct rt2x00lib_conf *libconf)
1105 +{
1106 + enum dev_state state =
1107 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
1108 + STATE_SLEEP : STATE_AWAKE;
1109 + u32 reg;
1110 +
1111 + if (state == STATE_SLEEP) {
1112 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1113 +
1114 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1115 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1116 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1117 + libconf->conf->listen_interval - 1);
1118 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1119 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1120 +
1121 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1122 + } else {
1123 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1124 +
1125 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1126 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1127 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1128 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1129 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1130 + }
1131 +}
1132 +
1133 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1134 + struct rt2x00lib_conf *libconf,
1135 + const unsigned int flags)
1136 +{
1137 + /* Always recalculate LNA gain before changing configuration */
1138 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
1139 +
1140 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1141 + rt2800pci_config_channel(rt2x00dev, libconf->conf,
1142 + &libconf->rf, &libconf->channel);
1143 + if (flags & IEEE80211_CONF_CHANGE_POWER)
1144 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1145 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1146 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
1147 + if (flags & IEEE80211_CONF_CHANGE_PS)
1148 + rt2800pci_config_ps(rt2x00dev, libconf);
1149 +}
1150 +
1151 +/*
1152 + * Link tuning
1153 + */
1154 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1155 + struct link_qual *qual)
1156 +{
1157 + u32 reg;
1158 +
1159 + /*
1160 + * Update FCS error count from register.
1161 + */
1162 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1163 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1164 +}
1165 +
1166 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1167 +{
1168 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1169 + return 0x2e + rt2x00dev->lna_gain;
1170 +
1171 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1172 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1173 + else
1174 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1175 +}
1176 +
1177 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1178 + struct link_qual *qual, u8 vgc_level)
1179 +{
1180 + if (qual->vgc_level != vgc_level) {
1181 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1182 + qual->vgc_level = vgc_level;
1183 + qual->vgc_level_reg = vgc_level;
1184 + }
1185 +}
1186 +
1187 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1188 + struct link_qual *qual)
1189 +{
1190 + rt2800pci_set_vgc(rt2x00dev, qual,
1191 + rt2800pci_get_default_vgc(rt2x00dev));
1192 +}
1193 +
1194 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1195 + struct link_qual *qual, const u32 count)
1196 +{
1197 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1198 + return;
1199 +
1200 + /*
1201 + * When RSSI is better then -80 increase VGC level with 0x10
1202 + */
1203 + rt2800pci_set_vgc(rt2x00dev, qual,
1204 + rt2800pci_get_default_vgc(rt2x00dev) +
1205 + ((qual->rssi > -80) * 0x10));
1206 +}
1207 +
1208 +/*
1209 + * Firmware functions
1210 + */
1211 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1212 +{
1213 + return FIRMWARE_RT2860;
1214 +}
1215 +
1216 +static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1217 + const u8 *data, const size_t len)
1218 +{
1219 + u16 fw_crc;
1220 + u16 crc;
1221 +
1222 + /*
1223 + * Only support 8kb firmware files.
1224 + */
1225 + if (len != 8192)
1226 + return FW_BAD_LENGTH;
1227 +
1228 + /*
1229 + * The last 2 bytes in the firmware array are the crc checksum itself,
1230 + * this means that we should never pass those 2 bytes to the crc
1231 + * algorithm.
1232 + */
1233 + fw_crc = (data[len - 2] << 8 | data[len - 1]);
1234 +
1235 + /*
1236 + * Use the crc ccitt algorithm.
1237 + * This will return the same value as the legacy driver which
1238 + * used bit ordering reversion on the both the firmware bytes
1239 + * before input input as well as on the final output.
1240 + * Obviously using crc ccitt directly is much more efficient.
1241 + */
1242 + crc = crc_ccitt(~0, data, len - 2);
1243 +
1244 + /*
1245 + * There is a small difference between the crc-itu-t + bitrev and
1246 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1247 + * will be swapped, use swab16 to convert the crc to the correct
1248 + * value.
1249 + */
1250 + crc = swab16(crc);
1251 +
1252 + return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1253 +}
1254 +
1255 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1256 + const u8 *data, const size_t len)
1257 +{
1258 + unsigned int i;
1259 + u32 reg;
1260 +
1261 + /*
1262 + * Wait for stable hardware.
1263 + */
1264 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1265 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1266 + if (reg && reg != ~0)
1267 + break;
1268 + msleep(1);
1269 + }
1270 +
1271 + if (i == REGISTER_BUSY_COUNT) {
1272 + ERROR(rt2x00dev, "Unstable hardware.\n");
1273 + return -EBUSY;
1274 + }
1275 +
1276 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1277 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1278 +
1279 + /*
1280 + * Disable DMA, will be reenabled later when enabling
1281 + * the radio.
1282 + */
1283 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1284 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1285 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1286 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1287 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1288 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1289 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1290 +
1291 + /*
1292 + * enable Host program ram write selection
1293 + */
1294 + reg = 0;
1295 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1296 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1297 +
1298 + /*
1299 + * Write firmware to device.
1300 + */
1301 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1302 + data, len);
1303 +
1304 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1305 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1306 +
1307 + /*
1308 + * Wait for device to stabilize.
1309 + */
1310 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1311 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1312 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1313 + break;
1314 + msleep(1);
1315 + }
1316 +
1317 + if (i == REGISTER_BUSY_COUNT) {
1318 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1319 + return -EBUSY;
1320 + }
1321 +
1322 + /*
1323 + * Disable interrupts
1324 + */
1325 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1326 +
1327 + /*
1328 + * Initialize BBP R/W access agent
1329 + */
1330 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1331 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1332 +
1333 + return 0;
1334 +}
1335 +
1336 +/*
1337 + * Initialization functions.
1338 + */
1339 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1340 +{
1341 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1342 + u32 word;
1343 +
1344 + if (entry->queue->qid == QID_RX) {
1345 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1346 +
1347 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1348 + } else {
1349 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1350 +
1351 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1352 + }
1353 +}
1354 +
1355 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1356 +{
1357 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1358 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1359 + u32 word;
1360 +
1361 + if (entry->queue->qid == QID_RX) {
1362 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1363 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1364 + rt2x00_desc_write(entry_priv->desc, 0, word);
1365 +
1366 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1367 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1368 + rt2x00_desc_write(entry_priv->desc, 1, word);
1369 + } else {
1370 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1371 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1372 + rt2x00_desc_write(entry_priv->desc, 1, word);
1373 + }
1374 +}
1375 +
1376 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1377 +{
1378 + struct queue_entry_priv_pci *entry_priv;
1379 + u32 reg;
1380 +
1381 + /*
1382 + * Initialize registers.
1383 + */
1384 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1385 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1386 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1387 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1388 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1389 +
1390 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1391 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1392 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1393 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1394 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1395 +
1396 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1397 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1398 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1399 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1400 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1401 +
1402 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1403 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1404 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1405 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1406 + rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1407 +
1408 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1409 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1410 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1411 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1412 + rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
1413 +
1414 + /*
1415 + * Enable global DMA configuration
1416 + */
1417 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1418 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1419 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1420 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1421 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1422 +
1423 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1424 +
1425 + return 0;
1426 +}
1427 +
1428 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1429 +{
1430 + u32 reg;
1431 + unsigned int i;
1432 +
1433 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1434 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1435 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1436 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1437 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1438 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1439 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1440 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1441 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1442 +
1443 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1444 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1445 +
1446 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1447 +
1448 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1449 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1450 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1451 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1452 +
1453 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1454 +
1455 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1456 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1457 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1458 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1459 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1460 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1461 +
1462 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1463 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1464 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1465 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1466 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1467 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1468 +
1469 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1470 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1471 +
1472 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1473 +
1474 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1475 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1476 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1477 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1478 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1479 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1480 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1481 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1482 +
1483 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1484 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1485 +
1486 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1487 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1488 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1489 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1490 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1491 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1492 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1493 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1494 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1495 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1496 +
1497 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1498 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1499 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1500 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1501 +
1502 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1503 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1504 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1505 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1506 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1507 + else
1508 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1509 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1510 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1511 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1512 +
1513 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1514 +
1515 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1516 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1517 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1518 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1519 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1520 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1521 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1522 +
1523 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1524 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1525 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1526 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1527 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1528 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1529 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1530 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1531 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1532 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1533 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1534 +
1535 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1536 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1537 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1538 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1539 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1540 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1541 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1542 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1543 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1544 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1545 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1546 +
1547 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1548 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1549 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1550 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1551 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1552 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1553 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1554 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1555 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1556 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1557 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1558 +
1559 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1560 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1561 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1562 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1563 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1564 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1565 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1566 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1567 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1568 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1569 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1570 +
1571 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1572 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1573 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1574 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1575 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1576 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1577 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1578 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1579 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1580 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1581 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1582 +
1583 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1584 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1585 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1586 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1587 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1588 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1589 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1590 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1591 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1592 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1593 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1594 +
1595 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1596 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1597 +
1598 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1599 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1600 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1601 + IEEE80211_MAX_RTS_THRESHOLD);
1602 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1603 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1604 +
1605 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1606 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1607 +
1608 + /*
1609 + * ASIC will keep garbage value after boot, clear encryption keys.
1610 + */
1611 + for (i = 0; i < 256; i++) {
1612 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1613 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1614 + wcid, sizeof(wcid));
1615 +
1616 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1617 + rt2x00pci_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1618 + }
1619 +
1620 + for (i = 0; i < 16; i++)
1621 + rt2x00pci_register_write(rt2x00dev,
1622 + SHARED_KEY_MODE_ENTRY(i), 0);
1623 +
1624 + /*
1625 + * Clear all beacons
1626 + * For the Beacon base registers we only need to clear
1627 + * the first byte since that byte contains the VALID and OWNER
1628 + * bits which (when set to 0) will invalidate the entire beacon.
1629 + */
1630 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1631 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1632 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1633 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1634 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1635 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1636 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1637 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1638 +
1639 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1640 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1641 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1642 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1643 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1644 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1645 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1646 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1647 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1648 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1649 +
1650 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1651 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1652 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1653 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1654 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1655 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1656 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1657 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1658 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1659 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1660 +
1661 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1662 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1663 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1664 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 3);
1665 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1666 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1667 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1668 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1669 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1670 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1671 +
1672 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1673 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1674 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1675 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1676 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1677 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1678 +
1679 + /*
1680 + * We must clear the error counters.
1681 + * These registers are cleared on read,
1682 + * so we may pass a useless variable to store the value.
1683 + */
1684 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1685 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1686 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1687 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1688 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1689 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1690 +
1691 + return 0;
1692 +}
1693 +
1694 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1695 +{
1696 + unsigned int i;
1697 + u32 reg;
1698 +
1699 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1700 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1701 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1702 + return 0;
1703 +
1704 + udelay(REGISTER_BUSY_DELAY);
1705 + }
1706 +
1707 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1708 + return -EACCES;
1709 +}
1710 +
1711 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1712 +{
1713 + unsigned int i;
1714 + u8 value;
1715 +
1716 + /*
1717 + * BBP was enabled after firmware was loaded,
1718 + * but we need to reactivate it now.
1719 + */
1720 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1721 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1722 + msleep(1);
1723 +
1724 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1725 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1726 + if ((value != 0xff) && (value != 0x00))
1727 + return 0;
1728 + udelay(REGISTER_BUSY_DELAY);
1729 + }
1730 +
1731 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1732 + return -EACCES;
1733 +}
1734 +
1735 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1736 +{
1737 + unsigned int i;
1738 + u16 eeprom;
1739 + u8 reg_id;
1740 + u8 value;
1741 +
1742 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1743 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1744 + return -EACCES;
1745 +
1746 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1747 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1748 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1749 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1750 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1751 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1752 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1753 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1754 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1755 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1756 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1757 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1758 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1759 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1760 +
1761 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1762 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1763 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1764 + }
1765 +
1766 + if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1767 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1768 +
1769 + if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1770 + rt2800pci_bbp_write(rt2x00dev, 31, 0x08);
1771 + rt2800pci_bbp_write(rt2x00dev, 78, 0x0e);
1772 + rt2800pci_bbp_write(rt2x00dev, 80, 0x08);
1773 + }
1774 +
1775 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1776 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1777 +
1778 + if (eeprom != 0xffff && eeprom != 0x0000) {
1779 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1780 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1781 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1782 + }
1783 + }
1784 +
1785 + return 0;
1786 +}
1787 +
1788 +static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1789 + bool bw40, u8 rfcsr24, u8 filter_target)
1790 +{
1791 + unsigned int i;
1792 + u8 bbp;
1793 + u8 rfcsr;
1794 + u8 passband;
1795 + u8 stopband;
1796 + u8 overtuned = 0;
1797 +
1798 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1799 +
1800 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1801 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1802 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1803 +
1804 + rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1805 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1806 + rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1807 +
1808 + /*
1809 + * Set power & frequency of passband test tone
1810 + */
1811 + rt2800pci_bbp_write(rt2x00dev, 24, 0);
1812 +
1813 + for (i = 0; i < 100; i++) {
1814 + rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1815 + msleep(1);
1816 +
1817 + rt2800pci_bbp_read(rt2x00dev, 55, &passband);
1818 + if (passband)
1819 + break;
1820 + }
1821 +
1822 + /*
1823 + * Set power & frequency of stopband test tone
1824 + */
1825 + rt2800pci_bbp_write(rt2x00dev, 24, 0x06);
1826 +
1827 + for (i = 0; i < 100; i++) {
1828 + rt2800pci_bbp_write(rt2x00dev, 25, 0x90);
1829 + msleep(1);
1830 +
1831 + rt2800pci_bbp_read(rt2x00dev, 55, &stopband);
1832 +
1833 + if ((passband - stopband) <= filter_target) {
1834 + rfcsr24++;
1835 + overtuned += ((passband - stopband) == filter_target);
1836 + } else
1837 + break;
1838 +
1839 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1840 + }
1841 +
1842 + rfcsr24 -= !!overtuned;
1843 +
1844 + rt2800pci_rfcsr_write(rt2x00dev, 24, rfcsr24);
1845 + return rfcsr24;
1846 +}
1847 +
1848 +static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1849 +{
1850 + u8 rfcsr;
1851 + u8 bbp;
1852 +
1853 + if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1854 + !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1855 + !rt2x00_rf(&rt2x00dev->chip, RF3022))
1856 + return 0;
1857 +
1858 + /*
1859 + * Init RF calibration.
1860 + */
1861 + rt2800pci_rfcsr_read(rt2x00dev, 30, &rfcsr);
1862 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1863 + rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1864 + msleep(1);
1865 + rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1866 + rt2800pci_rfcsr_write(rt2x00dev, 30, rfcsr);
1867 +
1868 + rt2800pci_rfcsr_write(rt2x00dev, 0, 0x50);
1869 + rt2800pci_rfcsr_write(rt2x00dev, 1, 0x01);
1870 + rt2800pci_rfcsr_write(rt2x00dev, 2, 0xf7);
1871 + rt2800pci_rfcsr_write(rt2x00dev, 3, 0x75);
1872 + rt2800pci_rfcsr_write(rt2x00dev, 4, 0x40);
1873 + rt2800pci_rfcsr_write(rt2x00dev, 5, 0x03);
1874 + rt2800pci_rfcsr_write(rt2x00dev, 6, 0x02);
1875 + rt2800pci_rfcsr_write(rt2x00dev, 7, 0x50);
1876 + rt2800pci_rfcsr_write(rt2x00dev, 8, 0x39);
1877 + rt2800pci_rfcsr_write(rt2x00dev, 9, 0x0f);
1878 + rt2800pci_rfcsr_write(rt2x00dev, 10, 0x60);
1879 + rt2800pci_rfcsr_write(rt2x00dev, 11, 0x21);
1880 + rt2800pci_rfcsr_write(rt2x00dev, 12, 0x75);
1881 + rt2800pci_rfcsr_write(rt2x00dev, 13, 0x75);
1882 + rt2800pci_rfcsr_write(rt2x00dev, 14, 0x90);
1883 + rt2800pci_rfcsr_write(rt2x00dev, 15, 0x58);
1884 + rt2800pci_rfcsr_write(rt2x00dev, 16, 0xb3);
1885 + rt2800pci_rfcsr_write(rt2x00dev, 17, 0x92);
1886 + rt2800pci_rfcsr_write(rt2x00dev, 18, 0x2c);
1887 + rt2800pci_rfcsr_write(rt2x00dev, 19, 0x02);
1888 + rt2800pci_rfcsr_write(rt2x00dev, 20, 0xba);
1889 + rt2800pci_rfcsr_write(rt2x00dev, 21, 0xdb);
1890 + rt2800pci_rfcsr_write(rt2x00dev, 22, 0x00);
1891 + rt2800pci_rfcsr_write(rt2x00dev, 23, 0x31);
1892 + rt2800pci_rfcsr_write(rt2x00dev, 24, 0x08);
1893 + rt2800pci_rfcsr_write(rt2x00dev, 25, 0x01);
1894 + rt2800pci_rfcsr_write(rt2x00dev, 26, 0x25);
1895 + rt2800pci_rfcsr_write(rt2x00dev, 27, 0x23);
1896 + rt2800pci_rfcsr_write(rt2x00dev, 28, 0x13);
1897 + rt2800pci_rfcsr_write(rt2x00dev, 29, 0x83);
1898 +
1899 + /*
1900 + * Set RX Filter calibration for 20MHz and 40MHz
1901 + */
1902 + rt2x00dev->calibration[0] =
1903 + rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1904 + rt2x00dev->calibration[1] =
1905 + rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1906 +
1907 + /*
1908 + * Set back to initial state
1909 + */
1910 + rt2800pci_bbp_write(rt2x00dev, 24, 0);
1911 +
1912 + rt2800pci_rfcsr_read(rt2x00dev, 22, &rfcsr);
1913 + rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1914 + rt2800pci_rfcsr_write(rt2x00dev, 22, rfcsr);
1915 +
1916 + /*
1917 + * set BBP back to BW20
1918 + */
1919 + rt2800pci_bbp_read(rt2x00dev, 4, &bbp);
1920 + rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1921 + rt2800pci_bbp_write(rt2x00dev, 4, bbp);
1922 +
1923 + return 0;
1924 +}
1925 +
1926 +/*
1927 + * Device state switch handlers.
1928 + */
1929 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1930 + enum dev_state state)
1931 +{
1932 + u32 reg;
1933 +
1934 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1935 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1936 + (state == STATE_RADIO_RX_ON) ||
1937 + (state == STATE_RADIO_RX_ON_LINK));
1938 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1939 +}
1940 +
1941 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1942 + enum dev_state state)
1943 +{
1944 + int mask = (state == STATE_RADIO_IRQ_ON);
1945 + u32 reg;
1946 +
1947 + /*
1948 + * When interrupts are being enabled, the interrupt registers
1949 + * should clear the register to assure a clean state.
1950 + */
1951 + if (state == STATE_RADIO_IRQ_ON) {
1952 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1953 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1954 + }
1955 +
1956 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1957 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1958 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1959 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1960 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1961 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1962 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1963 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1964 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1965 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1966 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1967 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1968 + rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1969 + rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1970 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1971 + rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1972 + rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1973 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1974 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1975 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1976 +}
1977 +
1978 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1979 +{
1980 + unsigned int i;
1981 + u32 reg;
1982 +
1983 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1984 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1985 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1986 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1987 + return 0;
1988 +
1989 + msleep(1);
1990 + }
1991 +
1992 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1993 + return -EACCES;
1994 +}
1995 +
1996 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1997 +{
1998 + u32 reg;
1999 + u16 word;
2000 +
2001 + /*
2002 + * Initialize all registers.
2003 + */
2004 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2005 + rt2800pci_init_queues(rt2x00dev) ||
2006 + rt2800pci_init_registers(rt2x00dev) ||
2007 + rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2008 + rt2800pci_init_bbp(rt2x00dev) ||
2009 + rt2800pci_init_rfcsr(rt2x00dev)))
2010 + return -EIO;
2011 +
2012 + /*
2013 + * Send signal to firmware during boot time.
2014 + */
2015 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2016 +
2017 + /*
2018 + * Enable RX.
2019 + */
2020 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2021 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2022 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2023 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2024 +
2025 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2026 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2027 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2028 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2029 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2030 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2031 +
2032 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2033 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2034 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2035 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2036 +
2037 + /*
2038 + * Initialize LED control
2039 + */
2040 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2041 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2042 + word & 0xff, (word >> 8) & 0xff);
2043 +
2044 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2045 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2046 + word & 0xff, (word >> 8) & 0xff);
2047 +
2048 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2049 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2050 + word & 0xff, (word >> 8) & 0xff);
2051 +
2052 + return 0;
2053 +}
2054 +
2055 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2056 +{
2057 + u32 reg;
2058 +
2059 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2060 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2061 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2062 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2063 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2064 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2065 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2066 +
2067 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2068 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2069 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
2070 +
2071 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2072 +
2073 + /* Wait for DMA, ignore error */
2074 + rt2800pci_wait_wpdma_ready(rt2x00dev);
2075 +}
2076 +
2077 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2078 + enum dev_state state)
2079 +{
2080 + /*
2081 + * Always put the device to sleep (even when we intend to wakup!)
2082 + * if the device is booting and wasn't asleep it will return
2083 + * failure when attempting to wakup.
2084 + */
2085 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2086 +
2087 + if (state == STATE_AWAKE) {
2088 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2089 + rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2090 + }
2091 +
2092 + return 0;
2093 +}
2094 +
2095 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
2096 + enum dev_state state)
2097 +{
2098 + int retval = 0;
2099 +
2100 + switch (state) {
2101 + case STATE_RADIO_ON:
2102 + /*
2103 + * Before the radio can be enabled, the device first has
2104 + * to be woken up. After that it needs a bit of time
2105 + * to be fully awake and the radio can be enabled.
2106 + */
2107 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
2108 + msleep(1);
2109 + retval = rt2800pci_enable_radio(rt2x00dev);
2110 + break;
2111 + case STATE_RADIO_OFF:
2112 + /*
2113 + * After the radio has been disablee, the device should
2114 + * be put to sleep for powersaving.
2115 + */
2116 + rt2800pci_disable_radio(rt2x00dev);
2117 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
2118 + break;
2119 + case STATE_RADIO_RX_ON:
2120 + case STATE_RADIO_RX_ON_LINK:
2121 + case STATE_RADIO_RX_OFF:
2122 + case STATE_RADIO_RX_OFF_LINK:
2123 + rt2800pci_toggle_rx(rt2x00dev, state);
2124 + break;
2125 + case STATE_RADIO_IRQ_ON:
2126 + case STATE_RADIO_IRQ_OFF:
2127 + rt2800pci_toggle_irq(rt2x00dev, state);
2128 + break;
2129 + case STATE_DEEP_SLEEP:
2130 + case STATE_SLEEP:
2131 + case STATE_STANDBY:
2132 + case STATE_AWAKE:
2133 + retval = rt2800pci_set_state(rt2x00dev, state);
2134 + break;
2135 + default:
2136 + retval = -ENOTSUPP;
2137 + break;
2138 + }
2139 +
2140 + if (unlikely(retval))
2141 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
2142 + state, retval);
2143 +
2144 + return retval;
2145 +}
2146 +
2147 +/*
2148 + * TX descriptor initialization
2149 + */
2150 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2151 + struct sk_buff *skb,
2152 + struct txentry_desc *txdesc)
2153 +{
2154 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2155 + __le32 *txd = skbdesc->desc;
2156 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
2157 + u32 word;
2158 +
2159 + /*
2160 + * Initialize TX Info descriptor
2161 + */
2162 + rt2x00_desc_read(txwi, 0, &word);
2163 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
2164 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2165 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2166 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2167 + rt2x00_set_field32(&word, TXWI_W0_TS,
2168 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2169 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2170 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2171 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2172 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2173 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2174 + rt2x00_set_field32(&word, TXWI_W0_BW,
2175 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2176 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2177 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2178 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2179 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2180 + rt2x00_desc_write(txwi, 0, word);
2181 +
2182 + rt2x00_desc_read(txwi, 1, &word);
2183 + rt2x00_set_field32(&word, TXWI_W1_ACK,
2184 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2185 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2186 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2187 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2188 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2189 + test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2190 + txdesc->key_idx : 0xff);
2191 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2192 + skb->len - txdesc->l2pad);
2193 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2194 + skbdesc->entry->queue->qid);
2195 + rt2x00_desc_write(txwi, 1, word);
2196 +
2197 + /*
2198 + * Always write 0 to IV/EIV fields, hardware will insert the IV
2199 + * from the IVEIV register when ENTRY_TXD_ENCRYPT_IV is set to 0.
2200 + * When ENTRY_TXD_ENCRYPT_IV is set to 1 it will use the IV data
2201 + * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2202 + * crypto entry in the registers should be used to encrypt the frame.
2203 + */
2204 + _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2205 + _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2206 +
2207 + /*
2208 + * Initialize TX descriptor
2209 + */
2210 + rt2x00_desc_read(txd, 0, &word);
2211 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2212 + rt2x00_desc_write(txd, 0, word);
2213 +
2214 + rt2x00_desc_read(txd, 1, &word);
2215 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2216 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
2217 + rt2x00_set_field32(&word, TXD_W1_BURST,
2218 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2219 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2220 + rt2x00dev->hw->extra_tx_headroom);
2221 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
2222 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2223 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2224 + rt2x00_desc_write(txd, 1, word);
2225 +
2226 + rt2x00_desc_read(txd, 2, &word);
2227 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2228 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2229 + rt2x00_desc_write(txd, 2, word);
2230 +
2231 + rt2x00_desc_read(txd, 3, &word);
2232 + rt2x00_set_field32(&word, TXD_W3_WIV,
2233 + !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2234 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2235 + rt2x00_desc_write(txd, 3, word);
2236 +}
2237 +
2238 +/*
2239 + * TX data initialization
2240 + */
2241 +static void rt2800pci_write_beacon(struct queue_entry *entry)
2242 +{
2243 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2244 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2245 + unsigned int beacon_base;
2246 + u32 reg;
2247 +
2248 + /*
2249 + * Disable beaconing while we are reloading the beacon data,
2250 + * otherwise we might be sending out invalid data.
2251 + */
2252 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2253 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2254 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2255 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2256 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2257 +
2258 + /*
2259 + * Write entire beacon with descriptor to register.
2260 + */
2261 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2262 + rt2x00pci_register_multiwrite(rt2x00dev,
2263 + beacon_base,
2264 + skbdesc->desc, skbdesc->desc_len);
2265 + rt2x00pci_register_multiwrite(rt2x00dev,
2266 + beacon_base + skbdesc->desc_len,
2267 + entry->skb->data, entry->skb->len);
2268 +
2269 + /*
2270 + * Clean up beacon skb.
2271 + */
2272 + dev_kfree_skb_any(entry->skb);
2273 + entry->skb = NULL;
2274 +}
2275 +
2276 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2277 + const enum data_queue_qid queue_idx)
2278 +{
2279 + struct data_queue *queue;
2280 + unsigned int idx, qidx = 0;
2281 + u32 reg;
2282 +
2283 + if (queue_idx == QID_BEACON) {
2284 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2285 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2286 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2287 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2288 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2289 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2290 + }
2291 + return;
2292 + }
2293 +
2294 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
2295 + return;
2296 +
2297 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2298 + idx = queue->index[Q_INDEX];
2299 +
2300 + if (queue_idx == QID_MGMT)
2301 + qidx = 5;
2302 + else
2303 + qidx = queue_idx;
2304 +
2305 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2306 +}
2307 +
2308 +static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2309 + const enum data_queue_qid qid)
2310 +{
2311 + u32 reg;
2312 +
2313 + if (qid == QID_BEACON) {
2314 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2315 + return;
2316 + }
2317 +
2318 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2319 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2320 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2321 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2322 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2323 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2324 +}
2325 +
2326 +/*
2327 + * RX control handlers
2328 + */
2329 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2330 + struct rxdone_entry_desc *rxdesc)
2331 +{
2332 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2333 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2334 + __le32 *rxd = entry_priv->desc;
2335 + __le32 *rxwi = (__le32 *)entry->skb->data;
2336 + u32 rxd3;
2337 + u32 rxwi0;
2338 + u32 rxwi1;
2339 + u32 rxwi2;
2340 + u32 rxwi3;
2341 +
2342 + rt2x00_desc_read(rxd, 3, &rxd3);
2343 + rt2x00_desc_read(rxwi, 0, &rxwi0);
2344 + rt2x00_desc_read(rxwi, 1, &rxwi1);
2345 + rt2x00_desc_read(rxwi, 2, &rxwi2);
2346 + rt2x00_desc_read(rxwi, 3, &rxwi3);
2347 +
2348 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2349 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2350 +
2351 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2352 + /*
2353 + * Unfortunately we don't know the cipher type used during
2354 + * decryption. This prevents us from correct providing
2355 + * correct statistics through debugfs.
2356 + */
2357 + rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2358 + rxdesc->cipher_status =
2359 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2360 + }
2361 +
2362 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2363 + /*
2364 + * Hardware has stripped IV/EIV data from 802.11 frame during
2365 + * decryption. Unfortunately the descriptor doesn't contain
2366 + * any fields with the EIV/IV data either, so they can't
2367 + * be restored by rt2x00lib.
2368 + */
2369 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2370 +
2371 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2372 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2373 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2374 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2375 + }
2376 +
2377 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2378 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2379 +
2380 + if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD))
2381 + rxdesc->dev_flags |= RXDONE_L2PAD;
2382 +
2383 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2384 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2385 +
2386 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2387 + rxdesc->flags |= RX_FLAG_40MHZ;
2388 +
2389 + /*
2390 + * Detect RX rate, always use MCS as signal type.
2391 + */
2392 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2393 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2394 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2395 +
2396 + /*
2397 + * Mask of 0x8 bit to remove the short preamble flag.
2398 + */
2399 + if (rxdesc->rate_mode == RATE_MODE_CCK)
2400 + rxdesc->signal &= ~0x8;
2401 +
2402 + rxdesc->rssi =
2403 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2404 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2405 +
2406 + rxdesc->noise =
2407 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2408 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2409 +
2410 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2411 +
2412 + /*
2413 + * Set RX IDX in register to inform hardware that we have handled
2414 + * this entry and it is available for reuse again.
2415 + */
2416 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2417 +
2418 + /*
2419 + * Remove TXWI descriptor from start of buffer.
2420 + */
2421 + skb_pull(entry->skb, RXWI_DESC_SIZE);
2422 + skb_trim(entry->skb, rxdesc->size);
2423 +}
2424 +
2425 +/*
2426 + * Interrupt functions.
2427 + */
2428 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2429 +{
2430 + struct data_queue *queue;
2431 + struct queue_entry *entry;
2432 + struct queue_entry *entry_done;
2433 + struct queue_entry_priv_pci *entry_priv;
2434 + struct txdone_entry_desc txdesc;
2435 + u32 word;
2436 + u32 reg;
2437 + u32 old_reg;
2438 + int type;
2439 + int index;
2440 +
2441 + /*
2442 + * During each loop we will compare the freshly read
2443 + * TX_STA_FIFO register value with the value read from
2444 + * the previous loop. If the 2 values are equal then
2445 + * we should stop processing because the chance it
2446 + * quite big that the device has been unplugged and
2447 + * we risk going into an endless loop.
2448 + */
2449 + old_reg = 0;
2450 +
2451 + while (1) {
2452 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2453 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2454 + break;
2455 +
2456 + if (old_reg == reg)
2457 + break;
2458 + old_reg = reg;
2459 +
2460 + /*
2461 + * Skip this entry when it contains an invalid
2462 + * queue identication number.
2463 + */
2464 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2465 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2466 + if (unlikely(!queue))
2467 + continue;
2468 +
2469 + /*
2470 + * Skip this entry when it contains an invalid
2471 + * index number.
2472 + */
2473 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2474 + if (unlikely(index >= queue->limit))
2475 + continue;
2476 +
2477 + entry = &queue->entries[index];
2478 + entry_priv = entry->priv_data;
2479 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2480 +
2481 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2482 + while (entry != entry_done) {
2483 + /*
2484 + * Catch up.
2485 + * Just report any entries we missed as failed.
2486 + */
2487 + WARNING(rt2x00dev,
2488 + "TX status report missed for entry %d\n",
2489 + entry_done->entry_idx);
2490 +
2491 + txdesc.flags = 0;
2492 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2493 + txdesc.retry = 0;
2494 +
2495 + rt2x00lib_txdone(entry_done, &txdesc);
2496 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2497 + }
2498 +
2499 + /*
2500 + * Obtain the status about this packet.
2501 + */
2502 + txdesc.flags = 0;
2503 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2504 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2505 + else
2506 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2507 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2508 +
2509 + rt2x00lib_txdone(entry, &txdesc);
2510 + }
2511 +}
2512 +
2513 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2514 +{
2515 + struct rt2x00_dev *rt2x00dev = dev_instance;
2516 + u32 reg;
2517 +
2518 + /* Read status and ACK all interrupts */
2519 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2520 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2521 +
2522 + if (!reg)
2523 + return IRQ_NONE;
2524 +
2525 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2526 + return IRQ_HANDLED;
2527 +
2528 + /*
2529 + * 1 - Rx ring done interrupt.
2530 + */
2531 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2532 + rt2x00pci_rxdone(rt2x00dev);
2533 +
2534 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2535 + rt2800pci_txdone(rt2x00dev);
2536 +
2537 + return IRQ_HANDLED;
2538 +}
2539 +
2540 +/*
2541 + * Device probe functions.
2542 + */
2543 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2544 +{
2545 + u16 word;
2546 + u8 *mac;
2547 + u8 default_lna_gain;
2548 +
2549 + /*
2550 + * Read EEPROM into buffer
2551 + */
2552 + switch(rt2x00dev->chip.rt) {
2553 + case RT2880:
2554 + case RT3052:
2555 + rt2800pci_read_eeprom_soc(rt2x00dev);
2556 + break;
2557 + default:
2558 + rt2800pci_read_eeprom_pci(rt2x00dev);
2559 + break;
2560 + }
2561 +
2562 + /*
2563 + * Start validation of the data that has been read.
2564 + */
2565 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2566 + if (!is_valid_ether_addr(mac)) {
2567 + DECLARE_MAC_BUF(macbuf);
2568 +
2569 + random_ether_addr(mac);
2570 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2571 + }
2572 +
2573 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2574 + if (word == 0xffff) {
2575 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2576 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2577 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2578 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2579 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2580 + } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2581 + /*
2582 + * There is a max of 2 RX streams for RT2860 series
2583 + */
2584 + if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2585 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2586 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2587 + }
2588 +
2589 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2590 + if (word == 0xffff) {
2591 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2592 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2593 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2594 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2595 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2596 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2597 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2598 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2599 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2600 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2601 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2602 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2603 + }
2604 +
2605 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2606 + if ((word & 0x00ff) == 0x00ff) {
2607 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2608 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2609 + LED_MODE_TXRX_ACTIVITY);
2610 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2611 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2612 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2613 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2614 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2615 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2616 + }
2617 +
2618 + /*
2619 + * During the LNA validation we are going to use
2620 + * lna0 as correct value. Note that EEPROM_LNA
2621 + * is never validated.
2622 + */
2623 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2624 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2625 +
2626 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2627 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2628 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2629 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2630 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2631 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2632 +
2633 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2634 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2635 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2636 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2637 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2638 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2639 + default_lna_gain);
2640 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2641 +
2642 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2643 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2644 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2645 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2646 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2647 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2648 +
2649 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2650 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2651 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2652 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2653 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2654 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2655 + default_lna_gain);
2656 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2657 +
2658 + return 0;
2659 +}
2660 +
2661 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2662 +{
2663 + u32 reg;
2664 + u16 value;
2665 + u16 eeprom;
2666 +
2667 + /*
2668 + * Read EEPROM word for configuration.
2669 + */
2670 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2671 +
2672 + /*
2673 + * Identify RF chipset.
2674 + */
2675 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2676 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2677 + rt2x00_set_chip_rf(rt2x00dev, value, reg);
2678 +
2679 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2680 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2681 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2682 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2683 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2684 + !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
2685 + !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
2686 + !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2687 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2688 + return -ENODEV;
2689 + }
2690 +
2691 + /*
2692 + * Identify default antenna configuration.
2693 + */
2694 + rt2x00dev->default_ant.tx =
2695 + rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2696 + rt2x00dev->default_ant.rx =
2697 + rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2698 +
2699 + /*
2700 + * Read frequency offset and RF programming sequence.
2701 + */
2702 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2703 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2704 +
2705 + /*
2706 + * Read external LNA informations.
2707 + */
2708 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2709 +
2710 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2711 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2712 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2713 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2714 +
2715 + /*
2716 + * Detect if this device has an hardware controlled radio.
2717 + */
2718 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2719 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2720 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2721 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2722 +
2723 + /*
2724 + * Store led settings, for correct led behaviour.
2725 + */
2726 +#ifdef CONFIG_RT2X00_LIB_LEDS
2727 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2728 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2729 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2730 +
2731 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2732 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2733 +
2734 + return 0;
2735 +}
2736 +
2737 +/*
2738 + * RF value list for rt2860
2739 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2740 + */
2741 +static const struct rf_channel rf_vals[] = {
2742 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2743 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2744 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2745 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2746 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2747 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2748 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2749 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2750 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2751 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2752 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2753 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2754 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2755 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2756 +
2757 + /* 802.11 UNI / HyperLan 2 */
2758 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2759 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2760 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2761 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2762 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2763 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2764 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2765 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2766 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2767 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2768 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2769 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2770 +
2771 + /* 802.11 HyperLan 2 */
2772 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2773 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2774 + { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2775 + { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2776 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2777 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2778 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2779 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2780 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2781 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2782 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2783 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2784 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2785 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2786 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2787 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2788 +
2789 + /* 802.11 UNII */
2790 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2791 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2792 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2793 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2794 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2795 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2796 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2797 +
2798 + /* 802.11 Japan */
2799 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2800 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2801 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2802 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2803 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2804 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2805 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2806 +};
2807 +
2808 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2809 +{
2810 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2811 + struct channel_info *info;
2812 + char *tx_power1;
2813 + char *tx_power2;
2814 + unsigned int i;
2815 + u16 eeprom;
2816 +
2817 + /*
2818 + * Initialize all hw fields.
2819 + */
2820 + rt2x00dev->hw->flags =
2821 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2822 + IEEE80211_HW_SIGNAL_DBM |
2823 + IEEE80211_HW_SUPPORTS_PS |
2824 + IEEE80211_HW_PS_NULLFUNC_STACK;
2825 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2826 +
2827 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2828 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2829 + rt2x00_eeprom_addr(rt2x00dev,
2830 + EEPROM_MAC_ADDR_0));
2831 +
2832 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2833 +
2834 + /*
2835 + * Initialize hw_mode information.
2836 + */
2837 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2838 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2839 +
2840 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2841 + rt2x00_rf(&rt2x00dev->chip, RF2720) ||
2842 + rt2x00_rf(&rt2x00dev->chip, RF3021) ||
2843 + rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2844 + spec->num_channels = 14;
2845 + spec->channels = rf_vals;
2846 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2847 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2848 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2849 + spec->num_channels = ARRAY_SIZE(rf_vals);
2850 + spec->channels = rf_vals;
2851 + }
2852 +
2853 + /*
2854 + * Initialize HT information.
2855 + */
2856 + spec->ht.ht_supported = true;
2857 + spec->ht.cap =
2858 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2859 + IEEE80211_HT_CAP_GRN_FLD |
2860 + IEEE80211_HT_CAP_SGI_20 |
2861 + IEEE80211_HT_CAP_SGI_40 |
2862 + IEEE80211_HT_CAP_TX_STBC |
2863 + IEEE80211_HT_CAP_RX_STBC |
2864 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2865 + spec->ht.ampdu_factor = 3;
2866 + spec->ht.ampdu_density = 4;
2867 + spec->ht.mcs.tx_params =
2868 + IEEE80211_HT_MCS_TX_DEFINED |
2869 + IEEE80211_HT_MCS_TX_RX_DIFF |
2870 + ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2871 + IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2872 +
2873 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2874 + case 3:
2875 + spec->ht.mcs.rx_mask[2] = 0xff;
2876 + case 2:
2877 + spec->ht.mcs.rx_mask[1] = 0xff;
2878 + case 1:
2879 + spec->ht.mcs.rx_mask[0] = 0xff;
2880 + spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2881 + break;
2882 + }
2883 +
2884 + /*
2885 + * Create channel information array
2886 + */
2887 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2888 + if (!info)
2889 + return -ENOMEM;
2890 +
2891 + spec->channels_info = info;
2892 +
2893 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2894 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2895 +
2896 + for (i = 0; i < 14; i++) {
2897 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2898 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2899 + }
2900 +
2901 + if (spec->num_channels > 14) {
2902 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2903 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2904 +
2905 + for (i = 14; i < spec->num_channels; i++) {
2906 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2907 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2908 + }
2909 + }
2910 +
2911 + return 0;
2912 +}
2913 +
2914 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2915 +{
2916 + int retval;
2917 +
2918 + /*
2919 + * Allocate eeprom data.
2920 + */
2921 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2922 + if (retval)
2923 + return retval;
2924 +
2925 + retval = rt2800pci_init_eeprom(rt2x00dev);
2926 + if (retval)
2927 + return retval;
2928 +
2929 + /*
2930 + * Initialize hw specifications.
2931 + */
2932 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2933 + if (retval)
2934 + return retval;
2935 +
2936 + /*
2937 + * This device requires firmware.
2938 + */
2939 + if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
2940 + !rt2x00_rt(&rt2x00dev->chip, RT3052))
2941 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2942 + __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2943 + __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
2944 + if (!modparam_nohwcrypt)
2945 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2946 +
2947 + /*
2948 + * Set the rssi offset.
2949 + */
2950 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2951 +
2952 + return 0;
2953 +}
2954 +
2955 +/*
2956 + * IEEE80211 stack callback functions.
2957 + */
2958 +static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
2959 + u32 *iv32, u16 *iv16)
2960 +{
2961 + struct rt2x00_dev *rt2x00dev = hw->priv;
2962 + struct mac_iveiv_entry iveiv_entry;
2963 + u32 offset;
2964 +
2965 + offset = MAC_IVEIV_ENTRY(hw_key_idx);
2966 + rt2x00pci_register_multiread(rt2x00dev, offset,
2967 + &iveiv_entry, sizeof(iveiv_entry));
2968 +
2969 + memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
2970 + memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
2971 +}
2972 +
2973 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2974 +{
2975 + struct rt2x00_dev *rt2x00dev = hw->priv;
2976 + u32 reg;
2977 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2978 +
2979 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2980 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2981 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2982 +
2983 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2984 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2985 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2986 +
2987 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2988 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2989 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2990 +
2991 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2992 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2993 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2994 +
2995 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2996 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2997 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2998 +
2999 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3000 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3001 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3002 +
3003 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3004 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3005 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3006 +
3007 + return 0;
3008 +}
3009 +
3010 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3011 + const struct ieee80211_tx_queue_params *params)
3012 +{
3013 + struct rt2x00_dev *rt2x00dev = hw->priv;
3014 + struct data_queue *queue;
3015 + struct rt2x00_field32 field;
3016 + int retval;
3017 + u32 reg;
3018 + u32 offset;
3019 +
3020 + /*
3021 + * First pass the configuration through rt2x00lib, that will
3022 + * update the queue settings and validate the input. After that
3023 + * we are free to update the registers based on the value
3024 + * in the queue parameter.
3025 + */
3026 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3027 + if (retval)
3028 + return retval;
3029 +
3030 + /*
3031 + * We only need to perform additional register initialization
3032 + * for WMM queues/
3033 + */
3034 + if (queue_idx >= 4)
3035 + return 0;
3036 +
3037 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3038 +
3039 + /* Update WMM TXOP register */
3040 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3041 + field.bit_offset = (queue_idx & 1) * 16;
3042 + field.bit_mask = 0xffff << field.bit_offset;
3043 +
3044 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
3045 + rt2x00_set_field32(&reg, field, queue->txop);
3046 + rt2x00pci_register_write(rt2x00dev, offset, reg);
3047 +
3048 + /* Update WMM registers */
3049 + field.bit_offset = queue_idx * 4;
3050 + field.bit_mask = 0xf << field.bit_offset;
3051 +
3052 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3053 + rt2x00_set_field32(&reg, field, queue->aifs);
3054 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3055 +
3056 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3057 + rt2x00_set_field32(&reg, field, queue->cw_min);
3058 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3059 +
3060 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3061 + rt2x00_set_field32(&reg, field, queue->cw_max);
3062 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3063 +
3064 + /* Update EDCA registers */
3065 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3066 +
3067 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
3068 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3069 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3070 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3071 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3072 + rt2x00pci_register_write(rt2x00dev, offset, reg);
3073 +
3074 + return 0;
3075 +}
3076 +
3077 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3078 +{
3079 + struct rt2x00_dev *rt2x00dev = hw->priv;
3080 + u64 tsf;
3081 + u32 reg;
3082 +
3083 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3084 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3085 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3086 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3087 +
3088 + return tsf;
3089 +}
3090 +
3091 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3092 + .tx = rt2x00mac_tx,
3093 + .start = rt2x00mac_start,
3094 + .stop = rt2x00mac_stop,
3095 + .add_interface = rt2x00mac_add_interface,
3096 + .remove_interface = rt2x00mac_remove_interface,
3097 + .config = rt2x00mac_config,
3098 + .configure_filter = rt2x00mac_configure_filter,
3099 + .set_key = rt2x00mac_set_key,
3100 + .get_stats = rt2x00mac_get_stats,
3101 + .get_tkip_seq = rt2800pci_get_tkip_seq,
3102 + .set_rts_threshold = rt2800pci_set_rts_threshold,
3103 + .bss_info_changed = rt2x00mac_bss_info_changed,
3104 + .conf_tx = rt2800pci_conf_tx,
3105 + .get_tx_stats = rt2x00mac_get_tx_stats,
3106 + .get_tsf = rt2800pci_get_tsf,
3107 +};
3108 +
3109 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3110 + .irq_handler = rt2800pci_interrupt,
3111 + .probe_hw = rt2800pci_probe_hw,
3112 + .get_firmware_name = rt2800pci_get_firmware_name,
3113 + .check_firmware = rt2800pci_check_firmware,
3114 + .load_firmware = rt2800pci_load_firmware,
3115 + .initialize = rt2x00pci_initialize,
3116 + .uninitialize = rt2x00pci_uninitialize,
3117 + .get_entry_state = rt2800pci_get_entry_state,
3118 + .clear_entry = rt2800pci_clear_entry,
3119 + .set_device_state = rt2800pci_set_device_state,
3120 + .rfkill_poll = rt2800pci_rfkill_poll,
3121 + .link_stats = rt2800pci_link_stats,
3122 + .reset_tuner = rt2800pci_reset_tuner,
3123 + .link_tuner = rt2800pci_link_tuner,
3124 + .write_tx_desc = rt2800pci_write_tx_desc,
3125 + .write_tx_data = rt2x00pci_write_tx_data,
3126 + .write_beacon = rt2800pci_write_beacon,
3127 + .kick_tx_queue = rt2800pci_kick_tx_queue,
3128 + .kill_tx_queue = rt2800pci_kill_tx_queue,
3129 + .fill_rxdone = rt2800pci_fill_rxdone,
3130 + .config_shared_key = rt2800pci_config_shared_key,
3131 + .config_pairwise_key = rt2800pci_config_pairwise_key,
3132 + .config_filter = rt2800pci_config_filter,
3133 + .config_intf = rt2800pci_config_intf,
3134 + .config_erp = rt2800pci_config_erp,
3135 + .config_ant = rt2800pci_config_ant,
3136 + .config = rt2800pci_config,
3137 +};
3138 +
3139 +static const struct data_queue_desc rt2800pci_queue_rx = {
3140 + .entry_num = RX_ENTRIES,
3141 + .data_size = AGGREGATION_SIZE,
3142 + .desc_size = RXD_DESC_SIZE,
3143 + .priv_size = sizeof(struct queue_entry_priv_pci),
3144 +};
3145 +
3146 +static const struct data_queue_desc rt2800pci_queue_tx = {
3147 + .entry_num = TX_ENTRIES,
3148 + .data_size = AGGREGATION_SIZE,
3149 + .desc_size = TXD_DESC_SIZE,
3150 + .priv_size = sizeof(struct queue_entry_priv_pci),
3151 +};
3152 +
3153 +static const struct data_queue_desc rt2800pci_queue_bcn = {
3154 + .entry_num = 8 * BEACON_ENTRIES,
3155 + .data_size = 0, /* No DMA required for beacons */
3156 + .desc_size = TXWI_DESC_SIZE,
3157 + .priv_size = sizeof(struct queue_entry_priv_pci),
3158 +};
3159 +
3160 +static const struct rt2x00_ops rt2800pci_ops = {
3161 + .name = KBUILD_MODNAME,
3162 + .max_sta_intf = 1,
3163 + .max_ap_intf = 8,
3164 + .eeprom_size = EEPROM_SIZE,
3165 + .rf_size = RF_SIZE,
3166 + .tx_queues = NUM_TX_QUEUES,
3167 + .rx = &rt2800pci_queue_rx,
3168 + .tx = &rt2800pci_queue_tx,
3169 + .bcn = &rt2800pci_queue_bcn,
3170 + .lib = &rt2800pci_rt2x00_ops,
3171 + .hw = &rt2800pci_mac80211_ops,
3172 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
3173 + .debugfs = &rt2800pci_rt2x00debug,
3174 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3175 +};
3176 +
3177 +/*
3178 + * RT2800pci module information.
3179 + */
3180 +static struct pci_device_id rt2800pci_device_table[] = {
3181 + /* Edimax */
3182 + { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
3183 + { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
3184 + { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
3185 + { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
3186 + { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
3187 + { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
3188 + { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
3189 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
3190 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
3191 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
3192 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
3193 + { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
3194 + { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
3195 + { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
3196 + { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
3197 + { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
3198 + { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
3199 + /* Awt */
3200 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
3201 + { 0, }
3202 +};
3203 +
3204 +MODULE_AUTHOR(DRV_PROJECT);
3205 +MODULE_VERSION(DRV_VERSION);
3206 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
3207 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
3208 +#ifdef CONFIG_RT2800PCI_PCI
3209 +MODULE_FIRMWARE(FIRMWARE_RT2860);
3210 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
3211 +#endif /* CONFIG_RT2800PCI_PCI */
3212 +MODULE_LICENSE("GPL");
3213 +
3214 +#ifdef CONFIG_RT2800PCI_WISOC
3215 +#if defined(CONFIG_RALINK_RT288X)
3216 +__rt2x00soc_probe(RT2880, &rt2800pci_ops);
3217 +#elif defined(CONFIG_RALINK_RT305X)
3218 +__rt2x00soc_probe(RT3052, &rt2800pci_ops);
3219 +#endif
3220 +
3221 +static struct platform_driver rt2800soc_driver = {
3222 + .driver = {
3223 + .name = "rt2800_wmac",
3224 + .owner = THIS_MODULE,
3225 + .mod_name = KBUILD_MODNAME,
3226 + },
3227 + .probe = __rt2x00soc_probe,
3228 + .remove = __devexit_p(rt2x00soc_remove),
3229 + .suspend = rt2x00soc_suspend,
3230 + .resume = rt2x00soc_resume,
3231 +};
3232 +#endif /* CONFIG_RT2800PCI_WISOC */
3233 +
3234 +#ifdef CONFIG_RT2800PCI_PCI
3235 +static struct pci_driver rt2800pci_driver = {
3236 + .name = KBUILD_MODNAME,
3237 + .id_table = rt2800pci_device_table,
3238 + .probe = rt2x00pci_probe,
3239 + .remove = __devexit_p(rt2x00pci_remove),
3240 + .suspend = rt2x00pci_suspend,
3241 + .resume = rt2x00pci_resume,
3242 +};
3243 +#endif /* CONFIG_RT2800PCI_PCI */
3244 +
3245 +static int __init rt2800pci_init(void)
3246 +{
3247 + int ret = 0;
3248 +
3249 +#ifdef CONFIG_RT2800PCI_WISOC
3250 + ret = platform_driver_register(&rt2800soc_driver);
3251 + if (ret)
3252 + return ret;
3253 +#endif
3254 +#ifdef CONFIG_RT2800PCI_PCI
3255 + ret = pci_register_driver(&rt2800pci_driver);
3256 + if (ret) {
3257 +#ifdef CONFIG_RT2800PCI_WISOC
3258 + platform_driver_unregister(&rt2800soc_driver);
3259 +#endif
3260 + return ret;
3261 + }
3262 +#endif
3263 +
3264 + return ret;
3265 +}
3266 +
3267 +static void __exit rt2800pci_exit(void)
3268 +{
3269 +#ifdef CONFIG_RT2800PCI_PCI
3270 + pci_unregister_driver(&rt2800pci_driver);
3271 +#endif
3272 +#ifdef CONFIG_RT2800PCI_WISOC
3273 + platform_driver_unregister(&rt2800soc_driver);
3274 +#endif
3275 +}
3276 +
3277 +module_init(rt2800pci_init);
3278 +module_exit(rt2800pci_exit);
3279 --- /dev/null
3280 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
3281 @@ -0,0 +1,1929 @@
3282 +/*
3283 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3284 + <http://rt2x00.serialmonkey.com>
3285 +
3286 + This program is free software; you can redistribute it and/or modify
3287 + it under the terms of the GNU General Public License as published by
3288 + the Free Software Foundation; either version 2 of the License, or
3289 + (at your option) any later version.
3290 +
3291 + This program is distributed in the hope that it will be useful,
3292 + but WITHOUT ANY WARRANTY; without even the implied warranty of
3293 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3294 + GNU General Public License for more details.
3295 +
3296 + You should have received a copy of the GNU General Public License
3297 + along with this program; if not, write to the
3298 + Free Software Foundation, Inc.,
3299 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3300 + */
3301 +
3302 +/*
3303 + Module: rt2800pci
3304 + Abstract: Data structures and registers for the rt2800pci module.
3305 + Supported chipsets: RT2800E & RT2800ED.
3306 + */
3307 +
3308 +#ifndef RT2800PCI_H
3309 +#define RT2800PCI_H
3310 +
3311 +/*
3312 + * RF chip defines.
3313 + *
3314 + * RF2820 2.4G 2T3R
3315 + * RF2850 2.4G/5G 2T3R
3316 + * RF2720 2.4G 1T2R
3317 + * RF2750 2.4G/5G 1T2R
3318 + * RF3020 2.4G 1T1R
3319 + * RF2020 2.4G B/G
3320 + * RF3021 2.4G 1T2R
3321 + * RF3022 2.4G 2T2R
3322 + */
3323 +#define RF2820 0x0001
3324 +#define RF2850 0x0002
3325 +#define RF2720 0x0003
3326 +#define RF2750 0x0004
3327 +#define RF3020 0x0005
3328 +#define RF2020 0x0006
3329 +#define RF3021 0x0007
3330 +#define RF3022 0x0008
3331 +
3332 +/*
3333 + * RT2860 version
3334 + */
3335 +#define RT2860C_VERSION 0x28600100
3336 +#define RT2860D_VERSION 0x28600101
3337 +#define RT2880E_VERSION 0x28720200
3338 +#define RT2883_VERSION 0x28830300
3339 +#define RT3070_VERSION 0x30700200
3340 +
3341 +/*
3342 + * Signal information.
3343 + * Defaul offset is required for RSSI <-> dBm conversion.
3344 + */
3345 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
3346 +
3347 +/*
3348 + * Register layout information.
3349 + */
3350 +#define CSR_REG_BASE 0x1000
3351 +#define CSR_REG_SIZE 0x0800
3352 +#define EEPROM_BASE 0x0000
3353 +#define EEPROM_SIZE 0x0110
3354 +#define BBP_BASE 0x0000
3355 +#define BBP_SIZE 0x0080
3356 +#define RF_BASE 0x0004
3357 +#define RF_SIZE 0x0010
3358 +
3359 +/*
3360 + * Number of TX queues.
3361 + */
3362 +#define NUM_TX_QUEUES 4
3363 +
3364 +/*
3365 + * PCI registers.
3366 + */
3367 +
3368 +/*
3369 + * E2PROM_CSR: EEPROM control register.
3370 + * RELOAD: Write 1 to reload eeprom content.
3371 + * TYPE: 0: 93c46, 1:93c66.
3372 + * LOAD_STATUS: 1:loading, 0:done.
3373 + */
3374 +#define E2PROM_CSR 0x0004
3375 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
3376 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
3377 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
3378 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
3379 +#define E2PROM_CSR_TYPE FIELD32(0x00000030)
3380 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
3381 +#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
3382 +
3383 +/*
3384 + * HOST-MCU shared memory
3385 + */
3386 +#define HOST_CMD_CSR 0x0404
3387 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
3388 +
3389 +/*
3390 + * INT_SOURCE_CSR: Interrupt source register.
3391 + * Write one to clear corresponding bit.
3392 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
3393 + */
3394 +#define INT_SOURCE_CSR 0x0200
3395 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
3396 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
3397 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
3398 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3399 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3400 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3401 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3402 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3403 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3404 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
3405 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
3406 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
3407 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
3408 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3409 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3410 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
3411 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
3412 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
3413 +
3414 +/*
3415 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
3416 + */
3417 +#define INT_MASK_CSR 0x0204
3418 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
3419 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
3420 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
3421 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
3422 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
3423 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
3424 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
3425 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
3426 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
3427 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
3428 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
3429 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
3430 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
3431 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
3432 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
3433 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
3434 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
3435 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
3436 +
3437 +/*
3438 + * WPDMA_GLO_CFG
3439 + */
3440 +#define WPDMA_GLO_CFG 0x0208
3441 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
3442 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
3443 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
3444 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
3445 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
3446 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
3447 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
3448 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
3449 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
3450 +
3451 +/*
3452 + * WPDMA_RST_IDX
3453 + */
3454 +#define WPDMA_RST_IDX 0x020c
3455 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
3456 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
3457 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
3458 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
3459 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
3460 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
3461 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
3462 +
3463 +/*
3464 + * DELAY_INT_CFG
3465 + */
3466 +#define DELAY_INT_CFG 0x0210
3467 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
3468 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
3469 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
3470 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
3471 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
3472 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
3473 +
3474 +/*
3475 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
3476 + * AIFSN0: AC_BE
3477 + * AIFSN1: AC_BK
3478 + * AIFSN1: AC_VI
3479 + * AIFSN1: AC_VO
3480 + */
3481 +#define WMM_AIFSN_CFG 0x0214
3482 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3483 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3484 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3485 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3486 +
3487 +/*
3488 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3489 + * CWMIN0: AC_BE
3490 + * CWMIN1: AC_BK
3491 + * CWMIN1: AC_VI
3492 + * CWMIN1: AC_VO
3493 + */
3494 +#define WMM_CWMIN_CFG 0x0218
3495 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3496 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3497 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3498 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3499 +
3500 +/*
3501 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3502 + * CWMAX0: AC_BE
3503 + * CWMAX1: AC_BK
3504 + * CWMAX1: AC_VI
3505 + * CWMAX1: AC_VO
3506 + */
3507 +#define WMM_CWMAX_CFG 0x021c
3508 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3509 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3510 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3511 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3512 +
3513 +/*
3514 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3515 + * AC0TXOP: AC_BK in unit of 32us
3516 + * AC1TXOP: AC_BE in unit of 32us
3517 + */
3518 +#define WMM_TXOP0_CFG 0x0220
3519 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3520 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3521 +
3522 +/*
3523 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3524 + * AC2TXOP: AC_VI in unit of 32us
3525 + * AC3TXOP: AC_VO in unit of 32us
3526 + */
3527 +#define WMM_TXOP1_CFG 0x0224
3528 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3529 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3530 +
3531 +/*
3532 + * GPIO_CTRL_CFG:
3533 + */
3534 +#define GPIO_CTRL_CFG 0x0228
3535 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3536 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3537 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3538 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3539 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3540 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3541 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3542 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3543 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3544 +
3545 +/*
3546 + * MCU_CMD_CFG
3547 + */
3548 +#define MCU_CMD_CFG 0x022c
3549 +
3550 +/*
3551 + * AC_BK register offsets
3552 + */
3553 +#define TX_BASE_PTR0 0x0230
3554 +#define TX_MAX_CNT0 0x0234
3555 +#define TX_CTX_IDX0 0x0238
3556 +#define TX_DTX_IDX0 0x023c
3557 +
3558 +/*
3559 + * AC_BE register offsets
3560 + */
3561 +#define TX_BASE_PTR1 0x0240
3562 +#define TX_MAX_CNT1 0x0244
3563 +#define TX_CTX_IDX1 0x0248
3564 +#define TX_DTX_IDX1 0x024c
3565 +
3566 +/*
3567 + * AC_VI register offsets
3568 + */
3569 +#define TX_BASE_PTR2 0x0250
3570 +#define TX_MAX_CNT2 0x0254
3571 +#define TX_CTX_IDX2 0x0258
3572 +#define TX_DTX_IDX2 0x025c
3573 +
3574 +/*
3575 + * AC_VO register offsets
3576 + */
3577 +#define TX_BASE_PTR3 0x0260
3578 +#define TX_MAX_CNT3 0x0264
3579 +#define TX_CTX_IDX3 0x0268
3580 +#define TX_DTX_IDX3 0x026c
3581 +
3582 +/*
3583 + * HCCA register offsets
3584 + */
3585 +#define TX_BASE_PTR4 0x0270
3586 +#define TX_MAX_CNT4 0x0274
3587 +#define TX_CTX_IDX4 0x0278
3588 +#define TX_DTX_IDX4 0x027c
3589 +
3590 +/*
3591 + * MGMT register offsets
3592 + */
3593 +#define TX_BASE_PTR5 0x0280
3594 +#define TX_MAX_CNT5 0x0284
3595 +#define TX_CTX_IDX5 0x0288
3596 +#define TX_DTX_IDX5 0x028c
3597 +
3598 +/*
3599 + * Queue register offset macros
3600 + */
3601 +#define TX_QUEUE_REG_OFFSET 0x10
3602 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3603 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3604 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3605 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3606 +
3607 +/*
3608 + * RX register offsets
3609 + */
3610 +#define RX_BASE_PTR 0x0290
3611 +#define RX_MAX_CNT 0x0294
3612 +#define RX_CRX_IDX 0x0298
3613 +#define RX_DRX_IDX 0x029c
3614 +
3615 +/*
3616 + * PBF_SYS_CTRL
3617 + * HOST_RAM_WRITE: enable Host program ram write selection
3618 + */
3619 +#define PBF_SYS_CTRL 0x0400
3620 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3621 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3622 +
3623 +/*
3624 + * PBF registers
3625 + * Most are for debug. Driver doesn't touch PBF register.
3626 + */
3627 +#define PBF_CFG 0x0408
3628 +#define PBF_MAX_PCNT 0x040c
3629 +#define PBF_CTRL 0x0410
3630 +#define PBF_INT_STA 0x0414
3631 +#define PBF_INT_ENA 0x0418
3632 +
3633 +/*
3634 + * BCN_OFFSET0:
3635 + */
3636 +#define BCN_OFFSET0 0x042c
3637 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3638 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3639 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3640 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3641 +
3642 +/*
3643 + * BCN_OFFSET1:
3644 + */
3645 +#define BCN_OFFSET1 0x0430
3646 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3647 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3648 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3649 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3650 +
3651 +/*
3652 + * PBF registers
3653 + * Most are for debug. Driver doesn't touch PBF register.
3654 + */
3655 +#define TXRXQ_PCNT 0x0438
3656 +#define PBF_DBG 0x043c
3657 +
3658 +/*
3659 + * RF registers
3660 + */
3661 +#define RF_CSR_CFG 0x0500
3662 +#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
3663 +#define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
3664 +#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
3665 +#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
3666 +
3667 +/*
3668 + * MAC Control/Status Registers(CSR).
3669 + * Some values are set in TU, whereas 1 TU == 1024 us.
3670 + */
3671 +
3672 +/*
3673 + * MAC_CSR0: ASIC revision number.
3674 + * ASIC_REV: 0
3675 + * ASIC_VER: 2860
3676 + */
3677 +#define MAC_CSR0 0x1000
3678 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3679 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3680 +
3681 +/*
3682 + * MAC_SYS_CTRL:
3683 + */
3684 +#define MAC_SYS_CTRL 0x1004
3685 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3686 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3687 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3688 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3689 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3690 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3691 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3692 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3693 +
3694 +/*
3695 + * MAC_ADDR_DW0: STA MAC register 0
3696 + */
3697 +#define MAC_ADDR_DW0 0x1008
3698 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3699 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3700 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3701 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3702 +
3703 +/*
3704 + * MAC_ADDR_DW1: STA MAC register 1
3705 + * UNICAST_TO_ME_MASK:
3706 + * Used to mask off bits from byte 5 of the MAC address
3707 + * to determine the UNICAST_TO_ME bit for RX frames.
3708 + * The full mask is complemented by BSS_ID_MASK:
3709 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3710 + */
3711 +#define MAC_ADDR_DW1 0x100c
3712 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3713 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3714 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3715 +
3716 +/*
3717 + * MAC_BSSID_DW0: BSSID register 0
3718 + */
3719 +#define MAC_BSSID_DW0 0x1010
3720 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3721 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3722 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3723 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3724 +
3725 +/*
3726 + * MAC_BSSID_DW1: BSSID register 1
3727 + * BSS_ID_MASK:
3728 + * 0: 1-BSSID mode (BSS index = 0)
3729 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3730 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3731 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3732 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3733 + * BSSID. This will make sure that those bits will be ignored
3734 + * when determining the MY_BSS of RX frames.
3735 + */
3736 +#define MAC_BSSID_DW1 0x1014
3737 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3738 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3739 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3740 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3741 +
3742 +/*
3743 + * MAX_LEN_CFG: Maximum frame length register.
3744 + * MAX_MPDU: rt2860b max 16k bytes
3745 + * MAX_PSDU: Maximum PSDU length
3746 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3747 + */
3748 +#define MAX_LEN_CFG 0x1018
3749 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3750 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3751 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3752 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3753 +
3754 +/*
3755 + * BBP_CSR_CFG: BBP serial control register
3756 + * VALUE: Register value to program into BBP
3757 + * REG_NUM: Selected BBP register
3758 + * READ_CONTROL: 0 write BBP, 1 read BBP
3759 + * BUSY: ASIC is busy executing BBP commands
3760 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3761 + * BBP_RW_MODE: 0 serial, 1 paralell
3762 + */
3763 +#define BBP_CSR_CFG 0x101c
3764 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3765 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3766 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3767 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3768 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3769 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3770 +
3771 +/*
3772 + * RF_CSR_CFG0: RF control register
3773 + * REGID_AND_VALUE: Register value to program into RF
3774 + * BITWIDTH: Selected RF register
3775 + * STANDBYMODE: 0 high when standby, 1 low when standby
3776 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3777 + * BUSY: ASIC is busy executing RF commands
3778 + */
3779 +#define RF_CSR_CFG0 0x1020
3780 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3781 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3782 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3783 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3784 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3785 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3786 +
3787 +/*
3788 + * RF_CSR_CFG1: RF control register
3789 + * REGID_AND_VALUE: Register value to program into RF
3790 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3791 + * 0: 3 system clock cycle (37.5usec)
3792 + * 1: 5 system clock cycle (62.5usec)
3793 + */
3794 +#define RF_CSR_CFG1 0x1024
3795 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3796 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3797 +
3798 +/*
3799 + * RF_CSR_CFG2: RF control register
3800 + * VALUE: Register value to program into RF
3801 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3802 + * 0: 3 system clock cycle (37.5usec)
3803 + * 1: 5 system clock cycle (62.5usec)
3804 + */
3805 +#define RF_CSR_CFG2 0x1028
3806 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3807 +
3808 +/*
3809 + * LED_CFG: LED control
3810 + * color LED's:
3811 + * 0: off
3812 + * 1: blinking upon TX2
3813 + * 2: periodic slow blinking
3814 + * 3: always on
3815 + * LED polarity:
3816 + * 0: active low
3817 + * 1: active high
3818 + */
3819 +#define LED_CFG 0x102c
3820 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3821 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3822 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3823 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3824 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3825 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3826 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3827 +
3828 +/*
3829 + * XIFS_TIME_CFG: MAC timing
3830 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3831 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3832 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3833 + * when MAC doesn't reference BBP signal BBRXEND
3834 + * EIFS: unit 1us
3835 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3836 + *
3837 + */
3838 +#define XIFS_TIME_CFG 0x1100
3839 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3840 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3841 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3842 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3843 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3844 +
3845 +/*
3846 + * BKOFF_SLOT_CFG:
3847 + */
3848 +#define BKOFF_SLOT_CFG 0x1104
3849 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3850 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3851 +
3852 +/*
3853 + * NAV_TIME_CFG:
3854 + */
3855 +#define NAV_TIME_CFG 0x1108
3856 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3857 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3858 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3859 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3860 +
3861 +/*
3862 + * CH_TIME_CFG: count as channel busy
3863 + */
3864 +#define CH_TIME_CFG 0x110c
3865 +
3866 +/*
3867 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3868 + */
3869 +#define PBF_LIFE_TIMER 0x1110
3870 +
3871 +/*
3872 + * BCN_TIME_CFG:
3873 + * BEACON_INTERVAL: in unit of 1/16 TU
3874 + * TSF_TICKING: Enable TSF auto counting
3875 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3876 + * BEACON_GEN: Enable beacon generator
3877 + */
3878 +#define BCN_TIME_CFG 0x1114
3879 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3880 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3881 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3882 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3883 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3884 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3885 +
3886 +/*
3887 + * TBTT_SYNC_CFG:
3888 + */
3889 +#define TBTT_SYNC_CFG 0x1118
3890 +
3891 +/*
3892 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3893 + */
3894 +#define TSF_TIMER_DW0 0x111c
3895 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3896 +
3897 +/*
3898 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3899 + */
3900 +#define TSF_TIMER_DW1 0x1120
3901 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3902 +
3903 +/*
3904 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3905 + */
3906 +#define TBTT_TIMER 0x1124
3907 +
3908 +/*
3909 + * INT_TIMER_CFG:
3910 + */
3911 +#define INT_TIMER_CFG 0x1128
3912 +
3913 +/*
3914 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3915 + */
3916 +#define INT_TIMER_EN 0x112c
3917 +
3918 +/*
3919 + * CH_IDLE_STA: channel idle time
3920 + */
3921 +#define CH_IDLE_STA 0x1130
3922 +
3923 +/*
3924 + * CH_BUSY_STA: channel busy time
3925 + */
3926 +#define CH_BUSY_STA 0x1134
3927 +
3928 +/*
3929 + * MAC_STATUS_CFG:
3930 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3931 + * if 1 or higher one of the 2 registers is busy.
3932 + */
3933 +#define MAC_STATUS_CFG 0x1200
3934 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3935 +
3936 +/*
3937 + * PWR_PIN_CFG:
3938 + */
3939 +#define PWR_PIN_CFG 0x1204
3940 +
3941 +/*
3942 + * AUTOWAKEUP_CFG: Manual power control / status register
3943 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3944 + * AUTOWAKE: 0:sleep, 1:awake
3945 + */
3946 +#define AUTOWAKEUP_CFG 0x1208
3947 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3948 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3949 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3950 +
3951 +/*
3952 + * EDCA_AC0_CFG:
3953 + */
3954 +#define EDCA_AC0_CFG 0x1300
3955 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3956 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3957 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3958 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3959 +
3960 +/*
3961 + * EDCA_AC1_CFG:
3962 + */
3963 +#define EDCA_AC1_CFG 0x1304
3964 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3965 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3966 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3967 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3968 +
3969 +/*
3970 + * EDCA_AC2_CFG:
3971 + */
3972 +#define EDCA_AC2_CFG 0x1308
3973 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3974 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3975 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3976 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3977 +
3978 +/*
3979 + * EDCA_AC3_CFG:
3980 + */
3981 +#define EDCA_AC3_CFG 0x130c
3982 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3983 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3984 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3985 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3986 +
3987 +/*
3988 + * EDCA_TID_AC_MAP:
3989 + */
3990 +#define EDCA_TID_AC_MAP 0x1310
3991 +
3992 +/*
3993 + * TX_PWR_CFG_0:
3994 + */
3995 +#define TX_PWR_CFG_0 0x1314
3996 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3997 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3998 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3999 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
4000 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
4001 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
4002 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
4003 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
4004 +
4005 +/*
4006 + * TX_PWR_CFG_1:
4007 + */
4008 +#define TX_PWR_CFG_1 0x1318
4009 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
4010 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
4011 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
4012 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
4013 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
4014 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
4015 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
4016 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
4017 +
4018 +/*
4019 + * TX_PWR_CFG_2:
4020 + */
4021 +#define TX_PWR_CFG_2 0x131c
4022 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
4023 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
4024 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
4025 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
4026 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
4027 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
4028 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
4029 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
4030 +
4031 +/*
4032 + * TX_PWR_CFG_3:
4033 + */
4034 +#define TX_PWR_CFG_3 0x1320
4035 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
4036 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
4037 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
4038 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
4039 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
4040 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
4041 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
4042 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
4043 +
4044 +/*
4045 + * TX_PWR_CFG_4:
4046 + */
4047 +#define TX_PWR_CFG_4 0x1324
4048 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
4049 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
4050 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
4051 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
4052 +
4053 +/*
4054 + * TX_PIN_CFG:
4055 + */
4056 +#define TX_PIN_CFG 0x1328
4057 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
4058 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
4059 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
4060 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
4061 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
4062 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
4063 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
4064 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
4065 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
4066 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
4067 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
4068 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
4069 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
4070 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
4071 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
4072 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
4073 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
4074 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
4075 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
4076 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
4077 +
4078 +/*
4079 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
4080 + */
4081 +#define TX_BAND_CFG 0x132c
4082 +#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001)
4083 +#define TX_BAND_CFG_A FIELD32(0x00000002)
4084 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
4085 +
4086 +/*
4087 + * TX_SW_CFG0:
4088 + */
4089 +#define TX_SW_CFG0 0x1330
4090 +
4091 +/*
4092 + * TX_SW_CFG1:
4093 + */
4094 +#define TX_SW_CFG1 0x1334
4095 +
4096 +/*
4097 + * TX_SW_CFG2:
4098 + */
4099 +#define TX_SW_CFG2 0x1338
4100 +
4101 +/*
4102 + * TXOP_THRES_CFG:
4103 + */
4104 +#define TXOP_THRES_CFG 0x133c
4105 +
4106 +/*
4107 + * TXOP_CTRL_CFG:
4108 + */
4109 +#define TXOP_CTRL_CFG 0x1340
4110 +
4111 +/*
4112 + * TX_RTS_CFG:
4113 + * RTS_THRES: unit:byte
4114 + * RTS_FBK_EN: enable rts rate fallback
4115 + */
4116 +#define TX_RTS_CFG 0x1344
4117 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
4118 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
4119 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
4120 +
4121 +/*
4122 + * TX_TIMEOUT_CFG:
4123 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
4124 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
4125 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
4126 + * it is recommended that:
4127 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
4128 + */
4129 +#define TX_TIMEOUT_CFG 0x1348
4130 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
4131 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
4132 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
4133 +
4134 +/*
4135 + * TX_RTY_CFG:
4136 + * SHORT_RTY_LIMIT: short retry limit
4137 + * LONG_RTY_LIMIT: long retry limit
4138 + * LONG_RTY_THRE: Long retry threshoold
4139 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
4140 + * 0:expired by retry limit, 1: expired by mpdu life timer
4141 + * AGG_RTY_MODE: Aggregate MPDU retry mode
4142 + * 0:expired by retry limit, 1: expired by mpdu life timer
4143 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
4144 + */
4145 +#define TX_RTY_CFG 0x134c
4146 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
4147 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
4148 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
4149 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
4150 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
4151 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
4152 +
4153 +/*
4154 + * TX_LINK_CFG:
4155 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
4156 + * MFB_ENABLE: TX apply remote MFB 1:enable
4157 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
4158 + * 0: not apply remote remote unsolicit (MFS=7)
4159 + * TX_MRQ_EN: MCS request TX enable
4160 + * TX_RDG_EN: RDG TX enable
4161 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
4162 + * REMOTE_MFB: remote MCS feedback
4163 + * REMOTE_MFS: remote MCS feedback sequence number
4164 + */
4165 +#define TX_LINK_CFG 0x1350
4166 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
4167 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
4168 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
4169 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
4170 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
4171 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
4172 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
4173 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
4174 +
4175 +/*
4176 + * HT_FBK_CFG0:
4177 + */
4178 +#define HT_FBK_CFG0 0x1354
4179 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
4180 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
4181 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
4182 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
4183 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
4184 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
4185 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
4186 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
4187 +
4188 +/*
4189 + * HT_FBK_CFG1:
4190 + */
4191 +#define HT_FBK_CFG1 0x1358
4192 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
4193 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
4194 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
4195 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
4196 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
4197 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
4198 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
4199 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
4200 +
4201 +/*
4202 + * LG_FBK_CFG0:
4203 + */
4204 +#define LG_FBK_CFG0 0x135c
4205 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
4206 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
4207 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
4208 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
4209 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
4210 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
4211 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
4212 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
4213 +
4214 +/*
4215 + * LG_FBK_CFG1:
4216 + */
4217 +#define LG_FBK_CFG1 0x1360
4218 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
4219 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
4220 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
4221 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
4222 +
4223 +/*
4224 + * CCK_PROT_CFG: CCK Protection
4225 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
4226 + * PROTECT_CTRL: Protection control frame type for CCK TX
4227 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
4228 + * PROTECT_NAV: TXOP protection type for CCK TX
4229 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
4230 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
4231 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
4232 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
4233 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
4234 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
4235 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
4236 + * RTS_TH_EN: RTS threshold enable on CCK TX
4237 + */
4238 +#define CCK_PROT_CFG 0x1364
4239 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4240 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4241 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4242 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4243 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4244 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4245 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4246 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4247 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4248 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4249 +
4250 +/*
4251 + * OFDM_PROT_CFG: OFDM Protection
4252 + */
4253 +#define OFDM_PROT_CFG 0x1368
4254 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4255 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4256 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4257 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4258 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4259 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4260 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4261 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4262 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4263 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4264 +
4265 +/*
4266 + * MM20_PROT_CFG: MM20 Protection
4267 + */
4268 +#define MM20_PROT_CFG 0x136c
4269 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4270 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4271 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4272 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4273 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4274 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4275 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4276 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4277 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4278 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4279 +
4280 +/*
4281 + * MM40_PROT_CFG: MM40 Protection
4282 + */
4283 +#define MM40_PROT_CFG 0x1370
4284 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4285 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4286 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4287 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4288 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4289 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4290 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4291 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4292 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4293 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4294 +
4295 +/*
4296 + * GF20_PROT_CFG: GF20 Protection
4297 + */
4298 +#define GF20_PROT_CFG 0x1374
4299 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4300 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4301 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4302 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4303 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4304 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4305 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4306 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4307 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4308 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4309 +
4310 +/*
4311 + * GF40_PROT_CFG: GF40 Protection
4312 + */
4313 +#define GF40_PROT_CFG 0x1378
4314 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
4315 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
4316 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
4317 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
4318 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
4319 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
4320 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
4321 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
4322 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
4323 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
4324 +
4325 +/*
4326 + * EXP_CTS_TIME:
4327 + */
4328 +#define EXP_CTS_TIME 0x137c
4329 +
4330 +/*
4331 + * EXP_ACK_TIME:
4332 + */
4333 +#define EXP_ACK_TIME 0x1380
4334 +
4335 +/*
4336 + * RX_FILTER_CFG: RX configuration register.
4337 + */
4338 +#define RX_FILTER_CFG 0x1400
4339 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
4340 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
4341 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
4342 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
4343 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
4344 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
4345 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
4346 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
4347 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
4348 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
4349 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
4350 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
4351 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
4352 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
4353 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
4354 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
4355 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
4356 +
4357 +/*
4358 + * AUTO_RSP_CFG:
4359 + * AUTORESPONDER: 0: disable, 1: enable
4360 + * BAC_ACK_POLICY: 0:long, 1:short preamble
4361 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
4362 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
4363 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
4364 + * DUAL_CTS_EN: Power bit value in control frame
4365 + * ACK_CTS_PSM_BIT:Power bit value in control frame
4366 + */
4367 +#define AUTO_RSP_CFG 0x1404
4368 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
4369 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
4370 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
4371 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
4372 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
4373 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
4374 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
4375 +
4376 +/*
4377 + * LEGACY_BASIC_RATE:
4378 + */
4379 +#define LEGACY_BASIC_RATE 0x1408
4380 +
4381 +/*
4382 + * HT_BASIC_RATE:
4383 + */
4384 +#define HT_BASIC_RATE 0x140c
4385 +
4386 +/*
4387 + * HT_CTRL_CFG:
4388 + */
4389 +#define HT_CTRL_CFG 0x1410
4390 +
4391 +/*
4392 + * SIFS_COST_CFG:
4393 + */
4394 +#define SIFS_COST_CFG 0x1414
4395 +
4396 +/*
4397 + * RX_PARSER_CFG:
4398 + * Set NAV for all received frames
4399 + */
4400 +#define RX_PARSER_CFG 0x1418
4401 +
4402 +/*
4403 + * TX_SEC_CNT0:
4404 + */
4405 +#define TX_SEC_CNT0 0x1500
4406 +
4407 +/*
4408 + * RX_SEC_CNT0:
4409 + */
4410 +#define RX_SEC_CNT0 0x1504
4411 +
4412 +/*
4413 + * CCMP_FC_MUTE:
4414 + */
4415 +#define CCMP_FC_MUTE 0x1508
4416 +
4417 +/*
4418 + * TXOP_HLDR_ADDR0:
4419 + */
4420 +#define TXOP_HLDR_ADDR0 0x1600
4421 +
4422 +/*
4423 + * TXOP_HLDR_ADDR1:
4424 + */
4425 +#define TXOP_HLDR_ADDR1 0x1604
4426 +
4427 +/*
4428 + * TXOP_HLDR_ET:
4429 + */
4430 +#define TXOP_HLDR_ET 0x1608
4431 +
4432 +/*
4433 + * QOS_CFPOLL_RA_DW0:
4434 + */
4435 +#define QOS_CFPOLL_RA_DW0 0x160c
4436 +
4437 +/*
4438 + * QOS_CFPOLL_RA_DW1:
4439 + */
4440 +#define QOS_CFPOLL_RA_DW1 0x1610
4441 +
4442 +/*
4443 + * QOS_CFPOLL_QC:
4444 + */
4445 +#define QOS_CFPOLL_QC 0x1614
4446 +
4447 +/*
4448 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
4449 + */
4450 +#define RX_STA_CNT0 0x1700
4451 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
4452 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
4453 +
4454 +/*
4455 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
4456 + */
4457 +#define RX_STA_CNT1 0x1704
4458 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
4459 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
4460 +
4461 +/*
4462 + * RX_STA_CNT2:
4463 + */
4464 +#define RX_STA_CNT2 0x1708
4465 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
4466 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
4467 +
4468 +/*
4469 + * TX_STA_CNT0: TX Beacon count
4470 + */
4471 +#define TX_STA_CNT0 0x170c
4472 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
4473 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
4474 +
4475 +/*
4476 + * TX_STA_CNT1: TX tx count
4477 + */
4478 +#define TX_STA_CNT1 0x1710
4479 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
4480 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
4481 +
4482 +/*
4483 + * TX_STA_CNT2: TX tx count
4484 + */
4485 +#define TX_STA_CNT2 0x1714
4486 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
4487 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
4488 +
4489 +/*
4490 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4491 + */
4492 +#define TX_STA_FIFO 0x1718
4493 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
4494 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
4495 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
4496 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4497 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4498 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4499 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4500 +
4501 +/*
4502 + * TX_AGG_CNT: Debug counter
4503 + */
4504 +#define TX_AGG_CNT 0x171c
4505 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4506 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4507 +
4508 +/*
4509 + * TX_AGG_CNT0:
4510 + */
4511 +#define TX_AGG_CNT0 0x1720
4512 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4513 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4514 +
4515 +/*
4516 + * TX_AGG_CNT1:
4517 + */
4518 +#define TX_AGG_CNT1 0x1724
4519 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4520 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4521 +
4522 +/*
4523 + * TX_AGG_CNT2:
4524 + */
4525 +#define TX_AGG_CNT2 0x1728
4526 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4527 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4528 +
4529 +/*
4530 + * TX_AGG_CNT3:
4531 + */
4532 +#define TX_AGG_CNT3 0x172c
4533 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4534 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4535 +
4536 +/*
4537 + * TX_AGG_CNT4:
4538 + */
4539 +#define TX_AGG_CNT4 0x1730
4540 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4541 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4542 +
4543 +/*
4544 + * TX_AGG_CNT5:
4545 + */
4546 +#define TX_AGG_CNT5 0x1734
4547 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4548 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4549 +
4550 +/*
4551 + * TX_AGG_CNT6:
4552 + */
4553 +#define TX_AGG_CNT6 0x1738
4554 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4555 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4556 +
4557 +/*
4558 + * TX_AGG_CNT7:
4559 + */
4560 +#define TX_AGG_CNT7 0x173c
4561 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4562 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4563 +
4564 +/*
4565 + * MPDU_DENSITY_CNT:
4566 + * TX_ZERO_DEL: TX zero length delimiter count
4567 + * RX_ZERO_DEL: RX zero length delimiter count
4568 + */
4569 +#define MPDU_DENSITY_CNT 0x1740
4570 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4571 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4572 +
4573 +/*
4574 + * Security key table memory.
4575 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4576 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4577 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4578 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4579 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4580 + * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
4581 + */
4582 +#define MAC_WCID_BASE 0x1800
4583 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4584 +#define MAC_IVEIV_TABLE_BASE 0x6000
4585 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4586 +#define SHARED_KEY_TABLE_BASE 0x6c00
4587 +#define SHARED_KEY_MODE_BASE 0x7000
4588 +
4589 +#define MAC_WCID_ENTRY(__idx) \
4590 + ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
4591 +#define PAIRWISE_KEY_ENTRY(__idx) \
4592 + ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4593 +#define MAC_IVEIV_ENTRY(__idx) \
4594 + ( MAC_IVEIV_TABLE_BASE + ((__idx) & sizeof(struct mac_iveiv_entry)) )
4595 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4596 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4597 +#define SHARED_KEY_ENTRY(__idx) \
4598 + ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
4599 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4600 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4601 +
4602 +struct mac_wcid_entry {
4603 + u8 mac[6];
4604 + u8 reserved[2];
4605 +} __attribute__ ((packed));
4606 +
4607 +struct hw_key_entry {
4608 + u8 key[16];
4609 + u8 tx_mic[8];
4610 + u8 rx_mic[8];
4611 +} __attribute__ ((packed));
4612 +
4613 +struct mac_iveiv_entry {
4614 + u8 iv[8];
4615 +} __attribute__ ((packed));
4616 +
4617 +/*
4618 + * MAC_WCID_ATTRIBUTE:
4619 + */
4620 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4621 +#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
4622 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4623 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4624 +
4625 +/*
4626 + * SHARED_KEY_MODE:
4627 + */
4628 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4629 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4630 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4631 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4632 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4633 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4634 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4635 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4636 +
4637 +/*
4638 + * HOST-MCU communication
4639 + */
4640 +
4641 +/*
4642 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4643 + */
4644 +#define H2M_MAILBOX_CSR 0x7010
4645 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4646 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4647 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4648 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4649 +
4650 +/*
4651 + * H2M_MAILBOX_CID:
4652 + */
4653 +#define H2M_MAILBOX_CID 0x7014
4654 +#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
4655 +#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
4656 +#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
4657 +#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
4658 +
4659 +/*
4660 + * H2M_MAILBOX_STATUS:
4661 + */
4662 +#define H2M_MAILBOX_STATUS 0x701c
4663 +
4664 +/*
4665 + * H2M_INT_SRC:
4666 + */
4667 +#define H2M_INT_SRC 0x7024
4668 +
4669 +/*
4670 + * H2M_BBP_AGENT:
4671 + */
4672 +#define H2M_BBP_AGENT 0x7028
4673 +
4674 +/*
4675 + * MCU_LEDCS: LED control for MCU Mailbox.
4676 + */
4677 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4678 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4679 +
4680 +/*
4681 + * HW_CS_CTS_BASE:
4682 + * Carrier-sense CTS frame base address.
4683 + * It's where mac stores carrier-sense frame for carrier-sense function.
4684 + */
4685 +#define HW_CS_CTS_BASE 0x7700
4686 +
4687 +/*
4688 + * HW_DFS_CTS_BASE:
4689 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4690 + */
4691 +#define HW_DFS_CTS_BASE 0x7780
4692 +
4693 +/*
4694 + * TXRX control registers - base address 0x3000
4695 + */
4696 +
4697 +/*
4698 + * TXRX_CSR1:
4699 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4700 + */
4701 +#define TXRX_CSR1 0x77d0
4702 +
4703 +/*
4704 + * HW_DEBUG_SETTING_BASE:
4705 + * since NULL frame won't be that long (256 byte)
4706 + * We steal 16 tail bytes to save debugging settings
4707 + */
4708 +#define HW_DEBUG_SETTING_BASE 0x77f0
4709 +#define HW_DEBUG_SETTING_BASE2 0x7770
4710 +
4711 +/*
4712 + * HW_BEACON_BASE
4713 + * In order to support maximum 8 MBSS and its maximum length
4714 + * is 512 bytes for each beacon
4715 + * Three section discontinue memory segments will be used.
4716 + * 1. The original region for BCN 0~3
4717 + * 2. Extract memory from FCE table for BCN 4~5
4718 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4719 + * It occupied those memory of wcid 238~253 for BCN 6
4720 + * and wcid 222~237 for BCN 7
4721 + *
4722 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4723 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4724 + */
4725 +#define HW_BEACON_BASE0 0x7800
4726 +#define HW_BEACON_BASE1 0x7a00
4727 +#define HW_BEACON_BASE2 0x7c00
4728 +#define HW_BEACON_BASE3 0x7e00
4729 +#define HW_BEACON_BASE4 0x7200
4730 +#define HW_BEACON_BASE5 0x7400
4731 +#define HW_BEACON_BASE6 0x5dc0
4732 +#define HW_BEACON_BASE7 0x5bc0
4733 +
4734 +#define HW_BEACON_OFFSET(__index) \
4735 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4736 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4737 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4738 +
4739 +/*
4740 + * 8051 firmware image.
4741 + */
4742 +#define FIRMWARE_RT2860 "rt2860.bin"
4743 +#define FIRMWARE_IMAGE_BASE 0x2000
4744 +
4745 +/*
4746 + * BBP registers.
4747 + * The wordsize of the BBP is 8 bits.
4748 + */
4749 +
4750 +/*
4751 + * BBP 1: TX Antenna
4752 + */
4753 +#define BBP1_TX_POWER FIELD8(0x07)
4754 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4755 +
4756 +/*
4757 + * BBP 3: RX Antenna
4758 + */
4759 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4760 +#define BBP3_HT40_PLUS FIELD8(0x20)
4761 +
4762 +/*
4763 + * BBP 4: Bandwidth
4764 + */
4765 +#define BBP4_TX_BF FIELD8(0x01)
4766 +#define BBP4_BANDWIDTH FIELD8(0x18)
4767 +
4768 +/*
4769 + * RFCSR registers
4770 + * The wordsize of the RFCSR is 8 bits.
4771 + */
4772 +
4773 +/*
4774 + * RFCSR 6:
4775 + */
4776 +#define RFCSR6_R FIELD8(0x03)
4777 +
4778 +/*
4779 + * RFCSR 7:
4780 + */
4781 +#define RFCSR7_RF_TUNING FIELD8(0x01)
4782 +
4783 +/*
4784 + * RFCSR 12:
4785 + */
4786 +#define RFCSR12_TX_POWER FIELD8(0x1f)
4787 +
4788 +/*
4789 + * RFCSR 22:
4790 + */
4791 +#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
4792 +
4793 +/*
4794 + * RFCSR 23:
4795 + */
4796 +#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
4797 +
4798 +/*
4799 + * RFCSR 30:
4800 + */
4801 +#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
4802 +
4803 +/*
4804 + * RF registers
4805 + */
4806 +
4807 +/*
4808 + * RF 2
4809 + */
4810 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4811 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4812 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4813 +
4814 +/*
4815 + * RF 3
4816 + */
4817 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4818 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4819 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4820 +
4821 +/*
4822 + * RF 4
4823 + */
4824 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4825 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4826 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4827 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4828 +#define RF4_HT40 FIELD32(0x00200000)
4829 +
4830 +/*
4831 + * EEPROM content.
4832 + * The wordsize of the EEPROM is 16 bits.
4833 + */
4834 +
4835 +/*
4836 + * EEPROM Version
4837 + */
4838 +#define EEPROM_VERSION 0x0001
4839 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4840 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4841 +
4842 +/*
4843 + * HW MAC address.
4844 + */
4845 +#define EEPROM_MAC_ADDR_0 0x0002
4846 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4847 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4848 +#define EEPROM_MAC_ADDR_1 0x0003
4849 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4850 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4851 +#define EEPROM_MAC_ADDR_2 0x0004
4852 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4853 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4854 +
4855 +/*
4856 + * EEPROM ANTENNA config
4857 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4858 + * TXPATH: 1: 1T, 2: 2T
4859 + */
4860 +#define EEPROM_ANTENNA 0x001a
4861 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4862 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4863 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4864 +
4865 +/*
4866 + * EEPROM NIC config
4867 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4868 + */
4869 +#define EEPROM_NIC 0x001b
4870 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4871 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4872 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4873 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4874 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4875 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4876 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4877 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4878 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4879 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4880 +
4881 +/*
4882 + * EEPROM frequency
4883 + */
4884 +#define EEPROM_FREQ 0x001d
4885 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4886 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4887 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4888 +
4889 +/*
4890 + * EEPROM LED
4891 + * POLARITY_RDY_G: Polarity RDY_G setting.
4892 + * POLARITY_RDY_A: Polarity RDY_A setting.
4893 + * POLARITY_ACT: Polarity ACT setting.
4894 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4895 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4896 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4897 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4898 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4899 + * LED_MODE: Led mode.
4900 + */
4901 +#define EEPROM_LED1 0x001e
4902 +#define EEPROM_LED2 0x001f
4903 +#define EEPROM_LED3 0x0020
4904 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4905 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4906 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4907 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4908 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4909 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4910 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4911 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4912 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4913 +
4914 +/*
4915 + * EEPROM LNA
4916 + */
4917 +#define EEPROM_LNA 0x0022
4918 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4919 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4920 +
4921 +/*
4922 + * EEPROM RSSI BG offset
4923 + */
4924 +#define EEPROM_RSSI_BG 0x0023
4925 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4926 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4927 +
4928 +/*
4929 + * EEPROM RSSI BG2 offset
4930 + */
4931 +#define EEPROM_RSSI_BG2 0x0024
4932 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4933 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4934 +
4935 +/*
4936 + * EEPROM RSSI A offset
4937 + */
4938 +#define EEPROM_RSSI_A 0x0025
4939 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4940 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4941 +
4942 +/*
4943 + * EEPROM RSSI A2 offset
4944 + */
4945 +#define EEPROM_RSSI_A2 0x0026
4946 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4947 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4948 +
4949 +/*
4950 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4951 + * This is delta in 40MHZ.
4952 + * VALUE: Tx Power dalta value (MAX=4)
4953 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4954 + * TXPOWER: Enable:
4955 + */
4956 +#define EEPROM_TXPOWER_DELTA 0x0028
4957 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4958 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4959 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4960 +
4961 +/*
4962 + * EEPROM TXPOWER 802.11BG
4963 + */
4964 +#define EEPROM_TXPOWER_BG1 0x0029
4965 +#define EEPROM_TXPOWER_BG2 0x0030
4966 +#define EEPROM_TXPOWER_BG_SIZE 7
4967 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4968 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4969 +
4970 +/*
4971 + * EEPROM TXPOWER 802.11A
4972 + */
4973 +#define EEPROM_TXPOWER_A1 0x003c
4974 +#define EEPROM_TXPOWER_A2 0x0053
4975 +#define EEPROM_TXPOWER_A_SIZE 6
4976 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4977 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4978 +
4979 +/*
4980 + * EEPROM TXpower byrate: 20MHZ power
4981 + */
4982 +#define EEPROM_TXPOWER_BYRATE 0x006f
4983 +
4984 +/*
4985 + * EEPROM BBP.
4986 + */
4987 +#define EEPROM_BBP_START 0x0078
4988 +#define EEPROM_BBP_SIZE 16
4989 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4990 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4991 +
4992 +/*
4993 + * MCU mailbox commands.
4994 + */
4995 +#define MCU_SLEEP 0x30
4996 +#define MCU_WAKEUP 0x31
4997 +#define MCU_RADIO_OFF 0x35
4998 +#define MCU_CURRENT 0x36
4999 +#define MCU_LED 0x50
5000 +#define MCU_LED_STRENGTH 0x51
5001 +#define MCU_LED_1 0x52
5002 +#define MCU_LED_2 0x53
5003 +#define MCU_LED_3 0x54
5004 +#define MCU_RADAR 0x60
5005 +#define MCU_BOOT_SIGNAL 0x72
5006 +#define MCU_BBP_SIGNAL 0x80
5007 +#define MCU_POWER_SAVE 0x83
5008 +
5009 +/*
5010 + * MCU mailbox tokens
5011 + */
5012 +#define TOKEN_WAKUP 3
5013 +
5014 +/*
5015 + * DMA descriptor defines.
5016 + */
5017 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
5018 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
5019 +#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
5020 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
5021 +
5022 +/*
5023 + * TX descriptor format for TX, PRIO and Beacon Ring.
5024 + */
5025 +
5026 +/*
5027 + * Word0
5028 + */
5029 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
5030 +
5031 +/*
5032 + * Word1
5033 + */
5034 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
5035 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
5036 +#define TXD_W1_BURST FIELD32(0x00008000)
5037 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
5038 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
5039 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
5040 +
5041 +/*
5042 + * Word2
5043 + */
5044 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
5045 +
5046 +/*
5047 + * Word3
5048 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
5049 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
5050 + * 0:MGMT, 1:HCCA 2:EDCA
5051 + */
5052 +#define TXD_W3_WIV FIELD32(0x01000000)
5053 +#define TXD_W3_QSEL FIELD32(0x06000000)
5054 +#define TXD_W3_TCO FIELD32(0x20000000)
5055 +#define TXD_W3_UCO FIELD32(0x40000000)
5056 +#define TXD_W3_ICO FIELD32(0x80000000)
5057 +
5058 +/*
5059 + * TX WI structure
5060 + */
5061 +
5062 +/*
5063 + * Word0
5064 + * FRAG: 1 To inform TKIP engine this is a fragment.
5065 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
5066 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
5067 + * BW: Channel bandwidth 20MHz or 40 MHz
5068 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
5069 + */
5070 +#define TXWI_W0_FRAG FIELD32(0x00000001)
5071 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
5072 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
5073 +#define TXWI_W0_TS FIELD32(0x00000008)
5074 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
5075 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
5076 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
5077 +#define TXWI_W0_MCS FIELD32(0x007f0000)
5078 +#define TXWI_W0_BW FIELD32(0x00800000)
5079 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
5080 +#define TXWI_W0_STBC FIELD32(0x06000000)
5081 +#define TXWI_W0_IFS FIELD32(0x08000000)
5082 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
5083 +
5084 +/*
5085 + * Word1
5086 + */
5087 +#define TXWI_W1_ACK FIELD32(0x00000001)
5088 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
5089 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
5090 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
5091 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
5092 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
5093 +
5094 +/*
5095 + * Word2
5096 + */
5097 +#define TXWI_W2_IV FIELD32(0xffffffff)
5098 +
5099 +/*
5100 + * Word3
5101 + */
5102 +#define TXWI_W3_EIV FIELD32(0xffffffff)
5103 +
5104 +/*
5105 + * RX descriptor format for RX Ring.
5106 + */
5107 +
5108 +/*
5109 + * Word0
5110 + */
5111 +#define RXD_W0_SDP0 FIELD32(0xffffffff)
5112 +
5113 +/*
5114 + * Word1
5115 + */
5116 +#define RXD_W1_SDL1 FIELD32(0x00003fff)
5117 +#define RXD_W1_SDL0 FIELD32(0x3fff0000)
5118 +#define RXD_W1_LS0 FIELD32(0x40000000)
5119 +#define RXD_W1_DMA_DONE FIELD32(0x80000000)
5120 +
5121 +/*
5122 + * Word2
5123 + */
5124 +#define RXD_W2_SDP1 FIELD32(0xffffffff)
5125 +
5126 +/*
5127 + * Word3
5128 + * AMSDU: RX with 802.3 header, not 802.11 header.
5129 + * DECRYPTED: This frame is being decrypted.
5130 + */
5131 +#define RXD_W3_BA FIELD32(0x00000001)
5132 +#define RXD_W3_DATA FIELD32(0x00000002)
5133 +#define RXD_W3_NULLDATA FIELD32(0x00000004)
5134 +#define RXD_W3_FRAG FIELD32(0x00000008)
5135 +#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
5136 +#define RXD_W3_MULTICAST FIELD32(0x00000020)
5137 +#define RXD_W3_BROADCAST FIELD32(0x00000040)
5138 +#define RXD_W3_MY_BSS FIELD32(0x00000080)
5139 +#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
5140 +#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
5141 +#define RXD_W3_AMSDU FIELD32(0x00000800)
5142 +#define RXD_W3_HTC FIELD32(0x00001000)
5143 +#define RXD_W3_RSSI FIELD32(0x00002000)
5144 +#define RXD_W3_L2PAD FIELD32(0x00004000)
5145 +#define RXD_W3_AMPDU FIELD32(0x00008000)
5146 +#define RXD_W3_DECRYPTED FIELD32(0x00010000)
5147 +#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
5148 +#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
5149 +
5150 +/*
5151 + * RX WI structure
5152 + */
5153 +
5154 +/*
5155 + * Word0
5156 + */
5157 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
5158 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
5159 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
5160 +#define RXWI_W0_UDF FIELD32(0x0000e000)
5161 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
5162 +#define RXWI_W0_TID FIELD32(0xf0000000)
5163 +
5164 +/*
5165 + * Word1
5166 + */
5167 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
5168 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
5169 +#define RXWI_W1_MCS FIELD32(0x007f0000)
5170 +#define RXWI_W1_BW FIELD32(0x00800000)
5171 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
5172 +#define RXWI_W1_STBC FIELD32(0x06000000)
5173 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
5174 +
5175 +/*
5176 + * Word2
5177 + */
5178 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
5179 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
5180 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
5181 +
5182 +/*
5183 + * Word3
5184 + */
5185 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
5186 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
5187 +
5188 +/*
5189 + * Macro's for converting txpower from EEPROM to mac80211 value
5190 + * and from mac80211 value to register value.
5191 + */
5192 +#define MIN_G_TXPOWER 0
5193 +#define MIN_A_TXPOWER -7
5194 +#define MAX_G_TXPOWER 31
5195 +#define MAX_A_TXPOWER 15
5196 +#define DEFAULT_TXPOWER 5
5197 +
5198 +#define TXPOWER_G_FROM_DEV(__txpower) \
5199 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5200 +
5201 +#define TXPOWER_G_TO_DEV(__txpower) \
5202 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
5203 +
5204 +#define TXPOWER_A_FROM_DEV(__txpower) \
5205 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
5206 +
5207 +#define TXPOWER_A_TO_DEV(__txpower) \
5208 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
5209 +
5210 +#endif /* RT2800PCI_H */
5211 --- a/drivers/net/wireless/rt2x00/rt2x00.h
5212 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
5213 @@ -147,6 +147,12 @@ struct rt2x00_chip {
5214 #define RT2561 0x0302
5215 #define RT2661 0x0401
5216 #define RT2571 0x1300
5217 +#define RT2860 0x0601 /* 2.4GHz PCI/CB */
5218 +#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
5219 +#define RT2890 0x0701 /* 2.4GHz PCIe */
5220 +#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
5221 +#define RT2880 0x2880 /* WSOC */
5222 +#define RT3052 0x3052 /* WSOC */
5223 #define RT2870 0x1600
5224
5225 u16 rf;
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