package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c

   1 /*****************************************************************************
   2  * DANUBE BootROM
   3  * Copyright (c) 2005, Infineon Technologies AG, All rights reserved
   4  * IFAP DC COM SD
   5  *****************************************************************************/
   6
   7 #include <config.h>
   8 //#include <lib.h>
   9 #include <asm/danube.h>
  10 #include <asm/addrspace.h>
  11 #include <asm/ifx_asc.h>
  12
  13
  14 #define ASC_FIFO_PRESENT
  15 #define SET_BIT(reg, mask)                  reg |= (mask)
  16 #define CLEAR_BIT(reg, mask)                reg &= (~mask)
  17 #define CLEAR_BITS(reg, mask)               CLEAR_BIT(reg, mask)
  18 #define SET_BITS(reg, mask)                 SET_BIT(reg, mask)
  19 #define SET_BITFIELD(reg, mask, off, val)   {reg &= (~mask); reg |= (val << off);}
  20
  21
  22 typedef unsigned char u8;
  23 typedef unsigned short u16;
  24 typedef unsigned long u32;
  25 typedef signed   long s32;
  26 typedef unsigned int uint;
  27 typedef unsigned long ulong;
  28 typedef volatile unsigned short vuint;
  29
  30
  31
  32 void serial_setbrg (void);
  33
  34 /*TODO: undefine this !!!*/
  35 #undef DEBUG_ASC_RAW
  36 #ifdef DEBUG_ASC_RAW
  37 #define DEBUG_ASC_RAW_RX_BUF            0xA0800000
  38 #define DEBUG_ASC_RAW_TX_BUF            0xA0900000
  39 #endif
  40
  41 static volatile DanubeAsc_t *pAsc = (DanubeAsc_t *)DANUBE_ASC1;
  42
  43 typedef struct{
  44   u16 fdv; /* 0~511 fractional divider value*/
  45   u16 reload; /* 13 bit reload value*/
  46 } ifx_asc_baud_reg_t;
  47
  48 #ifdef ON_VENUS
  49 /*9600 @1.25M rel 00.08*/
  50 //#define FDV 503
  51 //#define RELOAD 7
  52 /*9600 @0.625M rel final00.01 & rtl_freeze*/
  53 #define FDV 503
  54 #define RELOAD 3
  55 /* first index is DDR_SEL, second index is FPI_SEL */
  56 #endif
  57 static ifx_asc_baud_reg_t g_danube_asc_baud[4][2] =
  58 {
  59 #ifdef ON_VENUS
  60      {{503,3},{503,3}},   /* 1152000 @ 166.67M and half*/
  61       {{503,3},{503,3}},   /* 1152000 @ 133.3M  and half*/
  62       {{503,3},{503,3}},   /* 1152000 @ 111.11M and half*/
  63       {{503.3},{503,3}}    /* 1152000 @ 83.33M  and half*/
  64 #else
  65 /*  TAPEOUT table */
  66      {{436,76},{419,36}},   /* 1152000 @ 166.67M and half*/
  67       {{453,63},{453,31}},   /* 1152000 @ 133.3M  and half*/
  68       {{501,58},{510,29}},   /* 1152000 @ 111.11M and half*/
  69       {{419.36},{453,19}}    /* 1152000 @ 83.33M  and half*/
  70 #endif
  71 };
  72 /******************************************************************************
  73 *
  74 * asc_init - initialize a Danube ASC channel
  75 *
  76 * This routine initializes the number of data bits, parity
  77 * and set the selected baud rate. Interrupts are disabled.
  78 * Set the modem control signals if the option is selected.
  79 *
  80 * RETURNS: N/A
  81 */
  82
  83 int serial_init (void)
  84 {
  85
  86         /* and we have to set CLC register*/
  87         CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
  88         SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
  89
  90         /* initialy we are in async mode */
  91         pAsc->asc_con = ASCCON_M_8ASYNC;
  92
  93         /* select input port */
  94         pAsc->asc_pisel = (CONSOLE_TTY & 0x1);
  95
  96         /* TXFIFO's filling level */
  97         SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
  98                         ASCTXFCON_TXFITLOFF, DANUBEASC_TXFIFO_FL);
  99         /* enable TXFIFO */
 100         SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
 101
 102         /* RXFIFO's filling level */
 103         SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
 104                         ASCRXFCON_RXFITLOFF, DANUBEASC_RXFIFO_FL);
 105         /* enable RXFIFO */
 106         SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
 107
 108         /* set baud rate */
 109         serial_setbrg();
 110
 111         /* enable error signals &  Receiver enable  */
 112         SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
 113
 114         return 0;
 115 }
 116
 117 void serial_setbrg (void)
 118 {
 119         u32 uiReloadValue, fdv;
 120
 121 #if defined(ON_IKOS)
 122         /*1200 @77K */
 123         fdv=472;
 124         uiReloadValue=5;
 125 #else
 126         /*venus & tapeout */
 127   u32 ddr_sel,fpi_sel;
 128   ddr_sel = (* DANUBE_CGU_SYS) & 0x3;
 129   fpi_sel = ((* DANUBE_CGU_SYS) & 0x40)?1:0;
 130         fdv= g_danube_asc_baud[ddr_sel][fpi_sel].fdv;
 131         uiReloadValue=g_danube_asc_baud[ddr_sel][fpi_sel].reload;
 132 #endif  //ON_IKOS
 133         /* Disable Baud Rate Generator; BG should only be written when R=0 */
 134         CLEAR_BIT(pAsc->asc_con, ASCCON_R);
 135
 136         /* Enable Fractional Divider */
 137         SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */
 138
 139         /* Set fractional divider value */
 140         pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK;
 141
 142         /* Set reload value in BG */
 143         pAsc->asc_bg = uiReloadValue;
 144
 145         /* Enable Baud Rate Generator */
 146         SET_BIT(pAsc->asc_con, ASCCON_R);           /* R = 1 */
 147 }
 148
 149
 150 void serial_putc (const char c)
 151 {
 152         u32 txFl = 0;
 153 #ifdef DEBUG_ASC_RAW
 154         static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
 155         *debug++=c;
 156 #endif
 157         if (c == '\n')
 158                 serial_putc ('\r');
 159         /* check do we have a free space in the TX FIFO */
 160         /* get current filling level */
 161         do
 162         {
 163                 txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
 164         }
 165         while ( txFl == DANUBEASC_TXFIFO_FULL );
 166
 167         pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */
 168
 169         /* check for errors */
 170         if ( pAsc->asc_state & ASCSTATE_TOE )
 171         {
 172                 SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_CLRTOE);
 173                 return;
 174         }
 175 }
 176
 177 void serial_puts (const char *s)
 178 {
 179         while (*s)
 180         {
 181                 serial_putc (*s++);
 182         }
 183 }
 184
 185 int asc_inb(int timeout)
 186 {
 187         u32 symbol_mask;
 188         char c;
 189         while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) {
 190         }
 191         symbol_mask = ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
 192         c = (char)(pAsc->asc_rbuf & symbol_mask);
 193         return (c);
 194 }
 195
 196 int serial_getc (void)
 197 {
 198         char c;
 199         while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 );
 200         c = (char)(pAsc->asc_rbuf & 0xff);
 201
 202 #ifdef  DEBUG_ASC_RAW
 203         static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
 204         *debug++=c;
 205 #endif
 206         return c;
 207 }
 208
 209
 210
 211 int serial_tstc (void)
 212 {
 213          int res = 1;
 214
 215 #ifdef ASC_FIFO_PRESENT
 216     if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
 217     {
 218         res = 0;
 219     }
 220 #else
 221     if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
 222                                                                 FBS_ISR_AR))
 223
 224     {
 225         res = 0;
 226     }
 227 #endif
 228 #if 0
 229     else if ( pAsc->asc_con & ASCCON_FE )
 230     {
 231         SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
 232         res = 0;
 233     }
 234     else if ( pAsc->asc_con & ASCCON_PE )
 235     {
 236         SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
 237         res = 0;
 238     }
 239     else if ( pAsc->asc_con & ASCCON_OE )
 240     {
 241         SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
 242         res = 0;
 243     }
 244 #endif
 245   return res;
 246 }
 247
 248
 249 int serial_start(void)
 250 {
 251    return 1;
 252 }
 253
 254 int serial_stop(void)
 255 {
 256    return 1;
 257 }