target/linux/rb532/files/arch/mips/rb500/devices.c

   1 /*
   2  *  RouterBoard 500 Platform devices
   3  *
   4  *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
   5  *  Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  *  GNU General Public License for more details.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/ctype.h>
  20 #include <linux/string.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/mtd/nand.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25
  26 #include <asm/rc32434/rc32434.h>
  27 #include <asm/rc32434/dma.h>
  28 #include <asm/rc32434/dma_v.h>
  29 #include <asm/rc32434/eth.h>
  30 #include <asm/rc32434/rb.h>
  31
  32 #define ETH0_DMA_RX_IRQ         GROUP1_IRQ_BASE + 0
  33 #define ETH0_DMA_TX_IRQ         GROUP1_IRQ_BASE + 1
  34 #define ETH0_RX_OVR_IRQ         GROUP3_IRQ_BASE + 9
  35 #define ETH0_TX_UND_IRQ         GROUP3_IRQ_BASE + 10
  36
  37 #define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
  38 #define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
  39
  40 /* NAND definitions */
  41 #define MEM32(x) *((volatile unsigned *) (x))
  42
  43 #define GPIO_RDY (1 << 0x08)
  44 #define GPIO_WPX (1 << 0x09)
  45 #define GPIO_ALE (1 << 0x0a)
  46 #define GPIO_CLE (1 << 0x0b)
  47
  48 extern char* board_type;
  49
  50 static struct resource korina_dev0_res[] = {
  51         {
  52                 .name = "korina_regs",
  53                 .start = ETH0_PhysicalAddress,
  54                 .end = ETH0_PhysicalAddress + sizeof(ETH_t),
  55                 .flags = IORESOURCE_MEM,
  56          }, {
  57                 .name = "korina_rx",
  58                 .start = ETH0_DMA_RX_IRQ,
  59                 .end = ETH0_DMA_RX_IRQ,
  60                 .flags = IORESOURCE_IRQ
  61         }, {
  62                 .name = "korina_tx",
  63                 .start = ETH0_DMA_TX_IRQ,
  64                 .end = ETH0_DMA_TX_IRQ,
  65                 .flags = IORESOURCE_IRQ
  66         }, {
  67                 .name = "korina_ovr",
  68                 .start = ETH0_RX_OVR_IRQ,
  69                 .end = ETH0_RX_OVR_IRQ,
  70                 .flags = IORESOURCE_IRQ
  71         }, {
  72                 .name = "korina_und",
  73                 .start = ETH0_TX_UND_IRQ,
  74                 .end = ETH0_TX_UND_IRQ,
  75                 .flags = IORESOURCE_IRQ
  76         }, {
  77                 .name = "korina_dma_rx",
  78                 .start = ETH0_RX_DMA_ADDR,
  79                 .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  80                 .flags = IORESOURCE_MEM,
  81          }, {
  82                 .name = "korina_dma_tx",
  83                 .start = ETH0_TX_DMA_ADDR,
  84                 .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  85                 .flags = IORESOURCE_MEM,
  86          }
  87 };
  88
  89 static struct korina_device korina_dev0_data = {
  90         .name = "korina0",
  91         .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
  92 };
  93
  94 static struct platform_device korina_dev0 = {
  95         .id = 0,
  96         .name = "korina",
  97         .dev.platform_data = &korina_dev0_data,
  98         .resource = korina_dev0_res,
  99         .num_resources = ARRAY_SIZE(korina_dev0_res),
 100 };
 101
 102 #define CF_GPIO_NUM 13
 103
 104 static struct resource cf_slot0_res[] = {
 105         {
 106                 .name = "cf_membase",
 107                 .flags = IORESOURCE_MEM
 108         }, {
 109                 .name = "cf_irq",
 110                 .start = (8 + 4 * 32 + CF_GPIO_NUM),    /* 149 */
 111                 .end = (8 + 4 * 32 + CF_GPIO_NUM),
 112                 .flags = IORESOURCE_IRQ
 113         }
 114 };
 115
 116 static struct cf_device cf_slot0_data = {
 117         .gpio_pin = 13
 118 };
 119
 120 static struct platform_device cf_slot0 = {
 121         .id = 0,
 122         .name = "rb500-cf",
 123         .dev.platform_data = &cf_slot0_data,
 124         .resource = cf_slot0_res,
 125         .num_resources = ARRAY_SIZE(cf_slot0_res),
 126 };
 127
 128 /* Resources and device for NAND.  There is no data needed and no irqs, so just define the memory used. */
 129 int rb500_dev_ready(struct mtd_info *mtd)
 130 {
 131         return MEM32(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
 132 }
 133
 134 void rb500_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 135 {
 136         struct nand_chip *chip = mtd->priv;
 137         unsigned char orbits, nandbits;
 138
 139         if (ctrl & NAND_CTRL_CHANGE) {
 140
 141                 orbits = (ctrl & NAND_CLE) << 1;
 142                 orbits |= (ctrl & NAND_ALE) >> 1;
 143
 144                 nandbits = (~ctrl & NAND_CLE) << 1;
 145                 nandbits |= (~ctrl & NAND_ALE) >> 1;
 146
 147                 changeLatchU5(orbits, nandbits);
 148         }
 149         if (cmd != NAND_CMD_NONE)
 150                 writeb(cmd, chip->IO_ADDR_W);
 151 }
 152
 153 static struct resource nand_slot0_res[] = {
 154         {
 155                 .name = "nand_membase",
 156                 .flags = IORESOURCE_MEM
 157         }
 158 };
 159
 160 struct platform_nand_data rb500_nand_data = {
 161         .ctrl.dev_ready = rb500_dev_ready,
 162         .ctrl.cmd_ctrl  = rb500_cmd_ctrl,
 163 };
 164
 165 static struct platform_device nand_slot0 = {
 166         .id = 0,
 167         .name = "gen_nand",
 168         .resource = nand_slot0_res,
 169         .num_resources = ARRAY_SIZE(nand_slot0_res),
 170         .dev.platform_data = &rb500_nand_data,
 171 };
 172
 173 static struct mtd_partition rb500_partition_info[] = {
 174         {
 175                 .name = "Routerboard NAND boot",
 176                 .offset = 0,
 177                 .size = 4 * 1024 * 1024,
 178         }, {
 179                 .name = "rootfs",
 180                 .offset = MTDPART_OFS_NXTBLK,
 181                 .size = MTDPART_SIZ_FULL,
 182         }
 183 };
 184
 185
 186 static struct platform_device *rb500_devs[] = {
 187         &korina_dev0,
 188         &nand_slot0,
 189         &cf_slot0
 190 };
 191
 192 static void __init parse_mac_addr(char *macstr)
 193 {
 194         int i, j;
 195         unsigned char result, value;
 196
 197         for (i = 0; i < 6; i++) {
 198                 result = 0;
 199
 200                 if (i != 5 && *(macstr + 2) != ':')
 201                         return;
 202
 203                 for (j = 0; j < 2; j++) {
 204                         if (isxdigit(*macstr)
 205                             && (value =
 206                                 isdigit(*macstr) ? *macstr -
 207                                 '0' : toupper(*macstr) - 'A' + 10) < 16) {
 208                                 result = result * 16 + value;
 209                                 macstr++;
 210                         } else
 211                                 return;
 212                 }
 213
 214                 macstr++;
 215                 korina_dev0_data.mac[i] = result;
 216         }
 217 }
 218
 219
 220 /* DEVICE CONTROLLER 1 */
 221 #define CFG_DC_DEV1 (void*)0xb8010010
 222 #define CFG_DC_DEV2 (void*)0xb8010020
 223 #define CFG_DC_DEVBASE    0x0
 224 #define CFG_DC_DEVMASK    0x4
 225 #define CFG_DC_DEVC       0x8
 226 #define CFG_DC_DEVTC      0xC
 227
 228 /* NAND definitions */
 229 #define NAND_CHIP_DELAY 25
 230
 231 static void __init rb500_nand_setup(void)
 232 {
 233         if (!strcmp(board_type, "500r5"))
 234                 changeLatchU5(LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE | LO_WPX);
 235         else
 236                 changeLatchU5(LO_WPX | LO_FOFF | LO_CEX, LO_ULED | LO_ALE | LO_CLE);
 237 }
 238
 239
 240 static int __init plat_setup_devices(void)
 241 {
 242         /* Look for the CF card reader */
 243         if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
 244                 rb500_devs[1] = NULL;
 245         else {
 246                 cf_slot0_res[0].start =
 247                     readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
 248                 cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
 249         }
 250
 251         /* Initialise the NAND device */
 252         rb500_nand_setup();
 253
 254         /* Read the NAND resources from the device controller */
 255         nand_slot0_res[0].start = readl(CFG_DC_DEV2 + CFG_DC_DEVBASE);
 256         nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
 257
 258         /* Setup NAND specific settings */
 259         rb500_nand_data.chip.nr_chips = 1;
 260         rb500_nand_data.chip.nr_partitions = ARRAY_SIZE(rb500_partition_info);
 261         rb500_nand_data.chip.partitions = rb500_partition_info;
 262         rb500_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
 263         rb500_nand_data.chip.options = NAND_NO_AUTOINCR;
 264
 265         return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
 266 }
 267
 268 static int __init setup_kmac(char *s)
 269 {
 270         printk("korina mac = %s\n", s);
 271         parse_mac_addr(s);
 272         return 0;
 273 }
 274
 275 __setup("kmac=", setup_kmac);
 276
 277 arch_initcall(plat_setup_devices);