[package] kernel: added GPIO driver for CS5535/CS5536 companion chip. Thanks Markus...
[openwrt.git] / package / mac80211 / patches / 403-ath9k-introduce-bus-specific-cache-size-routine.patch
1 From a81f936d72caabbcf5698a6636185a8f6630d692 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Fri, 2 Jan 2009 16:08:22 +0100
4 Subject: [RFC 03/12] ath9k: introduce bus specific cache size routine
5
6 The PCI specific bus_read_cachesize routine won't work on the AHB bus,
7 we have to replace it with a suitable one later.
8
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
11 ---
12 drivers/net/wireless/ath9k/core.h | 7 +++++++
13 drivers/net/wireless/ath9k/main.c | 8 +++++---
14 2 files changed, 12 insertions(+), 3 deletions(-)
15
16 --- a/drivers/net/wireless/ath9k/core.h
17 +++ b/drivers/net/wireless/ath9k/core.h
18 @@ -721,6 +721,8 @@ struct ath_bus_ops {
19
20 u32 (*reg_read)(struct ath_hal *ah, unsigned reg);
21 void (*reg_write)(struct ath_hal *ah, unsigned reg, u32 val);
22 +
23 + void (*read_cachesize)(struct ath_softc *sc, int *csz);
24 };
25
26 struct ath_softc {
27 @@ -843,4 +845,9 @@ static inline void ath_reg_write(struct
28 sc->bus_ops->reg_write(ah, reg, val);
29 }
30
31 +static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
32 +{
33 + sc->bus_ops->read_cachesize(sc, csz);
34 +}
35 +
36 #endif /* CORE_H */
37 --- a/drivers/net/wireless/ath9k/main.c
38 +++ b/drivers/net/wireless/ath9k/main.c
39 @@ -41,8 +41,7 @@ static struct pci_device_id ath_pci_id_t
40 static void ath_detach(struct ath_softc *sc);
41
42 /* return bus cachesize in 4B word units */
43 -
44 -static void bus_read_cachesize(struct ath_softc *sc, int *csz)
45 +static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
46 {
47 u8 u8tmp;
48
49 @@ -59,6 +58,7 @@ static void bus_read_cachesize(struct at
50 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
51 }
52
53 +
54 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
55 {
56 sc->cur_rate_table = sc->hw_rate_table[mode];
57 @@ -1347,7 +1347,7 @@ static int ath_init(u16 devid, struct at
58 * Cache line size is used to size and align various
59 * structures used to communicate with the hardware.
60 */
61 - bus_read_cachesize(sc, &csz);
62 + ath_read_cachesize(sc, &csz);
63 /* XXX assert csz is non-zero */
64 sc->sc_cachelsz = csz << 2; /* convert to bytes */
65
66 @@ -2618,6 +2618,8 @@ static struct ath_bus_ops ath_pci_bus_op
67
68 .reg_read = ath_pci_reg_read,
69 .reg_write = ath_pci_reg_write,
70 +
71 + .read_cachesize = ath_pci_read_cachesize,
72 };
73
74 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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