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[xburst] time.c: Timer enable registers are only 8bit width.
[openwrt.git] / target / linux / xburst / files-2.6.32 / arch / mips / jz4740 / gpio.c
1 /*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19
20 #include <linux/spinlock.h>
21 #include <linux/sysdev.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27
28 #include <linux/debugfs.h>
29 #include <linux/seq_file.h>
30
31 #define JZ_GPIO_BASE_A (32*0)
32 #define JZ_GPIO_BASE_B (32*1)
33 #define JZ_GPIO_BASE_C (32*2)
34 #define JZ_GPIO_BASE_D (32*3)
35
36 #define JZ_GPIO_NUM_A 32
37 #define JZ_GPIO_NUM_B 32
38 #define JZ_GPIO_NUM_C 31
39 #define JZ_GPIO_NUM_D 32
40
41 #define JZ_IRQ_GPIO_BASE_A (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_A)
42 #define JZ_IRQ_GPIO_BASE_B (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_B)
43 #define JZ_IRQ_GPIO_BASE_C (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_C)
44 #define JZ_IRQ_GPIO_BASE_D (JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_D)
45
46 #define JZ_IRQ_GPIO_A(num) (JZ_IRQ_GPIO_BASE_A + num)
47 #define JZ_IRQ_GPIO_B(num) (JZ_IRQ_GPIO_BASE_B + num)
48 #define JZ_IRQ_GPIO_C(num) (JZ_IRQ_GPIO_BASE_C + num)
49 #define JZ_IRQ_GPIO_D(num) (JZ_IRQ_GPIO_BASE_D + num)
50
51 #define JZ_REG_GPIO_PIN 0x00
52 #define JZ_REG_GPIO_DATA 0x10
53 #define JZ_REG_GPIO_DATA_SET 0x14
54 #define JZ_REG_GPIO_DATA_CLEAR 0x18
55 #define JZ_REG_GPIO_MASK 0x20
56 #define JZ_REG_GPIO_MASK_SET 0x24
57 #define JZ_REG_GPIO_MASK_CLEAR 0x28
58 #define JZ_REG_GPIO_PULL 0x30
59 #define JZ_REG_GPIO_PULL_SET 0x34
60 #define JZ_REG_GPIO_PULL_CLEAR 0x38
61 #define JZ_REG_GPIO_FUNC 0x40
62 #define JZ_REG_GPIO_FUNC_SET 0x44
63 #define JZ_REG_GPIO_FUNC_CLEAR 0x48
64 #define JZ_REG_GPIO_SELECT 0x50
65 #define JZ_REG_GPIO_SELECT_SET 0x54
66 #define JZ_REG_GPIO_SELECT_CLEAR 0x58
67 #define JZ_REG_GPIO_DIRECTION 0x60
68 #define JZ_REG_GPIO_DIRECTION_SET 0x64
69 #define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
70 #define JZ_REG_GPIO_TRIGGER 0x70
71 #define JZ_REG_GPIO_TRIGGER_SET 0x74
72 #define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
73 #define JZ_REG_GPIO_FLAG 0x80
74 #define JZ_REG_GPIO_FLAG_CLEAR 0x14
75
76 #define CHIP_TO_REG(chip, reg) (jz_gpio_base + (((chip)->base) << 3) + reg)
77
78 #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
79 #define GPIO_TO_REG(gpio, reg) (jz_gpio_base + ((gpio >> 5) << 8) + reg)
80
81 static void __iomem *jz_gpio_base;
82
83 struct jz_gpio_chip {
84 unsigned int irq;
85 unsigned int irq_base;
86 uint32_t wakeup;
87 uint32_t suspend_mask;
88 uint32_t edge_trigger_both;
89 spinlock_t lock;
90 struct gpio_chip gpio_chip;
91 struct irq_chip irq_chip;
92 };
93
94 static struct jz_gpio_chip *jz_irq_to_chip(unsigned int irq)
95 {
96 return get_irq_chip_data(irq);
97 }
98
99 static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
100 {
101 writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
102 }
103
104 int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
105 {
106 if (function == JZ_GPIO_FUNC_NONE) {
107 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
108 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
109 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
110 } else {
111 jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
112 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
113 switch (function) {
114 case JZ_GPIO_FUNC1:
115 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
116 break;
117 case JZ_GPIO_FUNC3:
118 jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
119 case JZ_GPIO_FUNC2: /* Falltrough */
120 jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
121 break;
122 default:
123 BUG();
124 break;
125 }
126 }
127
128 return 0;
129 }
130 EXPORT_SYMBOL_GPL(jz_gpio_set_function);
131
132 int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
133 {
134 size_t i;
135 int ret;
136
137 for (i = 0; i < num; ++i, ++request) {
138 ret = gpio_request(request->gpio, request->name);
139 if (ret)
140 goto err;
141 jz_gpio_set_function(request->gpio, request->function);
142 }
143
144 return 0;
145 err:
146 for (--request; i > 0; --i, --request)
147 gpio_free(request->gpio);
148
149 return ret;
150 }
151 EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
152
153 void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
154 {
155 size_t i;
156
157 for (i = 0; i < num; ++i, ++request) {
158 gpio_free(request->gpio);
159 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
160 }
161
162 }
163 EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
164
165 void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
166 {
167 size_t i;
168
169 for (i = 0; i < num; ++i, ++request) {
170 jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
171 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
172 jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
173 }
174 }
175 EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
176
177 void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
178 {
179 size_t i;
180
181 for (i = 0; i < num; ++i, ++request) {
182 jz_gpio_set_function(request->gpio, request->function);
183 }
184 }
185 EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
186
187 void jz_gpio_enable_pullup(unsigned gpio)
188 {
189 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
190 }
191 EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
192
193 void jz_gpio_disable_pullup(unsigned gpio)
194 {
195 jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
196 }
197 EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
198
199 static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
200 {
201 return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
202 }
203
204 static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
205 {
206 uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
207 reg += !value;
208 writel(BIT(gpio), reg);
209 }
210
211 static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
212 {
213 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
214 jz_gpio_set_value(chip, gpio, value);
215
216 return 0;
217 }
218
219 static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
220 {
221 writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
222
223 return 0;
224 }
225
226 int jz_gpio_port_direction_input(int port, uint32_t mask)
227 {
228 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
229
230 return 0;
231 }
232 EXPORT_SYMBOL(jz_gpio_port_direction_input);
233
234 int jz_gpio_port_direction_output(int port, uint32_t mask)
235 {
236 writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
237
238 return 0;
239 }
240 EXPORT_SYMBOL(jz_gpio_port_direction_output);
241
242 void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
243 {
244 writel((~value) & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
245 writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
246 }
247 EXPORT_SYMBOL(jz_gpio_port_set_value);
248
249 uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
250 {
251 uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
252
253 return value & mask;
254 }
255 EXPORT_SYMBOL(jz_gpio_port_get_value);
256
257
258 #define IRQ_TO_GPIO(irq) (irq - JZ_IRQ_GPIO(0))
259 #define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
260
261 #define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
262
263 static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
264 {
265 uint32_t flag;
266 unsigned int gpio_irq;
267 unsigned int gpio_bank;
268 struct jz_gpio_chip *chip = get_irq_desc_data(desc);
269
270 gpio_bank = JZ_IRQ_GPIO0 - irq;
271
272 flag = readl(jz_gpio_base + (gpio_bank << 8) + JZ_REG_GPIO_FLAG);
273
274 gpio_irq = ffs(flag) - 1;
275
276 if (chip->edge_trigger_both & BIT(gpio_irq)) {
277 uint32_t value = readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN));
278 if (value & BIT(gpio_irq)) {
279 writel(BIT(gpio_irq),
280 CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_CLEAR));
281 } else {
282 writel(BIT(gpio_irq),
283 CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION_SET));
284 }
285 }
286
287 gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0);
288
289 generic_handle_irq(gpio_irq);
290 };
291
292 static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
293 {
294 writel(IRQ_TO_BIT(irq), IRQ_TO_REG(irq, reg));
295 }
296
297 static void jz_gpio_irq_mask(unsigned int irq)
298 {
299 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
300 };
301
302 static void jz_gpio_irq_unmask(unsigned int irq)
303 {
304 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
305 };
306
307
308 /* TODO: Check if function is gpio */
309 static unsigned int jz_gpio_irq_startup(unsigned int irq)
310 {
311 struct irq_desc *desc = irq_to_desc(irq);
312
313 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
314
315 desc->status &= ~IRQ_MASKED;
316 jz_gpio_irq_unmask(irq);
317
318 return 0;
319 }
320
321 static void jz_gpio_irq_shutdown(unsigned int irq)
322 {
323 struct irq_desc *desc = irq_to_desc(irq);
324
325 jz_gpio_irq_mask(irq);
326 desc->status |= IRQ_MASKED;
327
328 /* Set direction to input */
329 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
330 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
331 }
332
333 static void jz_gpio_irq_ack(unsigned int irq)
334 {
335 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
336 };
337
338 static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
339 {
340 struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
341 struct irq_desc *desc = irq_to_desc(irq);
342
343 jz_gpio_irq_mask(irq);
344
345 if (flow_type == IRQ_TYPE_EDGE_BOTH) {
346 uint32_t value = readl(IRQ_TO_REG(irq, JZ_REG_GPIO_PIN));
347 if (value & IRQ_TO_BIT(irq))
348 flow_type = IRQ_TYPE_EDGE_FALLING;
349 else
350 flow_type = IRQ_TYPE_EDGE_RISING;
351 chip->edge_trigger_both |= IRQ_TO_BIT(irq);
352 } else {
353 chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
354 }
355
356 switch(flow_type) {
357 case IRQ_TYPE_EDGE_RISING:
358 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
359 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
360 break;
361 case IRQ_TYPE_EDGE_FALLING:
362 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
363 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
364 break;
365 case IRQ_TYPE_LEVEL_HIGH:
366 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
367 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
368 break;
369 case IRQ_TYPE_LEVEL_LOW:
370 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
371 jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
372 break;
373 default:
374 return -EINVAL;
375 }
376
377 if (!(desc->status & IRQ_MASKED))
378 jz_gpio_irq_unmask(irq);
379
380 return 0;
381 }
382
383 static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
384 {
385 struct jz_gpio_chip *chip = jz_irq_to_chip(irq);
386 spin_lock(&chip->lock);
387 if (on)
388 chip->wakeup |= IRQ_TO_BIT(irq);
389 else
390 chip->wakeup &= ~IRQ_TO_BIT(irq);
391 spin_unlock(&chip->lock);
392
393 set_irq_wake(chip->irq, !!(chip->wakeup));
394 return 0;
395 }
396
397 int gpio_to_irq(unsigned gpio)
398 {
399 return JZ_IRQ_GPIO(0) + gpio;
400 }
401 EXPORT_SYMBOL_GPL(gpio_to_irq);
402
403 int irq_to_gpio(unsigned gpio)
404 {
405 return IRQ_TO_GPIO(gpio);
406 }
407 EXPORT_SYMBOL_GPL(irq_to_gpio);
408
409 #define JZ_GPIO_CHIP(_bank) { \
410 .irq_base = JZ_IRQ_GPIO_BASE_ ## _bank, \
411 .gpio_chip = { \
412 .label = "Bank " # _bank, \
413 .owner = THIS_MODULE, \
414 .set = jz_gpio_set_value, \
415 .get = jz_gpio_get_value, \
416 .direction_output = jz_gpio_direction_output, \
417 .direction_input = jz_gpio_direction_input, \
418 .base = JZ_GPIO_BASE_ ## _bank, \
419 .ngpio = JZ_GPIO_NUM_ ## _bank, \
420 }, \
421 .irq_chip = { \
422 .name = "GPIO Bank " # _bank, \
423 .mask = jz_gpio_irq_mask, \
424 .unmask = jz_gpio_irq_unmask, \
425 .ack = jz_gpio_irq_ack, \
426 .startup = jz_gpio_irq_startup, \
427 .shutdown = jz_gpio_irq_shutdown, \
428 .set_type = jz_gpio_irq_set_type, \
429 .set_wake = jz_gpio_irq_set_wake, \
430 }, \
431 }
432
433 static struct jz_gpio_chip jz_gpio_chips[] = {
434 JZ_GPIO_CHIP(A),
435 JZ_GPIO_CHIP(B),
436 JZ_GPIO_CHIP(C),
437 JZ_GPIO_CHIP(D),
438 };
439
440 int jz_gpio_suspend(void)
441 {
442 struct jz_gpio_chip *chip = jz_gpio_chips;
443 int i, gpio;
444
445 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
446 gpio = chip->gpio_chip.base;
447 chip->suspend_mask = readl(GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK));
448 writel(~(chip->wakeup), GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_SET));
449 writel(chip->wakeup, GPIO_TO_REG(gpio, JZ_REG_GPIO_MASK_CLEAR));
450 }
451
452 chip = jz_gpio_chips;
453
454 return 0;
455 }
456
457 int jz_gpio_resume(void)
458 {
459 struct jz_gpio_chip *chip = jz_gpio_chips;
460 int i;
461
462 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
463 writel(~(chip->suspend_mask), GPIO_TO_REG(chip->gpio_chip.base,
464 JZ_REG_GPIO_MASK_CLEAR));
465 writel(chip->suspend_mask, GPIO_TO_REG(chip->gpio_chip.base,
466 JZ_REG_GPIO_MASK_SET));
467 }
468
469 return 0;
470 }
471
472 int __init jz_gpiolib_init(void)
473 {
474 struct jz_gpio_chip *chip = jz_gpio_chips;
475 int i, irq;
476
477 jz_gpio_base = ioremap(0x10010000, 0x400);
478
479 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
480 gpiochip_add(&chip->gpio_chip);
481 spin_lock_init(&chip->lock);
482 chip->irq = JZ_IRQ_INTC_GPIO(i);
483 set_irq_data(chip->irq, chip);
484 set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
485 for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
486 set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
487 set_irq_chip_data(irq, chip);
488 }
489 }
490
491 printk("JZ GPIO initalized\n");
492
493 return 0;
494 }
495
496 #ifdef CONFIG_DEBUG_FS
497
498 static int gpio_regs_show(struct seq_file *s, void *unused)
499 {
500 struct jz_gpio_chip *chip = jz_gpio_chips;
501 int i;
502
503 for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
504 seq_printf(s, "GPIO %d: \n", i);
505 seq_printf(s, "\tPin: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PIN)));
506 seq_printf(s, "\tData: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DATA)));
507 seq_printf(s, "\tMask: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_MASK)));
508 seq_printf(s, "\tData: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DATA)));
509 seq_printf(s, "\tPull: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_PULL)));
510 seq_printf(s, "\tFunc: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_FUNC)));
511 seq_printf(s, "\tSelect: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_SELECT)));
512 seq_printf(s, "\tDirection: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_DIRECTION)));
513 seq_printf(s, "\tTrigger: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_TRIGGER)));
514 seq_printf(s, "\tFlag: %.8x\n", readl(CHIP_TO_REG(&chip->gpio_chip, JZ_REG_GPIO_FLAG)));
515 }
516
517 return 0;
518 }
519
520 static int gpio_regs_open(struct inode *inode, struct file *file)
521 {
522 return single_open(file, gpio_regs_show, NULL);
523 }
524
525 static const struct file_operations gpio_regs_operations = {
526 .open = gpio_regs_open,
527 .read = seq_read,
528 .llseek = seq_lseek,
529 .release = single_release,
530 };
531
532 static int __init gpio_debugfs_init(void)
533 {
534 (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
535 NULL, NULL, &gpio_regs_operations);
536 return 0;
537 }
538 subsys_initcall(gpio_debugfs_init);
539
540 #endif
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