target/linux/xburst/files-2.6.32/arch/mips/jz4740/time.c

   1 /*
   2  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
   3  *      JZ4740 platform timer support
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  *
  10  *  You should have received a copy of the  GNU General Public License along
  11  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  12  *  675 Mass Ave, Cambridge, MA 02139, USA.
  13  *
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/time.h>
  19 #include <linux/clockchips.h>
  20 #include <linux/clk.h>
  21
  22 #include <asm/mach-jz4740/irq.h>
  23 #include <asm/mach-jz4740/jz4740.h>
  24 #include <asm/time.h>
  25 #include "clock.h"
  26
  27 #define JZ_REG_TIMER_STOP               0x1C
  28 #define JZ_REG_TIMER_STOP_SET           0x2C
  29 #define JZ_REG_TIMER_STOP_CLEAR         0x3C
  30 #define JZ_REG_TIMER_ENABLE             0x10
  31 #define JZ_REG_TIMER_ENABLE_SET         0x14
  32 #define JZ_REG_TIMER_ENABLE_CLEAR       0x18
  33 #define JZ_REG_TIMER_FLAG               0x20
  34 #define JZ_REG_TIMER_FLAG_SET           0x24
  35 #define JZ_REG_TIMER_FLAG_CLEAR         0x28
  36 #define JZ_REG_TIMER_MASK               0x30
  37 #define JZ_REG_TIMER_MASK_SET           0x34
  38 #define JZ_REG_TIMER_MASK_CLEAR         0x38
  39
  40 #define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
  41 #define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
  42 #define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
  43 #define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
  44
  45 #define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
  46 #define JZ_TIMER_IRQ_FULL(x) BIT(x)
  47
  48 #define JZ_TIMER_CTRL_PWM_ACTIVE_LOW    BIT(8)
  49 #define JZ_TIMER_CTRL_PWM_ENABLE        BIT(7)
  50 #define JZ_TIMER_CTRL_PRESCALE_MASK     0x1c
  51 #define JZ_TIMER_CTRL_PRESCALE_OFFSET   0x3
  52 #define JZ_TIMER_CTRL_PRESCALE_1        (0 << 3)
  53 #define JZ_TIMER_CTRL_PRESCALE_4        (1 << 3)
  54 #define JZ_TIMER_CTRL_PRESCALE_16       (2 << 3)
  55 #define JZ_TIMER_CTRL_PRESCALE_64       (3 << 3)
  56 #define JZ_TIMER_CTRL_PRESCALE_256      (4 << 3)
  57 #define JZ_TIMER_CTRL_PRESCALE_1024     (5 << 3)
  58
  59 #define JZ_TIMER_CTRL_SRC_EXT           BIT(2)
  60 #define JZ_TIMER_CTRL_SRC_RTC           BIT(1)
  61 #define JZ_TIMER_CTRL_SRC_PCLK          BIT(0)
  62
  63 static void __iomem *jz4740_timer_base;
  64 static uint16_t jz4740_jiffies_per_tick;
  65
  66 void jz4740_timer_enable_watchdog(void)
  67 {
  68         writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
  69 }
  70
  71 void jz4740_timer_disable_watchdog(void)
  72 {
  73         writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
  74 }
  75
  76 static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
  77 {
  78         writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
  79 }
  80
  81 static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
  82 {
  83         writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
  84 }
  85
  86 static void jz4740_init_timer(void)
  87 {
  88         uint16_t val = 0;
  89         val |= JZ_TIMER_CTRL_PRESCALE_16;
  90         val |= JZ_TIMER_CTRL_SRC_EXT;
  91
  92         writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(0));
  93         writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
  94         writew(val, jz4740_timer_base + JZ_REG_TIMER_CTRL(1));
  95         writew(0xffff, jz4740_timer_base + JZ_REG_TIMER_DFR(1));
  96 }
  97
  98 static void jz4740_timer_enable(unsigned int timer)
  99 {
 100         writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
 101         writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
 102 }
 103
 104 static void jz4740_timer_disable(unsigned int timer)
 105 {
 106         writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
 107         writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
 108 }
 109
 110 static void jz4740_timer_irq_full_enable(unsigned int timer)
 111 {
 112         writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
 113         writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
 114 }
 115
 116 static int jz4740_timer_irq_full_is_enabled(unsigned int timer)
 117 {
 118         return !(readl(jz4740_timer_base + JZ_REG_TIMER_MASK) &
 119         JZ_TIMER_IRQ_FULL(timer));
 120 }
 121
 122 static void jz4740_timer_irq_full_disable(unsigned int timer)
 123 {
 124         writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
 125 }
 126
 127 static void jz4740_timer_irq_half_enable(unsigned int timer)
 128 {
 129         writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
 130         writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
 131 }
 132
 133 static void jz4740_timer_irq_half_disable(unsigned int timer)
 134 {
 135         writel(JZ_TIMER_IRQ_HALF(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
 136 }
 137
 138 static cycle_t jz4740_clocksource_read(struct clocksource *cs)
 139 {
 140     uint16_t val;
 141         val = readw(jz4740_timer_base + JZ_REG_TIMER_CNT(1));
 142         return val;
 143 }
 144
 145 static struct clocksource jz4740_clocksource = {
 146         .name = "jz4740-timer",
 147         .rating = 200,
 148         .read = jz4740_clocksource_read,
 149         .mask = CLOCKSOURCE_MASK(16),
 150         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 151 };
 152
 153 static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
 154 {
 155         struct clock_event_device *cd = devid;
 156
 157         writel(JZ_TIMER_IRQ_FULL(0), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
 158
 159         if (cd->mode != CLOCK_EVT_MODE_PERIODIC) {
 160                 jz4740_timer_disable(0);
 161                 cd->event_handler(cd);
 162          } else {
 163                 cd->event_handler(cd);
 164         }
 165
 166     return IRQ_HANDLED;
 167 }
 168
 169 static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
 170                                        struct clock_event_device *cd)
 171 {
 172         switch(mode) {
 173         case CLOCK_EVT_MODE_PERIODIC:
 174                 writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
 175                 writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
 176         case CLOCK_EVT_MODE_RESUME:
 177                 jz4740_timer_irq_full_enable(0);
 178                 jz4740_timer_enable(0);
 179                 break;
 180         case CLOCK_EVT_MODE_ONESHOT:
 181         case CLOCK_EVT_MODE_SHUTDOWN:
 182                 jz4740_timer_disable(0);
 183                 break;
 184         default:
 185                 break;
 186         }
 187 }
 188
 189 static int jz4740_clockevent_set_next(unsigned long evt, struct
 190 clock_event_device *cd)
 191 {
 192         writew(0x0, jz4740_timer_base + JZ_REG_TIMER_CNT(0));
 193         writew(evt, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
 194         jz4740_timer_enable(0);
 195
 196         return 0;
 197 }
 198
 199 static struct clock_event_device jz4740_clockevent = {
 200         .name = "jz4740-timer",
 201         .features = CLOCK_EVT_FEAT_PERIODIC,
 202         .set_next_event = jz4740_clockevent_set_next,
 203         .set_mode = jz4740_clockevent_set_mode,
 204         .rating = 200,
 205     .irq = JZ_IRQ_TCU0,
 206 };
 207
 208 static struct irqaction jz_irqaction = {
 209         .handler        = jz4740_clockevent_irq,
 210         .flags          = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
 211         .name           = "jz4740-timerirq",
 212     .dev_id      = &jz4740_clockevent,
 213 };
 214
 215
 216 void __init plat_time_init(void)
 217 {
 218     int ret;
 219         uint32_t clk_rate;
 220
 221         jz4740_timer_base = ioremap(CPHYSADDR(TCU_BASE), 0x100);
 222
 223         if (!jz4740_timer_base) {
 224             printk(KERN_ERR "Failed to ioremap timer registers");
 225             return;
 226         }
 227
 228         clk_rate = jz4740_clock_bdata.ext_rate >> 4;
 229     jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
 230
 231         clockevent_set_clock(&jz4740_clockevent, clk_rate);
 232         jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
 233         jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
 234         jz4740_clockevent.cpumask = cpumask_of(0);
 235
 236         clockevents_register_device(&jz4740_clockevent);
 237
 238         clocksource_set_clock(&jz4740_clocksource, clk_rate);
 239         ret = clocksource_register(&jz4740_clocksource);
 240
 241         if (ret)
 242             printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
 243
 244         setup_irq(JZ_IRQ_TCU0, &jz_irqaction);
 245
 246         jz4740_init_timer();
 247         writew(jz4740_jiffies_per_tick, jz4740_timer_base + JZ_REG_TIMER_DFR(0));
 248     jz4740_timer_irq_half_disable(0);
 249     jz4740_timer_irq_full_enable(0);
 250         jz4740_timer_enable(0);
 251
 252     jz4740_timer_irq_half_disable(1);
 253     jz4740_timer_irq_full_disable(1);
 254
 255         jz4740_timer_enable(1);
 256 }