package/ltq-vmmc/patches/100-ifxmips.patch

   1 --- a/src/drv_vmmc_access.h
   2 +++ b/src/drv_vmmc_access.h
   3 @@ -24,6 +24,10 @@
   4  #include "drv_mps_vmmc.h"
   5  #endif
   6
   7 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
   8 +#  define IFX_MPS IFXMIPS_MPS_BASE_ADDR
   9 +#endif
  10 +
  11  /* ============================= */
  12  /* Global Defines                */
  13  /* ============================= */
  14 --- a/src/drv_vmmc_bbd.c
  15 +++ b/src/drv_vmmc_bbd.c
  16 @@ -1072,7 +1072,11 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
  17     IFX_uint8_t  padBytes = 0;
  18  #endif
  19     IFX_uint16_t cram_offset, cram_crc,
  20 -                pCmd [MAX_CMD_WORD]  = {0};
  21 +                pCmd [MAX_CMD_WORD]
  22 +#if defined (__GNUC__) || defined (__GNUG__)
  23 +                   __attribute__ ((aligned(4)))
  24 +#endif
  25 +                   = {0};
  26
  27     /* read offset */
  28     cpb2w (&cram_offset, &bbd_cram->pData[0], sizeof (IFX_uint16_t));
  29 --- a/src/drv_vmmc_danube.h
  30 +++ b/src/drv_vmmc_danube.h
  31 @@ -15,56 +15,18 @@
  32  */
  33
  34  #if defined SYSTEM_DANUBE
  35 -#include <asm/ifx/ifx_gpio.h>
  36 +#include <lantiq_soc.h>
  37 +
  38  #else
  39  #error no system selected
  40  #endif
  41
  42 -#define VMMC_TAPI_GPIO_MODULE_ID                        IFX_GPIO_MODULE_TAPI_VMMC
  43 +#define VMMC_TAPI_GPIO_MODULE_ID             IFX_GPIO_MODULE_TAPI_VMMC
  44  /**
  45
  46  */
  47  #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
  48  do { \
  49 -   ret = VMMC_statusOk; \
  50 -   /* Reserve P0.0 as TDM/FSC */ \
  51 -   if (!GPIOreserved) \
  52 -      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
  53 -   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
  54 -   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
  55 -   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
  56 -   \
  57 -   /* Reserve P1.9 as TDM/DO */ \
  58 -   if (!GPIOreserved) \
  59 -      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
  60 -   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
  61 -   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
  62 -   ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
  63 -   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
  64 -   \
  65 -   /* Reserve P1.10 as TDM/DI */ \
  66 -   if (!GPIOreserved) \
  67 -      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
  68 -   ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
  69 -   ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID);\
  70 -   ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
  71 -   \
  72 -   /* Reserve P1.11 as TDM/DCL */ \
  73 -   if (!GPIOreserved) \
  74 -      ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
  75 -   ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
  76 -   ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
  77 -   ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
  78 -   \
  79 -   if (mode == 2) { \
  80 -      /* TDM/FSC+DCL Master */ \
  81 -      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
  82 -      ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
  83 -   } else { \
  84 -      /* TDM/FSC+DCL Slave */ \
  85 -      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
  86 -      ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
  87 -   } \
  88  } while(0);
  89
  90  /**
  91 @@ -72,11 +34,6 @@ do { \
  92  */
  93  #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
  94  do { \
  95 -   ret = VMMC_statusOk; \
  96 -   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
  97 -   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
  98 -   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
  99 -   ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
 100  } while (0)
 101
 102  #endif /* _DRV_VMMC_AMAZON_S_H */
 103 --- a/src/drv_vmmc_init.c
 104 +++ b/src/drv_vmmc_init.c
 105 @@ -52,6 +52,14 @@
 106  #include "ifx_pmu.h"
 107  #endif /* PMU_SUPPORTED */
 108
 109 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 110 +#  define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
 111 +#  define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
 112 +#  define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
 113 +#  define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
 114 +#  define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
 115 +#  define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
 116 +#endif
 117
 118  /* ============================= */
 119  /* Local Macros & Definitions    */
 120 --- a/src/drv_vmmc_init_cap.c
 121 +++ b/src/drv_vmmc_init_cap.c
 122 @@ -22,6 +22,11 @@
 123  #include "drv_mps_vmmc.h"
 124  #include "drv_mps_vmmc_device.h"
 125
 126 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 127 +#  define IFX_MPS_CHIPID_VERSION_GET   IFXMIPS_MPS_CHIPID_VERSION_GET
 128 +#  define IFX_MPS_CHIPID               IFXMIPS_MPS_CHIPID
 129 +#endif
 130 +
 131  /* ============================= */
 132  /* Configuration defintions      */
 133  /* ============================= */
 134 --- a/src/mps/drv_mps_vmmc_common.c
 135 +++ b/src/mps/drv_mps_vmmc_common.c
 136 @@ -17,6 +17,7 @@
 137  /* Includes                      */
 138  /* ============================= */
 139  #include "drv_config.h"
 140 +#include "drv_vmmc_init.h"
 141
 142  #undef USE_PLAIN_VOICE_FIRMWARE
 143  #undef PRINT_ON_ERR_INTERRUPT
 144 @@ -35,8 +36,22 @@
 145  #include "ifxos_interrupt.h"
 146  #include "ifxos_time.h"
 147
 148 -#include <asm/ifx/ifx_regs.h>
 149 -#include <asm/ifx/ifx_gptu.h>
 150 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 151 +#  include <lantiq.h>
 152 +#  include <irq.h>
 153 +#  include <lantiq_timer.h>
 154 +
 155 +#  define ifx_gptu_timer_request    lq_request_timer
 156 +#  define ifx_gptu_timer_start      lq_start_timer
 157 +#  define ifx_gptu_countvalue_get   lq_get_count_value
 158 +#  define ifx_gptu_timer_free       lq_free_timer
 159 +
 160 +
 161 +#  define bsp_mask_and_ack_irq      ltq_mask_and_ack_irq
 162 +#else
 163 +#  include <asm/ifx/ifx_regs.h>
 164 +#  include <asm/ifx/ifx_gptu.h>
 165 +#endif
 166
 167  #include "drv_mps_vmmc.h"
 168  #include "drv_mps_vmmc_dbg.h"
 169 @@ -98,6 +113,9 @@ extern IFX_void_t bsp_mask_and_ack_irq (
 170  extern IFX_void_t mask_and_ack_danube_irq (IFX_uint32_t irq_nr);
 171
 172  #endif /* */
 173 +
 174 +extern void sys_hw_setup (void);
 175 +
 176  extern IFXOS_event_t fw_ready_evt;
 177  /* callback function to free all data buffers currently used by voice FW */
 178  IFX_void_t (*ifx_mps_bufman_freeall)(IFX_void_t) = IFX_NULL;
 179 @@ -201,7 +219,8 @@ IFX_boolean_t ifx_mps_ext_bufman ()
 180   */
 181  IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
 182  {
 183 -   IFX_uint32_t ptr, flags;
 184 +   IFXOS_INTSTAT flags;
 185 +   IFX_uint32_t ptr;
 186     IFX_int32_t index = fastbuf_index;
 187
 188     if (fastbuf_initialized == 0)
 189 @@ -255,7 +274,7 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_
 190   */
 191  IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
 192  {
 193 -   IFX_uint32_t flags;
 194 +   IFXOS_INTSTAT flags;
 195     IFX_int32_t index = fastbuf_index;
 196
 197     IFXOS_LOCKINT (flags);
 198 @@ -451,7 +470,7 @@ static mps_buffer_state_e ifx_mps_bufman
 199   */
 200  static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
 201  {
 202 -   IFX_uint32_t flags;
 203 +   IFXOS_INTSTAT flags;
 204
 205     if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
 206     {
 207 @@ -478,7 +497,7 @@ static IFX_int32_t ifx_mps_bufman_inc_le
 208   */
 209  static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
 210  {
 211 -   IFX_uint32_t flags;
 212 +   IFXOS_INTSTAT flags;
 213
 214     if (mps_buffer.buf_level < value)
 215     {
 216 @@ -630,7 +649,7 @@ IFX_int32_t ifx_mps_bufman_buf_provide (
 217        mem_seg_ptr[i] =
 218           (IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) mps_buffer.
 219                                       malloc (segment_size, FASTBUF_FW_OWNED));
 220 -      if (mem_seg_ptr[i] == CPHYSADDR (IFX_NULL))
 221 +      if (mem_seg_ptr[i] == (IFX_uint32_t *)CPHYSADDR (IFX_NULL))
 222        {
 223           TRACE (MPS, DBG_LEVEL_HIGH,
 224                  ("%s(): cannot allocate buffer\n", __FUNCTION__));
 225 @@ -946,7 +965,7 @@ IFX_int32_t ifx_mps_common_open (mps_com
 226                                   mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
 227                                   IFX_boolean_t from_kernel)
 228  {
 229 -   IFX_uint32_t flags;
 230 +   IFXOS_INTSTAT flags;
 231
 232     IFXOS_LOCKINT (flags);
 233
 234 @@ -1062,7 +1081,7 @@ IFX_int32_t ifx_mps_common_close (mps_mb
 235  IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
 236  {
 237     IFX_int32_t count;
 238 -   IFX_uint32_t flags;
 239 +   IFXOS_INTSTAT flags;
 240
 241     IFXOS_LOCKINT (flags);
 242     IFXOS_BlockFree (pFW_img_data);
 243 @@ -1111,7 +1130,7 @@ IFX_uint32_t ifx_mps_init_structures (mp
 244
 245     /* Initialize MPS main structure */
 246     memset ((IFX_void_t *) pDev, 0, sizeof (mps_comm_dev));
 247 -   pDev->base_global = (mps_mbx_reg *) IFX_MPS_SRAM;
 248 +   pDev->base_global = (mps_mbx_reg *) IFXMIPS_MPS_SRAM;
 249     pDev->flags = 0x00000000;
 250     MBX_Memory = pDev->base_global;
 251
 252 @@ -1119,9 +1138,11 @@ IFX_uint32_t ifx_mps_init_structures (mp
 253        for MBX communication. These are: mailbox base address, mailbox size, *
 254        mailbox read index and mailbox write index. for command and voice
 255        mailbox, * upstream and downstream direction. */
 256 -   memset ((IFX_void_t *) MBX_Memory,   /* avoid to overwrite CPU boot
 257 -                                           registers */
 258 -           0, sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
 259 +   memset (
 260 +       /* avoid to overwrite CPU boot registers */
 261 +          (IFX_void_t *) MBX_Memory,
 262 +           0,
 263 +           sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
 264     MBX_Memory->MBX_UPSTR_CMD_BASE =
 265        (IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) MBX_UPSTRM_CMD_FIFO_BASE);
 266     MBX_Memory->MBX_UPSTR_CMD_SIZE = MBX_CMD_FIFO_SIZE;
 267 @@ -1558,7 +1579,7 @@ IFX_int32_t ifx_mps_mbx_read_message (mp
 268                                        IFX_uint32_t * bytes)
 269  {
 270     IFX_int32_t i, ret;
 271 -   IFX_uint32_t flags;
 272 +   IFXOS_INTSTAT flags;
 273
 274     IFXOS_LOCKINT (flags);
 275
 276 @@ -1768,7 +1789,7 @@ IFX_int32_t ifx_mps_mbx_write_message (m
 277  {
 278     mps_fifo *mbx;
 279     IFX_uint32_t i;
 280 -   IFX_uint32_t flags;
 281 +   IFXOS_INTSTAT flags;
 282     IFX_int32_t retval = -EAGAIN;
 283     IFX_int32_t retries = 0;
 284     IFX_uint32_t word = 0;
 285 @@ -2163,6 +2184,7 @@ IFX_int32_t ifx_mps_mbx_write_cmd (mps_m
 286        TRACE (MPS, DBG_LEVEL_HIGH,
 287               ("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
 288     }
 289 +
 290     return retval;
 291  }
 292
 293 @@ -2186,7 +2208,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
 294     mps_mbx_dev *mbx_dev;
 295     MbxMsg_s msg;
 296     IFX_uint32_t bytes_read = 0;
 297 -   IFX_uint32_t flags;
 298 +   IFXOS_INTSTAT flags;
 299     IFX_int32_t ret;
 300
 301     /* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
 302 @@ -2277,7 +2299,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
 303           {
 304              ifx_mps_bufman_dec_level (1);
 305              if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
 306 -                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
 307 +                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
 308              {
 309                 IFXOS_LockRelease (pMPSDev->provide_buffer);
 310              }
 311 @@ -2320,7 +2342,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
 312  #endif /* CONFIG_PROC_FS */
 313              ifx_mps_bufman_dec_level (1);
 314              if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
 315 -                (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
 316 +                ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
 317              {
 318                 IFXOS_LockRelease (pMPSDev->provide_buffer);
 319              }
 320 @@ -2350,7 +2372,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
 321  IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
 322  {
 323     mps_fifo *mbx;
 324 -   IFX_uint32_t flags;
 325 +   IFXOS_INTSTAT flags;
 326
 327     /* set pointer to upstream command mailbox */
 328     mbx = &(pMPSDev->cmd_upstrm_fifo);
 329 @@ -2398,7 +2420,7 @@ IFX_void_t ifx_mps_mbx_event_upstream (I
 330     mps_event_msg msg;
 331     IFX_int32_t length = 0;
 332     IFX_int32_t read_length = 0;
 333 -   IFX_uint32_t flags;
 334 +   IFXOS_INTSTAT flags;
 335
 336     /* set pointer to upstream event mailbox */
 337     mbx = &(pMPSDev->event_upstrm_fifo);
 338 @@ -2613,6 +2635,7 @@ IFX_void_t ifx_mps_enable_mailbox_int ()
 339  #endif
 340
 341     *IFX_MPS_AD0ENR = Ad0Reg.val;
 342 +
 343  }
 344
 345  /**
 346 @@ -2641,7 +2664,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (
 347  */
 348  IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
 349  {
 350 -   IFX_uint32_t flags;
 351 +   IFXOS_INTSTAT flags;
 352     MPS_Ad0Reg_u Ad0Reg;
 353
 354     IFXOS_LOCKINT (flags);
 355 @@ -2667,7 +2690,7 @@ IFX_void_t ifx_mps_dd_mbx_int_enable (IF
 356  */
 357  IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
 358  {
 359 -   IFX_uint32_t flags;
 360 +   IFXOS_INTSTAT flags;
 361     MPS_Ad0Reg_u Ad0Reg;
 362
 363     IFXOS_LOCKINT (flags);
 364 @@ -2732,7 +2755,6 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
 365  #else /* */
 366     mask_and_ack_danube_irq (irq);
 367  #endif /* */
 368 -
 369     /* FW is up and ready to process commands */
 370     if (MPS_Ad0StatusReg.fld.dl_end)
 371     {
 372 @@ -2794,6 +2816,7 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
 373        }
 374     }
 375
 376 +
 377     if (MPS_Ad0StatusReg.fld.du_mbx)
 378     {
 379  #ifdef CONFIG_PROC_FS
 380 @@ -2938,12 +2961,12 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t
 381     IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;
 382     /* handle only enabled interrupts */
 383     MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];
 384 -
 385  #ifdef LINUX_2_6
 386     bsp_mask_and_ack_irq (irq);
 387  #else /* */
 388     mask_and_ack_danube_irq (irq);
 389  #endif /* */
 390 +
 391     pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;
 392  #ifdef PRINT_ON_ERR_INTERRUPT
 393     if (MPS_VCStatusReg.fld.rcv_ov)
 394 @@ -3087,7 +3110,8 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_
 395   */
 396  IFX_return_t ifx_mps_init_gpt ()
 397  {
 398 -   IFX_uint32_t flags, timer_flags, timer, loops = 0;
 399 +   unsigned long flags;
 400 +   IFX_uint32_t timer_flags, timer, loops = 0;
 401     IFX_ulong_t count;
 402  #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 403     timer = TIMER1A;
 404 @@ -3160,6 +3184,7 @@ IFX_void_t ifx_mps_shutdown_gpt (IFX_voi
 405  #else /* Danube */
 406     timer = TIMER1B;
 407  #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
 408 +
 409     ifx_gptu_timer_free (timer);
 410  }
 411
 412 --- a/src/mps/drv_mps_vmmc_danube.c
 413 +++ b/src/mps/drv_mps_vmmc_danube.c
 414 @@ -32,9 +32,21 @@
 415  #include "ifxos_select.h"
 416  #include "ifxos_interrupt.h"
 417
 418 -#include <asm/ifx/ifx_regs.h>
 419 -#include <asm/ifx/ifx_gpio.h>
 420 -#include <asm/ifx/common_routines.h>
 421 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 422 +#  include <lantiq.h>
 423 +#  include <irq.h>
 424 +#  include <lantiq_timer.h>
 425 +#  include <linux/dma-mapping.h>
 426 +
 427 +
 428 +# define LQ_RCU_RST            ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
 429 +#define IFX_RCU_RST_REQ_CPU1             (1 << 3)
 430 +#  define IFX_RCU_RST_REQ        LQ_RCU_RST
 431 +#else
 432 +#  include <asm/ifx/ifx_regs.h>
 433 +#  include <asm/ifx_vpe.h>
 434 +#  include <asm/ifx/ifx_gpio.h>
 435 +#endif
 436
 437  #include "drv_mps_vmmc.h"
 438  #include "drv_mps_vmmc_dbg.h"
 439 @@ -71,6 +83,20 @@ IFX_void_t ifx_mps_release (IFX_void_t);
 440  /* Local function definition     */
 441  /* ============================= */
 442
 443 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 444 +IFX_uint32_t ifx_get_cp1_size(IFX_void_t)
 445 +{
 446 +       return 1;
 447 +}
 448 +
 449 +unsigned int *ltq_get_cp1_base(void);
 450 +
 451 +IFX_uint32_t *ifx_get_cp1_base(IFX_void_t)
 452 +{
 453 +       return ltq_get_cp1_base();
 454 +}
 455 +#endif
 456 +
 457  /******************************************************************************
 458   * DANUBE Specific Routines
 459   ******************************************************************************/
 460 @@ -130,6 +156,15 @@ IFX_int32_t ifx_mps_download_firmware (m
 461     }
 462
 463     /* check if FW image fits in available memory space */
 464 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 465 +   if (mem > ifx_get_cp1_size()<<20)
 466 +   {
 467 +      TRACE (MPS, DBG_LEVEL_HIGH,
 468 +      ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
 469 +                 __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20));
 470 +      return IFX_ERROR;
 471 +   }
 472 +#else
 473     if (mem > ifx_get_cp1_size())
 474     {
 475        TRACE (MPS, DBG_LEVEL_HIGH,
 476 @@ -137,6 +172,7 @@ IFX_int32_t ifx_mps_download_firmware (m
 477                   __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
 478        return IFX_ERROR;
 479     }
 480 +#endif
 481
 482     /* reset the driver */
 483     ifx_mps_reset ();
 484 @@ -357,7 +393,7 @@ IFX_void_t ifx_mps_release (IFX_void_t)
 485   */
 486  IFX_void_t ifx_mps_wdog_expiry()
 487  {
 488 -   IFX_uint32_t flags;
 489 +   unsigned long flags;
 490
 491     IFXOS_LOCKINT (flags);
 492     /* recalculate and compare the firmware checksum */
 493 --- a/src/mps/drv_mps_vmmc_device.h
 494 +++ b/src/mps/drv_mps_vmmc_device.h
 495 @@ -16,8 +16,58 @@
 496                   declarations.
 497  *******************************************************************************/
 498
 499 -#include <asm/ifx/ifx_regs.h>
 500 -#include <asm/ifx_vpe.h>
 501 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 502 +#  include <lantiq.h>
 503 +#  include <irq.h>
 504 +#  include <lantiq_soc.h>
 505 +#  include <gpio.h>
 506 +#define IFXMIPS_MPS_SRAM               ((u32 *)(KSEG1 + 0x1F200000))
 507 +#define IFXMIPS_MPS_BASE_ADDR          (KSEG1 + 0x1F107000)
 508 +#define IFXMIPS_MPS_CHIPID             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
 509 +#define IFXMIPS_MPS_VC0ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
 510 +#define IFXMIPS_MPS_RVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
 511 +#define IFXMIPS_MPS_CVC0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
 512 +#define IFXMIPS_MPS_CVC1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
 513 +#define IFXMIPS_MPS_CVC2SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
 514 +#define IFXMIPS_MPS_CVC3SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
 515 +#define IFXMIPS_MPS_RAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
 516 +#define IFXMIPS_MPS_RAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
 517 +#define IFXMIPS_MPS_SAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
 518 +#define IFXMIPS_MPS_SAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
 519 +#define IFXMIPS_MPS_CAD0SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
 520 +#define IFXMIPS_MPS_CAD1SR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
 521 +#define IFXMIPS_MPS_AD0ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
 522 +#define IFXMIPS_MPS_AD1ENR             ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
 523 +
 524 +#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)  (((value) >> 28) & ((1 << 4) - 1))
 525 +#define IFXMIPS_MPS_CHIPID_VERSION_SET(value)  ((((1 << 4) - 1) & (value)) << 28)
 526 +#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)  (((value) >> 12) & ((1 << 16) - 1))
 527 +#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)  ((((1 << 16) - 1) & (value)) << 12)
 528 +#define IFXMIPS_MPS_CHIPID_MANID_GET(value)    (((value) >> 1) & ((1 << 10) - 1))
 529 +#define IFXMIPS_MPS_CHIPID_MANID_SET(value)    ((((1 << 10) - 1) & (value)) << 1)
 530 +#else
 531 +#  include <asm/ifx/ifx_regs.h>
 532 +#  include <asm/ifx_vpe.h>
 533 +#endif
 534 +/* MPS register */
 535 +#  define IFX_MPS_AD0ENR      IFXMIPS_MPS_AD0ENR
 536 +#  define IFX_MPS_AD1ENR      IFXMIPS_MPS_AD1ENR
 537 +#  define IFX_MPS_RAD0SR      IFXMIPS_MPS_RAD0SR
 538 +#  define IFX_MPS_RAD1SR      IFXMIPS_MPS_RAD1SR
 539 +#  define IFX_MPS_VC0ENR      IFXMIPS_MPS_VC0ENR
 540 +#  define IFX_MPS_RVC0SR      IFXMIPS_MPS_RVC0SR
 541 +#  define IFX_MPS_CVC0SR      IFXMIPS_MPS_CVC0SR
 542 +#  define IFX_MPS_CAD0SR      IFXMIPS_MPS_CAD0SR
 543 +#  define IFX_MPS_CAD1SR      IFXMIPS_MPS_CAD1SR
 544 +#  define IFX_MPS_CVC1SR      IFXMIPS_MPS_CVC1SR
 545 +#  define IFX_MPS_CVC2SR      IFXMIPS_MPS_CVC2SR
 546 +#  define IFX_MPS_CVC3SR      IFXMIPS_MPS_CVC3SR
 547 +#  define IFX_MPS_SAD0SR      IFXMIPS_MPS_SAD0SR
 548 +/* interrupt vectors */
 549 +#  define INT_NUM_IM4_IRL14   (INT_NUM_IM4_IRL0 + 14)
 550 +#  define INT_NUM_IM4_IRL18   (INT_NUM_IM4_IRL0 + 18)
 551 +#  define INT_NUM_IM4_IRL19   (INT_NUM_IM4_IRL0 + 19)
 552 +#  define IFX_ICU_IM4_IER     IFXMIPS_ICU_IM4_IER
 553
 554  /* ============================= */
 555  /* MPS Common defines            */
 556 @@ -26,32 +76,28 @@
 557  #define MPS_BASEADDRESS 0xBF107000
 558  #define MPS_RAD0SR      MPS_BASEADDRESS + 0x0004
 559
 560 -#define MPS_RAD0SR_DU   (1<<0)
 561 -#define MPS_RAD0SR_CU   (1<<1)
 562 -
 563  #define MBX_BASEADDRESS 0xBF200000
 564  #define VCPU_BASEADDRESS 0xBF208000     /* 0xBF108000 */
 565  /*---------------------------------------------------------------------------*/
 566 +#if !defined(CONFIG_LANTIQ)
 567 +/* enabling interrupts is done with request_irq by the BSP
 568 +   The related code should not be needed anymore */
 569  #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 570  /* TODO: doublecheck - IM4 or different! */
 571  #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;
 572  #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;
 573 -#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;
 574 -#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */
 575  #else /* Danube */
 576  /* TODO: possibly needs to be changed to IM4 !!!!!! */
 577  #ifdef LINUX_2_6
 578  #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;
 579  #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;
 580 -#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;
 581 -#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */
 582  #else /* */
 583  #define MPS_INTERRUPTS_ENABLE(X)  *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) |= X;
 584  #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) &= ~X;
 585 -#define MPS_INTERRUPTS_CLEAR(X)   *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_ISR) = X;
 586 -#define MPS_INTERRUPTS_SET(X)     *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IRSR) = X;/* |= ? */
 587  #endif /* LINUX_2_6 */
 588  #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
 589 +#endif /* !defined(CONFIG_LANTIQ) */
 590 +
 591  /*---------------------------------------------------------------------------*/
 592
 593  /*---------------------------------------------------------------------------*/
 594 @@ -142,53 +188,9 @@
 595  #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
 596  /* ***** Amazon-S specific defines ***** */
 597  #define IFX_MPS_Base      AMAZON_S_MPS
 598 -
 599 -//#define IFX_MPS_CHIPID              AMAZON_S_MPS_CHIPID
 600 -//#define IFX_MPS_CHIPID_VERSION_GET  AMAZON_S_MPS_CHIPID_VERSION_GET
 601 -
 602 -//#define IFX_MPS_AD0ENR    AMAZON_S_MPS_AD0ENR
 603 -//#define IFX_MPS_AD1ENR    AMAZON_S_MPS_AD1ENR
 604 -//#define IFX_MPS_VC0ENR    AMAZON_S_MPS_VC0ENR
 605 -//#define IFX_MPS_SAD0SR    AMAZON_S_MPS_SAD0SR
 606 -//#define IFX_MPS_RAD0SR    AMAZON_S_MPS_RAD0SR
 607 -//#define IFX_MPS_CAD0SR    AMAZON_S_MPS_CAD0SR
 608 -//#define IFX_MPS_RAD1SR    AMAZON_S_MPS_RAD1SR
 609 -//#define IFX_MPS_CAD1SR    AMAZON_S_MPS_CAD1SR
 610 -//#define IFX_MPS_RVC0SR    AMAZON_S_MPS_RVC0SR
 611 -//#define IFX_MPS_CVC0SR    AMAZON_S_MPS_CVC0SR
 612 -//#define IFX_MPS_CVC1SR    AMAZON_S_MPS_CVC1SR
 613 -//#define IFX_MPS_CVC2SR    AMAZON_S_MPS_CVC2SR
 614 -//#define IFX_MPS_CVC3SR    AMAZON_S_MPS_CVC3SR
 615 -
 616 -//#define IFX_MPS_SRAM      AMAZON_S_MPS_SRAM
 617  #else /* */
 618  /* ***** DANUBE specific defines ***** */
 619  #define IFX_MPS_Base      DANUBE_MPS
 620 -
 621 -//#define IFX_MPS_CHIPID    DANUBE_MPS_CHIPID
 622 -//#define IFX_MPS_CHIPID_VERSION_GET  DANUBE_MPS_CHIPID_VERSION_GET
 623 -//#define IFX_MPS_CHIPID_VERSION_SET  DANUBE_MPS_CHIPID_VERSION_SET
 624 -//#define IFX_MPS_CHIPID_PARTNUM_GET  DANUBE_MPS_CHIPID_PARTNUM_GET
 625 -//#define IFX_MPS_CHIPID_PARTNUM_SET  DANUBE_MPS_CHIPID_PARTNUM_SET
 626 -//#define IFX_MPS_CHIPID_MANID_GET    DANUBE_MPS_CHIPID_MANID_GET
 627 -//#define IFX_MPS_CHIPID_MANID_SET    DANUBE_MPS_CHIPID_MANID_SET
 628 -//#define IFX_MPS_SUBVER              DANUBE_MPS_SUBVER
 629 -
 630 -//#define IFX_MPS_AD0ENR    DANUBE_MPS_AD0ENR
 631 -//#define IFX_MPS_AD1ENR    DANUBE_MPS_AD1ENR
 632 -//#define IFX_MPS_VC0ENR    DANUBE_MPS_VC0ENR
 633 -//#define IFX_MPS_SAD0SR    DANUBE_MPS_SAD0SR
 634 -//#define IFX_MPS_RAD0SR    DANUBE_MPS_RAD0SR
 635 -//#define IFX_MPS_CAD0SR    DANUBE_MPS_CAD0SR
 636 -//#define IFX_MPS_RAD1SR    DANUBE_MPS_RAD1SR
 637 -//#define IFX_MPS_CAD1SR    DANUBE_MPS_CAD1SR
 638 -//#define IFX_MPS_RVC0SR    DANUBE_MPS_RVC0SR
 639 -//#define IFX_MPS_CVC0SR    DANUBE_MPS_CVC0SR
 640 -//#define IFX_MPS_CVC1SR    DANUBE_MPS_CVC1SR
 641 -//#define IFX_MPS_CVC2SR    DANUBE_MPS_CVC2SR
 642 -//#define IFX_MPS_CVC3SR    DANUBE_MPS_CVC3SR
 643 -
 644 -//#define IFX_MPS_SRAM      DANUBE_MPS_SRAM
 645  #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
 646  typedef enum
 647  {
 648 --- a/src/mps/drv_mps_vmmc_linux.c
 649 +++ b/src/mps/drv_mps_vmmc_linux.c
 650 @@ -19,11 +19,16 @@
 651  #include "drv_config.h"
 652
 653  #include "drv_mps_version.h"
 654 +#include <linux/version.h>
 655
 656  #ifdef CONFIG_DEBUG_MINI_BOOT
 657  #define IKOS_MINI_BOOT
 658  #endif /* */
 659 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
 660 +#include <linux/autoconf.h>
 661 +#else
 662  #include <generated/autoconf.h>
 663 +#endif
 664  #include <linux/module.h>
 665  #include <linux/init.h>
 666  #include <linux/poll.h>
 667 @@ -34,16 +39,27 @@
 668  #include <linux/delay.h>
 669  #include <linux/interrupt.h>
 670  #ifdef LINUX_2_6
 671 +#ifndef UTS_RELEASE
 672 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)
 673 +#include <linux/utsrelease.h>
 674 +#else
 675  #include <generated/utsrelease.h>
 676 +#endif
 677 +#endif /* UTC_RELEASE */
 678  #else /* */
 679  #include <linux/uts.h>
 680  #include <linux/moduleparam.h>
 681  #endif /* */
 682
 683 -
 684 -#include <asm/ifx/irq.h>
 685 -#include <asm/ifx/ifx_regs.h>
 686 -#include <asm/ifx_vpe.h>
 687 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
 688 +#include "drv_vmmc_init.h"
 689 +#  include <lantiq.h>
 690 +#  include <irq.h>
 691 +#else
 692 +#  include <asm/ifx/irq.h>
 693 +#  include <asm/ifx/ifx_regs.h>
 694 +#  include <asm/ifx_vpe.h>
 695 +#endif
 696
 697  /* lib_ifxos headers */
 698  #include "ifx_types.h"
 699 @@ -915,7 +931,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode
 700  #endif /* MPS_FIFO_BLOCKING_WRITE */
 701        case FIO_MPS_GET_STATUS:
 702           {
 703 -            IFX_uint32_t flags;
 704 +            unsigned long flags;
 705
 706              /* get the status of the channel */
 707              if (!from_kernel)
 708 @@ -949,7 +965,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode
 709  #if CONFIG_MPS_HISTORY_SIZE > 0
 710        case FIO_MPS_GET_CMD_HISTORY:
 711           {
 712 -            IFX_uint32_t flags;
 713 +            unsigned long flags;
 714
 715              if (from_kernel)
 716              {
 717 @@ -1641,6 +1657,7 @@ IFX_int32_t ifx_mps_get_status_proc (IFX
 718           sprintf (buf + len, "   minLv: \t  %8d\n",
 719                    ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
 720     }
 721 +
 722     return len;
 723  }
 724
 725 @@ -2247,9 +2264,11 @@ IFX_int32_t __init ifx_mps_init_module (
 726           return result;
 727     }
 728
 729 +#if !defined(CONFIG_LANTIQ)
 730 +   /** \todo This is handled already with request_irq, remove */
 731     /* Enable all MPS Interrupts at ICU0 */
 732     MPS_INTERRUPTS_ENABLE (0x0000FF80);
 733 -
 734 +#endif
 735     /* enable mailbox interrupts */
 736     ifx_mps_enable_mailbox_int ();
 737     /* init FW ready event */
 738 @@ -2377,9 +2396,11 @@ ifx_mps_cleanup_module (IFX_void_t)
 739     /* disable mailbox interrupts */
 740     ifx_mps_disable_mailbox_int ();
 741
 742 +#if !defined(CONFIG_LANTIQ)
 743     /* disable Interrupts at ICU0 */
 744 -   MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4); /* Disable DFE/AFE 0 Interrupts
 745 -                                                 */
 746 +   /* Disable DFE/AFE 0 Interrupts*/
 747 +   MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4);
 748 +#endif
 749
 750     /* disable all MPS interrupts */
 751     ifx_mps_disable_all_int ();
 752 --- a/src/drv_vmmc_ioctl.c
 753 +++ b/src/drv_vmmc_ioctl.c
 754 @@ -18,6 +18,7 @@
 755  /* Includes                      */
 756  /* ============================= */
 757  #include "drv_api.h"
 758 +#include "drv_vmmc_init.h"
 759  #include "drv_vmmc_api.h"
 760  #include "drv_vmmc_bbd.h"
 761