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kernel: add a default for CONFIG_NEW_GPIO
[openwrt.git] / target / linux / ixp4xx / patches-2.6.23 / 200-npe_driver.patch
1 diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
2 index 4de432e..c4c810b 100644
3 --- a/arch/arm/kernel/setup.c
4 +++ b/arch/arm/kernel/setup.c
5 @@ -61,6 +61,7 @@ extern int root_mountflags;
6 extern void _stext, _text, _etext, __data_start, _edata, _end;
7
8 unsigned int processor_id;
9 +EXPORT_SYMBOL(processor_id);
10 unsigned int __machine_arch_type;
11 EXPORT_SYMBOL(__machine_arch_type);
12
13 diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
14 index 61b2dfc..e774447 100644
15 --- a/arch/arm/mach-ixp4xx/Kconfig
16 +++ b/arch/arm/mach-ixp4xx/Kconfig
17 @@ -189,6 +189,20 @@ config IXP4XX_INDIRECT_PCI
18 need to use the indirect method instead. If you don't know
19 what you need, leave this option unselected.
20
21 +config IXP4XX_QMGR
22 + tristate "IXP4xx Queue Manager support"
23 + help
24 + This driver supports IXP4xx built-in hardware queue manager
25 + and is automatically selected by Ethernet and HSS drivers.
26 +
27 +config IXP4XX_NPE
28 + tristate "IXP4xx Network Processor Engine support"
29 + select HOTPLUG
30 + select FW_LOADER
31 + help
32 + This driver supports IXP4xx built-in network coprocessors
33 + and is automatically selected by Ethernet and HSS drivers.
34 +
35 endmenu
36
37 endif
38 diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
39 index 77e00ad..4bb97e1 100644
40 --- a/arch/arm/mach-ixp4xx/Makefile
41 +++ b/arch/arm/mach-ixp4xx/Makefile
42 @@ -30,3 +30,5 @@ obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
43 obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
44
45 obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
46 +obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
47 +obj-$(CONFIG_IXP4XX_NPE) += ixp4xx_npe.o
48 diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
49 index d5008d8..10b41c6 100644
50 --- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
51 +++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
52 @@ -177,6 +177,31 @@ static struct platform_device ixdp425_uart = {
53 .resource = ixdp425_uart_resources
54 };
55
56 +/* Built-in 10/100 Ethernet MAC interfaces */
57 +static struct eth_plat_info ixdp425_plat_eth[] = {
58 + {
59 + .phy = 0,
60 + .rxq = 3,
61 + .txreadyq = 20,
62 + }, {
63 + .phy = 1,
64 + .rxq = 4,
65 + .txreadyq = 21,
66 + }
67 +};
68 +
69 +static struct platform_device ixdp425_eth[] = {
70 + {
71 + .name = "ixp4xx_eth",
72 + .id = IXP4XX_ETH_NPEB,
73 + .dev.platform_data = ixdp425_plat_eth,
74 + }, {
75 + .name = "ixp4xx_eth",
76 + .id = IXP4XX_ETH_NPEC,
77 + .dev.platform_data = ixdp425_plat_eth + 1,
78 + }
79 +};
80 +
81 static struct platform_device *ixdp425_devices[] __initdata = {
82 &ixdp425_i2c_controller,
83 &ixdp425_flash,
84 @@ -184,7 +209,9 @@ static struct platform_device *ixdp425_devices[] __initdata = {
85 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
86 &ixdp425_flash_nand,
87 #endif
88 - &ixdp425_uart
89 + &ixdp425_uart,
90 + &ixdp425_eth[0],
91 + &ixdp425_eth[1],
92 };
93
94 static void __init ixdp425_init(void)
95 diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
96 new file mode 100644
97 index 0000000..83c137e
98 --- /dev/null
99 +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
100 @@ -0,0 +1,741 @@
101 +/*
102 + * Intel IXP4xx Network Processor Engine driver for Linux
103 + *
104 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
105 + *
106 + * This program is free software; you can redistribute it and/or modify it
107 + * under the terms of version 2 of the GNU General Public License
108 + * as published by the Free Software Foundation.
109 + *
110 + * The code is based on publicly available information:
111 + * - Intel IXP4xx Developer's Manual and other e-papers
112 + * - Intel IXP400 Access Library Software (BSD license)
113 + * - previous works by Christian Hohnstaedt <chohnstaedt@innominate.com>
114 + * Thanks, Christian.
115 + */
116 +
117 +#include <linux/delay.h>
118 +#include <linux/dma-mapping.h>
119 +#include <linux/firmware.h>
120 +#include <linux/io.h>
121 +#include <linux/kernel.h>
122 +#include <linux/module.h>
123 +#include <linux/slab.h>
124 +#include <asm/arch/npe.h>
125 +
126 +#define DEBUG_MSG 0
127 +#define DEBUG_FW 0
128 +
129 +#define NPE_COUNT 3
130 +#define MAX_RETRIES 1000 /* microseconds */
131 +#define NPE_42X_DATA_SIZE 0x800 /* in dwords */
132 +#define NPE_46X_DATA_SIZE 0x1000
133 +#define NPE_A_42X_INSTR_SIZE 0x1000
134 +#define NPE_B_AND_C_42X_INSTR_SIZE 0x800
135 +#define NPE_46X_INSTR_SIZE 0x1000
136 +#define REGS_SIZE 0x1000
137 +
138 +#define NPE_PHYS_REG 32
139 +
140 +#define FW_MAGIC 0xFEEDF00D
141 +#define FW_BLOCK_TYPE_INSTR 0x0
142 +#define FW_BLOCK_TYPE_DATA 0x1
143 +#define FW_BLOCK_TYPE_EOF 0xF
144 +
145 +/* NPE exec status (read) and command (write) */
146 +#define CMD_NPE_STEP 0x01
147 +#define CMD_NPE_START 0x02
148 +#define CMD_NPE_STOP 0x03
149 +#define CMD_NPE_CLR_PIPE 0x04
150 +#define CMD_CLR_PROFILE_CNT 0x0C
151 +#define CMD_RD_INS_MEM 0x10 /* instruction memory */
152 +#define CMD_WR_INS_MEM 0x11
153 +#define CMD_RD_DATA_MEM 0x12 /* data memory */
154 +#define CMD_WR_DATA_MEM 0x13
155 +#define CMD_RD_ECS_REG 0x14 /* exec access register */
156 +#define CMD_WR_ECS_REG 0x15
157 +
158 +#define STAT_RUN 0x80000000
159 +#define STAT_STOP 0x40000000
160 +#define STAT_CLEAR 0x20000000
161 +#define STAT_ECS_K 0x00800000 /* pipeline clean */
162 +
163 +#define NPE_STEVT 0x1B
164 +#define NPE_STARTPC 0x1C
165 +#define NPE_REGMAP 0x1E
166 +#define NPE_CINDEX 0x1F
167 +
168 +#define INSTR_WR_REG_SHORT 0x0000C000
169 +#define INSTR_WR_REG_BYTE 0x00004000
170 +#define INSTR_RD_FIFO 0x0F888220
171 +#define INSTR_RESET_MBOX 0x0FAC8210
172 +
173 +#define ECS_BG_CTXT_REG_0 0x00 /* Background Executing Context */
174 +#define ECS_BG_CTXT_REG_1 0x01 /* Stack level */
175 +#define ECS_BG_CTXT_REG_2 0x02
176 +#define ECS_PRI_1_CTXT_REG_0 0x04 /* Priority 1 Executing Context */
177 +#define ECS_PRI_1_CTXT_REG_1 0x05 /* Stack level */
178 +#define ECS_PRI_1_CTXT_REG_2 0x06
179 +#define ECS_PRI_2_CTXT_REG_0 0x08 /* Priority 2 Executing Context */
180 +#define ECS_PRI_2_CTXT_REG_1 0x09 /* Stack level */
181 +#define ECS_PRI_2_CTXT_REG_2 0x0A
182 +#define ECS_DBG_CTXT_REG_0 0x0C /* Debug Executing Context */
183 +#define ECS_DBG_CTXT_REG_1 0x0D /* Stack level */
184 +#define ECS_DBG_CTXT_REG_2 0x0E
185 +#define ECS_INSTRUCT_REG 0x11 /* NPE Instruction Register */
186 +
187 +#define ECS_REG_0_ACTIVE 0x80000000 /* all levels */
188 +#define ECS_REG_0_NEXTPC_MASK 0x1FFF0000 /* BG/PRI1/PRI2 levels */
189 +#define ECS_REG_0_LDUR_BITS 8
190 +#define ECS_REG_0_LDUR_MASK 0x00000700 /* all levels */
191 +#define ECS_REG_1_CCTXT_BITS 16
192 +#define ECS_REG_1_CCTXT_MASK 0x000F0000 /* all levels */
193 +#define ECS_REG_1_SELCTXT_BITS 0
194 +#define ECS_REG_1_SELCTXT_MASK 0x0000000F /* all levels */
195 +#define ECS_DBG_REG_2_IF 0x00100000 /* debug level */
196 +#define ECS_DBG_REG_2_IE 0x00080000 /* debug level */
197 +
198 +/* NPE watchpoint_fifo register bit */
199 +#define WFIFO_VALID 0x80000000
200 +
201 +/* NPE messaging_status register bit definitions */
202 +#define MSGSTAT_OFNE 0x00010000 /* OutFifoNotEmpty */
203 +#define MSGSTAT_IFNF 0x00020000 /* InFifoNotFull */
204 +#define MSGSTAT_OFNF 0x00040000 /* OutFifoNotFull */
205 +#define MSGSTAT_IFNE 0x00080000 /* InFifoNotEmpty */
206 +#define MSGSTAT_MBINT 0x00100000 /* Mailbox interrupt */
207 +#define MSGSTAT_IFINT 0x00200000 /* InFifo interrupt */
208 +#define MSGSTAT_OFINT 0x00400000 /* OutFifo interrupt */
209 +#define MSGSTAT_WFINT 0x00800000 /* WatchFifo interrupt */
210 +
211 +/* NPE messaging_control register bit definitions */
212 +#define MSGCTL_OUT_FIFO 0x00010000 /* enable output FIFO */
213 +#define MSGCTL_IN_FIFO 0x00020000 /* enable input FIFO */
214 +#define MSGCTL_OUT_FIFO_WRITE 0x01000000 /* enable FIFO + WRITE */
215 +#define MSGCTL_IN_FIFO_WRITE 0x02000000
216 +
217 +/* NPE mailbox_status value for reset */
218 +#define RESET_MBOX_STAT 0x0000F0F0
219 +
220 +const char *npe_names[] = { "NPE-A", "NPE-B", "NPE-C" };
221 +
222 +#define print_npe(pri, npe, fmt, ...) \
223 + printk(pri "%s: " fmt, npe_name(npe), ## __VA_ARGS__)
224 +
225 +#if DEBUG_MSG
226 +#define debug_msg(npe, fmt, ...) \
227 + print_npe(KERN_DEBUG, npe, fmt, ## __VA_ARGS__)
228 +#else
229 +#define debug_msg(npe, fmt, ...)
230 +#endif
231 +
232 +static struct {
233 + u32 reg, val;
234 +} ecs_reset[] = {
235 + { ECS_BG_CTXT_REG_0, 0xA0000000 },
236 + { ECS_BG_CTXT_REG_1, 0x01000000 },
237 + { ECS_BG_CTXT_REG_2, 0x00008000 },
238 + { ECS_PRI_1_CTXT_REG_0, 0x20000080 },
239 + { ECS_PRI_1_CTXT_REG_1, 0x01000000 },
240 + { ECS_PRI_1_CTXT_REG_2, 0x00008000 },
241 + { ECS_PRI_2_CTXT_REG_0, 0x20000080 },
242 + { ECS_PRI_2_CTXT_REG_1, 0x01000000 },
243 + { ECS_PRI_2_CTXT_REG_2, 0x00008000 },
244 + { ECS_DBG_CTXT_REG_0, 0x20000000 },
245 + { ECS_DBG_CTXT_REG_1, 0x00000000 },
246 + { ECS_DBG_CTXT_REG_2, 0x001E0000 },
247 + { ECS_INSTRUCT_REG, 0x1003C00F },
248 +};
249 +
250 +static struct npe npe_tab[NPE_COUNT] = {
251 + {
252 + .id = 0,
253 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEA_BASE_VIRT,
254 + .regs_phys = IXP4XX_NPEA_BASE_PHYS,
255 + }, {
256 + .id = 1,
257 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEB_BASE_VIRT,
258 + .regs_phys = IXP4XX_NPEB_BASE_PHYS,
259 + }, {
260 + .id = 2,
261 + .regs = (struct npe_regs __iomem *)IXP4XX_NPEC_BASE_VIRT,
262 + .regs_phys = IXP4XX_NPEC_BASE_PHYS,
263 + }
264 +};
265 +
266 +int npe_running(struct npe *npe)
267 +{
268 + return (__raw_readl(&npe->regs->exec_status_cmd) & STAT_RUN) != 0;
269 +}
270 +
271 +static void npe_cmd_write(struct npe *npe, u32 addr, int cmd, u32 data)
272 +{
273 + __raw_writel(data, &npe->regs->exec_data);
274 + __raw_writel(addr, &npe->regs->exec_addr);
275 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
276 +}
277 +
278 +static u32 npe_cmd_read(struct npe *npe, u32 addr, int cmd)
279 +{
280 + __raw_writel(addr, &npe->regs->exec_addr);
281 + __raw_writel(cmd, &npe->regs->exec_status_cmd);
282 + /* Iintroduce extra read cycles after issuing read command to NPE
283 + so that we read the register after the NPE has updated it.
284 + This is to overcome race condition between XScale and NPE */
285 + __raw_readl(&npe->regs->exec_data);
286 + __raw_readl(&npe->regs->exec_data);
287 + return __raw_readl(&npe->regs->exec_data);
288 +}
289 +
290 +static void npe_clear_active(struct npe *npe, u32 reg)
291 +{
292 + u32 val = npe_cmd_read(npe, reg, CMD_RD_ECS_REG);
293 + npe_cmd_write(npe, reg, CMD_WR_ECS_REG, val & ~ECS_REG_0_ACTIVE);
294 +}
295 +
296 +static void npe_start(struct npe *npe)
297 +{
298 + /* ensure only Background Context Stack Level is active */
299 + npe_clear_active(npe, ECS_PRI_1_CTXT_REG_0);
300 + npe_clear_active(npe, ECS_PRI_2_CTXT_REG_0);
301 + npe_clear_active(npe, ECS_DBG_CTXT_REG_0);
302 +
303 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
304 + __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd);
305 +}
306 +
307 +static void npe_stop(struct npe *npe)
308 +{
309 + __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd);
310 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/
311 +}
312 +
313 +static int __must_check npe_debug_instr(struct npe *npe, u32 instr, u32 ctx,
314 + u32 ldur)
315 +{
316 + u32 wc;
317 + int i;
318 +
319 + /* set the Active bit, and the LDUR, in the debug level */
320 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG,
321 + ECS_REG_0_ACTIVE | (ldur << ECS_REG_0_LDUR_BITS));
322 +
323 + /* set CCTXT at ECS DEBUG L3 to specify in which context to execute
324 + the instruction, and set SELCTXT at ECS DEBUG Level to specify
325 + which context store to access.
326 + Debug ECS Level Reg 1 has form 0x000n000n, where n = context number
327 + */
328 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_1, CMD_WR_ECS_REG,
329 + (ctx << ECS_REG_1_CCTXT_BITS) |
330 + (ctx << ECS_REG_1_SELCTXT_BITS));
331 +
332 + /* clear the pipeline */
333 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
334 +
335 + /* load NPE instruction into the instruction register */
336 + npe_cmd_write(npe, ECS_INSTRUCT_REG, CMD_WR_ECS_REG, instr);
337 +
338 + /* we need this value later to wait for completion of NPE execution
339 + step */
340 + wc = __raw_readl(&npe->regs->watch_count);
341 +
342 + /* issue a Step One command via the Execution Control register */
343 + __raw_writel(CMD_NPE_STEP, &npe->regs->exec_status_cmd);
344 +
345 + /* Watch Count register increments when NPE completes an instruction */
346 + for (i = 0; i < MAX_RETRIES; i++) {
347 + if (wc != __raw_readl(&npe->regs->watch_count))
348 + return 0;
349 + udelay(1);
350 + }
351 +
352 + print_npe(KERN_ERR, npe, "reset: npe_debug_instr(): timeout\n");
353 + return -ETIMEDOUT;
354 +}
355 +
356 +static int __must_check npe_logical_reg_write8(struct npe *npe, u32 addr,
357 + u8 val, u32 ctx)
358 +{
359 + /* here we build the NPE assembler instruction: mov8 d0, #0 */
360 + u32 instr = INSTR_WR_REG_BYTE | /* OpCode */
361 + addr << 9 | /* base Operand */
362 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
363 + (val & ~0x1F) << (18 - 5);/* higher 3 bits to CoProc instr. */
364 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
365 +}
366 +
367 +static int __must_check npe_logical_reg_write16(struct npe *npe, u32 addr,
368 + u16 val, u32 ctx)
369 +{
370 + /* here we build the NPE assembler instruction: mov16 d0, #0 */
371 + u32 instr = INSTR_WR_REG_SHORT | /* OpCode */
372 + addr << 9 | /* base Operand */
373 + (val & 0x1F) << 4 | /* lower 5 bits to immediate data */
374 + (val & ~0x1F) << (18 - 5);/* higher 11 bits to CoProc instr. */
375 + return npe_debug_instr(npe, instr, ctx, 1); /* execute it */
376 +}
377 +
378 +static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr,
379 + u32 val, u32 ctx)
380 +{
381 + /* write in 16 bit steps first the high and then the low value */
382 + if (npe_logical_reg_write16(npe, addr, val >> 16, ctx))
383 + return -ETIMEDOUT;
384 + return npe_logical_reg_write16(npe, addr + 2, val & 0xFFFF, ctx);
385 +}
386 +
387 +static int npe_reset(struct npe *npe)
388 +{
389 + u32 val, ctl, exec_count, ctx_reg2;
390 + int i;
391 +
392 + ctl = (__raw_readl(&npe->regs->messaging_control) | 0x3F000000) &
393 + 0x3F3FFFFF;
394 +
395 + /* disable parity interrupt */
396 + __raw_writel(ctl & 0x3F00FFFF, &npe->regs->messaging_control);
397 +
398 + /* pre exec - debug instruction */
399 + /* turn off the halt bit by clearing Execution Count register. */
400 + exec_count = __raw_readl(&npe->regs->exec_count);
401 + __raw_writel(0, &npe->regs->exec_count);
402 + /* ensure that IF and IE are on (temporarily), so that we don't end up
403 + stepping forever */
404 + ctx_reg2 = npe_cmd_read(npe, ECS_DBG_CTXT_REG_2, CMD_RD_ECS_REG);
405 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2 |
406 + ECS_DBG_REG_2_IF | ECS_DBG_REG_2_IE);
407 +
408 + /* clear the FIFOs */
409 + while (__raw_readl(&npe->regs->watchpoint_fifo) & WFIFO_VALID)
410 + ;
411 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE)
412 + /* read from the outFIFO until empty */
413 + print_npe(KERN_DEBUG, npe, "npe_reset: read FIFO = 0x%X\n",
414 + __raw_readl(&npe->regs->in_out_fifo));
415 +
416 + while (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)
417 + /* step execution of the NPE intruction to read inFIFO using
418 + the Debug Executing Context stack */
419 + if (npe_debug_instr(npe, INSTR_RD_FIFO, 0, 0))
420 + return -ETIMEDOUT;
421 +
422 + /* reset the mailbox reg from the XScale side */
423 + __raw_writel(RESET_MBOX_STAT, &npe->regs->mailbox_status);
424 + /* from NPE side */
425 + if (npe_debug_instr(npe, INSTR_RESET_MBOX, 0, 0))
426 + return -ETIMEDOUT;
427 +
428 + /* Reset the physical registers in the NPE register file */
429 + for (val = 0; val < NPE_PHYS_REG; val++) {
430 + if (npe_logical_reg_write16(npe, NPE_REGMAP, val >> 1, 0))
431 + return -ETIMEDOUT;
432 + /* address is either 0 or 4 */
433 + if (npe_logical_reg_write32(npe, (val & 1) * 4, 0, 0))
434 + return -ETIMEDOUT;
435 + }
436 +
437 + /* Reset the context store = each context's Context Store registers */
438 +
439 + /* Context 0 has no STARTPC. Instead, this value is used to set NextPC
440 + for Background ECS, to set where NPE starts executing code */
441 + val = npe_cmd_read(npe, ECS_BG_CTXT_REG_0, CMD_RD_ECS_REG);
442 + val &= ~ECS_REG_0_NEXTPC_MASK;
443 + val |= (0 /* NextPC */ << 16) & ECS_REG_0_NEXTPC_MASK;
444 + npe_cmd_write(npe, ECS_BG_CTXT_REG_0, CMD_WR_ECS_REG, val);
445 +
446 + for (i = 0; i < 16; i++) {
447 + if (i) { /* Context 0 has no STEVT nor STARTPC */
448 + /* STEVT = off, 0x80 */
449 + if (npe_logical_reg_write8(npe, NPE_STEVT, 0x80, i))
450 + return -ETIMEDOUT;
451 + if (npe_logical_reg_write16(npe, NPE_STARTPC, 0, i))
452 + return -ETIMEDOUT;
453 + }
454 + /* REGMAP = d0->p0, d8->p2, d16->p4 */
455 + if (npe_logical_reg_write16(npe, NPE_REGMAP, 0x820, i))
456 + return -ETIMEDOUT;
457 + if (npe_logical_reg_write8(npe, NPE_CINDEX, 0, i))
458 + return -ETIMEDOUT;
459 + }
460 +
461 + /* post exec */
462 + /* clear active bit in debug level */
463 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_0, CMD_WR_ECS_REG, 0);
464 + /* clear the pipeline */
465 + __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd);
466 + /* restore previous values */
467 + __raw_writel(exec_count, &npe->regs->exec_count);
468 + npe_cmd_write(npe, ECS_DBG_CTXT_REG_2, CMD_WR_ECS_REG, ctx_reg2);
469 +
470 + /* write reset values to Execution Context Stack registers */
471 + for (val = 0; val < ARRAY_SIZE(ecs_reset); val++)
472 + npe_cmd_write(npe, ecs_reset[val].reg, CMD_WR_ECS_REG,
473 + ecs_reset[val].val);
474 +
475 + /* clear the profile counter */
476 + __raw_writel(CMD_CLR_PROFILE_CNT, &npe->regs->exec_status_cmd);
477 +
478 + __raw_writel(0, &npe->regs->exec_count);
479 + __raw_writel(0, &npe->regs->action_points[0]);
480 + __raw_writel(0, &npe->regs->action_points[1]);
481 + __raw_writel(0, &npe->regs->action_points[2]);
482 + __raw_writel(0, &npe->regs->action_points[3]);
483 + __raw_writel(0, &npe->regs->watch_count);
484 +
485 + val = ixp4xx_read_feature_bits();
486 + /* reset the NPE */
487 + ixp4xx_write_feature_bits(val &
488 + ~(IXP4XX_FEATURE_RESET_NPEA << npe->id));
489 + for (i = 0; i < MAX_RETRIES; i++) {
490 + if (!(ixp4xx_read_feature_bits() &
491 + (IXP4XX_FEATURE_RESET_NPEA << npe->id)))
492 + break; /* reset completed */
493 + udelay(1);
494 + }
495 + if (i == MAX_RETRIES)
496 + return -ETIMEDOUT;
497 +
498 + /* deassert reset */
499 + ixp4xx_write_feature_bits(val |
500 + (IXP4XX_FEATURE_RESET_NPEA << npe->id));
501 + for (i = 0; i < MAX_RETRIES; i++) {
502 + if (ixp4xx_read_feature_bits() &
503 + (IXP4XX_FEATURE_RESET_NPEA << npe->id))
504 + break; /* NPE is back alive */
505 + udelay(1);
506 + }
507 + if (i == MAX_RETRIES)
508 + return -ETIMEDOUT;
509 +
510 + npe_stop(npe);
511 +
512 + /* restore NPE configuration bus Control Register - parity settings */
513 + __raw_writel(ctl, &npe->regs->messaging_control);
514 + return 0;
515 +}
516 +
517 +
518 +int npe_send_message(struct npe *npe, const void *msg, const char *what)
519 +{
520 + const u32 *send = msg;
521 + int cycles = 0;
522 +
523 + debug_msg(npe, "Trying to send message %s [%08X:%08X]\n",
524 + what, send[0], send[1]);
525 +
526 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE) {
527 + debug_msg(npe, "NPE input FIFO not empty\n");
528 + return -EIO;
529 + }
530 +
531 + __raw_writel(send[0], &npe->regs->in_out_fifo);
532 +
533 + if (!(__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNF)) {
534 + debug_msg(npe, "NPE input FIFO full\n");
535 + return -EIO;
536 + }
537 +
538 + __raw_writel(send[1], &npe->regs->in_out_fifo);
539 +
540 + while ((cycles < MAX_RETRIES) &&
541 + (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_IFNE)) {
542 + udelay(1);
543 + cycles++;
544 + }
545 +
546 + if (cycles == MAX_RETRIES) {
547 + debug_msg(npe, "Timeout sending message\n");
548 + return -ETIMEDOUT;
549 + }
550 +
551 + debug_msg(npe, "Sending a message took %i cycles\n", cycles);
552 + return 0;
553 +}
554 +
555 +int npe_recv_message(struct npe *npe, void *msg, const char *what)
556 +{
557 + u32 *recv = msg;
558 + int cycles = 0, cnt = 0;
559 +
560 + debug_msg(npe, "Trying to receive message %s\n", what);
561 +
562 + while (cycles < MAX_RETRIES) {
563 + if (__raw_readl(&npe->regs->messaging_status) & MSGSTAT_OFNE) {
564 + recv[cnt++] = __raw_readl(&npe->regs->in_out_fifo);
565 + if (cnt == 2)
566 + break;
567 + } else {
568 + udelay(1);
569 + cycles++;
570 + }
571 + }
572 +
573 + switch(cnt) {
574 + case 1:
575 + debug_msg(npe, "Received [%08X]\n", recv[0]);
576 + break;
577 + case 2:
578 + debug_msg(npe, "Received [%08X:%08X]\n", recv[0], recv[1]);
579 + break;
580 + }
581 +
582 + if (cycles == MAX_RETRIES) {
583 + debug_msg(npe, "Timeout waiting for message\n");
584 + return -ETIMEDOUT;
585 + }
586 +
587 + debug_msg(npe, "Receiving a message took %i cycles\n", cycles);
588 + return 0;
589 +}
590 +
591 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what)
592 +{
593 + int result;
594 + u32 *send = msg, recv[2];
595 +
596 + if ((result = npe_send_message(npe, msg, what)) != 0)
597 + return result;
598 + if ((result = npe_recv_message(npe, recv, what)) != 0)
599 + return result;
600 +
601 + if ((recv[0] != send[0]) || (recv[1] != send[1])) {
602 + debug_msg(npe, "Message %s: unexpected message received\n",
603 + what);
604 + return -EIO;
605 + }
606 + return 0;
607 +}
608 +
609 +
610 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev)
611 +{
612 + const struct firmware *fw_entry;
613 +
614 + struct dl_block {
615 + u32 type;
616 + u32 offset;
617 + } *blk;
618 +
619 + struct dl_image {
620 + u32 magic;
621 + u32 id;
622 + u32 size;
623 + union {
624 + u32 data[0];
625 + struct dl_block blocks[0];
626 + };
627 + } *image;
628 +
629 + struct dl_codeblock {
630 + u32 npe_addr;
631 + u32 size;
632 + u32 data[0];
633 + } *cb;
634 +
635 + int i, j, err, data_size, instr_size, blocks, table_end;
636 + u32 cmd;
637 +
638 + if ((err = request_firmware(&fw_entry, name, dev)) != 0)
639 + return err;
640 +
641 + err = -EINVAL;
642 + if (fw_entry->size < sizeof(struct dl_image)) {
643 + print_npe(KERN_ERR, npe, "incomplete firmware file\n");
644 + goto err;
645 + }
646 + image = (struct dl_image*)fw_entry->data;
647 +
648 +#if DEBUG_FW
649 + print_npe(KERN_DEBUG, npe, "firmware: %08X %08X %08X (0x%X bytes)\n",
650 + image->magic, image->id, image->size, image->size * 4);
651 +#endif
652 +
653 + if (image->magic == swab32(FW_MAGIC)) { /* swapped file */
654 + image->id = swab32(image->id);
655 + image->size = swab32(image->size);
656 + } else if (image->magic != FW_MAGIC) {
657 + print_npe(KERN_ERR, npe, "bad firmware file magic: 0x%X\n",
658 + image->magic);
659 + goto err;
660 + }
661 + if ((image->size * 4 + sizeof(struct dl_image)) != fw_entry->size) {
662 + print_npe(KERN_ERR, npe,
663 + "inconsistent size of firmware file\n");
664 + goto err;
665 + }
666 + if (((image->id >> 24) & 0xF /* NPE ID */) != npe->id) {
667 + print_npe(KERN_ERR, npe, "firmware file NPE ID mismatch\n");
668 + goto err;
669 + }
670 + if (image->magic == swab32(FW_MAGIC))
671 + for (i = 0; i < image->size; i++)
672 + image->data[i] = swab32(image->data[i]);
673 +
674 + if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) {
675 + print_npe(KERN_INFO, npe, "IXP46x firmware ignored on "
676 + "IXP42x\n");
677 + goto err;
678 + }
679 +
680 + if (npe_running(npe)) {
681 + print_npe(KERN_INFO, npe, "unable to load firmware, NPE is "
682 + "already running\n");
683 + err = -EBUSY;
684 + goto err;
685 + }
686 +#if 0
687 + npe_stop(npe);
688 + npe_reset(npe);
689 +#endif
690 +
691 + print_npe(KERN_INFO, npe, "firmware functionality 0x%X, "
692 + "revision 0x%X:%X\n", (image->id >> 16) & 0xFF,
693 + (image->id >> 8) & 0xFF, image->id & 0xFF);
694 +
695 + if (!cpu_is_ixp46x()) {
696 + if (!npe->id)
697 + instr_size = NPE_A_42X_INSTR_SIZE;
698 + else
699 + instr_size = NPE_B_AND_C_42X_INSTR_SIZE;
700 + data_size = NPE_42X_DATA_SIZE;
701 + } else {
702 + instr_size = NPE_46X_INSTR_SIZE;
703 + data_size = NPE_46X_DATA_SIZE;
704 + }
705 +
706 + for (blocks = 0; blocks * sizeof(struct dl_block) / 4 < image->size;
707 + blocks++)
708 + if (image->blocks[blocks].type == FW_BLOCK_TYPE_EOF)
709 + break;
710 + if (blocks * sizeof(struct dl_block) / 4 >= image->size) {
711 + print_npe(KERN_INFO, npe, "firmware EOF block marker not "
712 + "found\n");
713 + goto err;
714 + }
715 +
716 +#if DEBUG_FW
717 + print_npe(KERN_DEBUG, npe, "%i firmware blocks found\n", blocks);
718 +#endif
719 +
720 + table_end = blocks * sizeof(struct dl_block) / 4 + 1 /* EOF marker */;
721 + for (i = 0, blk = image->blocks; i < blocks; i++, blk++) {
722 + if (blk->offset > image->size - sizeof(struct dl_codeblock) / 4
723 + || blk->offset < table_end) {
724 + print_npe(KERN_INFO, npe, "invalid offset 0x%X of "
725 + "firmware block #%i\n", blk->offset, i);
726 + goto err;
727 + }
728 +
729 + cb = (struct dl_codeblock*)&image->data[blk->offset];
730 + if (blk->type == FW_BLOCK_TYPE_INSTR) {
731 + if (cb->npe_addr + cb->size > instr_size)
732 + goto too_big;
733 + cmd = CMD_WR_INS_MEM;
734 + } else if (blk->type == FW_BLOCK_TYPE_DATA) {
735 + if (cb->npe_addr + cb->size > data_size)
736 + goto too_big;
737 + cmd = CMD_WR_DATA_MEM;
738 + } else {
739 + print_npe(KERN_INFO, npe, "invalid firmware block #%i "
740 + "type 0x%X\n", i, blk->type);
741 + goto err;
742 + }
743 + if (blk->offset + sizeof(*cb) / 4 + cb->size > image->size) {
744 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't "
745 + "fit in firmware image: type %c, start 0x%X,"
746 + " length 0x%X\n", i,
747 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
748 + cb->npe_addr, cb->size);
749 + goto err;
750 + }
751 +
752 + for (j = 0; j < cb->size; j++)
753 + npe_cmd_write(npe, cb->npe_addr + j, cmd, cb->data[j]);
754 + }
755 +
756 + npe_start(npe);
757 + if (!npe_running(npe))
758 + print_npe(KERN_ERR, npe, "unable to start\n");
759 + release_firmware(fw_entry);
760 + return 0;
761 +
762 +too_big:
763 + print_npe(KERN_INFO, npe, "firmware block #%i doesn't fit in NPE "
764 + "memory: type %c, start 0x%X, length 0x%X\n", i,
765 + blk->type == FW_BLOCK_TYPE_INSTR ? 'I' : 'D',
766 + cb->npe_addr, cb->size);
767 +err:
768 + release_firmware(fw_entry);
769 + return err;
770 +}
771 +
772 +
773 +struct npe *npe_request(int id)
774 +{
775 + if (id < NPE_COUNT)
776 + if (npe_tab[id].valid)
777 + if (try_module_get(THIS_MODULE))
778 + return &npe_tab[id];
779 + return NULL;
780 +}
781 +
782 +void npe_release(struct npe *npe)
783 +{
784 + module_put(THIS_MODULE);
785 +}
786 +
787 +
788 +static int __init npe_init_module(void)
789 +{
790 +
791 + int i, found = 0;
792 +
793 + for (i = 0; i < NPE_COUNT; i++) {
794 + struct npe *npe = &npe_tab[i];
795 + if (!(ixp4xx_read_feature_bits() &
796 + (IXP4XX_FEATURE_RESET_NPEA << i)))
797 + continue; /* NPE already disabled or not present */
798 + if (!(npe->mem_res = request_mem_region(npe->regs_phys,
799 + REGS_SIZE,
800 + npe_name(npe)))) {
801 + print_npe(KERN_ERR, npe,
802 + "failed to request memory region\n");
803 + continue;
804 + }
805 +
806 + if (npe_reset(npe))
807 + continue;
808 + npe->valid = 1;
809 + found++;
810 + }
811 +
812 + if (!found)
813 + return -ENOSYS;
814 + return 0;
815 +}
816 +
817 +static void __exit npe_cleanup_module(void)
818 +{
819 + int i;
820 +
821 + for (i = 0; i < NPE_COUNT; i++)
822 + if (npe_tab[i].mem_res) {
823 + npe_reset(&npe_tab[i]);
824 + release_resource(npe_tab[i].mem_res);
825 + }
826 +}
827 +
828 +module_init(npe_init_module);
829 +module_exit(npe_cleanup_module);
830 +
831 +MODULE_AUTHOR("Krzysztof Halasa");
832 +MODULE_LICENSE("GPL v2");
833 +
834 +EXPORT_SYMBOL(npe_names);
835 +EXPORT_SYMBOL(npe_running);
836 +EXPORT_SYMBOL(npe_request);
837 +EXPORT_SYMBOL(npe_release);
838 +EXPORT_SYMBOL(npe_load_firmware);
839 +EXPORT_SYMBOL(npe_send_message);
840 +EXPORT_SYMBOL(npe_recv_message);
841 +EXPORT_SYMBOL(npe_send_recv_message);
842 diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
843 new file mode 100644
844 index 0000000..e833013
845 --- /dev/null
846 +++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
847 @@ -0,0 +1,274 @@
848 +/*
849 + * Intel IXP4xx Queue Manager driver for Linux
850 + *
851 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
852 + *
853 + * This program is free software; you can redistribute it and/or modify it
854 + * under the terms of version 2 of the GNU General Public License
855 + * as published by the Free Software Foundation.
856 + */
857 +
858 +#include <linux/ioport.h>
859 +#include <linux/interrupt.h>
860 +#include <linux/kernel.h>
861 +#include <linux/module.h>
862 +#include <asm/arch/qmgr.h>
863 +
864 +#define DEBUG 0
865 +
866 +struct qmgr_regs __iomem *qmgr_regs;
867 +static struct resource *mem_res;
868 +static spinlock_t qmgr_lock;
869 +static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
870 +static void (*irq_handlers[HALF_QUEUES])(void *pdev);
871 +static void *irq_pdevs[HALF_QUEUES];
872 +
873 +void qmgr_set_irq(unsigned int queue, int src,
874 + void (*handler)(void *pdev), void *pdev)
875 +{
876 + u32 __iomem *reg = &qmgr_regs->irqsrc[queue / 8]; /* 8 queues / u32 */
877 + int bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
878 + unsigned long flags;
879 +
880 + src &= 7;
881 + spin_lock_irqsave(&qmgr_lock, flags);
882 + __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), reg);
883 + irq_handlers[queue] = handler;
884 + irq_pdevs[queue] = pdev;
885 + spin_unlock_irqrestore(&qmgr_lock, flags);
886 +}
887 +
888 +
889 +static irqreturn_t qmgr_irq1(int irq, void *pdev)
890 +{
891 + int i;
892 + u32 val = __raw_readl(&qmgr_regs->irqstat[0]);
893 + __raw_writel(val, &qmgr_regs->irqstat[0]); /* ACK */
894 +
895 + for (i = 0; i < HALF_QUEUES; i++)
896 + if (val & (1 << i))
897 + irq_handlers[i](irq_pdevs[i]);
898 +
899 + return val ? IRQ_HANDLED : 0;
900 +}
901 +
902 +
903 +void qmgr_enable_irq(unsigned int queue)
904 +{
905 + unsigned long flags;
906 +
907 + spin_lock_irqsave(&qmgr_lock, flags);
908 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) | (1 << queue),
909 + &qmgr_regs->irqen[0]);
910 + spin_unlock_irqrestore(&qmgr_lock, flags);
911 +}
912 +
913 +void qmgr_disable_irq(unsigned int queue)
914 +{
915 + unsigned long flags;
916 +
917 + spin_lock_irqsave(&qmgr_lock, flags);
918 + __raw_writel(__raw_readl(&qmgr_regs->irqen[0]) & ~(1 << queue),
919 + &qmgr_regs->irqen[0]);
920 + spin_unlock_irqrestore(&qmgr_lock, flags);
921 +}
922 +
923 +static inline void shift_mask(u32 *mask)
924 +{
925 + mask[3] = mask[3] << 1 | mask[2] >> 31;
926 + mask[2] = mask[2] << 1 | mask[1] >> 31;
927 + mask[1] = mask[1] << 1 | mask[0] >> 31;
928 + mask[0] <<= 1;
929 +}
930 +
931 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
932 + unsigned int nearly_empty_watermark,
933 + unsigned int nearly_full_watermark)
934 +{
935 + u32 cfg, addr = 0, mask[4]; /* in 16-dwords */
936 + int err;
937 +
938 + if (queue >= HALF_QUEUES)
939 + return -ERANGE;
940 +
941 + if ((nearly_empty_watermark | nearly_full_watermark) & ~7)
942 + return -EINVAL;
943 +
944 + switch (len) {
945 + case 16:
946 + cfg = 0 << 24;
947 + mask[0] = 0x1;
948 + break;
949 + case 32:
950 + cfg = 1 << 24;
951 + mask[0] = 0x3;
952 + break;
953 + case 64:
954 + cfg = 2 << 24;
955 + mask[0] = 0xF;
956 + break;
957 + case 128:
958 + cfg = 3 << 24;
959 + mask[0] = 0xFF;
960 + break;
961 + default:
962 + return -EINVAL;
963 + }
964 +
965 + cfg |= nearly_empty_watermark << 26;
966 + cfg |= nearly_full_watermark << 29;
967 + len /= 16; /* in 16-dwords: 1, 2, 4 or 8 */
968 + mask[1] = mask[2] = mask[3] = 0;
969 +
970 + if (!try_module_get(THIS_MODULE))
971 + return -ENODEV;
972 +
973 + spin_lock_irq(&qmgr_lock);
974 + if (__raw_readl(&qmgr_regs->sram[queue])) {
975 + err = -EBUSY;
976 + goto err;
977 + }
978 +
979 + while (1) {
980 + if (!(used_sram_bitmap[0] & mask[0]) &&
981 + !(used_sram_bitmap[1] & mask[1]) &&
982 + !(used_sram_bitmap[2] & mask[2]) &&
983 + !(used_sram_bitmap[3] & mask[3]))
984 + break; /* found free space */
985 +
986 + addr++;
987 + shift_mask(mask);
988 + if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {
989 + printk(KERN_ERR "qmgr: no free SRAM space for"
990 + " queue %i\n", queue);
991 + err = -ENOMEM;
992 + goto err;
993 + }
994 + }
995 +
996 + used_sram_bitmap[0] |= mask[0];
997 + used_sram_bitmap[1] |= mask[1];
998 + used_sram_bitmap[2] |= mask[2];
999 + used_sram_bitmap[3] |= mask[3];
1000 + __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
1001 + spin_unlock_irq(&qmgr_lock);
1002 +
1003 +#if DEBUG
1004 + printk(KERN_DEBUG "qmgr: requested queue %i, addr = 0x%02X\n",
1005 + queue, addr);
1006 +#endif
1007 + return 0;
1008 +
1009 +err:
1010 + spin_unlock_irq(&qmgr_lock);
1011 + module_put(THIS_MODULE);
1012 + return err;
1013 +}
1014 +
1015 +void qmgr_release_queue(unsigned int queue)
1016 +{
1017 + u32 cfg, addr, mask[4];
1018 +
1019 + BUG_ON(queue >= HALF_QUEUES); /* not in valid range */
1020 +
1021 + spin_lock_irq(&qmgr_lock);
1022 + cfg = __raw_readl(&qmgr_regs->sram[queue]);
1023 + addr = (cfg >> 14) & 0xFF;
1024 +
1025 + BUG_ON(!addr); /* not requested */
1026 +
1027 + switch ((cfg >> 24) & 3) {
1028 + case 0: mask[0] = 0x1; break;
1029 + case 1: mask[0] = 0x3; break;
1030 + case 2: mask[0] = 0xF; break;
1031 + case 3: mask[0] = 0xFF; break;
1032 + }
1033 +
1034 + while (addr--)
1035 + shift_mask(mask);
1036 +
1037 + __raw_writel(0, &qmgr_regs->sram[queue]);
1038 +
1039 + used_sram_bitmap[0] &= ~mask[0];
1040 + used_sram_bitmap[1] &= ~mask[1];
1041 + used_sram_bitmap[2] &= ~mask[2];
1042 + used_sram_bitmap[3] &= ~mask[3];
1043 + irq_handlers[queue] = NULL; /* catch IRQ bugs */
1044 + spin_unlock_irq(&qmgr_lock);
1045 +
1046 + module_put(THIS_MODULE);
1047 +#if DEBUG
1048 + printk(KERN_DEBUG "qmgr: released queue %i\n", queue);
1049 +#endif
1050 +}
1051 +
1052 +static int qmgr_init(void)
1053 +{
1054 + int i, err;
1055 + mem_res = request_mem_region(IXP4XX_QMGR_BASE_PHYS,
1056 + IXP4XX_QMGR_REGION_SIZE,
1057 + "IXP4xx Queue Manager");
1058 + if (mem_res == NULL)
1059 + return -EBUSY;
1060 +
1061 + qmgr_regs = ioremap(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1062 + if (qmgr_regs == NULL) {
1063 + err = -ENOMEM;
1064 + goto error_map;
1065 + }
1066 +
1067 + /* reset qmgr registers */
1068 + for (i = 0; i < 4; i++) {
1069 + __raw_writel(0x33333333, &qmgr_regs->stat1[i]);
1070 + __raw_writel(0, &qmgr_regs->irqsrc[i]);
1071 + }
1072 + for (i = 0; i < 2; i++) {
1073 + __raw_writel(0, &qmgr_regs->stat2[i]);
1074 + __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */
1075 + __raw_writel(0, &qmgr_regs->irqen[i]);
1076 + }
1077 +
1078 + for (i = 0; i < QUEUES; i++)
1079 + __raw_writel(0, &qmgr_regs->sram[i]);
1080 +
1081 + err = request_irq(IRQ_IXP4XX_QM1, qmgr_irq1, 0,
1082 + "IXP4xx Queue Manager", NULL);
1083 + if (err) {
1084 + printk(KERN_ERR "qmgr: failed to request IRQ%i\n",
1085 + IRQ_IXP4XX_QM1);
1086 + goto error_irq;
1087 + }
1088 +
1089 + used_sram_bitmap[0] = 0xF; /* 4 first pages reserved for config */
1090 + spin_lock_init(&qmgr_lock);
1091 +
1092 + printk(KERN_INFO "IXP4xx Queue Manager initialized.\n");
1093 + return 0;
1094 +
1095 +error_irq:
1096 + iounmap(qmgr_regs);
1097 +error_map:
1098 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1099 + return err;
1100 +}
1101 +
1102 +static void qmgr_remove(void)
1103 +{
1104 + free_irq(IRQ_IXP4XX_QM1, NULL);
1105 + synchronize_irq(IRQ_IXP4XX_QM1);
1106 + iounmap(qmgr_regs);
1107 + release_mem_region(IXP4XX_QMGR_BASE_PHYS, IXP4XX_QMGR_REGION_SIZE);
1108 +}
1109 +
1110 +module_init(qmgr_init);
1111 +module_exit(qmgr_remove);
1112 +
1113 +MODULE_LICENSE("GPL v2");
1114 +MODULE_AUTHOR("Krzysztof Halasa");
1115 +
1116 +EXPORT_SYMBOL(qmgr_regs);
1117 +EXPORT_SYMBOL(qmgr_set_irq);
1118 +EXPORT_SYMBOL(qmgr_enable_irq);
1119 +EXPORT_SYMBOL(qmgr_disable_irq);
1120 +EXPORT_SYMBOL(qmgr_request_queue);
1121 +EXPORT_SYMBOL(qmgr_release_queue);
1122 diff --git a/drivers/net/arm/Kconfig b/drivers/net/arm/Kconfig
1123 index f9cc2b6..9274d3f 100644
1124 --- a/drivers/net/arm/Kconfig
1125 +++ b/drivers/net/arm/Kconfig
1126 @@ -47,3 +47,13 @@ config EP93XX_ETH
1127 help
1128 This is a driver for the ethernet hardware included in EP93xx CPUs.
1129 Say Y if you are building a kernel for EP93xx based devices.
1130 +
1131 +config IXP4XX_ETH
1132 + tristate "IXP4xx Ethernet support"
1133 + depends on NET_ETHERNET && ARM && ARCH_IXP4XX
1134 + select IXP4XX_NPE
1135 + select IXP4XX_QMGR
1136 + select MII
1137 + help
1138 + Say Y here if you want to use built-in Ethernet ports
1139 + on IXP4xx processor.
1140 diff --git a/drivers/net/arm/Makefile b/drivers/net/arm/Makefile
1141 index a4c8682..7c812ac 100644
1142 --- a/drivers/net/arm/Makefile
1143 +++ b/drivers/net/arm/Makefile
1144 @@ -9,3 +9,4 @@ obj-$(CONFIG_ARM_ETHER3) += ether3.o
1145 obj-$(CONFIG_ARM_ETHER1) += ether1.o
1146 obj-$(CONFIG_ARM_AT91_ETHER) += at91_ether.o
1147 obj-$(CONFIG_EP93XX_ETH) += ep93xx_eth.o
1148 +obj-$(CONFIG_IXP4XX_ETH) += ixp4xx_eth.o
1149 diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
1150 new file mode 100644
1151 index 0000000..2c23f50
1152 --- /dev/null
1153 +++ b/drivers/net/arm/ixp4xx_eth.c
1154 @@ -0,0 +1,1259 @@
1155 +/*
1156 + * Intel IXP4xx Ethernet driver for Linux
1157 + *
1158 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
1159 + *
1160 + * This program is free software; you can redistribute it and/or modify it
1161 + * under the terms of version 2 of the GNU General Public License
1162 + * as published by the Free Software Foundation.
1163 + *
1164 + * Ethernet port config (0x00 is not present on IXP42X):
1165 + *
1166 + * logical port 0x00 0x10 0x20
1167 + * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
1168 + * physical PortId 2 0 1
1169 + * TX queue 23 24 25
1170 + * RX-free queue 26 27 28
1171 + * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
1172 + *
1173 + *
1174 + * Queue entries:
1175 + * bits 0 -> 1 - NPE ID (RX and TX-done)
1176 + * bits 0 -> 2 - priority (TX, per 802.1D)
1177 + * bits 3 -> 4 - port ID (user-set?)
1178 + * bits 5 -> 31 - physical descriptor address
1179 + */
1180 +
1181 +#include <linux/delay.h>
1182 +#include <linux/dma-mapping.h>
1183 +#include <linux/dmapool.h>
1184 +#include <linux/etherdevice.h>
1185 +#include <linux/io.h>
1186 +#include <linux/kernel.h>
1187 +#include <linux/mii.h>
1188 +#include <linux/platform_device.h>
1189 +#include <asm/arch/npe.h>
1190 +#include <asm/arch/qmgr.h>
1191 +
1192 +#define DEBUG_QUEUES 0
1193 +#define DEBUG_DESC 0
1194 +#define DEBUG_RX 0
1195 +#define DEBUG_TX 0
1196 +#define DEBUG_PKT_BYTES 0
1197 +#define DEBUG_MDIO 0
1198 +#define DEBUG_CLOSE 0
1199 +
1200 +#define DRV_NAME "ixp4xx_eth"
1201 +
1202 +#define MAX_NPES 3
1203 +
1204 +#define RX_DESCS 64 /* also length of all RX queues */
1205 +#define TX_DESCS 16 /* also length of all TX queues */
1206 +#define TXDONE_QUEUE_LEN 64 /* dwords */
1207 +
1208 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
1209 +#define REGS_SIZE 0x1000
1210 +#define MAX_MRU 1536 /* 0x600 */
1211 +
1212 +#define MDIO_INTERVAL (3 * HZ)
1213 +#define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
1214 +#define MAX_MII_RESET_RETRIES 100 /* mdio_read() cycles, typically 4 */
1215 +#define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
1216 +
1217 +#define NPE_ID(port_id) ((port_id) >> 4)
1218 +#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
1219 +#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
1220 +#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
1221 +#define TXDONE_QUEUE 31
1222 +
1223 +/* TX Control Registers */
1224 +#define TX_CNTRL0_TX_EN 0x01
1225 +#define TX_CNTRL0_HALFDUPLEX 0x02
1226 +#define TX_CNTRL0_RETRY 0x04
1227 +#define TX_CNTRL0_PAD_EN 0x08
1228 +#define TX_CNTRL0_APPEND_FCS 0x10
1229 +#define TX_CNTRL0_2DEFER 0x20
1230 +#define TX_CNTRL0_RMII 0x40 /* reduced MII */
1231 +#define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
1232 +
1233 +/* RX Control Registers */
1234 +#define RX_CNTRL0_RX_EN 0x01
1235 +#define RX_CNTRL0_PADSTRIP_EN 0x02
1236 +#define RX_CNTRL0_SEND_FCS 0x04
1237 +#define RX_CNTRL0_PAUSE_EN 0x08
1238 +#define RX_CNTRL0_LOOP_EN 0x10
1239 +#define RX_CNTRL0_ADDR_FLTR_EN 0x20
1240 +#define RX_CNTRL0_RX_RUNT_EN 0x40
1241 +#define RX_CNTRL0_BCAST_DIS 0x80
1242 +#define RX_CNTRL1_DEFER_EN 0x01
1243 +
1244 +/* Core Control Register */
1245 +#define CORE_RESET 0x01
1246 +#define CORE_RX_FIFO_FLUSH 0x02
1247 +#define CORE_TX_FIFO_FLUSH 0x04
1248 +#define CORE_SEND_JAM 0x08
1249 +#define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
1250 +
1251 +#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
1252 + TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
1253 + TX_CNTRL0_2DEFER)
1254 +#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
1255 +#define DEFAULT_CORE_CNTRL CORE_MDC_EN
1256 +
1257 +
1258 +/* NPE message codes */
1259 +#define NPE_GETSTATUS 0x00
1260 +#define NPE_EDB_SETPORTADDRESS 0x01
1261 +#define NPE_EDB_GETMACADDRESSDATABASE 0x02
1262 +#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
1263 +#define NPE_GETSTATS 0x04
1264 +#define NPE_RESETSTATS 0x05
1265 +#define NPE_SETMAXFRAMELENGTHS 0x06
1266 +#define NPE_VLAN_SETRXTAGMODE 0x07
1267 +#define NPE_VLAN_SETDEFAULTRXVID 0x08
1268 +#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
1269 +#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
1270 +#define NPE_VLAN_SETRXQOSENTRY 0x0B
1271 +#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
1272 +#define NPE_STP_SETBLOCKINGSTATE 0x0D
1273 +#define NPE_FW_SETFIREWALLMODE 0x0E
1274 +#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
1275 +#define NPE_PC_SETAPMACTABLE 0x11
1276 +#define NPE_SETLOOPBACK_MODE 0x12
1277 +#define NPE_PC_SETBSSIDTABLE 0x13
1278 +#define NPE_ADDRESS_FILTER_CONFIG 0x14
1279 +#define NPE_APPENDFCSCONFIG 0x15
1280 +#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
1281 +#define NPE_MAC_RECOVERY_START 0x17
1282 +
1283 +
1284 +#ifdef __ARMEB__
1285 +typedef struct sk_buff buffer_t;
1286 +#define free_buffer dev_kfree_skb
1287 +#define free_buffer_irq dev_kfree_skb_irq
1288 +#else
1289 +typedef void buffer_t;
1290 +#define free_buffer kfree
1291 +#define free_buffer_irq kfree
1292 +#endif
1293 +
1294 +struct eth_regs {
1295 + u32 tx_control[2], __res1[2]; /* 000 */
1296 + u32 rx_control[2], __res2[2]; /* 010 */
1297 + u32 random_seed, __res3[3]; /* 020 */
1298 + u32 partial_empty_threshold, __res4; /* 030 */
1299 + u32 partial_full_threshold, __res5; /* 038 */
1300 + u32 tx_start_bytes, __res6[3]; /* 040 */
1301 + u32 tx_deferral, rx_deferral,__res7[2]; /* 050 */
1302 + u32 tx_2part_deferral[2], __res8[2]; /* 060 */
1303 + u32 slot_time, __res9[3]; /* 070 */
1304 + u32 mdio_command[4]; /* 080 */
1305 + u32 mdio_status[4]; /* 090 */
1306 + u32 mcast_mask[6], __res10[2]; /* 0A0 */
1307 + u32 mcast_addr[6], __res11[2]; /* 0C0 */
1308 + u32 int_clock_threshold, __res12[3]; /* 0E0 */
1309 + u32 hw_addr[6], __res13[61]; /* 0F0 */
1310 + u32 core_control; /* 1FC */
1311 +};
1312 +
1313 +struct port {
1314 + struct resource *mem_res;
1315 + struct eth_regs __iomem *regs;
1316 + struct npe *npe;
1317 + struct net_device *netdev;
1318 + struct net_device_stats stat;
1319 + struct mii_if_info mii;
1320 + struct delayed_work mdio_thread;
1321 + struct eth_plat_info *plat;
1322 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
1323 + struct desc *desc_tab; /* coherent */
1324 + u32 desc_tab_phys;
1325 + int id; /* logical port ID */
1326 + u16 mii_bmcr;
1327 +};
1328 +
1329 +/* NPE message structure */
1330 +struct msg {
1331 +#ifdef __ARMEB__
1332 + u8 cmd, eth_id, byte2, byte3;
1333 + u8 byte4, byte5, byte6, byte7;
1334 +#else
1335 + u8 byte3, byte2, eth_id, cmd;
1336 + u8 byte7, byte6, byte5, byte4;
1337 +#endif
1338 +};
1339 +
1340 +/* Ethernet packet descriptor */
1341 +struct desc {
1342 + u32 next; /* pointer to next buffer, unused */
1343 +
1344 +#ifdef __ARMEB__
1345 + u16 buf_len; /* buffer length */
1346 + u16 pkt_len; /* packet length */
1347 + u32 data; /* pointer to data buffer in RAM */
1348 + u8 dest_id;
1349 + u8 src_id;
1350 + u16 flags;
1351 + u8 qos;
1352 + u8 padlen;
1353 + u16 vlan_tci;
1354 +#else
1355 + u16 pkt_len; /* packet length */
1356 + u16 buf_len; /* buffer length */
1357 + u32 data; /* pointer to data buffer in RAM */
1358 + u16 flags;
1359 + u8 src_id;
1360 + u8 dest_id;
1361 + u16 vlan_tci;
1362 + u8 padlen;
1363 + u8 qos;
1364 +#endif
1365 +
1366 +#ifdef __ARMEB__
1367 + u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
1368 + u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
1369 + u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
1370 +#else
1371 + u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
1372 + u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
1373 + u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
1374 +#endif
1375 +};
1376 +
1377 +
1378 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
1379 + (n) * sizeof(struct desc))
1380 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
1381 +
1382 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
1383 + ((n) + RX_DESCS) * sizeof(struct desc))
1384 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
1385 +
1386 +#ifndef __ARMEB__
1387 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
1388 +{
1389 + int i;
1390 + for (i = 0; i < cnt; i++)
1391 + dest[i] = swab32(src[i]);
1392 +}
1393 +#endif
1394 +
1395 +static spinlock_t mdio_lock;
1396 +static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
1397 +static int ports_open;
1398 +static struct port *npe_port_tab[MAX_NPES];
1399 +static struct dma_pool *dma_pool;
1400 +
1401 +
1402 +static u16 mdio_cmd(struct net_device *dev, int phy_id, int location,
1403 + int write, u16 cmd)
1404 +{
1405 + int cycles = 0;
1406 +
1407 + if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
1408 + printk(KERN_ERR "%s: MII not ready to transmit\n", dev->name);
1409 + return 0;
1410 + }
1411 +
1412 + if (write) {
1413 + __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
1414 + __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
1415 + }
1416 + __raw_writel(((phy_id << 5) | location) & 0xFF,
1417 + &mdio_regs->mdio_command[2]);
1418 + __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
1419 + &mdio_regs->mdio_command[3]);
1420 +
1421 + while ((cycles < MAX_MDIO_RETRIES) &&
1422 + (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
1423 + udelay(1);
1424 + cycles++;
1425 + }
1426 +
1427 + if (cycles == MAX_MDIO_RETRIES) {
1428 + printk(KERN_ERR "%s: MII write failed\n", dev->name);
1429 + return 0;
1430 + }
1431 +
1432 +#if DEBUG_MDIO
1433 + printk(KERN_DEBUG "%s: mdio_cmd() took %i cycles\n", dev->name,
1434 + cycles);
1435 +#endif
1436 +
1437 + if (write)
1438 + return 0;
1439 +
1440 + if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
1441 + printk(KERN_ERR "%s: MII read failed\n", dev->name);
1442 + return 0;
1443 + }
1444 +
1445 + return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
1446 + (__raw_readl(&mdio_regs->mdio_status[1]) << 8);
1447 +}
1448 +
1449 +static int mdio_read(struct net_device *dev, int phy_id, int location)
1450 +{
1451 + unsigned long flags;
1452 + u16 val;
1453 +
1454 + spin_lock_irqsave(&mdio_lock, flags);
1455 + val = mdio_cmd(dev, phy_id, location, 0, 0);
1456 + spin_unlock_irqrestore(&mdio_lock, flags);
1457 + return val;
1458 +}
1459 +
1460 +static void mdio_write(struct net_device *dev, int phy_id, int location,
1461 + int val)
1462 +{
1463 + unsigned long flags;
1464 +
1465 + spin_lock_irqsave(&mdio_lock, flags);
1466 + mdio_cmd(dev, phy_id, location, 1, val);
1467 + spin_unlock_irqrestore(&mdio_lock, flags);
1468 +}
1469 +
1470 +static void phy_reset(struct net_device *dev, int phy_id)
1471 +{
1472 + struct port *port = netdev_priv(dev);
1473 + int cycles = 0;
1474 +
1475 + mdio_write(dev, phy_id, MII_BMCR, port->mii_bmcr | BMCR_RESET);
1476 +
1477 + while (cycles < MAX_MII_RESET_RETRIES) {
1478 + if (!(mdio_read(dev, phy_id, MII_BMCR) & BMCR_RESET)) {
1479 +#if DEBUG_MDIO
1480 + printk(KERN_DEBUG "%s: phy_reset() took %i cycles\n",
1481 + dev->name, cycles);
1482 +#endif
1483 + return;
1484 + }
1485 + udelay(1);
1486 + cycles++;
1487 + }
1488 +
1489 + printk(KERN_ERR "%s: MII reset failed\n", dev->name);
1490 +}
1491 +
1492 +static void eth_set_duplex(struct port *port)
1493 +{
1494 + if (port->mii.full_duplex)
1495 + __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
1496 + &port->regs->tx_control[0]);
1497 + else
1498 + __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
1499 + &port->regs->tx_control[0]);
1500 +}
1501 +
1502 +
1503 +static void phy_check_media(struct port *port, int init)
1504 +{
1505 + if (mii_check_media(&port->mii, 1, init))
1506 + eth_set_duplex(port);
1507 + if (port->mii.force_media) { /* mii_check_media() doesn't work */
1508 + struct net_device *dev = port->netdev;
1509 + int cur_link = mii_link_ok(&port->mii);
1510 + int prev_link = netif_carrier_ok(dev);
1511 +
1512 + if (!prev_link && cur_link) {
1513 + printk(KERN_INFO "%s: link up\n", dev->name);
1514 + netif_carrier_on(dev);
1515 + } else if (prev_link && !cur_link) {
1516 + printk(KERN_INFO "%s: link down\n", dev->name);
1517 + netif_carrier_off(dev);
1518 + }
1519 + }
1520 +}
1521 +
1522 +
1523 +static void mdio_thread(struct work_struct *work)
1524 +{
1525 + struct port *port = container_of(work, struct port, mdio_thread.work);
1526 +
1527 + phy_check_media(port, 0);
1528 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
1529 +}
1530 +
1531 +
1532 +static inline void debug_pkt(struct net_device *dev, const char *func,
1533 + u8 *data, int len)
1534 +{
1535 +#if DEBUG_PKT_BYTES
1536 + int i;
1537 +
1538 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
1539 + for (i = 0; i < len; i++) {
1540 + if (i >= DEBUG_PKT_BYTES)
1541 + break;
1542 + printk("%s%02X",
1543 + ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
1544 + data[i]);
1545 + }
1546 + printk("\n");
1547 +#endif
1548 +}
1549 +
1550 +
1551 +static inline void debug_desc(u32 phys, struct desc *desc)
1552 +{
1553 +#if DEBUG_DESC
1554 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
1555 + " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
1556 + phys, desc->next, desc->buf_len, desc->pkt_len,
1557 + desc->data, desc->dest_id, desc->src_id, desc->flags,
1558 + desc->qos, desc->padlen, desc->vlan_tci,
1559 + desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
1560 + desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
1561 + desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
1562 + desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
1563 +#endif
1564 +}
1565 +
1566 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
1567 +{
1568 +#if DEBUG_QUEUES
1569 + static struct {
1570 + int queue;
1571 + char *name;
1572 + } names[] = {
1573 + { TX_QUEUE(0x10), "TX#0 " },
1574 + { TX_QUEUE(0x20), "TX#1 " },
1575 + { TX_QUEUE(0x00), "TX#2 " },
1576 + { RXFREE_QUEUE(0x10), "RX-free#0 " },
1577 + { RXFREE_QUEUE(0x20), "RX-free#1 " },
1578 + { RXFREE_QUEUE(0x00), "RX-free#2 " },
1579 + { TXDONE_QUEUE, "TX-done " },
1580 + };
1581 + int i;
1582 +
1583 + for (i = 0; i < ARRAY_SIZE(names); i++)
1584 + if (names[i].queue == queue)
1585 + break;
1586 +
1587 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
1588 + i < ARRAY_SIZE(names) ? names[i].name : "",
1589 + is_get ? "->" : "<-", phys);
1590 +#endif
1591 +}
1592 +
1593 +static inline u32 queue_get_entry(unsigned int queue)
1594 +{
1595 + u32 phys = qmgr_get_entry(queue);
1596 + debug_queue(queue, 1, phys);
1597 + return phys;
1598 +}
1599 +
1600 +static inline int queue_get_desc(unsigned int queue, struct port *port,
1601 + int is_tx)
1602 +{
1603 + u32 phys, tab_phys, n_desc;
1604 + struct desc *tab;
1605 +
1606 + if (!(phys = queue_get_entry(queue)))
1607 + return -1;
1608 +
1609 + phys &= ~0x1F; /* mask out non-address bits */
1610 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
1611 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
1612 + n_desc = (phys - tab_phys) / sizeof(struct desc);
1613 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
1614 + debug_desc(phys, &tab[n_desc]);
1615 + BUG_ON(tab[n_desc].next);
1616 + return n_desc;
1617 +}
1618 +
1619 +static inline void queue_put_desc(unsigned int queue, u32 phys,
1620 + struct desc *desc)
1621 +{
1622 + debug_queue(queue, 0, phys);
1623 + debug_desc(phys, desc);
1624 + BUG_ON(phys & 0x1F);
1625 + qmgr_put_entry(queue, phys);
1626 + BUG_ON(qmgr_stat_overflow(queue));
1627 +}
1628 +
1629 +
1630 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
1631 +{
1632 +#ifdef __ARMEB__
1633 + dma_unmap_single(&port->netdev->dev, desc->data,
1634 + desc->buf_len, DMA_TO_DEVICE);
1635 +#else
1636 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
1637 + ALIGN((desc->data & 3) + desc->buf_len, 4),
1638 + DMA_TO_DEVICE);
1639 +#endif
1640 +}
1641 +
1642 +
1643 +static void eth_rx_irq(void *pdev)
1644 +{
1645 + struct net_device *dev = pdev;
1646 + struct port *port = netdev_priv(dev);
1647 +
1648 +#if DEBUG_RX
1649 + printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
1650 +#endif
1651 + qmgr_disable_irq(port->plat->rxq);
1652 + netif_rx_schedule(dev);
1653 +}
1654 +
1655 +static int eth_poll(struct net_device *dev, int *budget)
1656 +{
1657 + struct port *port = netdev_priv(dev);
1658 + unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
1659 + int quota = dev->quota, received = 0;
1660 +
1661 +#if DEBUG_RX
1662 + printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
1663 +#endif
1664 +
1665 + while (quota) {
1666 + struct sk_buff *skb;
1667 + struct desc *desc;
1668 + int n;
1669 +#ifdef __ARMEB__
1670 + struct sk_buff *temp;
1671 + u32 phys;
1672 +#endif
1673 +
1674 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
1675 + dev->quota -= received; /* No packet received */
1676 + *budget -= received;
1677 + received = 0;
1678 +#if DEBUG_RX
1679 + printk(KERN_DEBUG "%s: eth_poll netif_rx_complete\n",
1680 + dev->name);
1681 +#endif
1682 + netif_rx_complete(dev);
1683 + qmgr_enable_irq(rxq);
1684 + if (!qmgr_stat_empty(rxq) &&
1685 + netif_rx_reschedule(dev, 0)) {
1686 +#if DEBUG_RX
1687 + printk(KERN_DEBUG "%s: eth_poll"
1688 + " netif_rx_reschedule successed\n",
1689 + dev->name);
1690 +#endif
1691 + qmgr_disable_irq(rxq);
1692 + continue;
1693 + }
1694 +#if DEBUG_RX
1695 + printk(KERN_DEBUG "%s: eth_poll all done\n",
1696 + dev->name);
1697 +#endif
1698 + return 0; /* all work done */
1699 + }
1700 +
1701 + desc = rx_desc_ptr(port, n);
1702 +
1703 +#ifdef __ARMEB__
1704 + if ((skb = netdev_alloc_skb(dev, MAX_MRU)) != NULL) {
1705 + phys = dma_map_single(&dev->dev, skb->data,
1706 + MAX_MRU, DMA_FROM_DEVICE);
1707 + if (dma_mapping_error(phys)) {
1708 + dev_kfree_skb(skb);
1709 + skb = NULL;
1710 + }
1711 + }
1712 +#else
1713 + skb = netdev_alloc_skb(dev, desc->pkt_len);
1714 +#endif
1715 +
1716 + if (!skb) {
1717 + port->stat.rx_dropped++;
1718 + /* put the desc back on RX-ready queue */
1719 + desc->buf_len = MAX_MRU;
1720 + desc->pkt_len = 0;
1721 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1722 + continue;
1723 + }
1724 +
1725 + /* process received frame */
1726 +#ifdef __ARMEB__
1727 + temp = skb;
1728 + skb = port->rx_buff_tab[n];
1729 + dma_unmap_single(&dev->dev, desc->data,
1730 + MAX_MRU, DMA_FROM_DEVICE);
1731 +#else
1732 + dma_sync_single(&dev->dev, desc->data,
1733 + MAX_MRU, DMA_FROM_DEVICE);
1734 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
1735 + ALIGN(desc->pkt_len, 4) / 4);
1736 +#endif
1737 + skb_put(skb, desc->pkt_len);
1738 +
1739 + debug_pkt(dev, "eth_poll", skb->data, skb->len);
1740 +
1741 + skb->protocol = eth_type_trans(skb, dev);
1742 + dev->last_rx = jiffies;
1743 + port->stat.rx_packets++;
1744 + port->stat.rx_bytes += skb->len;
1745 + netif_receive_skb(skb);
1746 +
1747 + /* put the new buffer on RX-free queue */
1748 +#ifdef __ARMEB__
1749 + port->rx_buff_tab[n] = temp;
1750 + desc->data = phys;
1751 +#endif
1752 + desc->buf_len = MAX_MRU;
1753 + desc->pkt_len = 0;
1754 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
1755 + quota--;
1756 + received++;
1757 + }
1758 + dev->quota -= received;
1759 + *budget -= received;
1760 +#if DEBUG_RX
1761 + printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
1762 +#endif
1763 + return 1; /* not all work done */
1764 +}
1765 +
1766 +
1767 +static void eth_txdone_irq(void *unused)
1768 +{
1769 + u32 phys;
1770 +
1771 +#if DEBUG_TX
1772 + printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
1773 +#endif
1774 + while ((phys = queue_get_entry(TXDONE_QUEUE)) != 0) {
1775 + u32 npe_id, n_desc;
1776 + struct port *port;
1777 + struct desc *desc;
1778 + int start;
1779 +
1780 + npe_id = phys & 3;
1781 + BUG_ON(npe_id >= MAX_NPES);
1782 + port = npe_port_tab[npe_id];
1783 + BUG_ON(!port);
1784 + phys &= ~0x1F; /* mask out non-address bits */
1785 + n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
1786 + BUG_ON(n_desc >= TX_DESCS);
1787 + desc = tx_desc_ptr(port, n_desc);
1788 + debug_desc(phys, desc);
1789 +
1790 + if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
1791 + port->stat.tx_packets++;
1792 + port->stat.tx_bytes += desc->pkt_len;
1793 +
1794 + dma_unmap_tx(port, desc);
1795 +#if DEBUG_TX
1796 + printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
1797 + port->netdev->name, port->tx_buff_tab[n_desc]);
1798 +#endif
1799 + free_buffer_irq(port->tx_buff_tab[n_desc]);
1800 + port->tx_buff_tab[n_desc] = NULL;
1801 + }
1802 +
1803 + start = qmgr_stat_empty(port->plat->txreadyq);
1804 + queue_put_desc(port->plat->txreadyq, phys, desc);
1805 + if (start) {
1806 +#if DEBUG_TX
1807 + printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
1808 + port->netdev->name);
1809 +#endif
1810 + netif_wake_queue(port->netdev);
1811 + }
1812 + }
1813 +}
1814 +
1815 +static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
1816 +{
1817 + struct port *port = netdev_priv(dev);
1818 + unsigned int txreadyq = port->plat->txreadyq;
1819 + int len, offset, bytes, n;
1820 + void *mem;
1821 + u32 phys;
1822 + struct desc *desc;
1823 +
1824 +#if DEBUG_TX
1825 + printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
1826 +#endif
1827 +
1828 + if (unlikely(skb->len > MAX_MRU)) {
1829 + dev_kfree_skb(skb);
1830 + port->stat.tx_errors++;
1831 + return NETDEV_TX_OK;
1832 + }
1833 +
1834 + debug_pkt(dev, "eth_xmit", skb->data, skb->len);
1835 +
1836 + len = skb->len;
1837 +#ifdef __ARMEB__
1838 + offset = 0; /* no need to keep alignment */
1839 + bytes = len;
1840 + mem = skb->data;
1841 +#else
1842 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
1843 + bytes = ALIGN(offset + len, 4);
1844 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
1845 + dev_kfree_skb(skb);
1846 + port->stat.tx_dropped++;
1847 + return NETDEV_TX_OK;
1848 + }
1849 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
1850 + dev_kfree_skb(skb);
1851 +#endif
1852 +
1853 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
1854 + if (dma_mapping_error(phys)) {
1855 +#ifdef __ARMEB__
1856 + dev_kfree_skb(skb);
1857 +#else
1858 + kfree(mem);
1859 +#endif
1860 + port->stat.tx_dropped++;
1861 + return NETDEV_TX_OK;
1862 + }
1863 +
1864 + n = queue_get_desc(txreadyq, port, 1);
1865 + BUG_ON(n < 0);
1866 + desc = tx_desc_ptr(port, n);
1867 +
1868 +#ifdef __ARMEB__
1869 + port->tx_buff_tab[n] = skb;
1870 +#else
1871 + port->tx_buff_tab[n] = mem;
1872 +#endif
1873 + desc->data = phys + offset;
1874 + desc->buf_len = desc->pkt_len = len;
1875 +
1876 + /* NPE firmware pads short frames with zeros internally */
1877 + wmb();
1878 + queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
1879 + dev->trans_start = jiffies;
1880 +
1881 + if (qmgr_stat_empty(txreadyq)) {
1882 +#if DEBUG_TX
1883 + printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
1884 +#endif
1885 + netif_stop_queue(dev);
1886 + /* we could miss TX ready interrupt */
1887 + if (!qmgr_stat_empty(txreadyq)) {
1888 +#if DEBUG_TX
1889 + printk(KERN_DEBUG "%s: eth_xmit ready again\n",
1890 + dev->name);
1891 +#endif
1892 + netif_wake_queue(dev);
1893 + }
1894 + }
1895 +
1896 +#if DEBUG_TX
1897 + printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
1898 +#endif
1899 + return NETDEV_TX_OK;
1900 +}
1901 +
1902 +
1903 +static struct net_device_stats *eth_stats(struct net_device *dev)
1904 +{
1905 + struct port *port = netdev_priv(dev);
1906 + return &port->stat;
1907 +}
1908 +
1909 +static void eth_set_mcast_list(struct net_device *dev)
1910 +{
1911 + struct port *port = netdev_priv(dev);
1912 + struct dev_mc_list *mclist = dev->mc_list;
1913 + u8 diffs[ETH_ALEN], *addr;
1914 + int cnt = dev->mc_count, i;
1915 +
1916 + if ((dev->flags & IFF_PROMISC) || !mclist || !cnt) {
1917 + __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
1918 + &port->regs->rx_control[0]);
1919 + return;
1920 + }
1921 +
1922 + memset(diffs, 0, ETH_ALEN);
1923 + addr = mclist->dmi_addr; /* first MAC address */
1924 +
1925 + while (--cnt && (mclist = mclist->next))
1926 + for (i = 0; i < ETH_ALEN; i++)
1927 + diffs[i] |= addr[i] ^ mclist->dmi_addr[i];
1928 +
1929 + for (i = 0; i < ETH_ALEN; i++) {
1930 + __raw_writel(addr[i], &port->regs->mcast_addr[i]);
1931 + __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
1932 + }
1933 +
1934 + __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
1935 + &port->regs->rx_control[0]);
1936 +}
1937 +
1938 +
1939 +static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1940 +{
1941 + struct port *port = netdev_priv(dev);
1942 + unsigned int duplex_chg;
1943 + int err;
1944 +
1945 + if (!netif_running(dev))
1946 + return -EINVAL;
1947 + err = generic_mii_ioctl(&port->mii, if_mii(req), cmd, &duplex_chg);
1948 + if (duplex_chg)
1949 + eth_set_duplex(port);
1950 + return err;
1951 +}
1952 +
1953 +
1954 +static int request_queues(struct port *port)
1955 +{
1956 + int err;
1957 +
1958 + err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0);
1959 + if (err)
1960 + return err;
1961 +
1962 + err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0);
1963 + if (err)
1964 + goto rel_rxfree;
1965 +
1966 + err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0);
1967 + if (err)
1968 + goto rel_rx;
1969 +
1970 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
1971 + if (err)
1972 + goto rel_tx;
1973 +
1974 + /* TX-done queue handles skbs sent out by the NPEs */
1975 + if (!ports_open) {
1976 + err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0);
1977 + if (err)
1978 + goto rel_txready;
1979 + }
1980 + return 0;
1981 +
1982 +rel_txready:
1983 + qmgr_release_queue(port->plat->txreadyq);
1984 +rel_tx:
1985 + qmgr_release_queue(TX_QUEUE(port->id));
1986 +rel_rx:
1987 + qmgr_release_queue(port->plat->rxq);
1988 +rel_rxfree:
1989 + qmgr_release_queue(RXFREE_QUEUE(port->id));
1990 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1991 + port->netdev->name);
1992 + return err;
1993 +}
1994 +
1995 +static void release_queues(struct port *port)
1996 +{
1997 + qmgr_release_queue(RXFREE_QUEUE(port->id));
1998 + qmgr_release_queue(port->plat->rxq);
1999 + qmgr_release_queue(TX_QUEUE(port->id));
2000 + qmgr_release_queue(port->plat->txreadyq);
2001 +
2002 + if (!ports_open)
2003 + qmgr_release_queue(TXDONE_QUEUE);
2004 +}
2005 +
2006 +static int init_queues(struct port *port)
2007 +{
2008 + int i;
2009 +
2010 + if (!ports_open)
2011 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
2012 + POOL_ALLOC_SIZE, 32, 0)))
2013 + return -ENOMEM;
2014 +
2015 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
2016 + &port->desc_tab_phys)))
2017 + return -ENOMEM;
2018 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
2019 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
2020 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
2021 +
2022 + /* Setup RX buffers */
2023 + for (i = 0; i < RX_DESCS; i++) {
2024 + struct desc *desc = rx_desc_ptr(port, i);
2025 + buffer_t *buff;
2026 + void *data;
2027 +#ifdef __ARMEB__
2028 + if (!(buff = netdev_alloc_skb(port->netdev, MAX_MRU)))
2029 + return -ENOMEM;
2030 + data = buff->data;
2031 +#else
2032 + if (!(buff = kmalloc(MAX_MRU, GFP_KERNEL)))
2033 + return -ENOMEM;
2034 + data = buff;
2035 +#endif
2036 + desc->buf_len = MAX_MRU;
2037 + desc->data = dma_map_single(&port->netdev->dev, data,
2038 + MAX_MRU, DMA_FROM_DEVICE);
2039 + if (dma_mapping_error(desc->data)) {
2040 + free_buffer(buff);
2041 + return -EIO;
2042 + }
2043 + port->rx_buff_tab[i] = buff;
2044 + }
2045 +
2046 + return 0;
2047 +}
2048 +
2049 +static void destroy_queues(struct port *port)
2050 +{
2051 + int i;
2052 +
2053 + if (port->desc_tab) {
2054 + for (i = 0; i < RX_DESCS; i++) {
2055 + struct desc *desc = rx_desc_ptr(port, i);
2056 + buffer_t *buff = port->rx_buff_tab[i];
2057 + if (buff) {
2058 + dma_unmap_single(&port->netdev->dev,
2059 + desc->data, MAX_MRU,
2060 + DMA_FROM_DEVICE);
2061 + free_buffer(buff);
2062 + }
2063 + }
2064 + for (i = 0; i < TX_DESCS; i++) {
2065 + struct desc *desc = tx_desc_ptr(port, i);
2066 + buffer_t *buff = port->tx_buff_tab[i];
2067 + if (buff) {
2068 + dma_unmap_tx(port, desc);
2069 + free_buffer(buff);
2070 + }
2071 + }
2072 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
2073 + port->desc_tab = NULL;
2074 + }
2075 +
2076 + if (!ports_open && dma_pool) {
2077 + dma_pool_destroy(dma_pool);
2078 + dma_pool = NULL;
2079 + }
2080 +}
2081 +
2082 +static int eth_open(struct net_device *dev)
2083 +{
2084 + struct port *port = netdev_priv(dev);
2085 + struct npe *npe = port->npe;
2086 + struct msg msg;
2087 + int i, err;
2088 +
2089 + if (!npe_running(npe)) {
2090 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
2091 + if (err)
2092 + return err;
2093 +
2094 + if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
2095 + printk(KERN_ERR "%s: %s not responding\n", dev->name,
2096 + npe_name(npe));
2097 + return -EIO;
2098 + }
2099 + }
2100 +
2101 + mdio_write(dev, port->plat->phy, MII_BMCR, port->mii_bmcr);
2102 +
2103 + memset(&msg, 0, sizeof(msg));
2104 + msg.cmd = NPE_VLAN_SETRXQOSENTRY;
2105 + msg.eth_id = port->id;
2106 + msg.byte5 = port->plat->rxq | 0x80;
2107 + msg.byte7 = port->plat->rxq << 4;
2108 + for (i = 0; i < 8; i++) {
2109 + msg.byte3 = i;
2110 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
2111 + return -EIO;
2112 + }
2113 +
2114 + msg.cmd = NPE_EDB_SETPORTADDRESS;
2115 + msg.eth_id = PHYSICAL_ID(port->id);
2116 + msg.byte2 = dev->dev_addr[0];
2117 + msg.byte3 = dev->dev_addr[1];
2118 + msg.byte4 = dev->dev_addr[2];
2119 + msg.byte5 = dev->dev_addr[3];
2120 + msg.byte6 = dev->dev_addr[4];
2121 + msg.byte7 = dev->dev_addr[5];
2122 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
2123 + return -EIO;
2124 +
2125 + memset(&msg, 0, sizeof(msg));
2126 + msg.cmd = NPE_FW_SETFIREWALLMODE;
2127 + msg.eth_id = port->id;
2128 + if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
2129 + return -EIO;
2130 +
2131 + if ((err = request_queues(port)) != 0)
2132 + return err;
2133 +
2134 + if ((err = init_queues(port)) != 0) {
2135 + destroy_queues(port);
2136 + release_queues(port);
2137 + return err;
2138 + }
2139 +
2140 + for (i = 0; i < ETH_ALEN; i++)
2141 + __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
2142 + __raw_writel(0x08, &port->regs->random_seed);
2143 + __raw_writel(0x12, &port->regs->partial_empty_threshold);
2144 + __raw_writel(0x30, &port->regs->partial_full_threshold);
2145 + __raw_writel(0x08, &port->regs->tx_start_bytes);
2146 + __raw_writel(0x15, &port->regs->tx_deferral);
2147 + __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
2148 + __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
2149 + __raw_writel(0x80, &port->regs->slot_time);
2150 + __raw_writel(0x01, &port->regs->int_clock_threshold);
2151 +
2152 + /* Populate queues with buffers, no failure after this point */
2153 + for (i = 0; i < TX_DESCS; i++)
2154 + queue_put_desc(port->plat->txreadyq,
2155 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
2156 +
2157 + for (i = 0; i < RX_DESCS; i++)
2158 + queue_put_desc(RXFREE_QUEUE(port->id),
2159 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
2160 +
2161 + __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
2162 + __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
2163 + __raw_writel(0, &port->regs->rx_control[1]);
2164 + __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
2165 +
2166 + phy_check_media(port, 1);
2167 + eth_set_mcast_list(dev);
2168 + netif_start_queue(dev);
2169 + schedule_delayed_work(&port->mdio_thread, MDIO_INTERVAL);
2170 +
2171 + qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
2172 + eth_rx_irq, dev);
2173 + if (!ports_open) {
2174 + qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
2175 + eth_txdone_irq, NULL);
2176 + qmgr_enable_irq(TXDONE_QUEUE);
2177 + }
2178 + ports_open++;
2179 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
2180 + return 0;
2181 +}
2182 +
2183 +static int eth_close(struct net_device *dev)
2184 +{
2185 + struct port *port = netdev_priv(dev);
2186 + struct msg msg;
2187 + int buffs = RX_DESCS; /* allocated RX buffers */
2188 + int i;
2189 +
2190 + ports_open--;
2191 + qmgr_disable_irq(port->plat->rxq);
2192 + netif_stop_queue(dev);
2193 +
2194 + while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
2195 + buffs--;
2196 +
2197 + memset(&msg, 0, sizeof(msg));
2198 + msg.cmd = NPE_SETLOOPBACK_MODE;
2199 + msg.eth_id = port->id;
2200 + msg.byte3 = 1;
2201 + if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
2202 + printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
2203 +
2204 + i = 0;
2205 + do { /* drain RX buffers */
2206 + while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
2207 + buffs--;
2208 + if (!buffs)
2209 + break;
2210 + if (qmgr_stat_empty(TX_QUEUE(port->id))) {
2211 + /* we have to inject some packet */
2212 + struct desc *desc;
2213 + u32 phys;
2214 + int n = queue_get_desc(port->plat->txreadyq, port, 1);
2215 + BUG_ON(n < 0);
2216 + desc = tx_desc_ptr(port, n);
2217 + phys = tx_desc_phys(port, n);
2218 + desc->buf_len = desc->pkt_len = 1;
2219 + wmb();
2220 + queue_put_desc(TX_QUEUE(port->id), phys, desc);
2221 + }
2222 + udelay(1);
2223 + } while (++i < MAX_CLOSE_WAIT);
2224 +
2225 + if (buffs)
2226 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
2227 + " left in NPE\n", dev->name, buffs);
2228 +#if DEBUG_CLOSE
2229 + if (!buffs)
2230 + printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
2231 +#endif
2232 +
2233 + buffs = TX_DESCS;
2234 + while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
2235 + buffs--; /* cancel TX */
2236 +
2237 + i = 0;
2238 + do {
2239 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
2240 + buffs--;
2241 + if (!buffs)
2242 + break;
2243 + } while (++i < MAX_CLOSE_WAIT);
2244 +
2245 + if (buffs)
2246 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
2247 + "left in NPE\n", dev->name, buffs);
2248 +#if DEBUG_CLOSE
2249 + if (!buffs)
2250 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
2251 +#endif
2252 +
2253 + msg.byte3 = 0;
2254 + if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
2255 + printk(KERN_CRIT "%s: unable to disable loopback\n",
2256 + dev->name);
2257 +
2258 + port->mii_bmcr = mdio_read(dev, port->plat->phy, MII_BMCR) &
2259 + ~(BMCR_RESET | BMCR_PDOWN); /* may have been altered */
2260 + mdio_write(dev, port->plat->phy, MII_BMCR,
2261 + port->mii_bmcr | BMCR_PDOWN);
2262 +
2263 + if (!ports_open)
2264 + qmgr_disable_irq(TXDONE_QUEUE);
2265 + cancel_rearming_delayed_work(&port->mdio_thread);
2266 + destroy_queues(port);
2267 + release_queues(port);
2268 + return 0;
2269 +}
2270 +
2271 +static int __devinit eth_init_one(struct platform_device *pdev)
2272 +{
2273 + struct port *port;
2274 + struct net_device *dev;
2275 + struct eth_plat_info *plat = pdev->dev.platform_data;
2276 + u32 regs_phys;
2277 + int err;
2278 +
2279 + if (!(dev = alloc_etherdev(sizeof(struct port))))
2280 + return -ENOMEM;
2281 +
2282 + SET_MODULE_OWNER(dev);
2283 + SET_NETDEV_DEV(dev, &pdev->dev);
2284 + port = netdev_priv(dev);
2285 + port->netdev = dev;
2286 + port->id = pdev->id;
2287 +
2288 + switch (port->id) {
2289 + case IXP4XX_ETH_NPEA:
2290 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
2291 + regs_phys = IXP4XX_EthA_BASE_PHYS;
2292 + break;
2293 + case IXP4XX_ETH_NPEB:
2294 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
2295 + regs_phys = IXP4XX_EthB_BASE_PHYS;
2296 + break;
2297 + case IXP4XX_ETH_NPEC:
2298 + port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
2299 + regs_phys = IXP4XX_EthC_BASE_PHYS;
2300 + break;
2301 + default:
2302 + err = -ENOSYS;
2303 + goto err_free;
2304 + }
2305 +
2306 + dev->open = eth_open;
2307 + dev->hard_start_xmit = eth_xmit;
2308 + dev->poll = eth_poll;
2309 + dev->stop = eth_close;
2310 + dev->get_stats = eth_stats;
2311 + dev->do_ioctl = eth_ioctl;
2312 + dev->set_multicast_list = eth_set_mcast_list;
2313 + dev->weight = 16;
2314 + dev->tx_queue_len = 100;
2315 +
2316 + if (!(port->npe = npe_request(NPE_ID(port->id)))) {
2317 + err = -EIO;
2318 + goto err_free;
2319 + }
2320 +
2321 + if (register_netdev(dev)) {
2322 + err = -EIO;
2323 + goto err_npe_rel;
2324 + }
2325 +
2326 + port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
2327 + if (!port->mem_res) {
2328 + err = -EBUSY;
2329 + goto err_unreg;
2330 + }
2331 +
2332 + port->plat = plat;
2333 + npe_port_tab[NPE_ID(port->id)] = port;
2334 + memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
2335 +
2336 + platform_set_drvdata(pdev, dev);
2337 +
2338 + __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
2339 + &port->regs->core_control);
2340 + udelay(50);
2341 + __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
2342 + udelay(50);
2343 +
2344 + port->mii.dev = dev;
2345 + port->mii.mdio_read = mdio_read;
2346 + port->mii.mdio_write = mdio_write;
2347 + port->mii.phy_id = plat->phy;
2348 + port->mii.phy_id_mask = 0x1F;
2349 + port->mii.reg_num_mask = 0x1F;
2350 +
2351 + printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
2352 + npe_name(port->npe));
2353 +
2354 + phy_reset(dev, plat->phy);
2355 + port->mii_bmcr = mdio_read(dev, plat->phy, MII_BMCR) &
2356 + ~(BMCR_RESET | BMCR_PDOWN);
2357 + mdio_write(dev, plat->phy, MII_BMCR, port->mii_bmcr | BMCR_PDOWN);
2358 +
2359 + INIT_DELAYED_WORK(&port->mdio_thread, mdio_thread);
2360 + return 0;
2361 +
2362 +err_unreg:
2363 + unregister_netdev(dev);
2364 +err_npe_rel:
2365 + npe_release(port->npe);
2366 +err_free:
2367 + free_netdev(dev);
2368 + return err;
2369 +}
2370 +
2371 +static int __devexit eth_remove_one(struct platform_device *pdev)
2372 +{
2373 + struct net_device *dev = platform_get_drvdata(pdev);
2374 + struct port *port = netdev_priv(dev);
2375 +
2376 + unregister_netdev(dev);
2377 + npe_port_tab[NPE_ID(port->id)] = NULL;
2378 + platform_set_drvdata(pdev, NULL);
2379 + npe_release(port->npe);
2380 + release_resource(port->mem_res);
2381 + free_netdev(dev);
2382 + return 0;
2383 +}
2384 +
2385 +static struct platform_driver drv = {
2386 + .driver.name = DRV_NAME,
2387 + .probe = eth_init_one,
2388 + .remove = eth_remove_one,
2389 +};
2390 +
2391 +static int __init eth_init_module(void)
2392 +{
2393 + if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
2394 + return -ENOSYS;
2395 +
2396 + /* All MII PHY accesses use NPE-B Ethernet registers */
2397 + spin_lock_init(&mdio_lock);
2398 + mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
2399 + __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
2400 +
2401 + return platform_driver_register(&drv);
2402 +}
2403 +
2404 +static void __exit eth_cleanup_module(void)
2405 +{
2406 + platform_driver_unregister(&drv);
2407 +}
2408 +
2409 +MODULE_AUTHOR("Krzysztof Halasa");
2410 +MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
2411 +MODULE_LICENSE("GPL v2");
2412 +module_init(eth_init_module);
2413 +module_exit(eth_cleanup_module);
2414 diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
2415 index a3df09e..94e7aa7 100644
2416 --- a/drivers/net/wan/Kconfig
2417 +++ b/drivers/net/wan/Kconfig
2418 @@ -334,6 +334,15 @@ config DSCC4_PCI_RST
2419
2420 Say Y if your card supports this feature.
2421
2422 +config IXP4XX_HSS
2423 + tristate "IXP4xx HSS (synchronous serial port) support"
2424 + depends on HDLC && ARM && ARCH_IXP4XX
2425 + select IXP4XX_NPE
2426 + select IXP4XX_QMGR
2427 + help
2428 + Say Y here if you want to use built-in HSS ports
2429 + on IXP4xx processor.
2430 +
2431 config DLCI
2432 tristate "Frame Relay DLCI support"
2433 ---help---
2434 diff --git a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
2435 index d61fef3..1b1d116 100644
2436 --- a/drivers/net/wan/Makefile
2437 +++ b/drivers/net/wan/Makefile
2438 @@ -42,6 +42,7 @@ obj-$(CONFIG_C101) += c101.o
2439 obj-$(CONFIG_WANXL) += wanxl.o
2440 obj-$(CONFIG_PCI200SYN) += pci200syn.o
2441 obj-$(CONFIG_PC300TOO) += pc300too.o
2442 +obj-$(CONFIG_IXP4XX_HSS) += ixp4xx_hss.o
2443
2444 clean-files := wanxlfw.inc
2445 $(obj)/wanxl.o: $(obj)/wanxlfw.inc
2446 diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c
2447 new file mode 100644
2448 index 0000000..c4cdace
2449 --- /dev/null
2450 +++ b/drivers/net/wan/ixp4xx_hss.c
2451 @@ -0,0 +1,1270 @@
2452 +/*
2453 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
2454 + *
2455 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
2456 + *
2457 + * This program is free software; you can redistribute it and/or modify it
2458 + * under the terms of version 2 of the GNU General Public License
2459 + * as published by the Free Software Foundation.
2460 + */
2461 +
2462 +#include <linux/dma-mapping.h>
2463 +#include <linux/dmapool.h>
2464 +#include <linux/io.h>
2465 +#include <linux/kernel.h>
2466 +#include <linux/hdlc.h>
2467 +#include <linux/platform_device.h>
2468 +#include <asm/arch/npe.h>
2469 +#include <asm/arch/qmgr.h>
2470 +
2471 +#define DEBUG_QUEUES 0
2472 +#define DEBUG_DESC 0
2473 +#define DEBUG_RX 0
2474 +#define DEBUG_TX 0
2475 +#define DEBUG_PKT_BYTES 0
2476 +#define DEBUG_CLOSE 0
2477 +
2478 +#define DRV_NAME "ixp4xx_hss"
2479 +
2480 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
2481 +#define FRAME_SYNC_OFFSET 0 /* unused, channelized only */
2482 +#define FRAME_SYNC_SIZE 1024
2483 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
2484 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
2485 +
2486 +#define RX_DESCS 16 /* also length of all RX queues */
2487 +#define TX_DESCS 16 /* also length of all TX queues */
2488 +
2489 +#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
2490 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
2491 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
2492 +
2493 +/* Queue IDs */
2494 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
2495 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
2496 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
2497 +#define HSS0_PKT_TX1_QUEUE 15
2498 +#define HSS0_PKT_TX2_QUEUE 16
2499 +#define HSS0_PKT_TX3_QUEUE 17
2500 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
2501 +#define HSS0_PKT_RXFREE1_QUEUE 19
2502 +#define HSS0_PKT_RXFREE2_QUEUE 20
2503 +#define HSS0_PKT_RXFREE3_QUEUE 21
2504 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
2505 +
2506 +#define HSS1_CHL_RXTRIG_QUEUE 10
2507 +#define HSS1_PKT_RX_QUEUE 0
2508 +#define HSS1_PKT_TX0_QUEUE 5
2509 +#define HSS1_PKT_TX1_QUEUE 6
2510 +#define HSS1_PKT_TX2_QUEUE 7
2511 +#define HSS1_PKT_TX3_QUEUE 8
2512 +#define HSS1_PKT_RXFREE0_QUEUE 1
2513 +#define HSS1_PKT_RXFREE1_QUEUE 2
2514 +#define HSS1_PKT_RXFREE2_QUEUE 3
2515 +#define HSS1_PKT_RXFREE3_QUEUE 4
2516 +#define HSS1_PKT_TXDONE_QUEUE 9
2517 +
2518 +#define NPE_PKT_MODE_HDLC 0
2519 +#define NPE_PKT_MODE_RAW 1
2520 +#define NPE_PKT_MODE_56KMODE 2
2521 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
2522 +
2523 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
2524 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
2525 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
2526 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
2527 +
2528 +
2529 +/* hss_config, PCRs */
2530 +/* Frame sync sampling, default = active low */
2531 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
2532 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
2533 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
2534 +
2535 +/* Frame sync pin: input (default) or output generated off a given clk edge */
2536 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
2537 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
2538 +
2539 +/* Frame and data clock sampling on edge, default = falling */
2540 +#define PCR_FCLK_EDGE_RISING 0x08000000
2541 +#define PCR_DCLK_EDGE_RISING 0x04000000
2542 +
2543 +/* Clock direction, default = input */
2544 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
2545 +
2546 +/* Generate/Receive frame pulses, default = enabled */
2547 +#define PCR_FRM_PULSE_DISABLED 0x01000000
2548 +
2549 + /* Data rate is full (default) or half the configured clk speed */
2550 +#define PCR_HALF_CLK_RATE 0x00200000
2551 +
2552 +/* Invert data between NPE and HSS FIFOs? (default = no) */
2553 +#define PCR_DATA_POLARITY_INVERT 0x00100000
2554 +
2555 +/* TX/RX endianness, default = LSB */
2556 +#define PCR_MSB_ENDIAN 0x00080000
2557 +
2558 +/* Normal (default) / open drain mode (TX only) */
2559 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
2560 +
2561 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
2562 +#define PCR_SOF_NO_FBIT 0x00020000
2563 +
2564 +/* Drive data pins? */
2565 +#define PCR_TX_DATA_ENABLE 0x00010000
2566 +
2567 +/* Voice 56k type: drive the data pins low (default), high, high Z */
2568 +#define PCR_TX_V56K_HIGH 0x00002000
2569 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
2570 +
2571 +/* Unassigned type: drive the data pins low (default), high, high Z */
2572 +#define PCR_TX_UNASS_HIGH 0x00000800
2573 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
2574 +
2575 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
2576 +#define PCR_TX_FB_HIGH_IMP 0x00000400
2577 +
2578 +/* 56k data endiannes - which bit unused: high (default) or low */
2579 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
2580 +
2581 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
2582 +#define PCR_TX_56KS_56K_DATA 0x00000100
2583 +
2584 +/* hss_config, cCR */
2585 +/* Number of packetized clients, default = 1 */
2586 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
2587 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
2588 +
2589 +/* default = no loopback */
2590 +#define CCR_LOOPBACK 0x02000000
2591 +
2592 +/* HSS number, default = 0 (first) */
2593 +#define CCR_SECOND_HSS 0x01000000
2594 +
2595 +
2596 +/* hss_config, clkCR: main:10, num:10, denom:12 */
2597 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
2598 +
2599 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
2600 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
2601 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
2602 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
2603 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
2604 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
2605 +
2606 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
2607 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
2608 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
2609 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
2610 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
2611 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
2612 +
2613 +
2614 +/* hss_config, LUT entries */
2615 +#define TDMMAP_UNASSIGNED 0
2616 +#define TDMMAP_HDLC 1 /* HDLC - packetized */
2617 +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
2618 +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
2619 +
2620 +#define TIMESLOTS 128
2621 +#define LUT_BITS 2
2622 +
2623 +/* offsets into HSS config */
2624 +#define HSS_CONFIG_TX_PCR 0x00
2625 +#define HSS_CONFIG_RX_PCR 0x04
2626 +#define HSS_CONFIG_CORE_CR 0x08
2627 +#define HSS_CONFIG_CLOCK_CR 0x0C
2628 +#define HSS_CONFIG_TX_FCR 0x10
2629 +#define HSS_CONFIG_RX_FCR 0x14
2630 +#define HSS_CONFIG_TX_LUT 0x18
2631 +#define HSS_CONFIG_RX_LUT 0x38
2632 +
2633 +
2634 +/* NPE command codes */
2635 +/* writes the ConfigWord value to the location specified by offset */
2636 +#define PORT_CONFIG_WRITE 0x40
2637 +
2638 +/* triggers the NPE to load the contents of the configuration table */
2639 +#define PORT_CONFIG_LOAD 0x41
2640 +
2641 +/* triggers the NPE to return an HssErrorReadResponse message */
2642 +#define PORT_ERROR_READ 0x42
2643 +
2644 +/* reset NPE internal status and enable the HssChannelized operation */
2645 +#define CHAN_FLOW_ENABLE 0x43
2646 +#define CHAN_FLOW_DISABLE 0x44
2647 +#define CHAN_IDLE_PATTERN_WRITE 0x45
2648 +#define CHAN_NUM_CHANS_WRITE 0x46
2649 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
2650 +#define CHAN_RX_BUF_CFG_WRITE 0x48
2651 +#define CHAN_TX_BLK_CFG_WRITE 0x49
2652 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
2653 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
2654 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
2655 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
2656 +
2657 +/* downloads the gainWord value for a timeslot switching channel associated
2658 + with bypassNum */
2659 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
2660 +
2661 +/* triggers the NPE to reset internal status and enable the HssPacketized
2662 + operation for the flow specified by pPipe */
2663 +#define PKT_PIPE_FLOW_ENABLE 0x50
2664 +#define PKT_PIPE_FLOW_DISABLE 0x51
2665 +#define PKT_NUM_PIPES_WRITE 0x52
2666 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
2667 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
2668 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
2669 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
2670 +#define PKT_PIPE_MODE_WRITE 0x57
2671 +
2672 +/* HDLC packet status values - desc->status */
2673 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
2674 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
2675 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
2676 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
2677 + this packet (if buf_len < pkt_len) */
2678 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
2679 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
2680 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
2681 +
2682 +
2683 +#ifdef __ARMEB__
2684 +typedef struct sk_buff buffer_t;
2685 +#define free_buffer dev_kfree_skb
2686 +#define free_buffer_irq dev_kfree_skb_irq
2687 +#else
2688 +typedef void buffer_t;
2689 +#define free_buffer kfree
2690 +#define free_buffer_irq kfree
2691 +#endif
2692 +
2693 +struct port {
2694 + struct npe *npe;
2695 + struct net_device *netdev;
2696 + struct hss_plat_info *plat;
2697 + buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
2698 + struct desc *desc_tab; /* coherent */
2699 + u32 desc_tab_phys;
2700 + int id;
2701 + unsigned int clock_type, clock_rate, loopback;
2702 + u8 hdlc_cfg;
2703 +};
2704 +
2705 +/* NPE message structure */
2706 +struct msg {
2707 +#ifdef __ARMEB__
2708 + u8 cmd, unused, hss_port, index;
2709 + union {
2710 + struct { u8 data8a, data8b, data8c, data8d; };
2711 + struct { u16 data16a, data16b; };
2712 + struct { u32 data32; };
2713 + };
2714 +#else
2715 + u8 index, hss_port, unused, cmd;
2716 + union {
2717 + struct { u8 data8d, data8c, data8b, data8a; };
2718 + struct { u16 data16b, data16a; };
2719 + struct { u32 data32; };
2720 + };
2721 +#endif
2722 +};
2723 +
2724 +/* HDLC packet descriptor */
2725 +struct desc {
2726 + u32 next; /* pointer to next buffer, unused */
2727 +
2728 +#ifdef __ARMEB__
2729 + u16 buf_len; /* buffer length */
2730 + u16 pkt_len; /* packet length */
2731 + u32 data; /* pointer to data buffer in RAM */
2732 + u8 status;
2733 + u8 error_count;
2734 + u16 __reserved;
2735 +#else
2736 + u16 pkt_len; /* packet length */
2737 + u16 buf_len; /* buffer length */
2738 + u32 data; /* pointer to data buffer in RAM */
2739 + u16 __reserved;
2740 + u8 error_count;
2741 + u8 status;
2742 +#endif
2743 + u32 __reserved1[4];
2744 +};
2745 +
2746 +
2747 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
2748 + (n) * sizeof(struct desc))
2749 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
2750 +
2751 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
2752 + ((n) + RX_DESCS) * sizeof(struct desc))
2753 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
2754 +
2755 +/*****************************************************************************
2756 + * global variables
2757 + ****************************************************************************/
2758 +
2759 +static int ports_open;
2760 +static struct dma_pool *dma_pool;
2761 +
2762 +static const struct {
2763 + int tx, txdone, rx, rxfree;
2764 +}queue_ids[2] = {{ HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE,
2765 + HSS0_PKT_RX_QUEUE, HSS0_PKT_RXFREE0_QUEUE },
2766 + { HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE,
2767 + HSS1_PKT_RX_QUEUE, HSS1_PKT_RXFREE0_QUEUE },
2768 +};
2769 +
2770 +/*****************************************************************************
2771 + * utility functions
2772 + ****************************************************************************/
2773 +
2774 +static inline struct port* dev_to_port(struct net_device *dev)
2775 +{
2776 + return dev_to_hdlc(dev)->priv;
2777 +}
2778 +
2779 +#ifndef __ARMEB__
2780 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
2781 +{
2782 + int i;
2783 + for (i = 0; i < cnt; i++)
2784 + dest[i] = swab32(src[i]);
2785 +}
2786 +#endif
2787 +
2788 +static inline void debug_pkt(struct net_device *dev, const char *func,
2789 + u8 *data, int len)
2790 +{
2791 +#if DEBUG_PKT_BYTES
2792 + int i;
2793 +
2794 + printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
2795 + for (i = 0; i < len; i++) {
2796 + if (i >= DEBUG_PKT_BYTES)
2797 + break;
2798 + printk("%s%02X", !(i % 4) ? " " : "", data[i]);
2799 + }
2800 + printk("\n");
2801 +#endif
2802 +}
2803 +
2804 +
2805 +static inline void debug_desc(u32 phys, struct desc *desc)
2806 +{
2807 +#if DEBUG_DESC
2808 + printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
2809 + phys, desc->next, desc->buf_len, desc->pkt_len,
2810 + desc->data, desc->status, desc->error_count);
2811 +#endif
2812 +}
2813 +
2814 +static inline void debug_queue(unsigned int queue, int is_get, u32 phys)
2815 +{
2816 +#if DEBUG_QUEUES
2817 + static struct {
2818 + int queue;
2819 + char *name;
2820 + } names[] = {
2821 + { HSS0_PKT_TX0_QUEUE, "TX#0 " },
2822 + { HSS0_PKT_TXDONE_QUEUE, "TX-done#0 " },
2823 + { HSS0_PKT_RX_QUEUE, "RX#0 " },
2824 + { HSS0_PKT_RXFREE0_QUEUE, "RX-free#0 " },
2825 + { HSS1_PKT_TX0_QUEUE, "TX#1 " },
2826 + { HSS1_PKT_TXDONE_QUEUE, "TX-done#1 " },
2827 + { HSS1_PKT_RX_QUEUE, "RX#1 " },
2828 + { HSS1_PKT_RXFREE0_QUEUE, "RX-free#1 " },
2829 + };
2830 + int i;
2831 +
2832 + for (i = 0; i < ARRAY_SIZE(names); i++)
2833 + if (names[i].queue == queue)
2834 + break;
2835 +
2836 + printk(KERN_DEBUG "Queue %i %s%s %X\n", queue,
2837 + i < ARRAY_SIZE(names) ? names[i].name : "",
2838 + is_get ? "->" : "<-", phys);
2839 +#endif
2840 +}
2841 +
2842 +static inline u32 queue_get_entry(unsigned int queue)
2843 +{
2844 + u32 phys = qmgr_get_entry(queue);
2845 + debug_queue(queue, 1, phys);
2846 + return phys;
2847 +}
2848 +
2849 +static inline int queue_get_desc(unsigned int queue, struct port *port,
2850 + int is_tx)
2851 +{
2852 + u32 phys, tab_phys, n_desc;
2853 + struct desc *tab;
2854 +
2855 + if (!(phys = queue_get_entry(queue)))
2856 + return -1;
2857 +
2858 + BUG_ON(phys & 0x1F);
2859 + tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
2860 + tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
2861 + n_desc = (phys - tab_phys) / sizeof(struct desc);
2862 + BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
2863 + debug_desc(phys, &tab[n_desc]);
2864 + BUG_ON(tab[n_desc].next);
2865 + return n_desc;
2866 +}
2867 +
2868 +static inline void queue_put_desc(unsigned int queue, u32 phys,
2869 + struct desc *desc)
2870 +{
2871 + debug_queue(queue, 0, phys);
2872 + debug_desc(phys, desc);
2873 + BUG_ON(phys & 0x1F);
2874 + qmgr_put_entry(queue, phys);
2875 + BUG_ON(qmgr_stat_overflow(queue));
2876 +}
2877 +
2878 +
2879 +static inline void dma_unmap_tx(struct port *port, struct desc *desc)
2880 +{
2881 +#ifdef __ARMEB__
2882 + dma_unmap_single(&port->netdev->dev, desc->data,
2883 + desc->buf_len, DMA_TO_DEVICE);
2884 +#else
2885 + dma_unmap_single(&port->netdev->dev, desc->data & ~3,
2886 + ALIGN((desc->data & 3) + desc->buf_len, 4),
2887 + DMA_TO_DEVICE);
2888 +#endif
2889 +}
2890 +
2891 +
2892 +static void hss_hdlc_set_carrier(void *pdev, int carrier)
2893 +{
2894 + struct net_device *dev = pdev;
2895 + if (carrier)
2896 + netif_carrier_on(dev);
2897 + else
2898 + netif_carrier_off(dev);
2899 +}
2900 +
2901 +static void hss_hdlc_rx_irq(void *pdev)
2902 +{
2903 + struct net_device *dev = pdev;
2904 + struct port *port = dev_to_port(dev);
2905 +
2906 +#if DEBUG_RX
2907 + printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
2908 +#endif
2909 + qmgr_disable_irq(queue_ids[port->id].rx);
2910 + netif_rx_schedule(dev);
2911 +}
2912 +
2913 +static int hss_hdlc_poll(struct net_device *dev, int *budget)
2914 +{
2915 + struct port *port = dev_to_port(dev);
2916 + unsigned int rxq = queue_ids[port->id].rx;
2917 + unsigned int rxfreeq = queue_ids[port->id].rxfree;
2918 + struct net_device_stats *stats = hdlc_stats(dev);
2919 + int quota = dev->quota, received = 0;
2920 +
2921 +#if DEBUG_RX
2922 + printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
2923 +#endif
2924 +
2925 + while (quota) {
2926 + struct sk_buff *skb;
2927 + struct desc *desc;
2928 + int n;
2929 +#ifdef __ARMEB__
2930 + struct sk_buff *temp;
2931 + u32 phys;
2932 +#endif
2933 +
2934 + if ((n = queue_get_desc(rxq, port, 0)) < 0) {
2935 + dev->quota -= received; /* No packet received */
2936 + *budget -= received;
2937 + received = 0;
2938 +#if DEBUG_RX
2939 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
2940 + " netif_rx_complete\n", dev->name);
2941 +#endif
2942 + netif_rx_complete(dev);
2943 + qmgr_enable_irq(rxq);
2944 + if (!qmgr_stat_empty(rxq) &&
2945 + netif_rx_reschedule(dev, 0)) {
2946 +#if DEBUG_RX
2947 + printk(KERN_DEBUG "%s: hss_hdlc_poll"
2948 + " netif_rx_reschedule successed\n",
2949 + dev->name);
2950 +#endif
2951 + qmgr_disable_irq(rxq);
2952 + continue;
2953 + }
2954 +#if DEBUG_RX
2955 + printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
2956 + dev->name);
2957 +#endif
2958 + return 0; /* all work done */
2959 + }
2960 +
2961 + desc = rx_desc_ptr(port, n);
2962 +
2963 + if (desc->error_count) /* FIXME - remove printk */
2964 + printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
2965 + " errors %u\n", dev->name, desc->status,
2966 + desc->error_count);
2967 +
2968 + skb = NULL;
2969 + switch (desc->status) {
2970 + case 0:
2971 +#ifdef __ARMEB__
2972 + if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
2973 + phys = dma_map_single(&dev->dev, skb->data,
2974 + RX_SIZE,
2975 + DMA_FROM_DEVICE);
2976 + if (dma_mapping_error(phys)) {
2977 + dev_kfree_skb(skb);
2978 + skb = NULL;
2979 + }
2980 + }
2981 +#else
2982 + skb = netdev_alloc_skb(dev, desc->pkt_len);
2983 +#endif
2984 + if (!skb)
2985 + stats->rx_dropped++;
2986 + break;
2987 + case ERR_HDLC_ALIGN:
2988 + case ERR_HDLC_ABORT:
2989 + stats->rx_frame_errors++;
2990 + stats->rx_errors++;
2991 + break;
2992 + case ERR_HDLC_FCS:
2993 + stats->rx_crc_errors++;
2994 + stats->rx_errors++;
2995 + break;
2996 + case ERR_HDLC_TOO_LONG:
2997 + stats->rx_length_errors++;
2998 + stats->rx_errors++;
2999 + break;
3000 + default: /* FIXME - remove printk */
3001 + printk(KERN_ERR "%s: hss_hdlc_poll: status 0x%02X"
3002 + " errors %u\n", dev->name, desc->status,
3003 + desc->error_count);
3004 + stats->rx_errors++;
3005 + }
3006 +
3007 + if (!skb) {
3008 + /* put the desc back on RX-ready queue */
3009 + desc->buf_len = RX_SIZE;
3010 + desc->pkt_len = desc->status = 0;
3011 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
3012 + continue;
3013 + }
3014 +
3015 + /* process received frame */
3016 +#ifdef __ARMEB__
3017 + temp = skb;
3018 + skb = port->rx_buff_tab[n];
3019 + dma_unmap_single(&dev->dev, desc->data,
3020 + RX_SIZE, DMA_FROM_DEVICE);
3021 +#else
3022 + dma_sync_single(&dev->dev, desc->data,
3023 + RX_SIZE, DMA_FROM_DEVICE);
3024 + memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
3025 + ALIGN(desc->pkt_len, 4) / 4);
3026 +#endif
3027 + skb_put(skb, desc->pkt_len);
3028 +
3029 + debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
3030 +
3031 + skb->protocol = hdlc_type_trans(skb, dev);
3032 + dev->last_rx = jiffies;
3033 + stats->rx_packets++;
3034 + stats->rx_bytes += skb->len;
3035 + netif_receive_skb(skb);
3036 +
3037 + /* put the new buffer on RX-free queue */
3038 +#ifdef __ARMEB__
3039 + port->rx_buff_tab[n] = temp;
3040 + desc->data = phys;
3041 +#endif
3042 + desc->buf_len = RX_SIZE;
3043 + desc->pkt_len = 0;
3044 + queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
3045 + quota--;
3046 + received++;
3047 + }
3048 + dev->quota -= received;
3049 + *budget -= received;
3050 +#if DEBUG_RX
3051 + printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
3052 +#endif
3053 + return 1; /* not all work done */
3054 +}
3055 +
3056 +
3057 +static void hss_hdlc_txdone_irq(void *pdev)
3058 +{
3059 + struct net_device *dev = pdev;
3060 + struct port *port = dev_to_port(dev);
3061 + struct net_device_stats *stats = hdlc_stats(dev);
3062 + int n_desc;
3063 +
3064 +#if DEBUG_TX
3065 + printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
3066 +#endif
3067 + while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
3068 + port, 1)) >= 0) {
3069 + struct desc *desc;
3070 + int start;
3071 +
3072 + desc = tx_desc_ptr(port, n_desc);
3073 +
3074 + stats->tx_packets++;
3075 + stats->tx_bytes += desc->pkt_len;
3076 +
3077 + dma_unmap_tx(port, desc);
3078 +#if DEBUG_TX
3079 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
3080 + port->netdev->name, port->tx_buff_tab[n_desc]);
3081 +#endif
3082 + free_buffer_irq(port->tx_buff_tab[n_desc]);
3083 + port->tx_buff_tab[n_desc] = NULL;
3084 +
3085 + start = qmgr_stat_empty(port->plat->txreadyq);
3086 + queue_put_desc(port->plat->txreadyq,
3087 + tx_desc_phys(port, n_desc), desc);
3088 + if (start) {
3089 +#if DEBUG_TX
3090 + printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
3091 + " ready\n", port->netdev->name);
3092 +#endif
3093 + netif_wake_queue(port->netdev);
3094 + }
3095 + }
3096 +}
3097 +
3098 +static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
3099 +{
3100 + struct port *port = dev_to_port(dev);
3101 + struct net_device_stats *stats = hdlc_stats(dev);
3102 + unsigned int txreadyq = port->plat->txreadyq;
3103 + int len, offset, bytes, n;
3104 + void *mem;
3105 + u32 phys;
3106 + struct desc *desc;
3107 +
3108 +#if DEBUG_TX
3109 + printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
3110 +#endif
3111 +
3112 + if (unlikely(skb->len > HDLC_MAX_MRU)) {
3113 + dev_kfree_skb(skb);
3114 + stats->tx_errors++;
3115 + return NETDEV_TX_OK;
3116 + }
3117 +
3118 + debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
3119 +
3120 + len = skb->len;
3121 +#ifdef __ARMEB__
3122 + offset = 0; /* no need to keep alignment */
3123 + bytes = len;
3124 + mem = skb->data;
3125 +#else
3126 + offset = (int)skb->data & 3; /* keep 32-bit alignment */
3127 + bytes = ALIGN(offset + len, 4);
3128 + if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
3129 + dev_kfree_skb(skb);
3130 + stats->tx_dropped++;
3131 + return NETDEV_TX_OK;
3132 + }
3133 + memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
3134 + dev_kfree_skb(skb);
3135 +#endif
3136 +
3137 + phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
3138 + if (dma_mapping_error(phys)) {
3139 +#ifdef __ARMEB__
3140 + dev_kfree_skb(skb);
3141 +#else
3142 + kfree(mem);
3143 +#endif
3144 + stats->tx_dropped++;
3145 + return NETDEV_TX_OK;
3146 + }
3147 +
3148 + n = queue_get_desc(txreadyq, port, 1);
3149 + BUG_ON(n < 0);
3150 + desc = tx_desc_ptr(port, n);
3151 +
3152 +#ifdef __ARMEB__
3153 + port->tx_buff_tab[n] = skb;
3154 +#else
3155 + port->tx_buff_tab[n] = mem;
3156 +#endif
3157 + desc->data = phys + offset;
3158 + desc->buf_len = desc->pkt_len = len;
3159 +
3160 + wmb();
3161 + queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
3162 + dev->trans_start = jiffies;
3163 +
3164 + if (qmgr_stat_empty(txreadyq)) {
3165 +#if DEBUG_TX
3166 + printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
3167 +#endif
3168 + netif_stop_queue(dev);
3169 + /* we could miss TX ready interrupt */
3170 + if (!qmgr_stat_empty(txreadyq)) {
3171 +#if DEBUG_TX
3172 + printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
3173 + dev->name);
3174 +#endif
3175 + netif_wake_queue(dev);
3176 + }
3177 + }
3178 +
3179 +#if DEBUG_TX
3180 + printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
3181 +#endif
3182 + return NETDEV_TX_OK;
3183 +}
3184 +
3185 +
3186 +static int request_hdlc_queues(struct port *port)
3187 +{
3188 + int err;
3189 +
3190 + err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0);
3191 + if (err)
3192 + return err;
3193 +
3194 + err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0);
3195 + if (err)
3196 + goto rel_rxfree;
3197 +
3198 + err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0);
3199 + if (err)
3200 + goto rel_rx;
3201 +
3202 + err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0);
3203 + if (err)
3204 + goto rel_tx;
3205 +
3206 + err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0);
3207 + if (err)
3208 + goto rel_txready;
3209 + return 0;
3210 +
3211 +rel_txready:
3212 + qmgr_release_queue(port->plat->txreadyq);
3213 +rel_tx:
3214 + qmgr_release_queue(queue_ids[port->id].tx);
3215 +rel_rx:
3216 + qmgr_release_queue(queue_ids[port->id].rx);
3217 +rel_rxfree:
3218 + qmgr_release_queue(queue_ids[port->id].rxfree);
3219 + printk(KERN_DEBUG "%s: unable to request hardware queues\n",
3220 + port->netdev->name);
3221 + return err;
3222 +}
3223 +
3224 +static void release_hdlc_queues(struct port *port)
3225 +{
3226 + qmgr_release_queue(queue_ids[port->id].rxfree);
3227 + qmgr_release_queue(queue_ids[port->id].rx);
3228 + qmgr_release_queue(queue_ids[port->id].txdone);
3229 + qmgr_release_queue(queue_ids[port->id].tx);
3230 + qmgr_release_queue(port->plat->txreadyq);
3231 +}
3232 +
3233 +static int init_hdlc_queues(struct port *port)
3234 +{
3235 + int i;
3236 +
3237 + if (!ports_open)
3238 + if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
3239 + POOL_ALLOC_SIZE, 32, 0)))
3240 + return -ENOMEM;
3241 +
3242 + if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
3243 + &port->desc_tab_phys)))
3244 + return -ENOMEM;
3245 + memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
3246 + memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
3247 + memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
3248 +
3249 + /* Setup RX buffers */
3250 + for (i = 0; i < RX_DESCS; i++) {
3251 + struct desc *desc = rx_desc_ptr(port, i);
3252 + buffer_t *buff;
3253 + void *data;
3254 +#ifdef __ARMEB__
3255 + if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
3256 + return -ENOMEM;
3257 + data = buff->data;
3258 +#else
3259 + if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
3260 + return -ENOMEM;
3261 + data = buff;
3262 +#endif
3263 + desc->buf_len = RX_SIZE;
3264 + desc->data = dma_map_single(&port->netdev->dev, data,
3265 + RX_SIZE, DMA_FROM_DEVICE);
3266 + if (dma_mapping_error(desc->data)) {
3267 + free_buffer(buff);
3268 + return -EIO;
3269 + }
3270 + port->rx_buff_tab[i] = buff;
3271 + }
3272 +
3273 + return 0;
3274 +}
3275 +
3276 +static void destroy_hdlc_queues(struct port *port)
3277 +{
3278 + int i;
3279 +
3280 + if (port->desc_tab) {
3281 + for (i = 0; i < RX_DESCS; i++) {
3282 + struct desc *desc = rx_desc_ptr(port, i);
3283 + buffer_t *buff = port->rx_buff_tab[i];
3284 + if (buff) {
3285 + dma_unmap_single(&port->netdev->dev,
3286 + desc->data, RX_SIZE,
3287 + DMA_FROM_DEVICE);
3288 + free_buffer(buff);
3289 + }
3290 + }
3291 + for (i = 0; i < TX_DESCS; i++) {
3292 + struct desc *desc = tx_desc_ptr(port, i);
3293 + buffer_t *buff = port->tx_buff_tab[i];
3294 + if (buff) {
3295 + dma_unmap_tx(port, desc);
3296 + free_buffer(buff);
3297 + }
3298 + }
3299 + dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
3300 + port->desc_tab = NULL;
3301 + }
3302 +
3303 + if (!ports_open && dma_pool) {
3304 + dma_pool_destroy(dma_pool);
3305 + dma_pool = NULL;
3306 + }
3307 +}
3308 +
3309 +static int hss_hdlc_open(struct net_device *dev)
3310 +{
3311 + struct port *port = dev_to_port(dev);
3312 + struct npe *npe = port->npe;
3313 + struct msg msg;
3314 + int i, err;
3315 +
3316 + if (!npe_running(npe)) {
3317 + err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
3318 + if (err)
3319 + return err;
3320 + }
3321 +
3322 + if ((err = hdlc_open(dev)) != 0)
3323 + return err;
3324 +
3325 + if (port->plat->open)
3326 + if ((err = port->plat->open(port->id, port->netdev,
3327 + hss_hdlc_set_carrier)) != 0)
3328 + goto err_hdlc_close;
3329 +
3330 + /* HSS main configuration */
3331 + memset(&msg, 0, sizeof(msg));
3332 + msg.cmd = PORT_CONFIG_WRITE;
3333 + msg.hss_port = port->id;
3334 + msg.index = 0; /* offset in HSS config */
3335 +
3336 + msg.data32 = PCR_FRM_PULSE_DISABLED |
3337 + PCR_SOF_NO_FBIT |
3338 + PCR_MSB_ENDIAN |
3339 + PCR_TX_DATA_ENABLE;
3340 +
3341 + if (port->clock_type == CLOCK_INT)
3342 + msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
3343 +
3344 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_PCR") != 0))
3345 + goto err_plat_close; /* 0: TX PCR */
3346 +
3347 + msg.index = 4;
3348 + msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
3349 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_PCR") != 0))
3350 + goto err_plat_close; /* 4: RX PCR */
3351 +
3352 + msg.index = 8;
3353 + msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
3354 + (port->id ? CCR_SECOND_HSS : 0);
3355 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CORE_CR") != 0))
3356 + goto err_plat_close; /* 8: Core CR */
3357 +
3358 + msg.index = 12;
3359 + msg.data32 = CLK42X_SPEED_2048KHZ /* FIXME */;
3360 + if ((err = npe_send_message(npe, &msg, "HSS_SET_CLK_CR") != 0))
3361 + goto err_plat_close; /* 12: CLK CR */
3362 +
3363 + msg.data32 = (FRAME_SYNC_OFFSET << 16) | (FRAME_SYNC_SIZE - 1);
3364 + msg.index = 16;
3365 + if ((err = npe_send_message(npe, &msg, "HSS_SET_TX_FCR") != 0))
3366 + goto err_plat_close; /* 16: TX FCR */
3367 +
3368 + msg.index = 20;
3369 + if ((err = npe_send_message(npe, &msg, "HSS_SET_RX_FCR") != 0))
3370 + goto err_plat_close; /* 20: RX FCR */
3371 +
3372 + msg.data32 = 0; /* Fill LUT with HDLC timeslots */
3373 + for (i = 0; i < 32 / LUT_BITS; i++)
3374 + msg.data32 |= TDMMAP_HDLC << (LUT_BITS * i);
3375 +
3376 + for (i = 0; i < 2 /* TX and RX */ * TIMESLOTS * LUT_BITS / 8; i += 4) {
3377 + msg.index = 24 + i; /* 24 - 55: TX LUT, 56 - 87: RX LUT */
3378 + if ((err = npe_send_message(npe, &msg, "HSS_SET_LUT") != 0))
3379 + goto err_plat_close;
3380 + }
3381 +
3382 + /* HDLC mode configuration */
3383 + memset(&msg, 0, sizeof(msg));
3384 + msg.cmd = PKT_NUM_PIPES_WRITE;
3385 + msg.hss_port = port->id;
3386 + msg.data8a = PKT_NUM_PIPES;
3387 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_PIPES") != 0))
3388 + goto err_plat_close;
3389 +
3390 + memset(&msg, 0, sizeof(msg));
3391 + msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
3392 + msg.hss_port = port->id;
3393 + msg.data8a = PKT_PIPE_FIFO_SIZEW;
3394 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_FIFO") != 0))
3395 + goto err_plat_close;
3396 +
3397 + memset(&msg, 0, sizeof(msg));
3398 + msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
3399 + msg.hss_port = port->id;
3400 + msg.data32 = 0x7F7F7F7F;
3401 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_IDLE") != 0))
3402 + goto err_plat_close;
3403 +
3404 + memset(&msg, 0, sizeof(msg));
3405 + msg.cmd = PORT_CONFIG_LOAD;
3406 + msg.hss_port = port->id;
3407 + if ((err = npe_send_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
3408 + goto err_plat_close;
3409 + if ((err = npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG") != 0))
3410 + goto err_plat_close;
3411 +
3412 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
3413 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
3414 + printk(KERN_DEBUG "%s: unexpected message received in"
3415 + " response to HSS_LOAD_CONFIG\n", npe_name(npe));
3416 + err = EIO;
3417 + goto err_plat_close;
3418 + }
3419 +
3420 + memset(&msg, 0, sizeof(msg));
3421 + msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
3422 + msg.hss_port = port->id;
3423 + msg.data8a = port->hdlc_cfg; /* rx_cfg */
3424 + msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
3425 + if ((err = npe_send_message(npe, &msg, "HSS_SET_HDLC_CFG") != 0))
3426 + goto err_plat_close;
3427 +
3428 + memset(&msg, 0, sizeof(msg));
3429 + msg.cmd = PKT_PIPE_MODE_WRITE;
3430 + msg.hss_port = port->id;
3431 + msg.data8a = NPE_PKT_MODE_HDLC;
3432 + /* msg.data8b = inv_mask */
3433 + /* msg.data8c = or_mask */
3434 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_MODE") != 0))
3435 + goto err_plat_close;
3436 +
3437 + memset(&msg, 0, sizeof(msg));
3438 + msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
3439 + msg.hss_port = port->id;
3440 + msg.data16a = HDLC_MAX_MRU;
3441 + if ((err = npe_send_message(npe, &msg, "HSS_SET_PKT_RX_SIZE") != 0))
3442 + goto err_plat_close;
3443 +
3444 + if ((err = request_hdlc_queues(port)) != 0)
3445 + goto err_plat_close;
3446 +
3447 + if ((err = init_hdlc_queues(port)) != 0)
3448 + goto err_destroy_queues;
3449 +
3450 + memset(&msg, 0, sizeof(msg));
3451 + msg.cmd = PKT_PIPE_FLOW_ENABLE;
3452 + msg.hss_port = port->id;
3453 + if ((err = npe_send_message(npe, &msg, "HSS_ENABLE_PKT_PIPE") != 0))
3454 + goto err_destroy_queues;
3455 +
3456 + /* Populate queues with buffers, no failure after this point */
3457 + for (i = 0; i < TX_DESCS; i++)
3458 + queue_put_desc(port->plat->txreadyq,
3459 + tx_desc_phys(port, i), tx_desc_ptr(port, i));
3460 +
3461 + for (i = 0; i < RX_DESCS; i++)
3462 + queue_put_desc(queue_ids[port->id].rxfree,
3463 + rx_desc_phys(port, i), rx_desc_ptr(port, i));
3464 +
3465 + netif_start_queue(dev);
3466 +
3467 + qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
3468 + hss_hdlc_rx_irq, dev);
3469 +
3470 + qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
3471 + hss_hdlc_txdone_irq, dev);
3472 + qmgr_enable_irq(queue_ids[port->id].txdone);
3473 +
3474 + ports_open++;
3475 + netif_rx_schedule(dev); /* we may already have RX data, enables IRQ */
3476 + return 0;
3477 +
3478 +err_destroy_queues:
3479 + destroy_hdlc_queues(port);
3480 + release_hdlc_queues(port);
3481 +err_plat_close:
3482 + if (port->plat->close)
3483 + port->plat->close(port->id, port->netdev);
3484 +err_hdlc_close:
3485 + hdlc_close(dev);
3486 + return err;
3487 +}
3488 +
3489 +static int hss_hdlc_close(struct net_device *dev)
3490 +{
3491 + struct port *port = dev_to_port(dev);
3492 + struct npe *npe = port->npe;
3493 + struct msg msg;
3494 + int buffs = RX_DESCS; /* allocated RX buffers */
3495 + int i;
3496 +
3497 + ports_open--;
3498 + qmgr_disable_irq(queue_ids[port->id].rx);
3499 + netif_stop_queue(dev);
3500 +
3501 + memset(&msg, 0, sizeof(msg));
3502 + msg.cmd = PKT_PIPE_FLOW_DISABLE;
3503 + msg.hss_port = port->id;
3504 + if (npe_send_message(npe, &msg, "HSS_DISABLE_PKT_PIPE")) {
3505 + printk(KERN_CRIT "HSS-%i: unable to stop HDLC flow\n",
3506 + port->id);
3507 + /* The upper level would ignore the error anyway */
3508 + }
3509 +
3510 + while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
3511 + buffs--;
3512 + while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
3513 + buffs--;
3514 +
3515 + if (buffs)
3516 + printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
3517 + " left in NPE\n", dev->name, buffs);
3518 +
3519 + buffs = TX_DESCS;
3520 + while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
3521 + buffs--; /* cancel TX */
3522 +
3523 + i = 0;
3524 + do {
3525 + while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
3526 + buffs--;
3527 + if (!buffs)
3528 + break;
3529 + } while (++i < MAX_CLOSE_WAIT);
3530 +
3531 + if (buffs)
3532 + printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
3533 + "left in NPE\n", dev->name, buffs);
3534 +#if DEBUG_CLOSE
3535 + if (!buffs)
3536 + printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
3537 +#endif
3538 + qmgr_disable_irq(queue_ids[port->id].txdone);
3539 + destroy_hdlc_queues(port);
3540 + release_hdlc_queues(port);
3541 +
3542 + if (port->plat->close)
3543 + port->plat->close(port->id, port->netdev);
3544 + hdlc_close(dev);
3545 + return 0;
3546 +}
3547 +
3548 +
3549 +static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
3550 + unsigned short parity)
3551 +{
3552 + struct port *port = dev_to_port(dev);
3553 +
3554 + if (encoding != ENCODING_NRZ)
3555 + return -EINVAL;
3556 +
3557 + switch(parity) {
3558 + case PARITY_CRC16_PR1_CCITT:
3559 + port->hdlc_cfg = 0;
3560 + return 0;
3561 +
3562 + case PARITY_CRC32_PR1_CCITT:
3563 + port->hdlc_cfg = PKT_HDLC_CRC_32;
3564 + return 0;
3565 +
3566 + default:
3567 + return -EINVAL;
3568 + }
3569 +}
3570 +
3571 +
3572 +static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3573 +{
3574 + const size_t size = sizeof(sync_serial_settings);
3575 + sync_serial_settings new_line;
3576 + int clk;
3577 + sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
3578 + struct port *port = dev_to_port(dev);
3579 +
3580 + if (cmd != SIOCWANDEV)
3581 + return hdlc_ioctl(dev, ifr, cmd);
3582 +
3583 + switch(ifr->ifr_settings.type) {
3584 + case IF_GET_IFACE:
3585 + ifr->ifr_settings.type = IF_IFACE_V35;
3586 + if (ifr->ifr_settings.size < size) {
3587 + ifr->ifr_settings.size = size; /* data size wanted */
3588 + return -ENOBUFS;
3589 + }
3590 + memset(&new_line, 0, sizeof(new_line));
3591 + new_line.clock_type = port->clock_type;
3592 + new_line.clock_rate = port->clock_rate;
3593 + new_line.loopback = port->loopback;
3594 + if (copy_to_user(line, &new_line, size))
3595 + return -EFAULT;
3596 + return 0;
3597 +
3598 + case IF_IFACE_SYNC_SERIAL:
3599 + case IF_IFACE_V35:
3600 + if(!capable(CAP_NET_ADMIN))
3601 + return -EPERM;
3602 + if (dev->flags & IFF_UP)
3603 + return -EBUSY; /* Cannot change parameters when open */
3604 +
3605 + if (copy_from_user(&new_line, line, size))
3606 + return -EFAULT;
3607 +
3608 + clk = new_line.clock_type;
3609 + if (port->plat->set_clock)
3610 + clk = port->plat->set_clock(port->id, clk);
3611 +
3612 + if (clk != CLOCK_EXT && clk != CLOCK_INT)
3613 + return -EINVAL; /* No such clock setting */
3614 +
3615 + if (new_line.loopback != 0 && new_line.loopback != 1)
3616 + return -EINVAL;
3617 +
3618 + port->clock_type = clk; /* Update settings */
3619 + port->clock_rate = new_line.clock_rate;
3620 + port->loopback = new_line.loopback;
3621 + return 0;
3622 +
3623 + default:
3624 + return hdlc_ioctl(dev, ifr, cmd);
3625 + }
3626 +}
3627 +
3628 +
3629 +static int __devinit hss_init_one(struct platform_device *pdev)
3630 +{
3631 + struct port *port;
3632 + struct net_device *dev;
3633 + hdlc_device *hdlc;
3634 + int err;
3635 +
3636 + if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
3637 + return -ENOMEM;
3638 + platform_set_drvdata(pdev, port);
3639 + port->id = pdev->id;
3640 +
3641 + if ((port->npe = npe_request(0)) == NULL) {
3642 + err = -ENOSYS;
3643 + goto err_free;
3644 + }
3645 +
3646 + port->plat = pdev->dev.platform_data;
3647 + if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
3648 + err = -ENOMEM;
3649 + goto err_plat;
3650 + }
3651 +
3652 + SET_MODULE_OWNER(net);
3653 + SET_NETDEV_DEV(dev, &pdev->dev);
3654 + hdlc = dev_to_hdlc(dev);
3655 + hdlc->attach = hss_hdlc_attach;
3656 + hdlc->xmit = hss_hdlc_xmit;
3657 + dev->open = hss_hdlc_open;
3658 + dev->poll = hss_hdlc_poll;
3659 + dev->stop = hss_hdlc_close;
3660 + dev->do_ioctl = hss_hdlc_ioctl;
3661 + dev->weight = 16;
3662 + dev->tx_queue_len = 100;
3663 + port->clock_type = CLOCK_EXT;
3664 + port->clock_rate = 2048000;
3665 +
3666 + if (register_hdlc_device(dev)) {
3667 + printk(KERN_ERR "HSS-%i: unable to register HDLC device\n",
3668 + port->id);
3669 + err = -ENOBUFS;
3670 + goto err_free_netdev;
3671 + }
3672 + printk(KERN_INFO "%s: HSS-%i\n", dev->name, port->id);
3673 + return 0;
3674 +
3675 +err_free_netdev:
3676 + free_netdev(dev);
3677 +err_plat:
3678 + npe_release(port->npe);
3679 + platform_set_drvdata(pdev, NULL);
3680 +err_free:
3681 + kfree(port);
3682 + return err;
3683 +}
3684 +
3685 +static int __devexit hss_remove_one(struct platform_device *pdev)
3686 +{
3687 + struct port *port = platform_get_drvdata(pdev);
3688 +
3689 + unregister_hdlc_device(port->netdev);
3690 + free_netdev(port->netdev);
3691 + npe_release(port->npe);
3692 + platform_set_drvdata(pdev, NULL);
3693 + kfree(port);
3694 + return 0;
3695 +}
3696 +
3697 +static struct platform_driver drv = {
3698 + .driver.name = DRV_NAME,
3699 + .probe = hss_init_one,
3700 + .remove = hss_remove_one,
3701 +};
3702 +
3703 +static int __init hss_init_module(void)
3704 +{
3705 + if ((ixp4xx_read_feature_bits() &
3706 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
3707 + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
3708 + return -ENOSYS;
3709 + return platform_driver_register(&drv);
3710 +}
3711 +
3712 +static void __exit hss_cleanup_module(void)
3713 +{
3714 + platform_driver_unregister(&drv);
3715 +}
3716 +
3717 +MODULE_AUTHOR("Krzysztof Halasa");
3718 +MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
3719 +MODULE_LICENSE("GPL v2");
3720 +module_init(hss_init_module);
3721 +module_exit(hss_cleanup_module);
3722 diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h
3723 index d2523b3..2fa3d6b 100644
3724 --- a/include/asm-arm/arch-ixp4xx/cpu.h
3725 +++ b/include/asm-arm/arch-ixp4xx/cpu.h
3726 @@ -28,4 +28,19 @@ extern unsigned int processor_id;
3727 #define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
3728 IXP465_PROCESSOR_ID_VALUE)
3729
3730 +static inline u32 ixp4xx_read_feature_bits(void)
3731 +{
3732 + unsigned int val = ~*IXP4XX_EXP_CFG2;
3733 + val &= ~IXP4XX_FEATURE_RESERVED;
3734 + if (!cpu_is_ixp46x())
3735 + val &= ~IXP4XX_FEATURE_IXP46X_ONLY;
3736 +
3737 + return val;
3738 +}
3739 +
3740 +static inline void ixp4xx_write_feature_bits(u32 value)
3741 +{
3742 + *IXP4XX_EXP_CFG2 = ~value;
3743 +}
3744 +
3745 #endif /* _ASM_ARCH_CPU_H */
3746 diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
3747 index 297ceda..73e8dc3 100644
3748 --- a/include/asm-arm/arch-ixp4xx/hardware.h
3749 +++ b/include/asm-arm/arch-ixp4xx/hardware.h
3750 @@ -27,13 +27,13 @@
3751
3752 #define pcibios_assign_all_busses() 1
3753
3754 +/* Register locations and bits */
3755 +#include "ixp4xx-regs.h"
3756 +
3757 #ifndef __ASSEMBLER__
3758 #include <asm/arch/cpu.h>
3759 #endif
3760
3761 -/* Register locations and bits */
3762 -#include "ixp4xx-regs.h"
3763 -
3764 /* Platform helper functions and definitions */
3765 #include "platform.h"
3766
3767 diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3768 index 5d949d7..c704fe8 100644
3769 --- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3770 +++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3771 @@ -15,10 +15,6 @@
3772 *
3773 */
3774
3775 -#ifndef __ASM_ARCH_HARDWARE_H__
3776 -#error "Do not include this directly, instead #include <asm/hardware.h>"
3777 -#endif
3778 -
3779 #ifndef _ASM_ARM_IXP4XX_H_
3780 #define _ASM_ARM_IXP4XX_H_
3781
3782 @@ -607,4 +603,36 @@
3783
3784 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
3785
3786 +/* "fuse" bits of IXP_EXP_CFG2 */
3787 +#define IXP4XX_FEATURE_RCOMP (1 << 0)
3788 +#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
3789 +#define IXP4XX_FEATURE_HASH (1 << 2)
3790 +#define IXP4XX_FEATURE_AES (1 << 3)
3791 +#define IXP4XX_FEATURE_DES (1 << 4)
3792 +#define IXP4XX_FEATURE_HDLC (1 << 5)
3793 +#define IXP4XX_FEATURE_AAL (1 << 6)
3794 +#define IXP4XX_FEATURE_HSS (1 << 7)
3795 +#define IXP4XX_FEATURE_UTOPIA (1 << 8)
3796 +#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
3797 +#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
3798 +#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
3799 +#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
3800 +#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
3801 +#define IXP4XX_FEATURE_PCI (1 << 14)
3802 +#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
3803 +#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
3804 +#define IXP4XX_FEATURE_USB_HOST (1 << 18)
3805 +#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
3806 +#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
3807 +#define IXP4XX_FEATURE_RSA (1 << 21)
3808 +#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
3809 +#define IXP4XX_FEATURE_RESERVED (0xFF << 24)
3810 +
3811 +#define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \
3812 + IXP4XX_FEATURE_USB_HOST | \
3813 + IXP4XX_FEATURE_NPEA_ETH | \
3814 + IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \
3815 + IXP4XX_FEATURE_RSA | \
3816 + IXP4XX_FEATURE_XSCALE_MAX_FREQ)
3817 +
3818 #endif
3819 diff --git a/include/asm-arm/arch-ixp4xx/npe.h b/include/asm-arm/arch-ixp4xx/npe.h
3820 new file mode 100644
3821 index 0000000..37d0511
3822 --- /dev/null
3823 +++ b/include/asm-arm/arch-ixp4xx/npe.h
3824 @@ -0,0 +1,39 @@
3825 +#ifndef __IXP4XX_NPE_H
3826 +#define __IXP4XX_NPE_H
3827 +
3828 +#include <linux/kernel.h>
3829 +
3830 +extern const char *npe_names[];
3831 +
3832 +struct npe_regs {
3833 + u32 exec_addr, exec_data, exec_status_cmd, exec_count;
3834 + u32 action_points[4];
3835 + u32 watchpoint_fifo, watch_count;
3836 + u32 profile_count;
3837 + u32 messaging_status, messaging_control;
3838 + u32 mailbox_status, /*messaging_*/ in_out_fifo;
3839 +};
3840 +
3841 +struct npe {
3842 + struct resource *mem_res;
3843 + struct npe_regs __iomem *regs;
3844 + u32 regs_phys;
3845 + int id;
3846 + int valid;
3847 +};
3848 +
3849 +
3850 +static inline const char *npe_name(struct npe *npe)
3851 +{
3852 + return npe_names[npe->id];
3853 +}
3854 +
3855 +int npe_running(struct npe *npe);
3856 +int npe_send_message(struct npe *npe, const void *msg, const char *what);
3857 +int npe_recv_message(struct npe *npe, void *msg, const char *what);
3858 +int npe_send_recv_message(struct npe *npe, void *msg, const char *what);
3859 +int npe_load_firmware(struct npe *npe, const char *name, struct device *dev);
3860 +struct npe *npe_request(int id);
3861 +void npe_release(struct npe *npe);
3862 +
3863 +#endif /* __IXP4XX_NPE_H */
3864 diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
3865 index 2a44d3d..695b9c4 100644
3866 --- a/include/asm-arm/arch-ixp4xx/platform.h
3867 +++ b/include/asm-arm/arch-ixp4xx/platform.h
3868 @@ -77,8 +77,7 @@ extern unsigned long ixp4xx_exp_bus_size;
3869
3870 /*
3871 * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
3872 - * used to
3873 - * Used as platform_data to provide GPIO pin information to the ixp42x
3874 + * used as platform_data to provide GPIO pin information to the ixp42x
3875 * I2C driver.
3876 */
3877 struct ixp4xx_i2c_pins {
3878 @@ -86,6 +85,27 @@ struct ixp4xx_i2c_pins {
3879 unsigned long scl_pin;
3880 };
3881
3882 +#define IXP4XX_ETH_NPEA 0x00
3883 +#define IXP4XX_ETH_NPEB 0x10
3884 +#define IXP4XX_ETH_NPEC 0x20
3885 +
3886 +/* Information about built-in Ethernet MAC interfaces */
3887 +struct eth_plat_info {
3888 + u8 phy; /* MII PHY ID, 0 - 31 */
3889 + u8 rxq; /* configurable, currently 0 - 31 only */
3890 + u8 txreadyq;
3891 + u8 hwaddr[6];
3892 +};
3893 +
3894 +/* Information about built-in HSS (synchronous serial) interfaces */
3895 +struct hss_plat_info {
3896 + int (*set_clock)(int port, unsigned int clock_type);
3897 + int (*open)(int port, void *pdev,
3898 + void (*set_carrier_cb)(void *pdev, int carrier));
3899 + void (*close)(int port, void *pdev);
3900 + u8 txreadyq;
3901 +};
3902 +
3903 /*
3904 * This structure provide a means for the board setup code
3905 * to give information to th pata_ixp4xx driver. It is
3906 diff --git a/include/asm-arm/arch-ixp4xx/qmgr.h b/include/asm-arm/arch-ixp4xx/qmgr.h
3907 new file mode 100644
3908 index 0000000..1e52b95
3909 --- /dev/null
3910 +++ b/include/asm-arm/arch-ixp4xx/qmgr.h
3911 @@ -0,0 +1,126 @@
3912 +/*
3913 + * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
3914 + *
3915 + * This program is free software; you can redistribute it and/or modify it
3916 + * under the terms of version 2 of the GNU General Public License
3917 + * as published by the Free Software Foundation.
3918 + */
3919 +
3920 +#ifndef IXP4XX_QMGR_H
3921 +#define IXP4XX_QMGR_H
3922 +
3923 +#include <linux/io.h>
3924 +#include <linux/kernel.h>
3925 +
3926 +#define HALF_QUEUES 32
3927 +#define QUEUES 64 /* only 32 lower queues currently supported */
3928 +#define MAX_QUEUE_LENGTH 4 /* in dwords */
3929 +
3930 +#define QUEUE_STAT1_EMPTY 1 /* queue status bits */
3931 +#define QUEUE_STAT1_NEARLY_EMPTY 2
3932 +#define QUEUE_STAT1_NEARLY_FULL 4
3933 +#define QUEUE_STAT1_FULL 8
3934 +#define QUEUE_STAT2_UNDERFLOW 1
3935 +#define QUEUE_STAT2_OVERFLOW 2
3936 +
3937 +#define QUEUE_WATERMARK_0_ENTRIES 0
3938 +#define QUEUE_WATERMARK_1_ENTRY 1
3939 +#define QUEUE_WATERMARK_2_ENTRIES 2
3940 +#define QUEUE_WATERMARK_4_ENTRIES 3
3941 +#define QUEUE_WATERMARK_8_ENTRIES 4
3942 +#define QUEUE_WATERMARK_16_ENTRIES 5
3943 +#define QUEUE_WATERMARK_32_ENTRIES 6
3944 +#define QUEUE_WATERMARK_64_ENTRIES 7
3945 +
3946 +/* queue interrupt request conditions */
3947 +#define QUEUE_IRQ_SRC_EMPTY 0
3948 +#define QUEUE_IRQ_SRC_NEARLY_EMPTY 1
3949 +#define QUEUE_IRQ_SRC_NEARLY_FULL 2
3950 +#define QUEUE_IRQ_SRC_FULL 3
3951 +#define QUEUE_IRQ_SRC_NOT_EMPTY 4
3952 +#define QUEUE_IRQ_SRC_NOT_NEARLY_EMPTY 5
3953 +#define QUEUE_IRQ_SRC_NOT_NEARLY_FULL 6
3954 +#define QUEUE_IRQ_SRC_NOT_FULL 7
3955 +
3956 +struct qmgr_regs {
3957 + u32 acc[QUEUES][MAX_QUEUE_LENGTH]; /* 0x000 - 0x3FF */
3958 + u32 stat1[4]; /* 0x400 - 0x40F */
3959 + u32 stat2[2]; /* 0x410 - 0x417 */
3960 + u32 statne_h; /* 0x418 - queue nearly empty */
3961 + u32 statf_h; /* 0x41C - queue full */
3962 + u32 irqsrc[4]; /* 0x420 - 0x42F IRC source */
3963 + u32 irqen[2]; /* 0x430 - 0x437 IRQ enabled */
3964 + u32 irqstat[2]; /* 0x438 - 0x43F - IRQ access only */
3965 + u32 reserved[1776];
3966 + u32 sram[2048]; /* 0x2000 - 0x3FFF - config and buffer */
3967 +};
3968 +
3969 +void qmgr_set_irq(unsigned int queue, int src,
3970 + void (*handler)(void *pdev), void *pdev);
3971 +void qmgr_enable_irq(unsigned int queue);
3972 +void qmgr_disable_irq(unsigned int queue);
3973 +
3974 +/* request_ and release_queue() must be called from non-IRQ context */
3975 +int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
3976 + unsigned int nearly_empty_watermark,
3977 + unsigned int nearly_full_watermark);
3978 +void qmgr_release_queue(unsigned int queue);
3979 +
3980 +
3981 +static inline void qmgr_put_entry(unsigned int queue, u32 val)
3982 +{
3983 + extern struct qmgr_regs __iomem *qmgr_regs;
3984 + __raw_writel(val, &qmgr_regs->acc[queue][0]);
3985 +}
3986 +
3987 +static inline u32 qmgr_get_entry(unsigned int queue)
3988 +{
3989 + extern struct qmgr_regs __iomem *qmgr_regs;
3990 + return __raw_readl(&qmgr_regs->acc[queue][0]);
3991 +}
3992 +
3993 +static inline int qmgr_get_stat1(unsigned int queue)
3994 +{
3995 + extern struct qmgr_regs __iomem *qmgr_regs;
3996 + return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
3997 + >> ((queue & 7) << 2)) & 0xF;
3998 +}
3999 +
4000 +static inline int qmgr_get_stat2(unsigned int queue)
4001 +{
4002 + extern struct qmgr_regs __iomem *qmgr_regs;
4003 + return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
4004 + >> ((queue & 0xF) << 1)) & 0x3;
4005 +}
4006 +
4007 +static inline int qmgr_stat_empty(unsigned int queue)
4008 +{
4009 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY);
4010 +}
4011 +
4012 +static inline int qmgr_stat_nearly_empty(unsigned int queue)
4013 +{
4014 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY);
4015 +}
4016 +
4017 +static inline int qmgr_stat_nearly_full(unsigned int queue)
4018 +{
4019 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_FULL);
4020 +}
4021 +
4022 +static inline int qmgr_stat_full(unsigned int queue)
4023 +{
4024 + return !!(qmgr_get_stat1(queue) & QUEUE_STAT1_FULL);
4025 +}
4026 +
4027 +static inline int qmgr_stat_underflow(unsigned int queue)
4028 +{
4029 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_UNDERFLOW);
4030 +}
4031 +
4032 +static inline int qmgr_stat_overflow(unsigned int queue)
4033 +{
4034 + return !!(qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW);
4035 +}
4036 +
4037 +#endif
4038 diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
4039 index f7a35b7..34ef48f 100644
4040 --- a/include/asm-arm/arch-ixp4xx/uncompress.h
4041 +++ b/include/asm-arm/arch-ixp4xx/uncompress.h
4042 @@ -13,7 +13,7 @@
4043 #ifndef _ARCH_UNCOMPRESS_H_
4044 #define _ARCH_UNCOMPRESS_H_
4045
4046 -#include <asm/hardware.h>
4047 +#include "ixp4xx-regs.h"
4048 #include <asm/mach-types.h>
4049 #include <linux/serial_reg.h>
4050
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